P1014CSE5DHB [NXP]
IC 32-BIT, 533 MHz, RISC PROCESSOR, PBGA425, 19 X 19 MM, 1.90 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, TEPBGA-425, Microprocessor;
| 型号： | P1014CSE5DHB |
| 厂家： | 
NXP |
| 描述： | IC 32-BIT, 533 MHz, RISC PROCESSOR, PBGA425, 19 X 19 MM, 1.90 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, TEPBGA-425, Microprocessor 时钟 外围集成电路 |
| 文件： | 总100页 (文件大小：802K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: P1014EC
Rev. 4, 05/2014
P1014
P1014 QorIQ Integrated
Processor Hardware
Specifications
TePBGA1-425
19 mm x 19 mm
The following list provides an overview of the P1014 feature
set:
• Programmable interrupt controller (PIC) compliant with
OpenPIC standard
• One 4-channel DMA controller
• Two I C interfaces
• Four UART interfaces
• Integrated Flash controller (IFC)
• TDM
• High-performance 32-bit Book E-enhanced core based on
the Power Architecture technology:
– 36-bit physical addressing
2
– Double-precision floating-point support
– 32-Kbyte L1 instruction cache and 32-Kbyte L1 data
cache
• 16 general-purpose I/O signals
• Operating temperature (Ta - T ) range: 0–105 C (standard)
– 400- to 1000-MHz clock frequency
• 256-Kbyte L2 cache with ECC. Also configurable as
SRAM and stashing memory
• Two enhanced three-speed Ethernet controllers (eTSECs)
– 10/100/1000 Mbps support
j
and –40 C to 105 C (extended)
• 19 19 mm 425-ball wirebond TePBGA-1 package with
0.8 mm pitch
– TCP/IP acceleration, quality of service, and
classification capabilities
– IEEE Std 1588™ support
– RGMII, SGMII
– eTSEC1 supports both RGMII/SGMII interfaces and
eTSEC2 support SGMII interface
• High-speed interfaces supporting the following
multiplexing options:
– Two PCI Express 1.1 interfaces
– Two SATA Revision 2.0 interfaces
– Five lanes of high-speed serial interfaces to be shared
between PCI Express, SATA, and SGMII
• High-speed USB controller (USB 2.0)
– Host and device support
– On-chip USB 2.0 high-speed PHY
– Enhanced host controller interface (EHCI)
– ULPI interface
• Enhanced secure digital host controller (SD/MMC)
• Enhanced serial peripheral interface (eSPI)
• Integrated security engine (ULE CAAM)
– Protocol support includes DES, AES, RNG, CRC,
MDE, PKE, SHA, and MD5.
• DDR3/DDR3L SDRAM memory controller supports and
16-bit with ECC
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2011-2014. All rights reserved.
Table of Contents
1
2
Pin assignments and reset states. . . . . . . . . . . . . . . . . . . . . . .4
2.21 PCI Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.22 Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Hardware design considerations. . . . . . . . . . . . . . . . . . . . . . 84
3.1 System clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.2 Supply power default setting . . . . . . . . . . . . . . . . . . . . 87
3.3 Power supply design and sequencing . . . . . . . . . . . . . 88
3.4 Decoupling recommendations. . . . . . . . . . . . . . . . . . . 89
3.5 SerDes block power supply decoupling
1.1 Ball layout diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Pinout assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.1 Overall DC electrical characteristics . . . . . . . . . . . . . . .21
2.2 Power sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3 Power-down Requirements. . . . . . . . . . . . . . . . . . . . . .25
2.4 Reset Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.5 Power-on ramp rate. . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.6 Power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.7 Input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.8 DDR3, and DDR3L SDRAM controller . . . . . . . . . . . . .31
2.9 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.10 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.11 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) .40
2.12 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
2.13 Integrated flash controller . . . . . . . . . . . . . . . . . . . . . . .55
2.14 Enhanced secure digital host controller (eSDHC) . . . .59
2.15 Programmable Interrupt Controller (PIC)
3
recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.6 Connection recommendations. . . . . . . . . . . . . . . . . . . 89
3.7 Pull-up and pull-down resistor requirements . . . . . . . . 89
3.8
Output buffer DC impedance . . . . . . . . . . . . . . . . . . . 90
3.9 Configuration pin muxing. . . . . . . . . . . . . . . . . . . . . . . 90
3.10 JTAG configuration signals . . . . . . . . . . . . . . . . . . . . . 91
3.11 Guidelines for high-speed interface termination . . . . . 93
3.12 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.1 Package parameters for P1014 . . . . . . . . . . . . . . . . . . 96
4.2 Mechanical dimensions of P1014 WB-TePBGA . . . . . 96
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.1 Part marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4
5
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.16 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.17 I2C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.18 GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2.19 TDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
2.20 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . .70
6
7
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
2
Freescale Semiconductor
This figure shows the major functional units within the P1014.
P1014
Power Architecture
e500 Core
Security
DDR3/DDR3L
Acceleration
SDRAM Controller
256-Kbyte
L2 Cache
32-Kbyte 32-Kbyte
XOR
2 x DUART,
2 x I2C, Timers,
Interrupt Control,
SD/MMC, SPI,
USB 2.0/ULPI,
L1
I-Cache
L1
D-Cache
GPIO
Coherency Module
SystemBus
Integrated Flash
Controller
(IFC)
On-Chip Network
2 x PCI Express
2 x Gigabit
Ethernet
TDM
4 Ch DMA
2 x SATA
5-lane SERDES
Core
Acceleration
Interface
Figure 1. P1014 block diagram
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
3
Pin assignments and reset states
1
Pin assignments and reset states
1.1
Ball layout diagrams
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
UART_ UART_
A
GPIO
_2
IIC1_
SDA
IIC2_
SDA
VSS
VSS
MA_06 MA_13
MA_09 MA_02
SD2_ S2VDD
RX_1
X2VDD
VSS
UART_ UART_
MA_04 MA_07 MA_11
MA_15 MCS_2
_B
S2VDD
SD2_
RX_0
SPI_
CTS_
CTS_
1_B
A
MOSI SOUT_2 SOUT_3 _0_B
SD2_
S2VSS
RXE_
B
VSS
IIC1_SCL GPIO
_4
VSS GPIO_3
X2VSS X2VSS
VSS
UART_
SIN_3
B
C
MCS0_B
NC
MA_03
VSS
VSS
MCS_3 X2VDD S2VSS
_B
SD2_RX
0_B
SPI_
MISO
B
UART_
RTS_
B00
UART_
SOUT
_00
C
D
E
UART_ IIC2_ OVDD IRQ_3
SOUT01 SCL
S2VDD SD2_REF
_CLK
SD2_TX S2VDD
_0
OVDD
MCKE_1MCS1_B MA_14 MBA_0 MBA_1 MA_08 MA_05 MDIC_1 X2VDD
SD2_
TX_1
X2VDD
SPI_CLK
IRQ_
OUT_
B
SD2_
TX1_
1_B
UART_
RTS_
B01
MA_00 MBA_2
MA_01
OVDD
GPIO_01 GPIO_0
D
MA_10
VSS
VSS
SD2_REF
S2VSS
SPI_CS0
_B
UART_
SIN00
MA_12
MDIC_0 X2VSS
X2VSS SD2_TX S2VSS
_0_B
UART_
SIN_2
_CLK_B
UART_ IRQ_1 GPIO_05HRESET
SIN01 _B
E
MODT
_1
MCKE
_0
VSS
MWE_B
MCK
MODT
_0
F
MRAS
_B
MCK_B
F
MCAS
_B
RTC READY IRQ_2 IRQ_0
SEE DETAIL B
SEE DETAIL A
SD2_IMP
_CAL_TX
SD2_IMP
_CAL_RX
SD2_PLL SD2_ SD2_PLL
BVDD_
VSEL_0
G
H
J
MDQ
_10
G
H
MDQ
_06
VDD
VDD
VDD
VDD
VDD
VDD
VDD
OVDD
TCK
VSS
TDI
TDD
VSS
GVDD GVDD GVDD
_TPA
VDD
VSS
AVDD
_TPD
S2VDD
VSS
SCAN
_MODE
_B
BVDD_
VSEL_1
AVDD_
SD2_
AVSS
HRESET
_REQ_B
MDQ
_12
VSS
MDQS
_0
MDQ
_08
VDD
VDD
VSS
VDD
TRST_B
OVDD
GVDD
VDD
CORE
VSS
USB
VDD1_8
VSS
VSS
VSS
MDQS
_1
MVREF VDD
J
VDD
VDD
VDD
VDD
MDQS
_0_B
TMS USBVSS
USBVSS UDP
MDQ
_14
MDQ
_02
USB
VDD1_8
K
MDQ
_00
VSS
VSS
VSS
K
GVDD
GVDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VVSSSS
VSS
VSS
VSS
VSS
VSS
VSS
MDQS
_1_B
MDQ_04
USBVDD3
_3
VUSB
CLMP
L
L
MDQ_07 VSS
MDM_1
USBVDD3
_3
USBVSS UDM
IBIAS
MDQ
_9
TEMP_
VSS
VSS
VSS
GVDD
GVDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M
N
P
M
N
MDQ_01
MDM_0
MDQ_11
USBVSS
_REXT
MDQ_15
USBPHY
_CLK
USBVSS
VSS
MDQ_05
MDQ_03
VSS
VSS
FA_
VDD
NC
NC
SYSCLK
VSS
MDQ_13 VSS
VDD AVDD_
DDR
IFC_
AD_00
VSS
VSS
VDD AVDD_
PLAT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P
GVDD
GVDD
VDD
VDD
NC
NC
NC
NC
VSS
MECC_6
MECC_2
MDQS_2
VSS
IFC_
AD_08
VDD
VDD
VDD
R
R
T
IFC_AD
_09
IFC_AD
_01
MECC_0
MECC_4
IFC_
ADDR
_02
IFC_
AD_10
GVDD
LVDD
VDD
VDD
VDD
X1VDD SD1_ S1VDD VDD
AVSS
VDD
BVDD
T
VSS
NC
NC
NC
IFC_AD
_11
IFC_AD
_03
IFC_
ADDR
_04
IFC_
AD_12
LVDD
VDD SD1_IMP SD1_PLL SD1_ SD1_PLLSD1_IMP VDD
_CAL_RX _TPD
AVDD _TPA _CAL_TX
BVDD BVDD
U
U
V
MDQS
_2_B
VSS
BVDD
IFC_AD
_05
IFC_
ADDR
_06
IFC_
AD_13
V
NC
NC
MECC_7
NC
MECC_1
IFC_AD
_14
IFC_AD
_07
SEE DETAIL C
SEE DETAIL D
IFC_
ADDR_
17
IFC_
ADDR
_16
W
Y
MDM_2 MECC_3
IFC_AD
_15
VSS
W
Y
VSS
IFC_
S1VDD SD1_RX X1VDD SD1_ S1VSS SD1_REF S1VDD SD1_TX X1VDD Other S1VSS CLK_0
TX_1 _CLK_B
_0 _2
IFC_
VSS ADDR_
21
TSEC1_
GTX_
CLK125
IFC_
ADDR
_19
IFC_
ADDR
_18
TSEC1_
RX_CLK
IFC_
RB_B
SENSE
VSS
NC
NC
MECC_5
VSS
IFC_
PERR_
B
IFC_
ADDR
_23
IFC_
ADDR
_20
TSEC1_TSEC1_
GTX_CLKTXD_3
EC_
MDC
SENSE
VDD
IFC_
BCTL
AA
AB
AC
TSEC1_
TXD_2
S1VSS SD1_RX X1VSS SD1_TX S1VDD SD1_REF S1VSS SD1_TX X1VSS
_1_B _CLK
_0_B _2_B
Other
S1VDD
IFC_CLE IFC_CS
_0_B
AA
AB
AC
IFC_
ADDR
_22
TSEC1_
RXD_2
TSEC1_
RXD_1
SD1_
TX_0
NC
VSS
LVDD TSEC1_ S1VDD X1VDD
RX_DV
S1VDD SD1_RX S1VDD SD1_RX S1VDD
_1
NC
X1VDD S1VSS IFC_PAR BVDD IFC_OE IFC_CS
VSS
_2
_1
_B
_1_B
IFC_
ADDR
_24
TSEC1_ EC_
TXD01 MDIO
TSEC1_ TSEC1_
RXD_3 RXD_0
TSEC1_ TSEC1_ VSS
X1VSS SD1_TX S1VSS SD1_RX S1VSS SD1_RX S1VSS
NC
X1VSS
VSS
IFC_WP
_B
IFC_CLK IFC_PAR
IFC_WE IFC_AVD
_B
TXD_0
_1_B
TX_EN
0_B
_2_B
_1
_0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
4
Freescale Semiconductor
Pin assignments and reset states
DETAIL A
1
2
3
4
5
6
7
8
9
10
11
12
VSS
VSS
MA_06 MA_13
MA_09 MA_02
SD2_ S2VDD
RX_1
MA_04 MA_07 MA_11
MA_15 MCS_2
_B
S2VDD
A
B
C
D
E
F
SD2_
RXE_
S2VSS
MCS0_B
NC
MA_03
VSS
VSS
MCS_3 X2VDD S2VSS
_B
B
S2VDD SD2_REF
_CLK
MCKE_1MCS1_B MA_14 MBA_0 MBA_1 MA_08 MA_05 MDIC_1 X2VDD
SD2_
TX_1
SD2_
TX1_
1_B
MBA_2
VSS
MA_00
MA_01
VSS
VSS
MA_10
SD2_REF
_CLK_B
MA_12
MDIC_0 X2VSS
S2VSS
MODT
_1
MCKE
_0
MODT
_0
MRAS
_B
MCK_B
MCAS
_B
MWE_B
MCK
SD2_IMP
_CAL_TX
SD2_PLL SD2_
MDQ
_10
G
H
J
MDQ
_06
VSS
GVDD GVDD GVDD
AVDD_
_TPA
VDD
VSS
AVDD
SD2_
AVSS
MDQ
_12
MDQS
_0
VSS
MDQ
_08
VDD
VSS
GVDD
VDD
CORE
VSS
VSS
MDQS
_1
MVREF VDD
MDQS
_0_B
MDQ
_14
MDQ
_02
MDQ
_00
VSS
VSS
K
L
VSS
GVDD
GVDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VVSSSS
MDQS
_1_B
MDQ_04
MDQ_07
MDQ_01
VSS
MDM_1
MDQ
_9
TEMP_
VSS
VSS
GVDD
VDD
VSS
VSS
M
MDQ_11
MDM_0
MDQ_15
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
5
Pin assignments and reset states
DETAIL B
13
14
15
16
17
18
19
20
21
22
23
UART_
CTS_
_0_B
UART_
CTS_
1_B
A
B
C
D
E
F
GPIO
_2
IIC1_
SDA
IIC2_
SDA
X2VDD VSS
X2VSS X2VSS
UART_ UART_
SOUT_2 SOUT_3
SD2_
RX_0
SPI_
MOSI
VSS
IIC1_SCL
GPIO_3
IRQ_3
GPIO
_4
VSS
VSS UART_
SIN_3
SD2_RX
0_B
SPI_
MISO
UART_
RTS_
B00
UART_
OVDD
UART_
SOUT01
IIC2_ OVDD
SCL
SD2_TX S2VDD
_0
X2VDD
SPI_CLK
SOUT
_00
IRQ_
OUT_
B
UART_
RTS_
B01
OVDD
GPIO_0
GPIO_01
SPI_CS0
_B
UART_
SIN00
X2VSS SD2_TX S2VSS
_0_B
UART_
SIN_2
UART_
SIN01
HRESET
_B
IRQ_1 GPIO_05
RTC
IRQ_0
TDD
READY IRQ_2
SD2_IMP
_CAL_RX
SD2_PLL
_TPD
BVDD_
VSEL_0
G
H
J
VDD
VDD
VDD
VDD
VDD
VDD
OVDD
VDD
TCK
VSS
SCAN
_MODE
_B
BVDD_
VSEL_1
HRESET
_REQ_B
VDD
VSS
VDD
VSS
TRST_B
OVDD
S2VDD
VSS
TDI
USB
VDD1_8
VDD
VDD
VDD
VDD
USBVSS
TMS
USB
VDD1_8
K
L
VSS
VSS
VSS
VSS
VSS
VSS
USBVDD3
_3
UDP
UDM
USBVSS
USBVSS
VUSB
CLMP
USBVDD3
_3
IBIAS
_REXT
VSS
VSS
VSS
M
USBPHY
_CLK
USBVSS
USBVSS
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
6
Freescale Semiconductor
Pin assignments and reset states
DETAIL C
VSS
VSS
VSS
VSS
GVDD
VDD
MDQ_05
MDQ_03
MDQ_13
NC
VSS
NC
N
P
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GVDD
GVDD
VDD
VDD
VSS
MECC_6
MECC_2
MDQS_2
NC
NC
MECC_0
MECC_4
R
GVDD
LVDD
VDD
VDD
VDD
X1VDD SD1_
AVSS
VSS
NC
NC
NC
T
LVDD
VDD SD1_IMP SD1_PLL SD1_
MDQS
_2_B
VSS
U
_CAL_RX _TPD
AVDD
MECC_7
MDM_2
NC
NC
NC
MECC_1
V
MECC_3
VSS
VSS
W
Y
TSEC1_
GTX_
CLK125
TSEC1_
RX_CLK
SENSE
VSS
NC
NC
MECC_5
SD1_RX
_0
S1VSS
S1VDD
S1VDD
S1VSS
X1VDD SD1_
TX_1
SD1_REF
_CLK_B
TSEC1_TSEC1_
GTX_CLKTXD_3
EC_
MDC
SENSE
VDD
TSEC1_
TXD_2
SD1_RX
_0_B
X1VSS SD1_TX
_1_B
SD1_REF
_CLK
AA
AB
AC
TSEC1_
RXD_2
TSEC1_
RXD_1
SD1_
TX_0
LVDD
X1VDD
X1VSS
SD1_RX
_1
NC
VSS
TSEC1_ S1VDD
RX_DV
S1VDD
S1VDD
S1VSS
TSEC1_ TSEC1_
RXD_3 RXD_0
TSEC1_ EC_
TXD01 MDIO
TSEC1_
TXD_0
SD1_RX
_1_B
TSEC1_ VSS
TX_EN
SD1_TX S1VSS
0_B
1
2
3
4
5
6
7
8
9
10
11
12
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
7
Pin assignments and reset states
DETAIL D
VSS
VSS
VSS
N
VSS
VSS
NC
SYSCLK
VSS
VDD AVDD_
FA_
VDD
NC
DDR
IFC_
AD_00
VDD AVDD_
PLAT
VSS
VSS
VSS
VSS
VSS
VSS
P
VSS
IFC_
AD_08
VDD
VDD
VDD
R
IFC_AD
_09
IFC_AD
_01
IFC_
ADDR
_02
IFC_
AD_10
S1VDD VDD
VDD
BVDD
T
IFC_AD
_11
IFC_AD
_03
IFC_
ADDR
_04
IFC_
AD_12
SD1_PLLSD1_IMP VDD
_TPA _CAL_TX
BVDD BVDD
U
BVDD
IFC_AD
_05
IFC_
ADDR
_06
IFC_
AD_13
V
IFC_AD
_14
IFC_AD
_07
IFC_
ADDR_
17
IFC_
ADDR
_16
IFC_AD
_15
VSS
W
Y
IFC_
CLK_0
IFC_
ADDR_
21
IFC_
ADDR
_19
IFC_
ADDR
_18
IFC_
RB_B
S1VDD
SD1_TX
_2
X1VDD Other S1VSS
VSS
IFC_
PERR_
B
IFC_
ADDR
_23
IFC_
ADDR
_20
IFC_
BCTL
SD1_TX
_2_B
S1VSS
X1VSS
NC
Other S1VDD
X1VDD S1VSS
IFC_CLE
IFC_CS
_0_B
AA
AB
AC
IFC_
ADDR
_22
S1VDD
SD1_RX
_2
IFC_OE
_B
IFC_PAR BVDD
_1
IFC_CS
_1_B
VSS
IFC_
ADDR
_24
S1VSS
SD1_RX
_2_B
NC
X1VSS
VSS
IFC_WP
_B
IFC_CLK IFC_PAR
IFC_WEIFC_AVD
_B
_1
_0
13
14
15
16
17
18
19
20
21
22
23
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
8
Freescale Semiconductor
Pin assignments and reset states
Table 1: Signals color coding
Name
Color
DDR Signals
Dew
LVDD, SVDD, BVDD,
S1VDD, X1VD, OVDD,
GVDD, X2VDD, S2VDD
Cloud LT
VDD
AVDD
VSS
Mist
Yellow
Cork DK
Cyan
IFC
UDP, UDM
Green
SYSCLK, RTC
Dew
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
9
Pin assignments and reset states
Table 1: Signals color coding (continued)
Name
Color
S1VSS, X1VSS
Cork DK
Mist DK
Slate
Serdes
TSEC1
NC
Yellow LT
SENSE
Moss DK
Ethernet Management
Blue
USB
IRQ
Dew DK
Mist DK
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
10
Freescale Semiconductor
Pin assignments and reset states
Table 1: Signals color coding (continued)
Name
Color
DUART
Magenta
READY, SCAN, VUSB,
IBIAS, FA
Orange
Cork
HRESET_B
TCK, TDD, TDI, TMS,
TRST_B
Orange
Yellow
MVREF
1.2
Pinout assignments
This table provides the pinout listing for the P1014.
1
Table 1. 1014 pinout listing
Pin
Type
Signal
Pin Number
Supply
Note
DDR Memory Controller Interface
MDQ_00
MDQ_01
MDQ_02
MDQ_03
MDQ_04
MDQ_05
MDQ_06
K4
M3
J4
IO
IO
IO
IO
IO
IO
IO
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
N4
K3
N3
G3
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
11
Pin assignments and reset states
1
Table 1. 1014 pinout listing (continued)
Pin
Type
Signal
Pin Number
Supply
Note
MDQ_07
MDQ_08
MDQ_09
MDQ_10
MDQ_11
MDQ_12
MDQ_13
MDQ_14
MDQ_15
MECC_0
MECC_1
MECC_2
MECC_3
MECC_4
MECC_5
MECC_6
MECC_7
MDQS_0
MDQS_1
MDQS_2
MDQS_0_B
MDQS_1_B
MDQS_2_B
MDM_0
L3
H2
L1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
G1
M2
H1
N1
J2
M1
R4
V4
R3
W4
T4
Y2
P3
V3
H3
J1
T3
J3
K1
U3
M4
L2
MDM_1
O
MDM_2
W3
D3
D7
B6
B3
A2
C7
A5
A3
O
MA_00
O
MA_01
O
MA_02
O
MA_03
O
MA_04
O
MA_05
O
MA_06
O
MA_07
O
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
12
Freescale Semiconductor
Pin assignments and reset states
1
Table 1. 1014 pinout listing (continued)
Pin
Type
Signal
Pin Number
Supply
Note
MA_08
C6
B5
D1
A4
D5
A6
C3
A7
C4
C5
D4
B1
C2
A8
B8
F1
F2
F4
E3
C1
G4
F3
E2
E1
D8
C8
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
IO
IO
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
MA_09
MA_10
MA_11
MA_12
MA_13
MA_14
MA_15
MBA_0
MBA_1
MBA_2
MCS_0_B
MCS_1_B
MCS_2_B
MCS_3_B
MRAS_B
MCAS_B
MWE_B
MCKE_0
MCKE_1
MCK
6
—
—
—
—
18
19
MCK_B
MODT_0
MODT_1
MDIC_0
MDIC_1
Ethernet MI
EC_MDC/cfg_cpu_boot
EC_MDIO
AA6
AC2
O
LVDD
LVDD
3
IO
—
eTSEC1/1588/DMA/GPIO
TSEC1_TXD_0/1588_ALARM_OUT1/cfg_rom_loc[0]
TSEC1_TXD_1/1588_ALARM_OUT2/cfg_rom_loc[1]
TSEC1_TXD_2/1588_PULSE_OUT1/cfg_rom_loc[2]
TSEC1_TXD_3/1588_PULSE_OUT2/cfg_rom_loc[3]
AC5
AC1
AA5
AA4
O
O
O
O
LVDD
LVDD
LVDD
LVDD
21
21
21
21
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
13
Pin assignments and reset states
1
Table 1. 1014 pinout listing (continued)
Pin
Type
Signal
Pin Number
Supply
Note
TSEC1_TX_EN/cfg_svr
AC6
AC4
O
I
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
3, 11
—
—
—
—
—
—
7
TSEC1_RXD_0/1588_TRIG_IN1
TSEC1_RXD_1/1588_TRIG_IN2/GPIO_12
TSEC1_RXD_2/1588_CLK_IN
AB4
AB3
AC3
AB6
Y6
IO
I
TSEC1_RXD_3/1588_CLK_OUT
IO
IO
IO
O
IO
TSEC1_RX_DV/DMA_DREQ_0_B/GPIO_13
TSEC1_RX_CLK/DMA_DACK_0_B/GPIO_14
TSEC1_GTX_CLK/DMA_DDONE_0_B
TSEC1_GTX_CLK125/GPIO_15
AA3
Y5
—
IFC/eSDHC/USB ULPI/DMA
IFC_AD_00/cfg_sys_pll_0
P21
R22
T23
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
21
21
21
21
21
21
3
IFC_AD_01/cfg_sys_pll_1
IFC_AD_02/cfg_sys_pll_2
IFC_AD_03/cfg_core_pll_0
T22
IFC_AD_04/cfg_core_pll_1
U23
U22
V23
V22
R21
R20
T21
IFC_AD_05/cfg_core_pll_2
IFC_AD_06/cfg_core_speed
IFC_AD_07/cfg_ddr_pll_0
21
21
3
IFC_AD_08/cfg_ddr_pll_1
IFC_AD_09/cfg_ifc_pb_0
IFC_AD_10/cfg_ifc_pb_1
3
IFC_AD_11/cfg_ifc_pb_2
T20
3
IFC_AD_12/cfg_srds_refclk
U21
V21
V20
W20
W23
W21
Y23
Y22
AA23
Y21
AB23
AA22
3
IFC_AD_13/cfg_io_ports_0
3
IFC_AD_14/cfg_io_ports_1
3
IFC_AD_15/cfg_ifc_adm
3
IFC_ADDR_16/SDHC_CLK/USB_CLK/IFC_CS_2_B
IFC_ADDR_17/SDHC_CMD/USB_D_0/DMA_DREQ_1_B
IFC_ADDR_18/SDHC_DATA_0/USB_D_1/DMA_DACK_1_B
IFC_ADDR_19/SDHC_DATA_1/USB_D_2/DMA_DDONE_1_B
IFC_ADDR_20/SDHC_DATA_2/USB_D_3
IFC_ADDR_21/SDHC_DATA_3/USB_D_4
IFC_ADDR_22/SDHC_WP/USB_D_5
IFC_ADDR_23/SDHC_CD/USB_D_6
8
—
—
—
—
—
—
—
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
14
Freescale Semiconductor
Pin assignments and reset states
1
Table 1. 1014 pinout listing (continued)
Pin
Type
Signal
Pin Number
Supply
Note
IFC_ADDR_24/USB_D_7
IFC_AVD/cfg_dram_type
IFC_CS_0_B
AC23
AC22
AA21
AB21
AC21
AA20
AB20
AC20
Y19
IO
O
O
O
O
O
O
O
I
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
—
3
—
—
3
IFC_CS_1_B
IFC_WE_B/cfg_ifc_flash_mode
IFC_CLE/cfg_host_agt_0
IFC_OE_B/cfg_host_agt_1
IFC_WP_B
3
3
7
IFC_RB_B
—
3
IFC_BCTL/cfg_boot_seq_0
IFC_PAR_0/USB_STP
IFC_PAR_1/cfg_plat_speed
IFC_PERR_B/USB_DIR
IFC_CLK_0
AA19
AC19
AB18
AA18
Y18
O
IO
IO
I
7
3
—
—
8
O
IO
IFC_CLK_1/USB_NXT/IFC_CS_3_B
AC18
SPI/GPIO
SPI_MOSI/GPIO_6
SPI_MISO/GPIO_7
SPI_CLK/GPIO_8
SPI_CS0_B/GPIO_9
A16
B16
C16
D16
IO
IO
IO
IO
OVDD
OVDD
OVDD
OVDD
—
—
—
—
DUART/TDM
UART_SOUT_2/TDM_TX_DATA/cfg_boot_seq_1
UART_SIN_2/TDM_RX_DATA
UART_SOUT_3/TDM_TFS
A17
D17
A18
B18
O
OVDD
OVDD
OVDD
OVDD
3
IO
IO
IO
—
—
—
UART_SIN_3/TDM_RFS
DUART/TDM/GPIO
UART_SOUT_0
C18
D18
A19
C19
C20
E20
A20
O
I
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
7
—
—
3
UART_SIN_0
UART_CTS_0_B
I
UART_RTS_0_B/cfg_ifc_ecc_0
UART_SOUT_1/cfg_ifc_ecc_1
UART_SIN_1
O
O
I
3
—
—
UART_CTS_1_B/GPIO_10/TDM_TX_CLK/IRQ_10
IO
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
15
Pin assignments and reset states
1
Table 1. 1014 pinout listing (continued)
Pin
Type
Signal
Pin Number
Supply
Note
UART_RTS_1_B/GPIO_11/IRQ_11/TDM_RX_CLK
D19
IO
OVDD
—
I2C
IIC1_SDA
IIC1_SCL
IIC2_SDA
IIC2_SCL
A21
B20
A22
C21
IO
IO
IO
IO
OVDD
OVDD
OVDD
OVDD
10
10
10
10
Interrupts
IRQ_0
F23
E21
F22
C23
D21
I
I
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
10
IRQ_1
IRQ_2/TRIG_IN
IRQ_3/SRESET_B/TMP_DETECT
IRQ_OUT_B
I
I
O
GPIO
GPIO_0/IRQ_4/DRVVBUS/MDVAL
D23
D22
A23
B23
B21
E22
IO
IO
IO
IO
IO
IO
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
9
GPIO_1/IRQ_5/VBUSPWRFAULT/MSRCID_0
GPIO_2/IRQ_6/CKSTP_IN_B/MSRCID_1
GPIO_3/IRQ_7/CKSTP_OUT_B/MSRCID_2
GPIO_4/IRQ_8/MCP_B/MSRCID_3/CLK_OUT
GPIO_5/IRQ_9/UDE_B/MSRCID_4
—
—
System Control/Power Management
HRESET_B
E23
H23
F21
I
OVDD
OVDD
OVDD
—
7
HRESET_REQ_B
READY/TRIG_OUT/ASLEEP
O
O
7
Clocking
SYSCLK
RTC
P23
F20
M20
I
I
I
OVDD
OVDD
OVDD
—
—
—
USBPHY_CLK
IO_VSEL
BVDD_VSEL_0
BVDD_VSEL_1
G17
H17
I
I
OVDD
OVDD
—
—
DFT
SCAN_MODE_B
H21
I
OVDD
2
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
16
Freescale Semiconductor
Pin assignments and reset states
1
Table 1. 1014 pinout listing (continued)
Pin
Type
Signal
Pin Number
Supply
Note
JTAG
TCK
G21
H22
G23
J22
I
I
OVDD
OVDD
OVDD
OVDD
OVDD
—
4
TDI
TDO
O
I
6
TMS
4
TRST_B
H20
I
4
Serdes1 (x3)
SD1_TX_2
Y14
Y10
O
O
O
O
O
O
I
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
12
13
—
—
SD1_TX_1
SD1_TX_0
AB9
AA14
AA10
AC9
AB13
AB11
Y8
SD1_TX_2_B
SD1_TX_1_B
SD1_TX_0_B
SD1_RX_2
SD1_RX_1
I
SD1_RX_0
I
SD1_RX_2_B
SD1_RX_1_B
SD1_RX_0_B
SD1_REF_CLK
SD1_REF_CLK_B
SD1_IMP_CAL_TX
SD1_IMP_CAL_RX
SD1_PLL_TPA
SD1_PLL_TPD
AC13
AC11
AA8
AA12
Y12
I
I
I
I
I
U14
I
U10
I
U13
O
O
U11
Serdes2 (x2)
SD2_TX_1
C10
C14
D10
D14
A11
A13
B11
O
O
O
O
I
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
—
—
—
—
—
—
—
SD2_TX_0
SD2_TX_1_B
SD2_TX_0_B
SD2_RX_1
SD2_RX_0
SD2_RX_1_B
I
I
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
17
Pin assignments and reset states
1
Table 1. 1014 pinout listing (continued)
Pin
Type
Signal
Pin Number
Supply
Note
SD2_RX_0_B
B13
C12
D12
G10
G14
G11
G13
I
I
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
—
—
—
12
13
—
—
SD2_REF_CLK
SD2_REF_CLK_B
SD2_IMP_CAL_TX
SD2_IMP_CAL_RX
SD2_PLL_TPA
I
I
I
O
O
SD2_PLL_TPD
USB PHY
VBUSCLMP
IBIAS_REXT
UDP
L21
M22
K23
L23
IO
I
USBVDD3_3
USBVDD3_3
USBVDD3_3
USBVDD3_3
—
14
—
—
IO
IO
UDM
Analog
MVREF
J7
—
—
—
GVDD/2
—
5
SENSEVDD
SENSEVSS
AA2
—
—
Y3
5
Other
Other Signals
Y16, AA16
—
—
17
Power and Ground Pins
AVDD_CORE
AVDD_PLAT
AVDD_DDR
FA_VDD
H9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
P17
N17
N21
SD1_AVDD
SD2_AVDD
SD1_AVSS
SD2_AVSS
BVDD
U12
—
—
—
—
—
—
G12
T12
H12
T17,U16, U17,U20, AB19
GVDD
G7,G8,G9,
H7,K7,L7,M7,N7,P7,
R7,T7
LVDD
U7,U8,AB5
—
—
—
—
—
—
OVDD
C17,C22, D20,G20, J20
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
18
Freescale Semiconductor
Pin assignments and reset states
1
Table 1. 1014 pinout listing (continued)
Pin
Type
Signal
Pin Number
Supply
Note
S1VDD
S1VSS
T13,Y7,Y13,AA11,AA17,
AB7, AB10,AB12,AB14
—
—
—
Y11,Y17, AA7,AA13,
—
—
—
AB17,AC10,AC12,AC14
S2VDD
A10,A12, C11,C15, H13
B10,B12, D11,D15
L17,M17
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20
16
—
—
—
S2VSS
USBVDD1_0
USBVDD1_8
USBVDD3_3
USBVSS
VDD
J21,K21
K20,L20
J23,K22,L22,M21,M23
G15,G16,H8,H10,H11,
H14,H15, H16,
J8,J16,J17,
K8,K16,K17,L8,L16,M8,
M16,N8,N16,P8,P16,R8,
R16,R17,T8,T9,T10,T14,
T15,T16,U9,U15
VSS
A1,A9,B4,
—
—
—
A15,B7,B17,B19,B22,D2,
D6,E4,G2, G22,H4,J9,
J10,J11,J12,J13,J14,J15,
K2,K9,K10,
K11,K12,K13,K14,K15,L4
,L9,L10,L11,
L12,L13,L14,L15,M9,M10
,M11,M12, M13,M14,
M15,N2,N9,N10,N11,
N12,N13,
N14,N15,P4,P9,P10,P11,
P12,P13, P14,P15,
P20,R9,R10,R11,R12,
R13,R14,
R15,R23,T2,U4,W2,W22,
Y4,Y20,AB2,AB22,AC7,
AC17,P22, N20
X1VDD
X1VSS
X2VDD
X2VSS
T11,Y9,Y15,AB8,AB16
AA9,AA15, AC8,AC16
A14,B9,C9, C13
—
—
—
—
—
—
—
—
—
—
—
—
B14,B15,D9,D13
Not Connected
NC
B2,N22, AA1, N23,
AB1,R2,V2,P1,W1,R1,
Y1,P2,U2, AB15, AC15,
T1, U1, V1
—
—
—
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
19
Pin assignments and reset states
1
Table 1. 1014 pinout listing (continued)
Pin
Type
Signal
Pin Number
Supply
Note
Note:
1. All multiplexed signals are listed only once and do not re-occur. For example,
IFC_ADDR[17]/SDHC_CMD/USB_D[1]/DMA_DREQ_B[1] is listed only once in the IFC section, and is not mentioned in
the DMA section even though the pin also functions as DMA_DREQ_B[1].
2. These are test signals for factory use only and must be pulled up (with 100 –1 k) to OVDD for normal operation.
3. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in
the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k pull-down resistor. However,
if the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the
net at reset, then a pullup or active driver is needed.
4. These pins have weak internal pull-up P-FETs that are always enabled.
5. Treat these pins as no connects (NC).
6. This output is actively driven during reset rather than being three-stated during reset.
7. This pin must NOT be pulled down, by a resistor or the component it is connected to, during power-on reset.
8. If this pin is configured for chip select usage than it is recommend to have a weak pull-up resistor (2-10 K) be placed on
this pin to BVDD, to ensure no random chip select assertion due to possible noise and etc.
9. If this pin is configured for check stop usage than it will behave as an open drain signal.
10.This pin is an open drain signal.
11.This pin must be pulled down during power-on reset.
12.This pin should be pulled down with 100 1ꢀ resistor if used in autocalibration mode and should be tied to 1V if fixed
calibration mode is used.
13.This pin should be pulled down with 200 1ꢀ resistor if used in autocalibration mode and should be tied to 1V if fixed
calibration mode is used.
14.For this pin the recommendations mentioned in Section 2.12.4, “IBIAS_REXT filter and Section 2.12.5, “Threshold detect
increase must be followed.
15.This pin is used for fuse programming. Should be tied to Vss for normal operation (fuse read). See section Section 2.2,
“Power sequencing” for more details.
16.This pin should be connected to Vss through 1F.No need to supply power to this pin. 1.8V output may be observed on
this pin during normal working conditions.
17.Connect these pins to Vss.
18.This is a DDR drive strength calibration pin. This should be connected to VSS through a 20(Full-strength mode) or 40
(Half-strength mode) precision 1ꢀ resistor.
19.This is a DDR drive strength calibration pin. This should be connected to GVDD through a 20(Full-strength mode) or 40
(Half-strength mode) precision 1ꢀ resistor.
20.This pin and VDD should be fed from the same source, with a filter circuit as described in Section 3.3.1, “PLL power supply
filtering.
21.This pin is a reset configuration pin. During reset sequence this should be pulled-up or down as needed, to the
corresponding power bank, with a weak pull-up/down resistor.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
20
Freescale Semiconductor
Electrical characteristics
2
Electrical characteristics
This section provides the AC and DC electrical specifications for the P1014. The P1014 is currently targeted to these
specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete
reference.These are not purely I/O buffer design specifications.
2.1
Overall DC electrical characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute maximum ratings
This table provides the absolute maximum ratings.
Table 2. Absolute maximum ratings
1
Characteristic
Symbol
Max Value
Unit Note
Platform supply voltage
PLL supply voltage
VDD
–0.3 to 1.05
–0.3 to 1.05
V
V
—
7
AVDD_CORE
AVDD_DDR
AVDD_PLAT
SD1_AVDD
SD2_AVDD
Core power supply for SerDes transceivers
Pad power supply for SerDes transceivers
USB PHY supply
S1VDD
S2VDD
–0.3 to 1.05
–0.3 to 1.05
V
V
V
V
V
—
—
—
—
—
X1VDD
X2VDD
USBVDD1_0
USBVDD3_3
–0.3 to 1.05
–0.3 to 3.63
DDR3/DDR3L DRAM I/O voltage
GVDD
–0.3 to 1.65
–0.3 to 1.45
Three-speed Ethernet I/O (eTSEC), MII management,
GPIO_(12-15), DMA, 1588 voltage
LVDD
–0.3 to 2.75
SPI, DUART, TDM, I2C, GPIO_(0-11) and JTAG I/O voltage
IFC, eSDHC, USB-ULPI voltage
OVDD
BVDD
–0.3 to 3.63
V
V
—
—
–0.3 to 3.63
–0.3 to 2.75
–0.3 to 1.98
Input voltage
DDR3/DDR3L DRAM signals
DDR3/DDR3L DRAM reference
MVIN
MVREF
LVIN
–0.3 to (GVDD + 0.3)
–0.3 to (GVDD/2 + 0.3)
–0.3 to (LVDD + 0.3)
V
V
V
2, 6
—
Three-speed Ethernet,1588, DMA,
GPIO_(12-15), signals
3, 6
IFC, USB, eSDHC signals
BVIN
OVIN
–0.3 to (BVDD + 0.3)
–0.3 to (OVDD + 0.3)
—
V
4
DUART, SYSCLK, system control and power
management, I2C, eSPI, clocking, I/O voltage
select, GPIO_(0-11)and JTAG I/O voltage
5, 6
Serdes signals
XVIN
–0.3 to (XVDD + 0.3)
V
—
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
21
Electrical characteristics
1
Table 2. Absolute maximum ratings (continued)
Characteristic
Symbol
Max Value
Unit Note
C
Storage temperature range
TSTG
–55 to 150
—
Note:
1. Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional
operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. Caution: BVIN must not exceed BVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
5. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
6. (X,B,G,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
7. AVDD is measured at the input to the filter and not at the pin of the device. The filter circuit is provided in Section 3.3.1,
“PLL power supply filtering.
2.1.2
Recommended operating conditions
This table provides the recommended operating conditions for this device. Note that the values in Table 3 are the recommended
and tested operating conditions. Proper device operation outside these conditions is not guaranteed.
3
Table 3. Recommended operating conditions
Recommended
Value
Characteristic
Symbol
Unit Note
Platform supply voltage
PLL supply voltage
VDD
1
1
50 mV
V
V
—
—
AVDD_CORE
AVDD_DDR
AVDD_PLAT
SD1_AVDD
SD2_AVDD
50 mV
Core power supply for SerDes transceivers
Pad power supply for SerDes transceivers and PCI Express
USB PHY supply
S1VDD
S2VDD
1
1
1
50 mV
50 mV
50 mV
V
V
V
—
—
—
X1VDD
X2VDD
USBVDD1_0
USBVDD3_3
3.3 V 165 mV
DDR3 DRAM I/O voltage
DDR3L DRAM I/O voltage
GVDD
GVDD
1.5 V 75 mV
—
—
—
—
1.35 V +100mV /
-67mV
Three-speed Ethernet I/O (eTSEC), MII management, GPIO_(12-15),
DMA, 1588 voltage
LVDD
2.5 V 125 mV
V
V
—
—
DUART, system control and power management, I2C, GPIO_(0-11),
and JTAG I/O voltage
OVDD
3.3 V 165 mV
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
22
Freescale Semiconductor
Electrical characteristics
3
Table 3. Recommended operating conditions
Recommended
Value
Characteristic
Integrated Flash Controller I/O
Symbol
Unit Note
BVDD
3.3 V 165 mV
2.5 V 125 mV
1.8 V 90 mV
V
1
Input voltage
DDR3/DDR3L DRAM signals
MVIN
MVREF
LVIN
GND to GVDD
GND to GVDD/2
GND to LVDD
V
V
V
—
—
2
DDR3/DDR3L DRAM reference
Three-speed Ethernet,1588, DMA, GPIO_(12-15),
signals
IFC, USB, eSDHC signals
BVIN
OVIN
GND to BVDD
GND to OVDD
V
V
2
2
DUART, SYSCLK, system control and power
management, I2C, eSPI, GPIO_(0-11) and JTAG
signals
Serdes signals
XVIN
TA/TJ
GND to X1VDD
V
2
Operating
Temperature
range
Standard Temperature Range
TA=0 (min) to
TJ=105 (max)
C
—
Extended Temperature Range
TA/TJ
TA=–40 (min) to
TJ=105 (max)
C
—
Note:
1. BVDD = 3.3 V or 1.8 V is selected for USB, all other signals associated with BVDD must meet all VIH requirements
associated with external device inputs.
2. (L,X,B,O,G)VIN may overshoot (for VIH) or undershoot (for VIL) to the voltages and maximum duration shown in Figure 2.
3. Power should be applied to all power pins even if the corresponding interface is not used.
This figure shows the undershoot and overshoot voltages at the interfaces of the P1014.
NOTE
1. t
refers to the clock period associated with the respective interface:
CLOCK
2
•
•
•
•
•
For I C and JTAG, t
references SYSCLK.
CLOCK
For DDR, t
references MCLK.
CLOCK
For eTSEC, t
references EC_GTX_CLK125.
CLOCK
For IFC, t
references IFC_CLK.
CLOCK
For SERDES, t
references SDx_REF_CLK.
CLOCK
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
23
Electrical characteristics
X/B/G/L/OVDD + 20ꢀ
X/B/G/L/OVDD + 5ꢀ
X/B/G/L/OVDD
VIH
GND
GND – 0.3 V
VIL
GND – 0.7 V
Not to Exceed 10ꢀ
1
of tCLOCK
Figure 2. Overshoot/Undershoot voltage for BV /MV /LV /OV /XV
IN
IN
IN
IN
IN
The core voltage must always be provided at nominal 1V (see Table 3 for actual recommended core voltage). Voltage to the
processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 3.
The input voltage threshold scales with respect to the associated I/O supply voltage. BV , OV and LV -based receivers
DD
DD
DD
are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR3 SDRAM interface uses a
differential receiver referenced the externally supplied MV signal (nominally set to GV /2). The DDR DQS receivers
REF
DD
cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.
2.1.3
Output driver characteristics
This table provides information on the characteristics of the output driver strengths. The values are preliminary estimates.
Table 4. Output drive capability
Driver Type
IFC, GPIO, USB, eSDHC
Output Impedance ()
Supply Voltage
Note
45
45
45
BVDD = 3.3 V
BVDD = 2.5 V
BVDD = 1.8 V
—
DDR3 signal (Programmable)
20 (full strength)
40 (half strength)
GVDD = 1.5 V DDR3
GVDD = 1.35 V DDR3L
1
TSEC signals
45
45
45
LVDD = 2.5V
OVDD = 3.3 V
OVDD = 3.3 V
—
—
—
DUART, system control, JTAG, SPI
I2C
Note:
1. The drive strength of the DDR3 interface in half-strength mode is at Tj = 105C and at GVDD (min).
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
24
Freescale Semiconductor
Electrical characteristics
2.2
Power sequencing
The P1014 requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These
requirements are as follows for power up:
1.
V
, AV
, AV
AV
SD1_AV , SD2_AV
S1V , S2V , X1V , X2V , BV
,
DD
DD_CORE
DD_DDR,
DD_PLAT,
DD
DD,
DD
DD
DD
DD
DD
LV , OV
.
DD
DD
2. USBV
, GV
DD3_3
DD.
NOTE
POVDD must be stable at 1.5 V prior to initiating fuse programming.
All supplies must be at their stable values within 50 ms from the start of first supply.
Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered
sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step
reach 10% of theirs.
In order to guarantee MCKE low during power-up, the above sequencing for GV is required. If there is no concern about any
DD
of the DDR signals being in an indeterminate state during power-up, then the sequencing for GV is not required.
DD
NOTE
From a system standpoint, if any of the I/O power supplies ramp prior to the V core
DD
supply, the I/Os associated with that I/O supply may drive a logic one or zero during
power-up, and extra current may be drawn by the device.
2.3
Power-down Requirements
The power-down cycle must complete such that power supply values are below 0.4 V before a new power-up cycle can be
started.
2.4
Reset Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements. This table provides the
RESET initialization AC timing specifications.
Table 5. RESET initialization timing specifications
Parameter
Min Max
Unit
Note
Required assertion time of HRESET
600
25
—
3
—
—
1
s
ns
1, 2, 5
Minimum assertion time of TRESET simultaneous to HRESET assertion
Maximum rise/fall time of HRESET
3
—
4
tSYSCLK
tSYSCLK
s
Minimum assertion time for SRESET
—
—
—
PLL input setup time with stable SYSCLK before HRESET negation
25
4
—
4
Input setup time for POR configurations (other than PLL configuration) with respect to negation
of HRESET
tSYSCLK
Input hold time for all POR configurations (including PLL configuration) with respect to
negation of HRESET
2
—
5
tSYSCLK
4
4
Maximum valid-to-high impedance time for actively driven POR configurations with respect to
negation of HRESET
—
tSYSCLK
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
25
Electrical characteristics
Table 5. RESET initialization timing specifications
Parameter
Min Max
Unit
Note
Note:
1. There may be some extra current leakage when driving signals high during this time.
2. Reset assertion timing requirements for DDR3 DRAMs may differ.
3. TRST is an asynchronous level sensitive signal. For guidance on how this requirement can be met, refer to the JTAG signal
termination guidelines in Section 3.10.1, “Termination of unused signals.”
4. SYSCLK is the primary clock input for the P1014.
5. Reset initialization should start only after all power supplies are stable.
This table provides the PLL lock times.
Table 6. PLL lock times
Parameter
Min
Max
Unit
Note
PLL lock times
—
100
s
—
2.5
Power-on ramp rate
This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum
Power-On Ramp Rate is required to avoid falsely triggering the ESD circuitry. This table provides the power supply ramp rate
specifications.
Table 7. Power supply ramp rate
Parameter
Min
Max
Unit
Note
Required ramp rate for all voltage supplies (including OVDD/GVDD/BVDD/SVDD/LVDD, All VDD
supplies, MVREF and all AVDD supplies except USBVDD3_3.)
—
36000 Volts/Sec 1,3
Required ramp rate for USBVDD3_3
—
3300 Volts/Sec
2
Note:
1. Ramp rate is specified as a linear ramp from 10 to 90ꢀ. If non-linear (for example, exponential), the maximum rate of change
from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry.
2. Ramp rate is specified as a linear ramp from 10 to 90ꢀ.
3. Over full recommended operating temperature range. See Table 3.
2.6
Power characteristics
This table shows the power dissipations of the V supply for various operating core complex bus clock (CCB_clk) frequencies
DD
versus the core and DDR clock frequencies. Note that these numbers are based on design estimates only and are preliminary.
More accurate power numbers will be available after the measurement on the silicon is complete.
Table 8. P1014 power dissipation
Core CCB
Frequency Frequency
DDR
Data Rate
(MHz)
Junction
Temperature
(C)
Power
Mode
VDD Core
(V)
Core1 Power
(W)
SVDD
Power (W)
Note
(MHz)
(MHz)
Typical
65
1.04
1.97
2.17
0.20
0.20
0.20
2, 3
5, 7
533
266
667
1.0
Thermal
105
105
Maximum
4, 6, 7
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
26
Freescale Semiconductor
Electrical characteristics
Table 8. P1014 power dissipation (continued)
Core
CCB
DDR
Data Rate
(MHz)
Junction
Temperature
(C)
Power
Mode
VDD Core
(V)
Core1 Power
(W)
SVDD
Power (W)
Frequency Frequency
Note
(MHz)
(MHz)
Typical
65
105
105
65
1.08
2.06
2.27
1.13
2.15
2.37
0.20
0.20
0.20
0.20
0.20
0.20
2, 3
5, 7
667
333
667
800
1.0
1.0
Thermal
Maximum
Typical
4, 6, 7
2, 3
800
400
Thermal
Maximum
Note:
105
105
5, 7
4, 6, 7
1. Combined power of all 1 volt supplies except SVDD with DDR controller/s and all SerDes banks active. Does not include
I/O power.
2. Typical power assumes that Dhrystone is running with an activity factor of 90ꢀ and executing DMA on the platform with
90ꢀ activity factor.
3. Typical power based on nominal processed device.
4. Maximum power assumes that Dhrystone is running with an activity factor of 100ꢀ and executing DMA on the platform at
100ꢀ activity factor.
5. Thermal power assumes a Dhrystone activity factor of 90ꢀ and executing DMA on the platform at 90ꢀ activity factor.
6. Maximum power provided for power supply design sizing.
7. Thermal and maximum power are based on worst case processed device.
2.6.1
I/O DC power supply recommendation
This table provides estimated I/O power numbers for each block: DDR, PCI Express, eLBC, eTSEC, SGMII, eSDHC, USB,
eSPI, DUART, I2C and GPIO.
Table 9. I/O power supply estimated values
Interface
Parameter
Symbol
Typical
Max
Unit
Note
DDR3
(16 bit, w/ ECC)
667 MHz data rate
800 MHz data rate
667 MHz data rate
800 MHz data rate
×1, 2.5 G-baud
×1, 1.25G-baud
3.0G-baud
GVDD (1.5 V)
GVDD (1.5 V)
GVDD (1.35 V)
GVDD (1.35 V)
XVDD (1.0 V)
XVDD (1.0 V)
XVDD (1.0 V)
BVDD (1.8 V)
BVDD (2.5 V)
BVDD (3.3 V)
LVDD (2.5 V)
0.40
0.40
0.45
0.45
W
W
W
W
W
W
W
W
W
W
W
1, 2, 6
1, 2, 6
1,2
DDR3L
(16 bit, w/ ECC)
0.35
0.40
0.35
0.40
1,2
PCI Express
SGMII
SATA
0.02
0.02
1
0.014
0.022
0.017
0.03
0.014
0.022
0.025
0.038
0.063
0.1
1
1
IFC
16-bit, 100MHz
1,3,7
1,3,7
1,3,7
1,3,4,7
0.047
0.075
RGMII
—
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
27
Electrical characteristics
Table 9. I/O power supply estimated values (continued)
Interface
Parameter
Symbol
Typical
Max
Unit
Note
eSDHC
—
—
—
—
—
—
—
—
—
—
—
x8
x8
BVDD (1.8 V)
BVDD (3.3 V)
BVDD (1.8 V)
BVDD (2.5 V)
BVDD (3.3 V)
USBVDD3_3 (3.3V)
OVDD (1.8 V)
OVDD (3.3 V)
OVDD (3.3 V)
OVDD (3.3 V)
LVDD (2.5 V)
0.0042
0.014
0.004
0.008
0.012
0.15
0.0053
0.0175
0.004
0.008
0.012
0.15
W
W
W
W
W
W
W
W
W
W
W
W
W
1,3,7
1,3
USB (ULPI)
1,3
1,3
1,3
USB (PHY)
eSPI
1,3,7
1,3,7
1,3
0.01
0.0125
0.002
0.008
0.005
0.005
0.011
0.009
I2C
0.002
0.006
0.004
0.004
0.009
0.007
DUART
TDM
1,3,7
1,3,7
1,3,7
1,3,5,7
1,3,5,7
IEEE1588
GPIO
OVDD (3.3 V)
LVDD (2.5 V)
Note:
1. The typical values are estimates based on simulations at 65C junction temperature.
2. Typical DDR power numbers are based on one rank DIMM with 40ꢀ utilization.
3. Assuming 15pF total capacitance load per pin.
4. The current values are per each eTSEC used.
5. GPIO are supported on OVDD and LVDD power rails.
6. Maximum DDR power numbers are based on two ranks DIMM with 75ꢀ utilization.
7. The maximum values are estimated and they are based on simulations at 105C junction temperature.
2.7
Input clocks
2.7.1
System clock specifications
This table provides the system clock (SYSCLK) 3.3 V DC specifications.
Table 10. SYSCLK DC electrical characteristics
At recommended operating conditions with OVDD = 3.3 V 165 mV
Parameter
Input high voltage
Symbol
Min
Typical
Max
Unit
Note
VIH
VIL
CIN
IIN
2.0
—
—
—
—
—
7
—
0.8
15
50
V
V
1
1
Input low voltage
Input capacitance
Input current (VIN= 0 V or VIN = VDD)
Note:
pf
—
2
—
A
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 3.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
28
Freescale Semiconductor
Electrical characteristics
This table provides the system clock (SYSCLK) AC timing specifications.
Table 11. SYSCLK AC timing specifications
At recommended operating conditions with OVDD = 3.3 V 165 mV
Parameter/Condition
SYSCLK frequency
Symbol
Min
Typ
Max
Unit
Note
fSYSCLK
64
10
40
1
—
—
—
—
—
—
—
100
15.6
60
MHz
ns
1, 2
1, 2
2
SYSCLK cycle time
tSYSCLK
SYSCLK duty cycle
tKHK/ tSYSCLK
ꢀ
SYSCLK slew rate
—
—
4
V/ns
ps
3
SYSCLK peak period jitter
SYSCLK jitter phase noise at –56 dBc
AC Input Swing Limits at 3.3 V OVDD
Note:
—
—
1.9
150
500
—
—
4
—
kHz
V
VAC
—
1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency does not exceed their
respective maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD/2.
3. Slew rate as measured from 0.3 VAC at the center of peak to peak voltage at clock input.
4. Phase noise is calculated as FFT of TIE jitter.
2.7.2
Spread spectrum sources
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (EMI) by
spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and
government requirements. These clock sources intentionally add long-term jitter in order to diffuse the EMI spectral content.
The jitter specification given in Table 12 considers short-term (cycle-to-cycle) jitter only. The clock generator’s cycle-to-cycle
output jitter should meet the P1014 input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate
concerns. The P1014 is compatible with spread spectrum sources if the recommendations listed in Table 12 are observed.
Table 12. Spread spectrum clock source recommendations
At recommended operating conditions. See Table 3.
Parameter
Min
Max
Unit
Note
Frequency modulation
Frequency spread
Note:
—
—
60
kHz
ꢀ
—
1.0
1, 2
1. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the
minimum and maximum specifications given in Table 78.
2. Maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of the device
CAUTION
The processor’s minimum and maximum SYSCLK, core, and VCO frequencies must not
be exceeded, regardless of the type of clock source. Therefore, systems in which the
processor is operated at its maximum rated e500 core frequency should avoid violating the
stated limits by using down-spreading only.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
29
Electrical characteristics
2.7.3
Real time clock specifications
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then used as an input to the
counters of the PIC and the TimeBase unit of the e500. There is no jitter specification. The minimum pulse width of the RTC
signal should be greater than 2x the period of the CCB clock; that is, minimum clock high time is 2 t
, and minimum clock
CCB
low time is 2 t
. There is no minimum RTC frequency; RTC may be grounded, if not needed.
CCB
2.7.4
eTSEC gigabit reference clock specifications
This table lists the eTSEC gigabit reference clock (TSEC1_GTX_CLK125) DC electrical characteristics for the P1014.
Table 13. eTSEC gigabit reference clock DC electrical characteristics
Parameter
High-level input voltage
Symbol
Min
Max
Unit
Note
VIH
VIL
IIN
1.7
—
—
0.8
40
V
V
1
1
2
Low-level input voltage
Input current (VIN = 0 V or VIN = VDD)
Note:
—
A
1. The max VIH, and min VIL values can be found in Table 3.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 3.
This table provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for the P1014.
Table 14. EC_GTX_CLK125 AC timing specifications
At recommended operating conditions with LVDD = 2.5 0.125 mV
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Note
EC_GTX_CLK125 frequency
EC_GTX_CLK125 cycle time
tG125
tG125
tG125R/tG125F
—
—
—
125
8
—
—
MHz
ns
—
—
1
EC_GTX_CLK rise and fall time
LVDD = 2.5 V
—
ns
0.75
EC_GTX_CLK125 duty cycle
1000Base-T for RGMII
tG125H G125
/t
—
—
ꢀ
2
2
47
—
53
EC_GTX_CLK125 jitter
—
150
ps
Note:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V and from 0.6.
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2ꢀ degradation. The
EC_GTX_CLK125 duty cycle can be loosened from 47ꢀ/53ꢀ as long as the PHY device can tolerate the duty cycle
generated by the eTSEC GTX_CLK. See Section 2.11.1.2, “RGMII AC timing specifications,” for the duty cycle for 10Base-T
and 100Base-T reference clock.
2.7.5
Other input clocks
A description of the overall clocking of this device is available in the P1014 QorIQ Integrated Processor Reference Manual, in
the form of a clock subsystem block diagram. For information about the input clock requirements of other functional blocks
such as SerDes, Ethernet Management, eSDHC, and IFC, see the specific interface section.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
30
Freescale Semiconductor
Electrical characteristics
2.8
DDR3, and DDR3L SDRAM controller
This section describes the DC and AC electrical specifications for the DDR3, and DDR3L SDRAM controller interface. Note
that the required GV (typ) voltage is 1.5 V, and 1.35 V when interfacing to DDR3, or DDR3L SDRAMrespectively.
DD
2.8.1
DDR3, and DDR3L SDRAM interface DC electrical characteristics
This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3
SDRAM.
Table 15. DDR3 SDRAM interface DC electrical characteristics
At recommended operating condition with GVDD = 1.5 V1
Parameter
I/O reference voltage
Symbol
Min
Max
Unit
Note
MVREFn
VIH
0.49 GVDD
MVREFn + 0.100
GND
0.51 GVDD
GVDD
V
V
2, 3, 4
Input high voltage
Input low voltage
I/O leakage current
Note:
5
5
6
VIL
MVREFn – 0.100
50
V
IOZ
–50
A
1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s
voltage supply may or may not be from the same source.
2. MVREFn is expected to be equal to 0.5 GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREFn may not exceed 1ꢀ of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MVREFn with a min value of MVREFn – 0.04 and a max value of MVREFn + 0.04. VTT should track variations in
the DC level of MVREFn.
4. The voltage regulator for MVREFn must meet the specification states in Table 18.
5. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD
.
This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3L
SDRAM.
Table 16. DDR3L SDRAM interface DC electrical characteristics
At recommended operating condition with GVDD = 1.35 V1
Parameter
I/O reference voltage
Symbol
Min
Max
Unit
Note
MVREFn
VIH
0.49 GVDD
0.51 GVDD
V
V
2, 3, 4
5
Input high voltage
MVREFn + 0.09
GVDD
Input low voltage
VIL
GND
—
MVREFn – 0.09
V
5
Output high current (VOUT = 0.641V)
Output low current (VOUT = 0.641 V)
I/O leakage current
IOH
–23.3
—
mA
mA
A
6, 7
6, 7
8
IOL
23.3
–50
IOZ
50
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
31
Electrical characteristics
Table 16. DDR3L SDRAM interface DC electrical characteristics (continued)
At recommended operating condition with GVDD = 1.35 V1
Parameter
Symbol
Min
Max
Unit
Note
Note:
1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s
voltage supply may or may not be from the same source.
2. MVREFn is expected to be equal to 0.5 GVDD and to track GVDD DC variations as measured at the receiver.Peak-to-peak
noise on MVREFn may not exceed the MVREFn DC level by more than 1ꢀ of GVDD (i.e. 13.5 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MVREFn with a min value of MVREFn – 0.04 and a max value of MVREFn + 0.04. VTT should track variations in
the DC level of MVREFn.
4. The voltage regulator for MVREFn must meet the specification states in Table 18.
5. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models.
6. IOH and IOL are measured at GVDD = 1.282 V
7. See the IBIS model for the complete output IV curve characteristics.
8. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD
.
This table provides the DDR controller interface capacitance for DDR3.
Table 17. DDR3 SDRAM capacitance
At recommended operating conditions with GVDD of 1.5 V 5ꢀ for DDR3 or 1.35 V 5ꢀ for DDR3L
Parameter
Symbol
Min
Max
Unit
Note
Input/output capacitance: DQ, DQS, DQS
CIO
6
8
pF
pF
—
—
Delta input/output capacitance: DQ, DQS, DQS
CDIO
—
0.5
This table provides the current draw characteristics for MVREFn.
Table 18. Current draw characteristics for MVREFn
For recommended operating conditions, seeTable 3.
Parameter
Symbol
Min
Max
Unit
Note
Current draw for DDR3 SDRAM for MVREFn
Current draw for DDR3L SDRAM for MVREFn
IMVREFn
IMVREFn
—
—
1250
1150
A
A
—
—
2.8.2
DDR3 and DDR3L SDRAM interface AC timing specifications
This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR controller supports
DDR3 memories. Note that the required GV (typ) voltage is 1.5 V or 1.35 V when interfacing to DDR3 or DDR3L SDRAM
DD
respectively.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
32
Freescale Semiconductor
Electrical characteristics
2.8.2.1
DDR3 and DDR3L SDRAM interface Input AC timing specifications
This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM.
Table 19. DDR3 SDRAM interface input AC timing specifications
At recommended operating conditions with GVDD of 1.5 V 5ꢀ
Parameter
Symbol
Min
Max
Unit
Note
AC input low voltage
AC input high voltage
VILAC
VIHAC
—
MVREFn – 0.175
V
V
—
—
MVREFn + 0.175
—
This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3L SDRAM.
Table 20. DDR3L SDRAM interface Input AC timing specifications
At recommended operating conditions with GVDD of 1.35 V 5ꢀ
Parameter
Symbol
Min
Max
Unit
Note
AC input low voltage
AC input high voltage
VILAC
VIHAC
—
MVREFn – 0.160
V
V
—
—
MVREFn + 0.160
—
This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM.
Table 21. DDR3, and DDR3L SDRAM interface input AC timing specifications
At recommended operating conditions with GVDD of 1.5 V 5ꢀ for DDR3 or 1.35 V 5ꢀ for DDR3L
Parameter
Symbol
Min
Max
Unit
Note
Controller Skew for MDQS—MDQ/MECC
800 MHz data rate
tCISKEW
—
—
ps
1
1
1
3
3
3
–350
–390
—
350
390
—
667 MHz data rate
Tolerated Skew for MDQS—MDQ/MECC
800 MHz data rate
tDISKEW
ps
–275
–360
275
360
667 MHz data rate
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This should be subtracted from the total timing budget.
2. DDR3 only
3. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW
absolute value of tCISKEW
= (T 4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
33
Electrical characteristics
This figure shows the DDR3 SDRAM interface input timing diagram.
MCK[n]
MCK[n]
tMCK
MDQS[n]
tDISKEW
MDQ[x]
D0
D1
tDISKEW
tDISKEW
Figure 3. DDR3 SDRAM interface input timing diagram
2.8.2.2
DDR3 SDRAM interface output AC timing specifications
This table contains the output AC timing targets for the DDR3 and DDR3L SDRAM interface.
Table 22. DDR3 SDRAM interface output AC timing specifications
At recommended operating conditions with GVDD of 1.5 V 5ꢀ for DDR3 or 1.35 V 5ꢀ for DDR3L
Parameter
MCK[n] cycle time
Symbol1
Min
Max
Unit
Note
tMCK
2.5
—
3
ns
ns
2
3
3
3
3
3
3
3
3
3
3
3
3
ADDR/CMD output setup with respect to MCK
800 MHz data rate
tDDKHAS
—
—
—
—
—
—
—
—
—
—
—
—
0.767
0.95
—
667 MHz data rate
ADDR/CMD output hold with respect to MCK
800 MHz data rate
tDDKHAX
tDDKHCS
tDDKHCX
ns
ns
ns
0.767
0.95
—
667 MHz data rate
MCS[n] output setup with respect to MCK
800 MHz data rate
0.767
0.95
—
667 MHz data rate
MCS[n] output hold with respect to MCK
800 MHz data rate
0.767
0.95
667 MHz data rate
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
34
Freescale Semiconductor
Electrical characteristics
Table 22. DDR3 SDRAM interface output AC timing specifications (continued)
At recommended operating conditions with GVDD of 1.5 V 5ꢀ for DDR3 or 1.35 V 5ꢀ for DDR3L
Parameter
MCK to MDQS Skew
Symbol1
Min
Max
Unit
Note
tDDKHMH
—
–0.525
–0.6
—
—
0.525
0.6
ns
4
4
4
5
800 MHz data rate
667 MHz data rate
MDQ/MECC/MDM output setup with respect
to MDQS
tDDKHDS,
tDDKLDS
—
ps
ps
800 MHz data rate
667 MHz data rate
225
325
—
—
—
—
5
5
5
MDQ/MECC/MDM output hold with respect to
MDQS
tDDKHDX,
tDDKLDX
800 MHz data rate
667 MHz data rate
MDQS preamble
MDQS postamble
Note:
225
—
—
5
5
325
tDDKHMP
tDDKHME
0.9 tMCK
0.4 tMCK
—
ns
ns
—
—
0.6 tMCK
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK and MDQS/MDQS referenced measurements are made from the crossing of the two signals.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from
the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of
the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay
as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two
parameters have been set to the same adjustment value. See the P1014 QorIQ Integrated Processor Reference Manual for
a description and explanation of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
NOTE
For the ADDR/CMD setup and hold specifications in Table 22, it is assumed that the clock
control register is set to adjust the memory clocks by ½ applied cycle.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
35
Electrical characteristics
This figure shows theDDR3 SDRAM interface output timing for the MCK to MDQS skew measurement (t
).
DDKHMH
MCK[n]
MCK[n]
tMCK
tDDKHMHmax) = 0.6 ns or 0.375 n
s
MDQS
MDQS
tDDKHMH(min) = –0.6 ns or –0.375 ns
Figure 4. t
timing diagram
DDKHMH
This figure shows the DDR3 SDRAM output timing diagram.
MCK
MCK
tMCK
tDDKHAS, tDDKHCS
tDDKHAX, tDDKHCX
ADDR/CMD
Write A0
tDDKHMP
NOOP
tDDKHMH
MDQS[n]
MDQ[x]
tDDKHME
tDDKHDS
tDDKLDS
D0
D1
tDDKLDX
tDDKHDX
Figure 5. DDR3 output timing diagram
This figure provides the AC test load for the DDR3 controller bus.
Output
GVDD/2
Z0 = 50
RL = 50
Figure 6. DDR3 controller bus AC test load
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
36
Freescale Semiconductor
Electrical characteristics
2.8.2.3
DDR3 and DDR3L SDRAM differential timing specifications
This section describes the DC and AC differential timing specifications for the DDR3 SDRAM controller interface. This figure
shows the differential timing specification.
GVDD
VTR
GVDD/2
VOX or VIX
VCP
GND
Figure 7. DDR3, and DDR3L SDRAM differential timing specifications
NOTE
VTR specifies the true input signal (such as MCK or MDQS) and VCP is the
complementary input signal (such as MCK or MDQS).
This table provides the DDR3 differential specifications for the differential signals MDQS/MDQS and MCK/MCK.
Table 23. DDR3 SDRAM differential electrical characteristics
Parameter
Symbol
Min
Max
Unit
Note
Input AC Differential Cross-Point Voltage
Output AC Differential Cross-Point Voltage
Note:
VIXAC
0.5 GVDD – 0.150 0.5 GVDD + 0.150
0.5 GVDD – 0.115 0.5 GVDD + 0.115
V
V
1
1
VOXAC
1. I/O drivers are calibrated before making measurements.
This table provides the DDR3 differential specifications for the differential signals MDQS/MDQS and MCK/MCK.
Table 24. DDR3L SDRAM differential electrical characteristics
Parameter
Symbol
Min
Max
Unit
Note
Input AC Differential Cross-Point Voltage
Output AC Differential Cross-Point Voltage
Note:
VIXAC
0.5 GVDD – 0.135 0.5 GVDD + 0.135
0.5 GVDD – 0.105 0.5 GVDD + 0.105
V
V
1
1
VOXAC
1. I/O drivers are calibrated before making measurements.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
37
Electrical characteristics
2.9
eSPI
This section describes the DC and AC electrical specifications for the SPI of the P1014.
2.9.1
SPI DC electrical characteristics
This table provides the DC electrical characteristics for the device SPI.
Table 25. SPI DC Electrical characteristics
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
Input low voltage
VIH
VIL
2.0
—
—
0.8
10
V
V
1
1
Input current (0 V VIN CVDD
)
IIN
—
A
V
2
Output high voltage (IOH = –6.0 mA)
Output low voltage (IOL = 6.0mA)
Output low voltage (IOL = 3.2mA)
Note:
VOH
VOL
2.4
—
—
—
—
—
0.5
0.4
V
V
—
V
OL
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
2.9.2
eSPI AC timing specifications
This table provides the SPI input and output AC timing specifications.
Table 26. SPI AC timing specifications
1
For recommended operating conditions, see Table 3.
Characteristic
Symbol
Min
Max
Unit
Note
SPI clock (SPI_CLK) clock period
tSPK
10
—
—
ns
ns
—
SPI outputs—Master data (internal clock) hold time
tNIKHOX
0.5+(tIPSPI
xSPMODE
[HO_ADJ])
2, 3
SPI outputs—Master data (internal clock) delay
tNIKHOV
—
2.5+(tIPSPI
x
ns
2, 3
SPMODE
[HO_ADJ])
SPI_CS outputs—Master data (internal clock) hold time
SPI_CS outputs—Master data (internal clock) delay
SPI inputs—Master data (internal clock) input setup time
SPI inputs—Master data (internal clock) input hold time
tNIKHOX2
tNIKHOV2
tNIIVKH
0
—
5
—
6.0
—
ns
ns
ns
ns
2
2
—
—
tNIIXKH
0
—
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
38
Freescale Semiconductor
Electrical characteristics
1
Table 26. SPI AC timing specifications (continued)
For recommended operating conditions, see Table 3.
Characteristic
Symbol
Min
Max
Unit
Note
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI
outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are
valid (V).
2. Output specifications are measured from the 50ꢀ level of the rising edge of CLKIN to the 50ꢀ level of the signal. Timings
are measured at the pin.
3. tIPSPI represents the clock period of the clock on which eSPI block is running. In P1010/14 eSPI runs on CCB/2 freq.
This figure provides the AC test load for the SPI.
Output
OVDD/2
Z0 = 50
RL = 50
Figure 8. SPI AC Test Load
This figure represents the AC timing, from Table 26, in master mode (internal clock). Note that although the specifications
generally refer to the rising edge of the clock, Figure 8 also applies when the falling edge is the active edge. Also, note that the
clock edge is selectable on SPI.
SPICLK (output)1
tNIIXKH
tNIIVKH
Input Signals:
SPIMISO
tNIKHOX
tNIKHOV
Output Signals:
SPIMOSI
tNIKHOX2
tNIKHOV2
Output Signals:
SPI_CS_01
Note:
1
A part of SPICLK has been shown as dotted because SPICLK appears on the interface only after CS assertion.
Figure 9. SPI AC timing in master mode (internal clock) diagram
2.10 DUART
This section describes the DC and AC electrical specifications for the DUART interface of the P1014.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
39
Electrical characteristics
2.10.1 DUART DC electrical characteristics
This table provides the DC electrical characteristics for the DUART interface.
Table 27. DUART DC electrical characteristics
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
Input low voltage
VIH
VIL
2
—
—
2.4
—
—
0.8
40
—
V
V
1
1
Input current (OVIN = 0 V or OVIN = OVDD
)
IIN
A
V
2
Output high voltage (OVDD = mn, IOH = –mA)
Output low voltage (OVDD = min, IOL = 2 mA)
Note:
VOH
VOL
—
—
0.4
V
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Figure 3.
2. The symbol OVIN represents the input voltage of the supply. It is referenced in Figure 3.
2.10.2 DUART AC electrical specifications
This table provides the AC timing parameters for the DUART interface.
Table 28. DUART AC timing specifications
Parameter
Minimum baud rate
Value
Unit
Note
CCB clock/1,048,576
CCB clock/16
16
baud
baud
—
1
2
3
Maximum baud rate
Oversample rate
Note:
1. CCB clock refers to the platform clock.
2. Actual attainable baud rate is limited by the latency of interrupt processing.
3. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the
start bit. Subsequent bit values are sampled each 16th sample.
2.11 Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
This section provides the AC and DC electrical characteristics for enhanced three-speed Ethernet10/100/1000 controller and
MII management.
2.11.1 RGMII interface electrical specifications
This section provides AC and DC electrical characteristics of RGMII interface for eTSEC.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
40
Freescale Semiconductor
Electrical characteristics
2.11.1.1 RGMII DC electrical characteristics
This table shows the RGMII DC electrical characteristics when operating from a 2.5-V supply.
Table 29. RGMII DC electrical characteristics (2.5 V)
At recommended operating conditions with LVDD = 2.5 V
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
Input low voltage
VIH
VIL
IIH
1.70
—
—
0.70
V
V
—
—
—
1
Input high current (VIN = LVDD
Input low current (VIN = GND)
)
—
10
A
A
V
IIL
–15
—
Output high voltage (LVDD = min, IOH = –1.0 mA)
Output low voltage (LVDD = min, IOL = 1.0 mA)
Note:
VOH
VOL
2.00
LVDD + 0.3
0.40
—
—
GND– 0.3
V
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol VIN, in this case, represents the LVIN symbols referenced in Table 3.
2.11.1.2 RGMII AC timing specifications
This table presents the RGMII AC timing specifications.
Table 30. RGMII AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol1
Min
Typ
Max
Unit
Note
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver)
Clock period duration
tSKRGT_TX
tSKRGT_RX
tRGT
–500
1.0
7.2
40
0
500
2.6
8.8
60
ps
ns
ns
ꢀ
5
2
—
8.0
50
50
—
—
3
Duty cycle for 10BASE-T and 100BASE-TX
Duty cycle for Gigabit
tRGTH RGT
tRGTH/tRGT
tRGTR
tRGTF
/t
3, 4
—
—
—
45
55
ꢀ
Rise time (20ꢀ–80ꢀ)
—
0.75
0.75
ns
ns
Fall time (20ꢀ–80ꢀ)
—
Note:
1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII
and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing
skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns
is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their chip.
If so, additional PCB delay is probably not needed.
3. For 10 and 100 Mbps, tRGT scales to 400 ns 40 ns and 40 ns 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains
as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
5. The frequency of RX_CLK should not exceed the frequency of GTX_CLK125 by more than 300 ppm.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
41
Electrical characteristics
This figure shows the RGMII and RTBI AC timing and multiplexing diagrams.
tRGT
tRGTH
GTX_CLK
(At MAC, output)
tSKRGT_TX
tSKRGT_TX
TXD[8:5][3:0]
TXD[7:4][3:0]
TXD[8:5]
TXD[7:4]
TXD[3:0]
(At MAC, output)
TXD[9]
TXERR
TXD[4]
TXEN
TX_CTL
(At MAC, output)
PHY equivalent to t
PHY equivalent to t
SKRGT_RX
SKRGT_RX
TX_CLK
(At PHY, input)
t
RGT
tRGTH
RX_CLK
(At PHY, output)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[7:4]
RXD[3:0]
PHY equivalent to t
(At PHY, output)
SKRGT_TX
PHY equivalent to t
SKRGT_TX
RXD[9]
RXERR
RXD[4]
RXDV
RX_CTL
(At PHY, output)
tSKRGT_RX
tSKRGT_RX
RX_CLK
(At MAC, input)
Figure 10. RGMII and RTBI AC timing and multiplexing diagrams
WARNING
Freescale guarantees timings generated from the MAC. Board designers must ensure delays
needed at the PHY or the MAC.
2.11.2 SGMII Interface electrical characteristics
Each SGMII port features a 4-wire AC-Coupled serial link from the dedicated SerDes interface of P1014, as shown in Figure 11,
where C is the external (on board) AC-Coupled capacitor. Each output pin of the SerDes transmitter differential pair features
TX
50-output impedance. Each input of the SerDes receiver differential pair features 50- on-die termination to SGND_SRDS.
The reference circuit of the SerDes transmitter and receiver is shown in Figure 42.
2.11.2.1 SGMII DC electrical characteristics
This section discusses the electrical characteristics for the SGMII interface.
2.11.2.1.1
DC requirements for SGMII SD_REF_CLK and SD_REF_CLK
The characteristics and DC requirements of the separate SerDes reference clock are described in Section 2.20.2.2, “DC level
requirement for SerDes reference clocks.”
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
42
Freescale Semiconductor
Electrical characteristics
2.11.2.1.2
SGMII transmit DC Timing specifications
This table describes the SGMII SerDes transmitter AC-Coupled DC electrical characteristics. Transmitter DC characteristics
are measured at the transmitter outputs (SDn_TX[n] and SDn_TX[n]), as shown in Figure 11.
Table 31. SGMII DC transmitter electrical characteristics
For recommended operating conditions, see Table 3.
Symbo
l
Parameter
Min
Typ
Max
Unit
Note
Output high voltage
VOH
—
—
XVDD_SRDS2-Typ/2+ mV
|VOD -max/2
1
|
Output low voltage
VOL
XVDD_SRDS2-Typ/2
—
—
mV
1
– |VOD -max/2
|
Output differential voltage2, 3, 4 |VOD
|
304
279
254
229
202
178
152
40
475
436
396
357
316
277
237
50
689
632
574
518
459
402
344
60
mV Equalization setting: 1.0x
Equalization setting: 1.09x
Equalization setting: 1.2x
Equalization setting: 1.33x
Equalization setting: 1.5x
Equalization setting: 1.71x
Equalization setting: 2.0x
Output impedance
(single-ended)
RO
—
Note:
1. This does not align to DC-coupled SGMII.
2. |VOD| = |VSD2_TXn – VSD2_TXn|. |VOD| is also referred as output differential peak voltage. VTX-DIFFp-p = 2*|VOD .
|
3. The |VOD| value shown in the table assumes the following transmit equalization setting in the XMITEQAB (for SerDes
lanes A and B) or XMITEQEF (for SerDes lanes E and E) bit field of P1014’s SerDes 2 Control Register:
4. The MSB (bit 0) of the above bit field is set to zero (selecting the full VDD-DIFF-p-p amplitude - power up default);
5. The LSB (bit [1:3]) of the above bit field is set based on the equalization setting shown in table.
6. The |VOD| value shown in the Typ column is based on the condition of XVDD_SRDS2-Typ=1.0V, no common mode offset
variation (VOS =500 mV), SerDes transmitter is terminated with 100- differential load between SD_TX[n] and SD_TX[n].
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
43
Electrical characteristics
SD_TX
SD_RX
SD_RX
50
50
CTX
50
50
Receiver
Transmitter
CTX
SD_TX
SD_RX
P1014 SGMII
SerDes Interface
CTX
SD_TX
50
50
50
Receiver
Transmitter
50
CTX
SD_RX
SD_TX
Figure 11. 4-Wire AC-coupled SGMII serial link connection example
P1014 SGMII
SerDes Interface
SD_TXn
50
50
50
Transmitter
Vos
VOD
50
SD_TXn
Figure 12. SGMII transmitter DC measurement circuit
2.11.2.1.3
SGMII DC receiver timing specification
This table lists the SGMII DC receiver electrical characteristics. Source synchronous clocking is not supported. The clock is
recovered from the data.
5
Table 32. SGMII DC receiver electrical characteristics
For recommended operating conditions, see Table 3.
Parameter
DC Input voltage range
Symbol
Min
Typ
Max
Unit
Note
—
N/A
—
1
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
44
Freescale Semiconductor
Electrical characteristics
Table 32. SGMII DC receiver electrical characteristics (continued)
5
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Input differential voltage
LSTS = 001
LSTS = 100
LSTS = 001
LSTS = 100
VRX_DIFFp-p
100
175
30
—
—
—
—
—
1200
mV
2, 4
Loss of signal threshold
VLOS
100
175
120
mV
3, 4
—
65
Receiver differential input impedance
ZRX_DIFF
80
Note:
1. Input must be externally AC-coupled.
2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
3. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in PCI Express. See
Section Table 64., “PCI Express (2.5 Gb/s) differential receiver (RX) input DC specifications section for further explanation.
4. The LSTS shown in the table refers to the EIC2[0:2] or EIC3[0:2] bit field of P1014’s SerDes Control Register.
5. The supply voltage is 1 V.
2.11.2.2 SGMII AC timing specifications
This section describes the AC timing specifications for the SGMII interface.
2.11.2.2.1
AC requirements for SGMII SD_REF_CLK and SD_REF_CLK
Note that the SGMII clock requirements for SD_REF_CLK and SD_REF_CLK are intended to be used within the clocking
guidelines specified by Section 2.20.2.3, “AC requirements for SerDes reference clocks.”
2.11.2.2.2
SGMII transmit AC timing specifications
This table provides the SGMII transmit AC timing specifications. A source synchronous clock is not supported. The AC timing
specifications do not include RefClk jitter
Table 33. SGMII Transmit AC Timing Specifications
At recommended operating conditions with XVDD_SRDS = 1V 50mV
Parameter
Deterministic Jitter
Symbol
Min
Typ
Max
Unit
Note
JD
JT
—
—
—
—
0.17
0.35
UI p-p
UI p-p
ps
—
—
—
3
Total Jitter
Unit Interval
UI
799.92
5
800
100
800.08
200
AC coupling capacitor
CTX
nF
Note:
1. Each UI is 800 ps 100 ppm.
2. See Figure 14 for single frequency sinusoidal jitter limits.
3. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter outputs.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
45
Electrical characteristics
2.11.2.2.3
SGMII AC measurement details
Transmitter and receiver AC characteristics are measured at the transmitter outputs (SD_TX[n] and SD_TX[n]) or at the receiver
inputs (SD_RX[n] and SD_RX[n]) as depicted in Figure 13, respectively.
Figure 13. SGMII AC test/measurement load
2.11.2.2.4
SGMII receiver AC timing specifications
This table provides the SGMII receive AC timing specifications. The AC timing specifications do not include RefClk jitter.
Source synchronous clocking is not supported. Clock is recovered from the data.
Table 34. SGMII receive AC timing specifications
At recommended operating conditions with XVDD_SRDS2 = 1 V 50 mV
Parameter
Deterministic jitter tolerance
Symbol
Min
Typ
Max
Unit
Note
JD
JDR
JT
0.37
0.55
0.65
—
—
—
—
—
UI p-p
UI p-p
UI p-p
—
1, 2
1, 2
1, 2
—
Combined deterministic and random jitter tolerance
Total jitter tolerance
Bit error ratio
—
—
BER
UI
—
10-12
800.08
Unit interval
799.92
800
ps
3
Note:
1. Measured at receiver
2. See RapidIO™ 1x/4x LP Serial Physical Layer Specification for interpretation of jitter specifications.
3. Each UI is 800 ps 100 ppm.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
46
Freescale Semiconductor
Electrical characteristics
The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of this figure.
8.5 UI p-p
Sinusoidal
Jitter
Amplitude
0.10 UI p-p
22.1 kHz
Frequency
1.875 MHz
20 MHz
Figure 14. Single frequency sinusoidal jitter limits
2.11.3 MII management
This section provides electrical and thermal design recommendations for successful application of the P1014.
2.11.3.1 MII management DC electrical characteristics
The MDC and MDIO are defined to operate at a supply voltage of 2.5 V. The DC electrical characteristics for MDIO and MDC
are provided in this table.
Table 35. MII management DC electrical characteristics
At recommended operating conditions with LVDD = 2.5 V
Parameter
Symbol
Min
Max
Unit
Note
Output high voltage
VOH
2.00
LVDD + 0.3
V
—
(LVDD = Min, IOH = –1.0 mA)
Output low voltage
VOL
GND– 0.3
0.40
V
—
(LVDD = Min, IOL = 1.0 mA)
Input high voltage
Input low voltage
Input high current
VIH
VIL
IIH
1.70
–0.3
—
LVDD + 0.3
0.70
V
V
—
—
10
A
1, 2
(VIN = LVDD
)
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
47
Electrical characteristics
Table 35. MII management DC electrical characteristics
At recommended operating conditions with LVDD = 2.5 V
Parameter
Symbol
Min
Max
Unit
Note
Input low current
(VIN = GND)
IIL
–15
—
A
—
Note:
1. EC1_MDC and EC1_MDIO operate on LVDD
.
2. In this case, the symbol VIN represents the LVIN and TVIN symbols referenced in Table 3.
2.11.3.1.1
MII management AC electrical specifications
This table provides the MII management AC timing specifications.
Table 36. MII Management AC Timing Specifications
Parameter/Condition
MDC frequency
Symbol
Min
Typ
Max
Unit
Note
fMDC
tMDC
—
2.5
400
—
—
MHz
ns
2
—
MDC period
—
—
MDC clock pulse width high
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
Note:
tMDCH
32
—
ns
—
tMDKHDX
tMDDVKH
tMDDXKH
(16*tplb_clk) – 3
—
(16*tplb_clk) + 3
ns
3, 4
—
5
0
—
—
—
ns
—
ns
—
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes
management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or
data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D)
reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the platform clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency
of the MgmtClk Clock EC_MDC).
3. This parameter is dependent on the platform clock frequency. The delay is equal to 16 platform clock periods 3 ns. For
example, with a platform clock of 333 MHz, the min/max delay is 48 ns 3 ns. Similarly, if the platform clock is 400 MHz,
the min/max delay is 40 ns 3 ns.
4. tplb_clk is the platform (CCB) clock.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
48
Freescale Semiconductor
Electrical characteristics
This figure shows the MII management interface timing diagram.
tMDC
tMDCR
MDC
tMDCF
tMDCH
MDIO
(Input)
tMDDVKH
tMDDXKH
MDIO
(Output)
tMDKHDX
Figure 15. MII management interface timing diagram
2.11.4 eTSEC IEEE Std 1588™ timing specifications
2.11.4.1 eTSEC IEEE Std 1588 DC electrical characteristics
This table shows the IEEE 1588 DC electrical characteristics when operating at LV = 2.5 V supply.
DD
Table 37. eTSEC IEEE 1588 DC Electrical Characteristics (LV = 2.5 V)
DD
For recommended operating conditions with LVDD = 2.5 V
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
Input low voltage
VIH
VIL
1.70
—
—
0.70
40
V
V
—
—
2
Input current (LVIN = 0 V or LVIN = LVDD
)
IIH
—
A
V
Output high voltage (LVDD = min, IOH = –1.0 mA)
Output low voltage (LVDD = min, IOL = 1.0 mA)
Note:
VOH
VOL
2.00
—
—
—
—
0.40
V
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3..
2. The symbol VIN, in this case, represents the LVIN symbols referenced in Table 2 and Table 3..
2.11.5 eTSEC IEEE 1588 AC specifications
This table provides the IEEE 1588 AC timing specifications.
Table 38. eTSEC IEEE 1588 AC timing specifications
For recommended operating conditions, see Table 3.
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Note
TSEC_1588_CLK clock period
TSEC_1588_CLK duty cycle
tT1588CLK
tCCB/2
40
—
TRX_CLK*7
60
ns
ꢀ
1, 3, 4
—
tT1588CLKH
/tT1588CLK
50
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
49
Electrical characteristics
Table 38. eTSEC IEEE 1588 AC timing specifications (continued)
For recommended operating conditions, see Table 3.
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Note
TSEC_1588_CLK peak-to-peak jitter
Rise time eTSEC_1588_CLK (20ꢀ–80ꢀ)
Fall time eTSEC_1588_CLK (80ꢀ–20ꢀ)
TSEC_1588_CLK_OUT clock period
TSEC_1588_CLK_OUT duty cycle
tT1588CLKINJ
tT1588CLKINR
tT1588CLKINF
tT1588CLKOUT
—
—
—
—
—
50
250
2.0
2.0
—
ps
ns
ns
ns
ꢀ
—
—
—
—
—
1.0
1.0
2 x tT1588CLK
30
tT1588CLKOTH
/tT1588CLKOUT
70
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_IN pulse width
Note:
tT1588OV
0.5
—
—
3.0
—
ns
ns
—
2
tT1588TRIGH
2*tT1588CLK_MAX
1. TRX_CLK is the max clock period of eTSEC receiving clock selected by TMR_CTRL[CKSEL]. See the P1014 QorIQ
Integrated Processor Reference Manual for a description of TMR_CTRL registers.
2. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the P1014 QorIQ
Integrated Processor Reference Manual for a description of TMR_CTRL registers.
3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For
example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK is 2800, 280, and 56 ns respectively.
4. tCCB denotes the clock period of system clock (CCB).
This figure shows the data and command output AC timing diagram.
NOTE
In the following figure, the output delay is counted by starting at the rising edge if
t
is non-inverting. Otherwise, it is counted starting at the falling edge.
T1588CLKOUT
tT1588CLKOUT
tT1588CLKOTH
TSEC_1588_CLK_OUT
tT1588OV
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_OUT
Figure 16. eTSEC IEEE 1588 output AC timing
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
50
Freescale Semiconductor
Electrical characteristics
This figure shows the data and command input AC timing diagram.
tT1588CLK
tT1588CLKH
TSEC_1588_CLK
TSEC_1588_TRIG_IN
tT1588TRIGH
Figure 17. eTSEC IEEE 1588 input AC timing
2.12 USB
This section provides the AC and DC electrical specifications for the USB interface.
2.12.1 USB DC electrical characteristics
This table provides the DC electrical characteristics for the ULPI interface when operating at BV = 3.3 V.
DD
Table 39. USB DC electrical characteristics (3.3 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
Input low voltage
VIH
VIL
2
—
0.8
40
—
V
V
1
1
—
—
2.8
—
Input current (BVIN = 0 V or BVIN = BVDD
)
IIN
A
V
2
Output high voltage (BVDD = min, IOH = –2 mA)
Output low voltage (BVDD = min, IOL = 2 mA)
Note:
VOH
VOL
—
—
0.3
V
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
2. The symbol BVIN represents the input voltage of the supply. It is referenced in Table 3.
This table provides the DC electrical characteristics for the ULPI interface when operating at BV = 2.5 V.
DD
Table 40. USB DC electrical characteristics (2.5 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
Input low voltage
VIH
VIL
1.7
—
—
0.7
40
—
V
V
1
1
Input current (BVIN = 0 V or BVIN = BVDD
)
IIN
—
A
V
2
Output high voltage (BVDD = min, IOH = –2 mA)
VOH
2.0
—
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
51
Electrical characteristics
Table 40. USB DC electrical characteristics (2.5 V) (continued)
For recommended operating conditions, see Table 3.
Output low voltage (BVDD = min, IOL = 2 mA)
VOL
—
0.4
V
—
Note:
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
2. The symbol BVIN represents the input voltage of the supply. It is referenced in Table 3.
This table provides the DC electrical characteristics for the ULPI interface when operating at BV = 1.8 V.
DD
Table 41. USB DC Electrical characteristics (1.8 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
Input low voltage
VIH
VIL
1.25
—
—
0.6
40
—
V
V
1
1
Input current (BVIN = 0 V or BVIN = BVDD
)
IIN
—
A
V
2
Output high voltage (BVDD = min, IOH = –2 mA)
Output low voltage (BVDD = min, IOL = 2 mA)
Note:
VOH
VOL
1.35
—
—
—
0.4
V
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
2. The symbol BVIN represents the input voltage of the supply. It is referenced in Table 3.
2.12.2 USB AC electrical specifications
This table describes the general timing parameters of the USB interface of the device.
6
Table 42. USB general timing parameters (ULPI Mode Only)
For recommended operating conditions, see Table 3.
Parameter
USB clock cycle time
Symbol1
Min
Max
Unit
Note
tUSCK
tUSIVKH
tUSIXKH
tUSKHOV
tUSKHOX
15
4
—
—
—
7
ns
ns
ns
ns
ns
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
Input setup to USB clock—all inputs
input hold to USB clock—all inputs
USB clock to output valid—all outputs
Output hold from USB clock—all outputs
1
—
2
—
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
52
Freescale Semiconductor
Electrical characteristics
6 (continued)
Table 42. USB general timing parameters (ULPI Mode Only)
For recommended operating conditions, see Table 3.
Parameter
Symbol1
Min
Max
Unit
Note
Note:
1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB
timing (US) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also,
tUSKHOX symbolizes USB timing (US) for the USB clock reference (K) to go high (H) with respect to the output (O) going
invalid (X) or output hold time.
2. All timings are in reference to USB clock.
3. All signals are measured from BVDD/2 of the rising edge of the USB clock to 0.4 OVDD of the signal in question for 3.3
V signaling levels.
4. Input timings are measured at the pin.
5. For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered
through the component pin is less than or equal to that of the leakage current specification.
6. When switching the data pins from outputs to inputs using the USBn_DIR pin, the output timings will be violated on that
cycle because the output buffers are tristated asynchronously. This should not be a problem, because the PHY should
not be functionally looking at these signals on that cycle as per ULPI specifications.
These two figures provide the USB AC test load and signals, respectively.
Output
OVDD/2
Z0 = 50
RL = 50
Figure 18. USB AC test load
USB_CLK
tUSIXKH
tUSIVKH
Input Signals
tUSKHOV
tUSKHOX
Output Signals:
Figure 19. USB signals
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
53
Electrical characteristics
This table provides the USB clock input (USB_CLK) AC timing specifications.
Table 43. USB_CLK AC timing specifications
Parameter/Condition
Conditions
Symbol
Min
Typ
Max
Unit
Frequency range
Steady state
fUSB_CLK_IN
tCLK_TOL
tCLK_DUTY
tCLK_PJ
59.97
–0.05
40
60
0
60.03
0.05
60
MHz
ꢀ
Clock frequency tolerance
—
Reference clock duty cycle Measured at 1.6 V
50
—
ꢀ
Total input jitter/time interval Peak-to-peak value measured with a
—
200
ps
error
second order high-pass filter of 500 kHz
bandwidth
2.12.3 On-chip USB PHY
This section describes the AC electrical specifications for the on-chip USB PHY. See Chapter 7 in the USB Specifications, Rev.
2, for more information.
This table provides the USB clock input (USBPHY_CLK) AC timing specifications.
Table 44. USBPHY_CLK AC Timing specifications
For recommended operating conditions, see Table 3.
Parameter
Conditions
Symbol1
Min
Max
Unit Note
Frequency range
Steady state
fUSB_CLK_IN
tUSRF
24
—
24
MHz
ns
—
—
—
—
—
Rise/Fall time
—
—
6
+0.005
60
Clock frequency tolerance
tCLK_TOL
tCLK_DUTY
tCLK_PJ
–0.005
40
ꢀ
Reference clock duty cycle Measured at 1.6 V
ꢀ
Total input jitter/time
interval error
RMS value measured with a second order
high-pass filter of 500 kHz bandwidth
—
5
ps
2.12.4 IBIAS_REXT filter
Following filter circuit must be implemented on IBIAS_REXT pin.
Filter component should be placed as much close to SoC pin as possible.
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Electrical characteristics
P1010/14
IBIAS_REXT
100
10k
100nf
VSS
Figure 20. IBIAS_REXT filter circuit
2.12.5 Threshold detect increase
Following register programming should be performed during USB PHY initialization
1. Read S1[26:31]
2. Set C1[8] and C1[9] to '1'
3. Write C2[11] = 1 and C2[13:15] = S1[29:31] and C2[16:18] = S1[26:28]
where C1 is the register at (CCSRBAR + 0xe5000), C2 is the register at (CCSRBAR + 0xe5004) and S1 is the register at
(CCSRBAR + 0xe5014).
2.13 Integrated flash controller
This section describes the DC and AC electrical specifications for the integrated flash controller.
2.13.1 Integrated flash controller DC electrical characteristics
This table provides the DC electrical characteristics for the integrated flash controller when operating at BV = 3.3 V.
DD
Table 45. Integrated flash controller DC electrical characteristics (3.3 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
Input low voltage
Input current
VIH
VIL
IIN
2
—
0.8
40
V
V
1
1
2
—
—
A
(VIN = 0 V or VIN = BVDD)
Output high voltage
(BVDD = min, IOH = –1 mA)
VOH
2.8
—
—
V
V
—
—
Output low voltage
VOL
0.4
(BVDD = min, IOH = 2 mA)
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Freescale Semiconductor
55
Electrical characteristics
Table 45. Integrated flash controller DC electrical characteristics (3.3 V) (continued)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Note:
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
This table provides the DC electrical characteristics for the integrated flash controller when operating at BV = 2.5 V.
DD
Table 46. Integrated flash controller DC electrical characteristics (2.5 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
Input low voltage
Input current
VIH
VIL
IIN
1.7
—
—
0.7
40
V
V
1
1
2
—
A
(VIN = 0 V or VIN = BVDD)
Output high voltage
(BVDD = min, IOH = –1 mA)
VOH
2.0
—
—
V
V
—
—
Output low voltage
VOL
0.4
(BVDD = min, IOL = 1 mA)
Note:
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
This table provides the DC electrical characteristics for the integrated flash controller when operating at BV = 1.8 V.
DD
Table 47. Integrated Flash controller DC electrical characteristics (1.8 V)
For recommended operating conditions, see Table 3.
Parameter
Input high voltage
Symbol
Min
Max
Unit
Note
VIH
VIL
IIN
1.25
—
—
0.6
40
V
V
1
1
2
Input low voltage
Input current
—
A
(VIN = 0 V or VIN = BVDD
)
Output high voltage
(BVDD = min, IOH = –0.5 mA)
VOH
1.35
—
—
V
V
—
—
Output low voltage
VOL
0.4
(BVDD = min, IOL = 0.5 mA)
Note:
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
2.13.2 Integrated flash controller AC Timing specifications
This section describes the AC timing specifications for the integrated flash controller.
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56
Freescale Semiconductor
Electrical characteristics
2.13.2.1 Integrated flash controller AC timing specifications
All output signal timings are relative to the falling edge of any IFC_CLK. The external circuit must use the rising edge of the
IFC_CLKs to latch the data. All input timings are relative to the rising edge of IFC_CLKs.
This table describes the timing specifications of the integrated flash controller interface.
Table 48. Integrated Flash controller timing specifications (BV = 3.3 V, 2.5 V, and 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol1
Min
Max Unit Note
IFC_CLK cycle time
IFC_CLK duty cycle
IFC_CLK[n] skew to IFC_CLK[m]
Input setup
tIBK
10
45
—
4
—
55
150
—
—
1.5
1
ns
ꢀ
—
—
2
tIBKH/tIBK
tIBKSKEW
tIBIVKH
ps
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
5
Input hold
tIBIXKH
1
Output delay (Except AVD)
Output delay (For AVD)
Output hold
tIBKLOV1
tIBKLOV2
tIBKLOX
tIBKLOZ
tIBONOT
—
—
–2
—
0.5
—
2
IFC_CLK to output high impedance for AD
AVD output negation to AD output transition (LATCH hold time)
Note:
3
—
4
1. All signals are measured from BVDD/2 of the rising/falling edge of IFC_CLK to BVDD/2 of the signal in question.
2. Skew is measured between different IFC_CLK signals at BVDD/2.
3. For the purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. tIBONOT is a measurement of the maximum time between the negation of AVD and any change in AD when
FTIM0_CSn[TEAHC]=0.
5. Here the negative sign means output transit happens earlier than the falling edge of IFC_CLK.
2.13.2.2 Test condition
This figure provides the AC test load for the integrated flash controller.
BVDD/2
Output
Z0 = 50
RL = 50
Figure 21. Integrated flash controller AC Test load
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Freescale Semiconductor
57
Electrical characteristics
This figure shows the AC timing diagram.
IFC_CLK[m]
Input Signals
tIBIXKH
tIBIVKH
tIBKLOV1
tIBKLOX
Output Signals
(Except AVD)
AD
(address phase)
tIBKLOV2
tIBONOT
AVD
tIBKLOZ
tIBKLOX
AD
(data phase)
Figure 22. Integrated flash controller signals
This figure applies to all the controllers that IFC supports.
For input signals, the AC timing data is used directly for all controllers. For output signals, each type of controller provides its
own unique method to control the signal timing. The final signal delay value for output signals is the programmed delay plus
the AC timing delay.
This figure shows how the AC timing diagram applies to GPCM. The same principle also applies to other controllers of IFC.
NOTE
In the following figure, t , t , t , t , t , t , t , t are programmable. See the
aco rad eahc eadc acse cs ch wp
P1014 reference manual.
For output signals, each type of controller provides its own unique method to control the
signal timing. The final signal delay value for output signals is the programmed delay plus
the AC timing delay.
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Freescale Semiconductor
Electrical characteristics
IFC_CLK
AD[0:31]
address
read data
address
write data
teahc + t
IBKLOV
teadc + t
IBKLOV
AVD
tacse + t
IBKLOV
CE_B
taco + t
IBKLOV
trad + t
IBKHOV
OE_B
WE_B
tch + t
IBKLOV
tcs+ t
IBKLOV
twp + t
IBKLOV
BCTL
read
write
Figure 23. GPCM output timing diagram
2.14 Enhanced secure digital host controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC interface of the P1014.
2.14.1 eSDHC DC electrical characteristics
This table provides the DC electrical characteristics for the eSDHC interface of the P1014.
Table 49. eSDHC interface DC electrical characteristics
At recommended operating conditions with BVDD = 3.3 V or 1.8V
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
Note
VIH
VIL
—
0.625 BVDD
—
0.25 BVDD
—
V
V
1
Input low voltage
Output high voltage
Output low voltage
Input/output leakage current
Note:
—
—
0.75 BVDD
—
1
VOH
VOL
IOH = –100 uA at BVDDmin
IOL = 100uA at BVDDmin
—
V
—
—
—
0.125 BVDD
10
V
IIN/IOZ
–10
uA
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
59
Electrical characteristics
2.14.2 eSDHC AC timing specifications
This table provides the eSDHC AC timing specifications as defined in Figure 25.
Table 50. eSDHC AC Timing Specifications
At recommended operating conditions with BVDD = 3.3 V or 1.8V
Parameter
SDHC_CLK clock frequency:
Symbol
Min
Max
Unit
Note
fSFSCK
MHz
2, 4
SD/SDIO Full-speed/High-speed mode
MMC Full-speed/High-speed mode
0
25/50
20/52
SDHC_CLK clock low time—Full-speed/High-speed mode
SDHC_CLK clock high time—Full-speed/High-speed mode
SDHC_CLK clock rise and fall times
tSFSCKL
tSFSCKH
tSFSCKR/
10/7
10/7
—
—
—
3
ns
ns
ns
4
4
4
tSFSCKF
Input setup times: SDHC_CMD, SDHC_DAT_x, SDHC_CD to
SDHC_CLK
tSFSIVKH
tSFSIXKH
tSHSKHOV
2.5
2.5
–3
—
—
3
ns
ns
ns
4
3,4
4
Input hold times: SDHC_CMD, SDHC_DAT_x, SDHC_CD to
SDHC_CLK
Output delay time: SDHC_CLK to SDHC_CMD, SDHC_DAT_x
valid
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV
symbolizes eSDHC high speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to
the output (O) reaching the invalid state (X) or output hold time. Note that, in general, the clock reference symbol
representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. In full speed mode, clock frequency value can be 0–25 MHz for a SD/SDIO card and 0–20 MHz for a MMC card. In high
speed mode, clock frequency value can be 0–50 MHz for a SD/SDIO card and 0–52 MHz for a MMC card.
3. To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2ns.
4. CCARD 10 pF, (1 card), and CL = CBUS + CHOST + CCARD 40 pF
This figure provides the eSDHC clock input timing diagram.
eSDHC
External Clock
VM
VM
VM
operational mode
tSHSCKL
tSHSCKH
tSHSCK
VM = Midpoint Voltage (OVDD/2)
Figure 24. eSDHC Clock input timing diagram
tSHSCKF
tSH SC KR
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Freescale Semiconductor
Electrical characteristics
This figure provides the data and command input/output timing diagram.
VM
VM
VM
VM
SD_CK
External Clock
tSHSIXKH
tSH SIVKH
SD_DAT/CMD
Inputs
SD_DAT/CMD
Outputs
tSHSKHOV
VM = Midpoint Voltage (OVDD/2)
Figure 25. eSDHC data and command input/output timing diagram referenced to clock
2.15 Programmable Interrupt Controller (PIC)
specifications
This section describes the DC and AC electrical specifications for PIC on the P1014.
2.15.1 PIC DC electrical characteristics
This table provides the DC electrical characteristics for the PIC interface.
Table 51. PIC DC electrical characteristics
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
Input low voltage
VIH
VIL
2
—
0.8
40
—
V
V
1
1
—
—
2.4
—
Input current (OVIN = 0V or OVIN = OVDD
)
IIN
A
V
2
Output high voltage (OVDD = min, IOH = –2 mA)
Output low voltage (OVDD = min, IOL = 2 mA)
Note:
VOH
VOL
—
—
0.4
V
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol OVIN represents the input voltage of the supply. It is referenced in Table 3.
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Freescale Semiconductor
61
Electrical characteristics
2.15.2 PIC AC timing specifications
This table provides the PIC input and output AC timing specifications.
Table 52. PIC input AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
PIC inputs—minimum pulse width
tPIWID
3
—
SYSCLK
1
Note:
1. PIC inputs and outputs are asynchronous to any visible clock. PIC outputs should be synchronized before use by any
external synchronous logic. PIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working
in edge-triggered mode.
2.16 JTAG
This section describes the AC electrical specifications for the IEEE Std 1149.1™ (JTAG) interface of the P1014.
2.16.1 JTAG DC electrical characteristics
This table provides the JTAG DC electrical characteristics.
Table 53. JTAG DC electrical characteristics
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
Input low voltage
VIH
VIL
2
—
0.8
40
—
V
V
1
1
—
—
2.4
—
Input current (OVIN = 0V or OVIN = OVDD
)
IIN
A
V
2
Output high voltage (OVDD = min, IOH = –2 mA)
Output low voltage (OVDD = min, IOL = 2 mA)
Note:
VOH
VOL
—
—
0.4
V
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3
2. The symbol OVIN represents the input voltage of the supply. It is referenced in Table 3.
2.16.2 JTAG AC timing specifications
This table provides the JTAG AC timing specifications as defined in Figure 26 through Figure 29.
Table 54. JTAG AC timing specifications
For recommended operating conditions see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
JTAG external clock frequency of operation
JTAG external clock cycle time
fJTG
tJTG
0
30
15
0
33.3
—
MHz
ns
—
—
—
—
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
tJTKHKL
—
ns
tJTGR and tJTGF
2
ns
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Freescale Semiconductor
Electrical characteristics
Table 54. JTAG AC timing specifications (continued)
For recommended operating conditions see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
TRST assert time
Input setup times
tTRST
25
—
ns
2
—
Boundary-scan USB only
14
4
tJTDVKH
—
—
ns
ns
TDI, and TMS
—
—
3
Input hold times
tJTDXKH
10
Output valid times
Boundary Scan Data
TDO
tJTKLDV
15
10
—
ns
Output hold times
tJTKLDX
tJTKLDZ
30
4
—
ns
ns
3
JTAG external clock to output high impedance
10
—
Note:
1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing
(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going
to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D)
reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-load. Time-of-flight delays
must be added for trace lengths, vias, and connectors in the system.
This figure provides the AC test load for TDO and the boundary-scan outputs.
Z0 = 50
Output
OVDD/2
RL = 50
Figure 26. AC Test load for the JTAG interface
This figure provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
tJTKHKL
VM
VM
tJTGR
tJTGF
tJTG
VM = Midpoint Voltage (OV /2)
DD
Figure 27. JTAG clock input timing diagram
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
63
Electrical characteristics
This figure provides the TRST timing diagram.
TRST
VM
VM
tTRST
VM = Midpoint Voltage (OV /2)
DD
Figure 28. TRST Timing Diagram
This figure provides the boundary-scan timing diagram.
JTAG
VM
VM
External Clock
tJTDVKH
tJTDXKH
Boundary
Data Inputs
Input
Data Valid
tJTKLDV
tJTKLDX
Boundary
Data Outputs
Output Data Valid
tJTKLDZ
Boundary
Output Data Valid
Data Outputs
VM = Midpoint Voltage (OV /2)
DD
Figure 29. Boundary-scan timing diagram
2
2.17 I C
This section describes the DC and AC electrical characteristics for the I C interfaces of the P1014.
2
2.17.1 I2C DC electrical characteristics
2
This table provides the DC electrical characteristics for the I C interfaces.
2
Table 55. I C DC electrical characteristics
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
Input low voltage
Output high voltage
Output low voltage
VIH
VIL
2
—
2.4
0
—
0.8
—
V
V
1
1
VOH
VOL
tI2KHKL
II
V
—
2
0.4
50
10
V
Pulse width of spikes which must be suppressed by the input filter
0
ns
A
3
Input current each I/O pin (input voltage is between 0.1 OVDD
and 0.9 OVDD(max)
–10
4
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Electrical characteristics
2
Table 55. I C DC electrical characteristics (continued)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Capacitance for each I/O pin
Note:
CI
—
10
pF
—
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. Output voltage (open drain or open collector) condition = 3 mA sink current.
3. See the P1014 QorIQ Integrated Processor Reference Manual for information on the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.
2.17.2 I2C AC electrical specifications
2
This table provides the AC timing parameters for the I C interfaces.
2
Table 56. I C AC electrical specifications
For recommended operating conditions see Table 3. All values refer to VIH (min) and VIL (max) levels (see Table 55)
Parameter
Symbol
Min
Max
Unit
Note
SCL clock frequency
fI2C
tI2CL
0
400
—
kHz
s
2
Low period of the SCL clock
1.3
0.6
0.6
0.6
—
—
—
—
High period of the SCL clock
tI2CH
—
s
Setup time for a repeated START condition
tI2SVKH
tI2SXKL
—
s
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
—
s
Data setup time
Data hold time:
tI2DVKH
tI2DXKL
100
—
ns
—
3
s
—
0
—
—
CBUS compatible masters
I2C bus devices
Data output delay time
tI2OVKL
—
0.6
0.9
—
—
—
s
s
s
V
4
Set-up time for STOP condition
t
—
—
—
I2PVKH
Bus free time between a STOP and START condition
tI2KHDX
VNL
1.3
Noise margin at the LOW level for each connected device
(including hysteresis)
0.1 OVDD
Noise margin at the HIGH level for each connected device
(including hysteresis)
VNH
Cb
0.2 OVDD
—
V
—
—
Capacitive load for each bus line
—
400
pF
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Freescale Semiconductor
65
Electrical characteristics
2
Table 56. I C AC electrical specifications (continued)
For recommended operating conditions see Table 3. All values refer to VIH (min) and VIL (max) levels (see Table 55)
Parameter
Symbol
Min
Max
Unit
Note
Note:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing
(I2) with respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to
the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START
condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH
symbolizes I2C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative
to the tI2C clock reference (K) going to the high (H) state or setup time.
2. The requirements for I2C frequency calculation must be followed. See Freescale application note AN2919, “Determining the
I2C Frequency Divider Ratio for SCL.”
3. As a transmitter, the P1014 provides a delay time of at least 300 ns for the SDA signal (referred to as the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP
condition. When the P1014 acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load
on SCL and SDA are balanced, the P1014 does not generate an unintended START or STOP condition. Therefore, the 300
ns SDA output delay time is not a concern. If under some rare condition, the 300 ns SDA output delay time is required for
the P1014 as transmitter, application note AN2919 referred to in note 4 below is recommended.
4. The maximum tI2OVKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
2
This figure provides the AC test load for the I C.
Output
OVDD/2
Z0 = 50
RL = 50
2
Figure 30. I C AC test load
2
This figure shows the AC timing diagram for the I C bus.
SDA
tI2DVKH
tI2KHKL
tI2CL
tI2SXKL
SCL
tI2SXKL
tI2CH
tI2SVKH
tI2PVKH
tI2DXKL, I2OVKL
t
S
Sr
P
S
2
Figure 31. I C Bus AC timing diagram
2.18 GPIO
This section describes the DC and AC electrical specifications for the GPIO interface of the P1014.
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66
Freescale Semiconductor
Electrical characteristics
2.18.1 GPIO DC electrical characteristics
This table provides the DC electrical characteristics for the GPIO interface when operating from 3.3V supply.
Table 57. GPIO_[0:11] DC electrical characteristics (3.3 V)
For recommended operating conditions, see Table 3.
Parameter
Input high voltage
Symbol
Min
Max
Unit
Note
VIH
VIL
IIN
2
—
0.8
40
V
V
1
1
2
Input low voltage
—
—
Input current
A
(OVIN = 0 V or OVIN = OVDD
)
Output high voltage
VOH
2.4
—
—
V
V
—
—
(OVIN= min, IOH = –2 mA)
Low-level output voltage
(OVIN = min, IOL = 2 mA)
VOL
0.4
Note:
1. The min VILand max VIH values are based on the min and max OVIN respective values found in Table 3.
2. The symbol OVIN represents the input voltage of the supply. It is referenced in Table 3.
This table provides the DC electrical characteristics for the GPIO interface when operating from 2.5V supply.
Table 58. GPIO_[12:15] DC electrical characteristics (2.5 V)
For recommended operating conditions, see Table 3.
Parameter
Input high voltage
Symbol
Min
Max
Unit
Note
VIH
VIL
IIN
1.7
—
—
0.7
40
V
V
1
1
2
Input low voltage
Input current
—
A
(LVIN = 0 V or LVIN = LVDD
)
Output high voltage
(LVIN = min, IOH = 2 mA)
VOH
1.7
—
—
V
V
—
—
Low-level output voltage
(LVIN = min, IOL = 2 mA)
VOL
0.7
Note:
1. The min VILand max VIH values are based on the min and max LVIN respective values found in Table 3.
2. The symbol LVIN represents the input voltage of the supply. It is referenced in Table 3.
NOTE
•
•
GPIO_[0:11] are powered by OV
.
DD
GPIO_[12:15] are powered by LV
.
DD
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Electrical characteristics
2.18.2 GPIO AC timing specifications
This table provides the GPIO input and output AC timing specifications.
Table 59. GPIO input AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Unit
Note
GPIO inputs—minimum pulse width
tPIWID
20
ns
1
Note:
1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID to ensure proper operation.
This figure provides the AC test load for the GPIO.
OVDD/2
Output
Z = 50
0
R = 50
L
Figure 32. GPIO AC test load
2.19 TDM
This section describes the DC and AC electrical specifications for the TDM of the P1014
2.19.1 TDM DC electrical characteristics
This table provides the DC electrical characteristics TDM.
Table 60. TDM DC electrical characteristics
For recommended operating conditions, see Table 3.
Characteristic
Input high voltage
Symbol
Min
Max
Unit
Note
VIH
VIL
2.0
–0.3
—
—
0.8
40
—
V
V
1
1
Input low voltage
Input current (OVIN = 0V or OVIN = OVDD
)
IIN
A
V
2
Output high voltage (OVDD = min, IOH = –2 mA)
Output low voltage (OVDD = min, IOL = 2 mA)
Note:
VOH
VOL
2.4
—
—
—
0.4
V
1. The min VILand max VIH values are based on the min and max BVIN respective values found in Table 3.
2. The symbol BVIN represents the input voltage of the supply. It is referenced in Table 3.
2.19.2 TDM AC electrical characteristics
This table provides input and output AC timing specifications for TDM interface.
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Electrical characteristics
Table 61. TDM AC timing specifications
Parameter/Condition
TDM_TX_CLK/TDM_RX_CLK
Symbol
Min
Max
Unit
Note
tDM
62.5
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
2
TDM_TX_CLK/TDM_RX_CLK rise/fall time
TDM_TX_CLK/TDM_RX_CLK high pulse width
TDM_TX_CLK/TDM_RX_CLK low pulse width
TDM all input setup time
tDMR DMF
tDM_HIGH
tDM_LOW
/t
8.0
8.0
3.0
3.5
2.0
4.0
—
—
—
tDMIVKH
—
TDM_RX_DATA hold time
tDMRDIXKH
tDMFSIXKH
tDM_OUTAC
tDMTKHOV
tDMTKHOX
tDM_OUTHI
—
TDM_TFS/TDM_RFS input hold time
TDM_TX_CLK High to TDM_TX_DATA output active
TDM_TX_CLK High to TDM_TX_DATA output valid
TDM_TX_DATA hold time
—
—
2
14.0
—
—
—
—
2.0
—
TDM_TX_CLK High to TDM_TX_DATA output high
impedance
10.0
TDM_TFS/TDM_RFS output valid
TDM_TFS/TDM_RFS output hold time
Note:
tDMFSKHOV
tDMFSKHOX
—
13.5
—
ns
ns
—
—
2.5
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTDMIVKH
symbolizes TDM timing (DM) with respect to the time the input signals (I) reach the valid state (V) relative to the TDM Clock,
tTC, reference (K) going to the high (H) state or setup time. Also, output signals (O), hold (X).
2. Output values are based on 30 pF capacitive load.
3. Inputs are referenced to the sampling that the TDM is programmed to use. Outputs are referenced to the programming
edge they are programmed to use. Use of the rising edge or falling edge as a reference is programmable. TDMxTCK and
TDMxRCK are shown using the rising edge.
This figure shows the TDM receive signal timing.
tDM
tDM_HIGH
tDM_LOW
TDM_RX_CLK
tDMIVKH
tDMRDIXKH
TDMxRD
tDMFSIXKH
tDMIVKH
TDMxRFS
tDMFSKHOV
tDMFSKHOX
TDM_RFS (output)
Figure 33. TDM receive signals
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
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Electrical characteristics
This figure shows the TDM transmit signal timing.
tDM
tDM_HIGH
tDM_LOW
tDM_OUTHI
tDMTKHOX
TDM_TX_CLK
tDMTKHOV
tDM_OUTAC
TDM_TX_DATA
TDM_RX_CLK
tDMFSKHOV
tDMFSKHOX
TDM_TFS (output)
tDMFSIXKH
tDMIVKH
TDMxTFS (input)
_
Figure 34. TDM Transmit Signals
2.20 High-Speed Serial Interfaces (HSSI)
The P1014 features one Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications.
The SerDes interface can be used for PCI Express data transfers and for SGMII application.
This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes
Reference Clocks. This section also shows the SerDes data lane’s transmitter and receiver reference circuits.
2.20.1 Signal terms definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description
and specification of differential signals.
Figure 35 shows how the signals are defined. For the purpose of illustration, only one SerDes lane is used for description. The
figure shows the waveform for either a transmitter output (SDn_TX and SDn_TX) or a receiver input (SDn_RX and SDn_RX).
Each signal swings between A volts and B volts where A > B.
Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes
transmitter and receiver operate in a fully symmetrical differential signaling environment.
1. Single-Ended Swing
The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and SDn_RX each have a
peak-to-peak swing of A – B volts. This is also referred as each signal wire’s Single-Ended Swing.
2. Differential Output Voltage, V (or Differential Output Swing):
OD
The Differential Output Voltage (or Swing) of the transmitter, V , is defined as the difference of the two
OD
complimentary output voltages: V
– V
The V value can be either positive or negative.
SDn_TX
SDn_TX. OD
3. Differential Input Voltage, V (or Differential Input Swing):
ID
The Differential Input Voltage (or Swing) of the receiver, V , is defined as the difference of the two complimentary
ID
input voltages: V
– V
The V value can be either positive or negative.
SDn_RX
SDn_RX. ID
4. Differential Peak Voltage, V
DIFFp
The peak value of the differential transmitter output signal or the differential receiver input signal is defined as
Differential Peak Voltage, V = |A – B| Volts.
DIFFp
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Electrical characteristics
5. Differential Peak-to-Peak, V
DIFFp-p
Since the differential output signal of the transmitter and the differential input signal of the receiver each range from
A – B to –(A – B) Volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver
input signal is defined as Differential Peak-to-Peak Voltage, V
= 2 V
= 2 |(A – B)| Volts, which is twice
DIFFp-p
DIFFp
of differential swing in amplitude, or twice of the differential peak. For example, the output differential peak-peak
voltage can also be calculated as V
= 2 |V |.
TX-DIFFp-p
OD
6. Differential Waveform
The differential waveform is constructed by subtracting the inverting signal (SDn_TX, for example) from the
non-inverting signal (SDn_TX, for example) within a differential pair. There is only one signal trace curve in a
differential waveform. The voltage represented in the differential waveform is not referenced to ground. See Figure 35
as an example for differential waveform.
7. Common Mode Voltage, V
cm
The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor of a balanced
interchange circuit and ground. In this example, for SerDes output, V = (VSDn_TX + VSDn_TX)/2 = (A + B) /
cm_out
2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. In a system, the
common mode voltage may often differ from one component’s output to the other’s input. Sometimes, it may even be
different between the receiver input and driver output circuits within the same component. It is also referred to as the
DC offset occasionally.
SDn_TX or
SDn_RX
A Volts
Vcm = (A + B)/2
SDn_TX or
SDn_RX
B Volts
Differential Swing, VID or VOD = A – B
Differential Peak Voltage, VDIFFp = |A – B|
Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown)
Figure 35. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a current mode logic (CML) transmitter that has a common
mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 V and 2.0 V. Using these values,
the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred as the single-ended swing for each
signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential
swing (V ) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500
OD
mV and –500 mV, in other words, V is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage
OD
(V
) is 500 mV. The peak-to-peak differential voltage (V
) is 1000 mV p-p.
DIFFp
DIFFp-p
2.20.2 SerDes reference clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clock inputs are SD_REF_CLK and SD_REF_CLK for PCI Express and SGMII interface.
The following sections describe the SerDes reference clock requirements and some application information.
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Freescale Semiconductor
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Electrical characteristics
2.20.2.1 SerDes reference clock receiver characteristics
This figure shows a receiver reference diagram of the SerDes reference clocks.
50
SDn_REF_CLK
Input
Amp
SDn_REF_CLK
50
Figure 36. Receiver of SerDes reference clocks
The characteristics of the clock signals are as follows:
•
•
The supply voltage requirements for XV
are specified in Table 2 and Table 3.
DD_SRDS2
SerDes reference clock receiver reference circuit structure:
— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown in Figure 36. Each
differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50- termination to SGND_SRDS followed by
on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. See the Differential Mode and
Single-ended Mode description below for further detailed requirements.
•
The maximum average current requirement that also determines the common mode voltage range:
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the
following bullet for more detail), since the input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 = 8 mA)
while the minimum common mode input level is 0.1 V above SGND_SRDS. For example, a clock with a 50/50
duty cycle can be produced by a clock driver with output driven by its current source from 0mA to 16mA
(0-0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the
common mode voltage at 400 mV.
— If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50 to SGND_SRDS DC, or it
exceeds the maximum input current limitations, then it must be AC-coupled off-chip.
•
The input amplitude requirement is described in detail in the following sections.
2.20.2.2 DC level requirement for SerDes reference clocks
The DC level requirement for the P1014 SerDes reference clock inputs is different depending on the signaling mode used to
connect the clock driver chip and SerDes reference clock inputs as described below.
•
Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or
between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing less than 800 mV and greater than 200 mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
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Electrical characteristics
— For external DC-coupled connection, as described in Section 2.20.2.1, “SerDes reference clock receiver
characteristics,” the maximum average current requirements sets the requirement for average voltage (common
mode voltage) to be between 100 mV and 400 mV. Figure 37 shows the SerDes reference clock input requirement
for DC-coupled connection scheme.
— For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since
the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver
operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has
its common mode voltage set to SGND_SRDS. Each signal wire of the differential inputs is allowed to swing
below and above the command mode voltage (SGND_SRDS). Figure 38 shows the SerDes reference clock input
requirement for AC-coupled connection scheme.
200 mV < Input Amplitude or Differential Peak < 800 mV
SD_REF_CLK
Vmax < 800 mV
100mV < Vcm < 400 mV
Vmin > 0 V
SD_REF_CLK
Figure 37. Differential reference clock input DC requirements (external DC-coupled)
200 mV < Input Amplitude or Differential Peak < 800mV
SDn_REF_CLK
Vmax < Vcm + 400 mV
Vcm
Vmin > Vcm – 400 mV
SDn_REF_CLK
Figure 38. Differential Reference clock input DC requirements (external AC-coupled)
•
Single-ended Mode
— The reference clock can also be single-ended. The SD_REF_CLK input amplitude (single-ended swing) must be
between 400 mV and 800 mV peak-peak (from V
tied to ground.
to V
) with SD_REF_CLK either left unconnected or
MIN
MAX
— The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 39 shows the SerDes
reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or AC-coupled
externally. For the best noise performance, the reference of the clock could be DC or AC-coupled into the unused
phase (SD_REF_CLK) through the same source impedance as the clock input (SD_REF_CLK) in use
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
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Electrical characteristics
.
400mV < SD_REF_CLK Input Amplitude < 800mV
SD_REF_CLK
SD_REF_CLK
0 V
Figure 39. Single-Ended reference clock input DC requirements
2.20.2.3 AC requirements for SerDes reference clocks
This table lists the AC requirements, for the PCI Express and SGMII SerDes reference clocks, that should be guaranteed by the
customer’s application design.
Table 62. SD_REF_CLK and SD_REF_CLK input clock requirements
Parameter
Symbol
Min
Typ Max Unit Note
SD_REF_CLK/ SD_REF_CLK frequency range
tCLK_REF
—
100/12
5
—
MHz
1
SD_REF_CLK/ SD_REF_CLK clock frequency tolerance
tCLK_TOL
-350
—
+35 ppm
0
—
SD_REF_CLK/ SD_REF_CLK reference clock duty cycle
tCLK_DUTY
tCLK_DJ
40
—
50
—
60
42
ꢀ
4
SD_REF_CLK/ SD_REF_CLK max deterministic peak-peak Jitter at 10-6
BER
ps
—
SD_REF_CLK/ SD_REF_CLK total reference clock jitter at 10-6 BER
(Peak-to-peak jitter at refClk input)
tCLK_TJ
—
1
—
—
86
4
ps
V/ns
mV
2
3
SD_REF_CLK/ SD_REF_CLK rising/falling edge rate
tCLKRR/tCLKFR
Differential input high voltage
Differential input low voltage
VIH
VIL
200
—
—
—
—
4
4
–20 mV
0
Rising edge rate (SDn_REF_CLK) to falling edge rate (SDn_REF_CLK)
matching
Rise-Fall
Matching
—
—
20
ꢀ
5, 6
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Electrical characteristics
Table 62. SD_REF_CLK and SD_REF_CLK input clock requirements (continued)
Parameter Symbol Min Typ Max Unit Note
Note:
1. Only 100/125 have been tested. Other in-between values do not work correctly with the rest of the system.
2. Limits from PCI Express CEM Rev 2.0
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK).The
signal must be monotonic through the measurement region for rise and fall time. The 400-mV measurement window is
centered on the differential zero crossing.
4. Measurement is taken from the differential waveform.
5. Measurement is taken from the single-ended waveform.
6. Matching applies to the rising edge for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a
200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median
cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge
rate of SDn_REF_CLK should be compared to the fall edge rate of SDn_REF_CLK, the maximum allowed difference should
not exceed 20ꢀ of the slowest edge rate. See Figure 41.
Rise Edge Rate
Fall Edge Rate
VIH = +200 mV
0.0 V
VIL = –200 mV
SDn_REF_CLK –
SDn_REF_CLK
Figure 40. Differential measurement points for rise and fall time
Figure 41. Single-ended measurement points for rise and fall time matching
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
75
Electrical characteristics
2.20.2.4 SerDes transmitter and receiver reference circuits
This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.
SD_RXn
SD_TXn
50
50
50
50
Transmitter
Receiver
SD_TXn
SD_RXn
Figure 42. SerDes transmitter and receiver reference circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below, based on the application
usage:
•
•
•
Section 2.21, “PCI Express”
Section 2.22, “Serial ATA (SATA)”
Section 2.11.2, “SGMII Interface electrical characteristics”
Note that external AC Coupling capacitor is required for the above three serial transmission protocols per the protocol’s standard
requirements.
2.21 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus of the P1014.
2.21.1 DC requirements for PCI Express SD_REF_CLK and SD_REF_CLK
For more information, see Section 2.20.2.2, “DC level requirement for SerDes reference clocks.”
2.21.2 PCI Express DC physical layer specifications
This section contains the DC specifications for the physical layer of PCI Express on this device.
2.21.2.1 PCI Express DC physical layer transmitter specifications
This section discusses PCI Express DC physical layer transmitter specifications for 2.5 Gb/s.
This table defines the PCI Express (2.5 Gb/s) DC specifications for the differential output at all transmitters (TXs). The
parameters are specified at the component pins.
Table 63. PCI Express (2.5Gb/s) Differential transmitter (TX) output DC specifications
For recommended operating conditions, see Table 3.
Symbol
Parameter
Min Typical Max Unit
Comments
VTX-DIFFp-p Differential Peak-to-Peak
Output Voltage
800 1000 1200 mV VTX-DIFFp-p = 2*|VTX-D+ – VTX-D-|. See Note 1.
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Electrical characteristics
Table 63. PCI Express (2.5Gb/s) Differential transmitter (TX) output DC specifications (continued)
For recommended operating conditions, see Table 3.
Symbol
Parameter
Min Typical Max Unit
Comments
VTX-DE-RATIO De- Emphasized Differential 3.0
Output Voltage (Ratio)
3.5
4.0
dB Ratio of the VTX-DIFFp-p of the second and following
bits after a transition divided by the VTX-DIFFp-p of
the first bit after a transition. See Note 1.
ZTX-DIFF-DC DC Differential TX
Impedance
80
40
100
50
120
60
TX DC Differential mode Low Impedance
ZTX-DC
Transmitter DC Impedance
Required TX D+ as well as D- DC Impedance
during all states
Note:
1. Specified at the measurement point into a timing and voltage compliance test load, as shown in Figure 43, and measured
over any 250 consecutive TX UIs.
2.21.2.2 PCI Express DC physical layer receiver specifications
This section discusses PCI Express DC physical layer receiver specifications for 2.5 Gb/s.
This table defines the PCI Express (2.5 Gb/s) DC specifications for the differential output at all transmitters (TXs). The
parameters are specified at the component pins.
Table 64. PCI Express (2.5 Gb/s) differential receiver (RX) input DC specifications
For recommended operating conditions, see Table 3.
Symbol
VRX-DIFFp-p
Parameter
Min
Typical
Max
Unit
Comments
Differential Input
Peak-to-Peak Voltage
175
—
1200
mV
VRX-DIFFp-p = 2*|VRX-D+ – VRX-D-|.
See Note 1.
ZRX-DIFF-DC
DC Differential Input
Impedance
80
40
100
50
120
60
RX DC Differential mode impedance.
See Note 2
ZRX-DC
DC Input Impedance
Required RX D+ as well as D- DC
Impedance (50 20ꢀ tolerance). See
Notes 1 and 2.
ZRX-HIGH-IMP-DC
Powered Down DC
Input Impedance
50 k
65
—
—
—
Required RX D+ as well as D- DC
Impedance when the Receiver
terminations do not have power. See
Note 3.
VRX-IDLE-DET-DIFFp-p Electrical Idle Detect
Threshold
235
mV
VRX-IDLE-DET-DIFFp-p = 2*|VRX-D+ -VRX-D-
Measured at the package pins of the
Receiver
|
Note:
1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 43 should be used
as the RX device when taking measurements. If the clocks to the RX and TX are not derived from the same reference clock,
the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
2. Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM)
there is a 5 ms transition time before Receiver termination values must be met on all un-configured Lanes of a Port.
3. The RX DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps
ensure that the receiver detect circuit does not falsely assume a Receiver is powered on when it is not. This term must be
measured at 300 mV above the RX ground.
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Freescale Semiconductor
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Electrical characteristics
2.21.3 PCI Express AC physical layer specifications
This section contains the DC specifications for the physical layer of PCI Express on this device.
2.21.3.1 PCI Express AC physical layer transmitter specifications
This section discusses the PCI Express AC physical layer transmitter specifications for 2.5Gb/s.
This table defines the PCI Express (2.5Gb/s) AC specifications for the differential output at all transmitters (TXs). The
parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter.
Table 65. PCI Express (2.5Gb/s) differential transmitter (TX) output AC specifications
Symbol
Parameter
Min Typical Max
Unit
Comments
UI
Unit Interval
399.8 400.00 400.1
ps Each UI is 400 ps 300 ppm. UI does not account for
Spread Spectrum Clock dictated variations. See Note 1.
8
2
TTX-EYE
Minimum TX
Eye Width
0.70
—
—
—
UI The maximum Transmitter jitter can be derived as
TTX-MAX-JITTER = 1 – TTX-EYE= 0.3 UI.
See Notes 2 and 3.
TTX-EYE-MEDIAN-to Maximum time
—
0.15
200
UI Jitter is defined as the measurement variation of the
crossing points (VTX-DIFFp-p = 0 V) in relation to a
recovered TX UI. A recovered TX UI is calculated over
3500 consecutive unit intervals of sample data. Jitter is
measured using all edges of the 250 consecutive UI in the
center of the 3500 UI used for calculating the TX UI. See
Notes 2 and 3.
between the
jitter median
and maximum
deviation from
the median.
-MAX-JITTER
CTX
AC Coupling
Capacitor
75
—
nF All Transmitters shall be AC coupled. The AC coupling is
required either within the media or within the transmitting
component itself. See Note 4.
Note:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load, as shown in Figure 43, and measured
over any 250 consecutive TX UIs.
3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the
Transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the
total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the
mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal
as opposed to the averaged time value.
4. P1014 SerDes transmitter does not have CTX built-in. An external AC Coupling capacitor is required.
2.21.3.2 PCI Express AC physical layer receiver specifications
This section discusses the PCI Express AC physical layer receiver specifications for 2.5 Gb/s.
This table defines the AC specifications for the PCI Express (2.5 Gb/s) differential input at all receivers (RXs). The parameters
are specified at the component pins. The AC timing specifications do not include RefClk jitter.
Table 66. PCI Express (2.5 Gb/s) Differential Receiver (rx) input AC specifications
Symbol
Parameter
Min Typical Max
Unit
Comments
UI
Unit Interval
399.88 400.00 400.12
ps
Each UI is 400 ps 300 ppm. UI does not account for
Spread Spectrum Clock dictated variations. See Note 1.
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Freescale Semiconductor
Electrical characteristics
Table 66. PCI Express (2.5 Gb/s) Differential Receiver (rx) input AC specifications (continued)
Symbol
TRX-EYE
Parameter
Min Typical Max
Unit
Comments
Minimum
Receiver Eye
Width
0.4
—
—
—
—
UI
The maximum interconnect media and Transmitter jitter
that can be tolerated by the Receiver can be derived as
TRX-MAX-JITTER = 1 - TRX-EYE= 0.6 UI.
See Notes 2 and 3.
TRX-EYE-MEDIAN- Maximum time
0.3
UI
Jitter is defined as the measurement variation of the
crossing points (VRX-DIFFp-p = 0 V) in relation to a
recovered TX UI. A recovered TX UI is calculated over
3500 consecutive unit intervals of sample data. Jitter is
measured using all edges of the 250 consecutive UI in
the center of the 3500 UI used for calculating the TX UI.
See Notes 2, 3 and 4.
between the
jitter median
and maximum
deviation from
the median.
to-MAX-JITTER
Note:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 43 should be used
as the RX device when taking measurements. If the clocks to the RX and TX are not derived from the same reference clock,
the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget
collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median
describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged
time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500
consecutive UI must be used as the reference for the eye diagram.
4. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit
algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental
and simulated data.
2.21.3.3 Compliance test and measurement load
The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package
pins, into a test/measurement load shown in this figure.
NOTE
The allowance of the measurement point to be within 0.2 inches of the package pins is
meant to acknowledge that package/board routing may benefit from D+ and D– not being
exactly matched in length at the package pin boundary. If the vendor does not explicitly
state where the measurement point is located, the measurement point is assumed to be the
D+ and D– package pins.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
79
Electrical characteristics
Figure 43. Compliance Test/Measurement Load
2.22 Serial ATA (SATA)
This section describes the DC and AC electrical specifications for the serial ATA (SATA) interface.
2.22.1 SATA DC Electrical characteristics
This section describes the DC electrical characteristics for SATA.
2.22.1.1 SATA DC transmitter output characteristics
This table provides the DC differential transmitter output DC characteristics for the SATA interface at Gen1i or 1.5 Gbits/s
transmission.
Table 67. Gen1i/1.5G transmitter (Tx) DC specifications
At recommended operating conditions with SDx_AVDD = 1.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Tx differential output voltage
Tx differential pair impedance
Note:
VSATA_TXDIFF
400
85
475
100
600
115
mV p-p
1
2
ZSATA_TXDIFFIM
1. Terminated by 50 load.
2. DC impedance
This table provides the differential transmitter output DC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s
transmission.
Table 68. Gen 2i/3G transmitter (Tx) DC specifications
At recommended operating conditions with SDx_AVDD = 1.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Tx diff output voltage
VSATA_TXDIFF
400
85
522.5
100
700
115
mV p-p
1
Tx differential pair impedance
ZSATA_TXDIFFIM
—
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Freescale Semiconductor
Electrical characteristics
Table 68. Gen 2i/3G transmitter (Tx) DC specifications (continued)
At recommended operating conditions with SDx_AVDD = 1.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Note:
1. Terminated by 50 load.
2.22.1.2 SATA DC receiver (Rx) input characteristics
This table provides the Gen1i or 1.5 Gbits/s differential receiver input DC characteristics for the SATA interface.
Table 69. Gen1i/1.5 G receiver (Rx) input DC specifications
At recommended operating conditions with SDx_AVDD = 1.
Parameter
Symbol
Min
Typical
Max
Unit
Note
Differential input voltage
Differential Rx input impedance
OOB signal detection threshold
Note:
VSATA_RXDIFF
ZSATA_RXSEIM
VSATA_OOB
240
85
475
100
120
600
115
240
mV p-p
1
—
5
50
mV p-p
1. Voltage relative to common of either signal comprising a differential pair
This table provides the Gen2i or 3 Gbits/s differential receiver input DC characteristics for the SATA interface.
Table 70. Gen2i/3 G receiver (Rx) input DC specifications
At recommended operating conditions with SDx_AVDD = 1.
Parameter
Symbol
Min
Typical
Max
Unit
Note
Differential input voltage
Differential Rx input impedance
OOB signal detection threshold
Note:
VSATA_RXDIFF
ZSATA_RXSEIM
VSATA_OOB
275
85
475
100
120
750
115
275
mV p-p
1
2
2
75
mV p-p
1. Voltage relative to common of either signal comprising a differential pair
2. DC impedance
2.22.2 SATA AC timing specifications
This section discusses the SATA AC timing specifications.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
81
Electrical characteristics
2.22.2.1 AC requirements for SATA REF_CLK
The AC requirements for the SATA reference clock are listed in this table to be guaranteed by the customer’s application design.
Table 71. SATA Reference clock input requirements
At recommended operating conditions with SDx_AVDD = 1
Uni
t
Parameter
Symbol Min
tCLK_REF
Typ
Max
Note
SD_REF_CLK/SD_REF_CLK frequency range
—
100/125
/150
—
MH
z
1
SD_REF_CLK/SD_REF_CLK clock frequency tolerance
tCLK_TOL –350
—
+35 pp
—
—
2
0
m
SD_REF_CLK/SD_REF_CLK reference clock duty cycle (measured at 1.6 V) tCLK_DUT 40
50
60
ꢀ
Y
SD_REF_CLK/SD_REF_CLK cycle-to-cycle clock jitter (period jitter)
tCLK_CJ
tCLK_PJ
—
—
—
100 ps
SD_REF_CLK/SD_REF_CLK total reference clock jitter, phase jitter
(peak-peak)
–50
+50 ps 2, 3,
4
Note:
1. Caution: Only 100, 125, and 150 MHz have been tested. In-between values do not work correctly with the rest of the
system.
2. At RefClk input
3. In a frequency band from 150 kHz to 15 MHz at BER of 10-12
4. Total peak-to-peak deterministic jitter should be less than or equal to 50 ps.
This figure shows the reference clock timing waveform.
TH
Ref_CLK
TL
Figure 44. Reference clock timing waveform
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
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Freescale Semiconductor
Electrical characteristics
2.22.3 AC transmitter output characteristics
This table provides the differential transmitter output AC characteristics for the SATA interface at Gen1i or 1.5 Gbits/s
transmission. The AC timing specifications do not include RefClk jitter.
Table 72. Gen1i/1.5 G transmitter (Tx) AC specifications
At recommended operating conditions with SDx_AVDD = 1
Parameter
Channel speed
Symbol
Min
Typ
Max
Unit
Note
tCH_SPEED
TUI
—
1.5
—
670.2333
0.355
0.47
Gbps
ps
—
—
1
Unit Interval
666.4333
666.6667
Total jitter data-data 5 UI
Total jitter, data-data 250 UI
Deterministic jitter, data-data 5 UI
Deterministic jitter, data-data 250 UI
Note:
USATA_TXTJ5UI
USATA_TXTJ250UI
USATA_TXDJ5UI
USATA_TXDJ250UI
—
—
—
—
—
—
—
—
UI p-p
UI p-p
UI p-p
UI p-p
1
0.175
0.22
1
1
1. Measured at Tx output pins peak to peak phase variation, random data pattern.
This table provides the differential transmitter output AC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s
transmission. The AC timing specifications do not include RefClk jitter.
Table 73. Gen 2i/3 G transmitter (Tx) AC specifications
At recommended operating conditions with SDx_AVDD = 1
Parameter
Channel speed
Symbol
Min
Typ
Max
Unit
Note
tCH_SPEED
TUI
—
3.0
—
335.1167
0.3
Gbps
ps
—
—
1
Unit Interval
333.2167
333.3333
Total jitter fC3dB = fBAUD 10
Total jitter fC3dB = fBAUD 500
Total jitter fC3dB = fBAUD 1667
USATA_TXTJfB/10
USATA_TXTJfB/500
USATA_TXTJfB/1667
USATA_TXDJfB/10
—
—
—
—
—
—
—
—
UI p-p
UI p-p
UI p-p
UI p-p
0.37
1
0.55
1
Deterministic jitter,
0.17
1
fC3dB = fBAUD 10
Deterministic jitter,
USATA_TXDJfB/500
—
—
0.19
0.35
UI p-p
UI p-p
1
1
f
C3dB = fBAUD 500
Deterministic jitter,
USATA_TXDJfB/1667
—
—
f
C3dB = fBAUD 1667
Note:
1. Measured at Tx output pins peak-to-peak phase variation, random data pattern
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
83
Hardware design considerations
2.22.4 AC differential receiver input characteristics
This table provides the Gen1i or 1.5 Gbits/s differential receiver input AC characteristics for the SATA interface. The AC timing
specifications do not include RefClk jitter.
Table 74. Gen 1i/1.5G receiver (Rx) AC specifications
At recommended operating conditions with SDx_AVDD = 1
Parameter
Symbol
Min
Typical
Max
Unit
Note
Unit Interval
TUI
666.4333
666.6667
670.2333
0.43
ps
—
1
Total jitter data-data 5 UI
USATA_TXTJ5UI
USATA_TXTJ250UI
USATA_TXDJ5UI
USATA_TXDJ250UI
—
—
—
—
—
—
—
—
UI p-p
UI p-p
UI p-p
UI p-p
Total jitter, data-data 250 UI
0.60
1
Deterministic jitter, data-data 5 UI
Deterministic jitter, data-data 250 UI
0.25
1
0.35
1
Note:
1. Measured at receiver
This table provides the differential receiver input AC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s transmission.
The AC timing specifications do not include RefClk jitter.
Table 75. Gen 2i/3G receiver (Rx) AC specifications
Parameter
Symbol
Min
Typical
Max
Unit
Note
Unit Interval
TUI
333.2167
333.3333
335.1167
0.46
ps
—
1
Total jitter fC3dB = fBAUD 10
USATA_TXTJfB/10
USATA_TXTJfB/500
USATA_TXTJfB/1667
USATA_TXDJfB/10
USATA_TXDJfB/500
USATA_TXDJfB/1667
—
—
—
—
—
—
—
—
—
—
—
—
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
Total jitter fC3dB = fBAUD 500
0.60
1
Total jitter fC3dB = fBAUD 1667
Deterministic jitter, fC3dB = fBAUD 10
Deterministic jitter, fC3dB = fBAUD 500
0.65
1
0.35
1
0.42
1
Deterministic jitter,
0.35
1
fC3dB = fBAUD 1667
Note:
1. Measured at receiver
3
Hardware design considerations
3.1
System clocking
This section describes the PLL configuration of the P1014. Note that the platform clock is identical to the internal Core Complex
Bus (CCB) clock.
This device includes 6 PLLs, as follows:
•
The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio
between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in
Section 3.1.2, “Platform to SYSCLK PLL ratio.”
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Freescale Semiconductor
Hardware design considerations
•
•
The e500 core PLL generates the core clock from the platform clock. The frequency ratio between the e500 core clock
and the platform clock is selected using the e500 PLL ratio configuration bits as described in Section 3.1.3, “e500 core
to platform clock PLL ratio.”
The DDR PLL generates the clocking for the DDR SDRAM controller. The frequency ratio between DDR clock and
platform clock is selected using the DDR PLL ratio configuration bits as described in section Section 3.1.4,
“DDR/SYSCLK PLL ratio.”
•
•
Each of the two SerDes blocks has a PLL.
USB PHY PLL generates the clocking for internal USB PHY.
3.1.1
Clock ranges
This table provides the clocking specifications for the processor core, platform, memory.
Table 76. Processor clocking specifications
Maximum Frequency
Characteristic
Unit
Note
Min
Max
e500 core processor frequency
Platform CCB bus clock frequency
Note:
400
267
800
400
MHz
MHz
1, 2, 3
1, 4, 5
1. Caution: The platform clock to SYSCLK ratio and e500 core to platform clock ratio settings must be chosen such that
the resulting SYSCLK frequency, e500 (core) frequency, and platform clock frequency do not exceed their respective
maximum or minimum operating frequencies. See Section 3.1.2, “Platform to SYSCLK PLL ratio,” and Section 3.1.3,
“e500 core to platform clock PLL ratio,” and Section 3.1.4, “DDR/SYSCLK PLL ratio,” for ratio settings.
2. The minimum e500 core frequency is based on the minimum platform clock frequency of 267 MHz.
3. The reset config signal cfg_core_speed must be pulled low if the core frequency is 500MHz or below.
4. These values are preliminary and subject to change.
5. The reset config signal cfg_plat_speed must be pulled low if the CCB bus frequency is lower than 300 MHz.
3.1.1.1
DDR clock ranges
The DDR memory controller can run only in asynchronous mode.
This table provides the clocking specifications for the memory bus.
Table 77. Memory Bus Clocking specifications
Characteristic
Min
Max
Unit
Note
Memory bus clock frequency
Note:
333
400
MHz
1, 2, 3
1. Caution: The platform clock to SYSCLK ratio and e500 core to platform clock ratio settings must be chosen such that the
resulting SYSCLK frequency, e500 (core) frequency, and platform frequency do not exceed their respective maximum or
minimum operating frequencies. See Section 3.1.2, “Platform to SYSCLK PLL ratio,” and Section 3.1.3, “e500 core to
platform clock PLL ratio,” and Section 3.1.4, “DDR/SYSCLK PLL ratio,” for ratio settings.
2. The memory bus clock refers to the P1014 memory controllers’ Dn_MCK[0:5] and Dn_MCK[0:5] output clocks, running at
half of the DDR data rate.
3. In asynchronous mode, if the DDR data rate to the CCB clock rate is greater than 3:1 (i.e. DDR=3:CCB=1), than the DDR
performance monitor statistic accuracy cannot be guaranteed.
As a general guideline, the following procedures can be used for selecting the DDR data rate or platform frequency:
1. Start with the processor core frequency selection.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
85
Hardware design considerations
2. Once the processor core frequency is determined, select the platform frequency from the options listed in Table 79.
3. Check the platform to SYSCLK ratio to verify a valid ratio can be choose from Table 81.
4. DDR data rate must be greater than the platform frequency. In other words, running DDR data rate lower than the
platform frequency in asynchronous mode is not supported by the P1014.
5. Verify all clock ratios to ensure that there is no violation to any clock and/or ratio specification.
3.1.2
Platform to SYSCLK PLL ratio
The clock that drives the internal CCB bus is called the platform clock. The frequency of the platform clock is set using the
following reset signals, as shown in Table 78:
•
•
SYSCLK input signal
Binary value on IFC_AD[0:2] at power up
These signals must be pulled to the desired values.
Table 78. Platform/SYSCLK clock ratios
Binary Value of
IFC_AD[0:2]Signals
Platform: SYSCLK
Ratio
000
001
4:1
5:1
010
6:1
All Others
Reserved
3.1.3
e500 core to platform clock PLL ratio
The clock ratio between the e500 core and the platform clock is determined by the binary value of IFC_AD[3:5] signals at power
up. Table 79 describes the supported ratios. Note that IFC_AD[6] must be pulled low if the core frequency is 450 MHz or below.
Table 79. e500 core to platform clock ratios
Binary Value of
e500 Core: Platform Ratio
IFC_AD[3:5]Signals
010
011
1:1
1.5:1
2:1
100
101
2.5:1
3:1
110
All Others
Reserved
3.1.4
DDR/SYSCLK PLL ratio
This table describes the clock ratio between the DDR memory controller complex and the DDR PLL reference clock, SYSCLK,
which is not the memory bus clock. The DDR memory controller complex clock frequency is equal to the DDR data rate.P1014
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Freescale Semiconductor
Hardware design considerations
Table 80. DDR Clock ratio
Binary Value of
IFC_AD[7:8]Signals
DDR:SYSCLK Ratio
00
01
10
11
8:1
10:1
12:1
Reserved
3.1.5
Frequency options
This section discusses interface frequency options.
3.1.5.1
SYSCLK and platform frequency options
This table shows the expected frequency options for SYSCLK and platform frequencies.
Table 81. SYSCLK and platform frequency options
SYSCLK (MHz)
83.33
Platform:
SYSCLK Ratio
66.66
100.00
Platform Frequency (MHz)1
4:1
5:1
267
333
400
333
—
400
—
6:1
—
—
Note:
1
Platform frequency values are shown rounded down to the
nearest whole number (decimal place accuracy removed)
3.2
Supply power default setting
P1014 is capable of supporting multiple power supply levels on its I/O supply. Table 82 show the encoding used to select the
voltage level for each I/O supply.
Table 82. Default voltage level for BV
DD
BVDD_VSEL [0:1]
I/O Voltage Level
00
01
10
11
3.3 V
2.5 V
1.8 v
3.3 v
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
87
Hardware design considerations
3.3
Power supply design and sequencing
3.3.1
PLL power supply filtering
Each of the PLLs is provided with power through independent power supply pins. The AV level should always be equivalent
DD
to V , and these voltages must be derived directly from V through a low frequency filter scheme.
DD
DD
The recommended solution for PLL filtering is to provide independent filter circuits per PLL power supply, as illustrated in
Figure 45, one for each of the AV pins. By providing independent filters to each PLL, the opportunity to cause noise injection
DD
from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLL’s resonant frequency range from a 500-kHz to 10-MHz range. It should be built
with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr.
Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors
of equal value are recommended over a single large value capacitor.
Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize noise coupled from
DD
nearby circuits. It should be possible to route directly from the capacitors to the AV pin, which is on the periphery of device
DD
footprint, without the inductance of vias.
This figure shows the PLL power supply filter circuit for AVDD_CORE, AVDD_DDR, AVDD_PLAT
.
NOTE
•
•
•
R = 5 5%
C1 = 10µF 10%, 603, X5R with ESL 0.5nH
C2 = 1µF 10%, 402 X5R with ESL 0.5 nH
R
VDD
AVDD
C1
C2
Low ESL Surface Mount Capacitors
GND
Figure 45. P1014 PLL power supply filter circuit
The SD1_AV , SD2_AV and USBVDD1_0 signals provides power for the analog portions of the SerDes PLL and USB
DD
DD
PHY PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one
shown in following Figure 46. For maximum effectiveness, the filter circuit should be placed as closely as possible to the device
balls to ensure it filters out as much noise as possible. The ground connection should be near the SD1_AV , SD2_AV and
DD
DD
USBVDD1_0 balls. The 0.003-µF capacitor is closest to the balls, followed by two 2.2-µF capacitor, and finally the 1- resistor
to the board supply plane. The capacitors are connected from SD1_AV , SD2_AV and USBVDD1_0 to the ground plane.
DD
DD
Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept short, wide and direct.
This figure shows the PLL power supply filter circuit for SD1_AV , SD2_AV and USBVDD1_0.
DD
DD
1.0
AVDD-SRDS
2.2 µF 1
2.2 µF 1
0.003 µF
GND
1. An 0805 sized capacitor is recommended for system initial bring-up
Figure 46. SerDes PLL power supply filter circuit
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
88
Freescale Semiconductor
Hardware design considerations
3.4
Decoupling recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high
frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the P1014 system. The device itself requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer place at least one decoupling capacitor at each V , BV , OV , GV , and LV
DD
DD
DD
DD
DD
pin of the device. These decoupling capacitors should receive their power from separate V
BV , OV , GV , and LV
,
DD
DD,
DD
DD
DD
and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the
device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be
used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the V , BV
,
DD
DD
OV , GV , and LV planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have
DD
DD
DD
a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to
the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON).
3.5
SerDes block power supply decoupling
recommendations
The SerDes block requires a clean, tightly regulated source of power (SV and XV ) to ensure low jitter on transmit and
DD
DD
reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to
power and ground should be done with multiple vias to further reduce inductance.
1. The board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls of the
device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and ground
connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the device
as close to the supply and ground connections as possible.
2. There should be a 1-µF ceramic chip capacitor on each side of the device. This should be done for all SerDes supplies.
3. Between the device and any SerDes voltage regulator there should be a 10-µF, low equivalent series resistance (ESR)
SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all SerDes
supplies.
3.6
Connection recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. All unused active
low inputs should be tied to V , BV , OV , GV , and LV as required. All unused active high inputs should be
DD
DD
DD
DD
DD
connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all
external V
BV , OV , GV , and LV and GND pins of the device.
DD,
DD DD DD DD
3.7 Pull-up and pull-down resistor requirements
2
The P1014 requires weak pull-up resistors on open drain type pins including I C pins (1 k is recommended) and MPIC
interrupt pins (2–10 k is recommended).
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 49.
NOTE
Care must be taken to ensure that these pins are maintained at a valid deasserted state under
normal operating conditions, because most have asynchronous behavior, and spurious
assertion gives unpredictable results.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
89
Hardware design considerations
3.8
Output buffer DC impedance
The P1014 drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended
2
driver type (open drain for I C).
To measure Z (output impedance) for the single-ended drivers, an external resistor is connected from the chip pad to OV or
0
DD
GND. Then, the value of each resistor is varied until the pad voltage is OV /2 (see Figure 61). The output impedance is the
DD
average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2
is open) and R is trimmed until the voltage at the pad equals OV /2. R then becomes the resistance of the pull-up devices.
P
DD
P
R and R are designed to be close to each other in value. Then, Z = (R + R )/2. Here OV refers to the power supply
P
N
0
P
N
DD
associated with that particular pin, to know about the supply associated with any pin see Table 47.
OVDD
RN
SW2
Pad
Data
SW1
RP
GND
Figure 47. Driver Impedance measurement
This table summarizes the signal impedance targets. The driver impedances are targeted at minimum V , nominal OV
,
DD
DD
90C.
Table 83. Impedance characteristics
IFC, Ethernet, DUART, Control,
Configuration, Power Management
Impedance
DDR DRAM Symbol
Unit
R
43
43
20
20
Z0
Z0
N
R
P
Note: Nominal supply voltages. See Table 3.
3.9
Configuration pin muxing
The P1014 provides the user with power-on configuration options which can be set through the use of external pull-up or
pull-down resistors of 4.7 k on certain output pins (see customer visible configuration pins). These pins are generally used as
output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is
asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal
function. Most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 k. This
value should permit the 4.7-kresistor to pull the configuration pin to a valid logic low level. The pull-up resistor is enabled
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
90
Freescale Semiconductor
Hardware design considerations
only during HRESET (and for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When
the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal
quality or delay disruption. The default value for all configuration bits treated this way has been encoded such that a high voltage
level puts the device into the default state and external resistors are needed only when non-default settings are required by the
user.
Careful board layout, including stubless connections to these pull-down resistors, coupled with the large value of the pull-down
resistor should minimize the disruption of signal quality or speed for output pins thus configured.
The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up devices.
3.10 JTAG configuration signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1
specification, but is provided on all processors that implement the PowerPC architecture. The device requires TRST to be
asserted during reset conditions to ensure the JTAG boundary logic does not interfere with normal chip operation. While it is
possible to force the TAP controller to the reset state using only the TCK and TMS signals, generally systems assert TRST
during the power-on reset flow. Simply tying TRST to HRESET is not practical because the JTAG interface is also used for
accessing the common on-chip processor (COP) function.
The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging
software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG
port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert
HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage
monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into
these signals with logic.
The arrangement shown in Figure 49 allows the COP port to independently assert HRESET or TRST, while ensuring that the
target can drive HRESET as well.
The COP interface has a standard header, shown in Figure 49 for connection to the target system, and is based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a
connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and
other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed.
There is no standardized way to number the COP header; consequently, many different pin numbers have been observed from
emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while
still others number the pins counter clockwise from pin 1 (as with an IC).
Regardless of the numbering, the signal placement recommended in Figure 49 is common to all known emulators.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
91
Hardware design considerations
OVDD
10 k
10 k
SRESET 6
SRESET
HRESET
From Target
Board Sources
(if any)
HRESET1
COP_HRESET
13
11
10 k
10 k
10 k
10 k
COP_SRESET
5
TRST1
COP_TRST
4
2
1
3
COP_VDD_SENSE2
NC
10
4
6
5
7
6
8
5 3
COP_CHKSTP_OUT
CKSTP_OUT
15
10 k
9
10
12
14 3
11
10 k
KEY
13
15
COP_CHKSTP_IN
COP_TMS
No pin
CKSTP_IN
TMS
8
9
1
3
16
COP_TDO
COP_TDI
COP_TCK
COP Connector
Physical Pinout
TDO
TDI
7
2
TCK
10 k
NC
NC
10
4
12
16
Notes:
1. The COP port and target board should be able to independently assert HRESET and TRST to the processor
in order to fully control the processor as shown here.
2. Populate this with a 10 resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for
improved signal integrity.
5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid
accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.
6. Asserting SRESET causes a machine check interrupt to the e500 core.
Figure 48. JTAG interface connection
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
92
Freescale Semiconductor
Hardware design considerations
2
4
1
3
COP_TDO
COP_TDI
NC
NC
COP_TRST
COP_VDD_SENSE
COP_CHKSTP_IN
5
7
6
8
COP_TCK
COP_TMS
COP_SRESET
9
10
12
NC
NC
11
KEY
13
15
COP_HRESET
No pin
GND
COP_CHKSTP_OUT
16
Figure 49. COP connector physical pinout
3.10.1 Termination of unused signals
If the JTAG interface and COP header is not used, Freescale recommends the following connections:
•
TRST should be tied to HRESET through a 0 k isolation resistor so that it is asserted when the system reset signal
(HRESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale
recommends that the COP header be designed into the system as shown in Figure 49. If this is not possible, the isolation
resistor allows future access to TRST in case a JTAG interface may need to be wired onto the system in future debug
situations.
•
•
Tie TCK to OV through a 10 k resistor. This prevents TCK from changing state and reading incorrect data into
the device.
DD
No connection is required for TDI, TMS, or TDO.
3.11 Guidelines for high-speed interface termination
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section. However,
the SerDes must always have power applied to its supply pins.
The following pins must be left unconnected (float):
•
•
SD_TX[3:0]
SD_TX[3:0]
The following pins must be connected to GND:
•
•
•
•
SD_RX[3:0]
SD_RX[3:0]
SD_REF_CLK
SD_REF_CLK
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
93
Hardware design considerations
3.12 Thermal
This section describes the thermal specifications of the P1014.
3.12.1 Thermal characteristics
This table provides the package thermal characteristics.
Table 84. Package thermal characteristics
Characteristic
JEDEC Board
Symbol
Value
Unit
Note
Junction-to-ambient Natural Convection
Junction-to-ambient Natural Convection
Junction-to-ambient (at 200 ft/min)
Junction-to-ambient (at 200 ft/min)
Junction-to-board thermal
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
—
RJA
RJA
RJMA
RJMA
RJB
RJC
JT
34
22
27
18
11
7
C/W
C/W
C/W
C/W
C/W
C/W
C/W
1, 2
1, 2, 3
1, 3
1, 3
4
Junction-to-case thermal
—
5
Junction-to-package top thermal
Note:
Natural Convection
2
6
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 and JESD51-6 with the board (JESD51-9) horizontal.
3. Per JEDEC JESD51-6 with board horizontal.
4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written as Psi-JT.
This table provides the thermal resistance with heat sink in open flow.
Table 85. Thermal resistance with heat sink in open flow
Heat Sink with Thermal Grease
Air Flow
Thermal Resistance (C/W)
23x23x10 mm Pin Fin
Natural Convection
0.5 m/s
16.9
13.4
11.6
10.0
13.8
10.7
9.3
1 m/s
2 m/s
35x35x18 mm Pin Fin
Natural Convection
0.5 m/s
1 m/s
2 m/s
8.6
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
94
Freescale Semiconductor
Hardware design considerations
Table 85. Thermal resistance with heat sink in open flow (continued)
Heat Sink with Thermal Grease
Air Flow
Thermal Resistance (C/W)
53x54x25 mm Pin Fin
Natural Convection
0.5 m/s
11.5
9.1
8.3
7.9
1 m/s
2 m/s
Simulations with heat sinks were done with the package mounted on the 2s2p thermal test board. A power value of TBD was
used for the heat sink simulations.The thermal interface material was a typical thermal grease such as Dow Corning 340 or
Wakefield 120 grease.
3.12.2 Recommended thermal model
Information about Flotherm models of the package or thermal data not available in this document can be obtained from your
local Freescale sales office.
3.12.3 Thermal management information
This section provides thermal management information for the plastic ball grid array (WB-TePBGA) package for air-cooled
applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and
thermal interface material. The recommended attachment method to the heat sink is shown in Figure 50. The heat sink should
be attached to the printed-circuit board with the spring force centered over the die. This spring force should not exceed 10
pounds force (45 Newton).
WB-TePBGA Package
Heat Sink
Heat Sink
Clip
Thermal Interface Material
Wire
Die
Printed-Circuit Board
Figure 50. Package exploded cross-sectional view with several heat sink options
The system board designer can choose between several types of heat sinks to place on the device. Ultimately, the final selection
of an appropriate heat sink depends on factors such as thermal performance at a given air velocity, spatial volume, mass,
attachment method, assembly, and cost.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
95
Package information
4
Package information
The following section describes the detailed content and mechanical description of the package.
4.1
Package parameters for P1014
The package type is 19mm 19mm, 425 plastic ball grid array (WB-TePBGA-1). The package parameters are as follows:
Package outline
Interconnects
19 mm 19mm
425
Pitch
0.8 mm
Module height (typical)
Solder Balls
1.50 mm to 1.90 mm (Maximum)
3.5% Ag, 96.5% Sn
0.45 mm
Ball diameter (typical)
4.2
Mechanical dimensions of P1014 WB-TePBGA
This figure shows mechanical dimensions and bottom surface nomenclature of the P1014 WB-TePBGA.
NOTE
•
•
•
•
•
All dimensions are in millimeters.
Dimensioning and tolerancing per ASME Y14. 5M-1994.
Maximum solder ball diameter measured parallel to Datum A.
Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
Parallelism measurement shall exclude any effect of mark on top surface of package.
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
96
Freescale Semiconductor
Package information
Figure 51. Mechanical Dimensions of P1014 WB-TePBGA package
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
97
Ordering information
5
Ordering information
This table provides the Freescale part numbering nomenclature for the P1010. Note that the individual part numbers correspond
to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. Each part number
also contains a revision code which refers to the die mask revision number.
Table 86. Part numbering nomenclature
p
1
01
a
x
t
e
n
c
d
r
P = 45 nm
1
01 =
Single
core
4
P = Prototype
C = Qual’d to
Commercial Tier X = Ext. N = SEC
N = Qual’d to
Industrial Tier
S = Std E = SEC
Temp
5 =
H = 800 MHz H = 800
A =
Rev 1.0
B =
Present TEPBGA-1 F = 667 MHz
Pb free D = 533 MHz
MHZ
F= 667
MHz
Temp
Not
Rev 2.01
Present
5.1
Part marking
Parts are marked as the example shown in Figure 52.
NOTE
•
•
•
•
•
ATWLYYWW is the traceability code.
CCCCC is the country code.
MMMMM is the mask number.
YWWLAZ is the assembly traceability code.
P101axtencdr is the orderable part number. See Table 86 for details.
P101axtencdr
CPU/DDR MHZ
ATWLYYWW
CCCCC
*MMMMM
YWWLAZ
TePBGA II
Figure 52. Part marking for WB-TePBGA device
6
Product documentation
The following documents are required for a complete description of the device and are needed to design properly with the part:
•
•
P1014 QorIQ Integrated Processor Reference Manual (P1014RM)
e500 PowerPC Core Reference Manual (E500CORERM)
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
98
Freescale Semiconductor
Revision history
7
Revision history
This table summarizes a revision history for this document.
Table 87. Revision history
Rev.
Number
Date
Substantive Change(s)
4
3
05/2014
04/2014
• In Table 86 added part numbering information for die revision 2.01.
• In Table 1, modified IO type of SD2_RX_1 from output to input.
• In note above Figure 2, added serdes reference clock.
• In Table 2, modified characteristics column for symbol ‘LVDD’, ‘LVIN’, ‘OVDD’, and ‘OVIN’.
• In Table 3, modified characteristics column for symbol ‘LVDD’, ‘LVIN’, ‘OVDD’, and ‘OVIN’.
• In Table 44, added min frequency for USB_CLK_IN.
• In Table 57, replaced BVIN with OVIN.
• In Table 58, replaced BVIN with LVIN.
• Removed the table, “GPIO DC electrical characteristics (1.8 V)”.
• Added a note in Section 2.18.1, “GPIO DC electrical characteristics.
2
1
03/2013
06/2012
• In Table 3, modified names of temperature ranges.
• In Table 9, added power numbers for 1000 MHz CPU frequency.
• In Table 9, added power numbers for SVDD power for typical and maximum.
• In Table 76, modified max core clock frequency to 1000 MHz.
• In Table 86, added option for parts with CPU frequency of 1000 MHz.
• Everywhere replaced signal name ALE with AVD.
• In Table 1, replaced note references from 5 to 25 for following signals, cfg_sys_pll_0, cfg_sys_pll_1,
cfg_sys_pll_2, cfg_ddr_pll_0, cfg_ddr_pll_1, cfg_core_pll_0, cfg_core_pll_1, cfg_core_pll_2,
cfg_rom_loc[0], cfg_rom_loc[1], cfg_rom_loc[2], cfg_rom_loc[3] because these signals doesn’t have
internal pull-ups during POR sequence.
• In Table 1, modified note associated with IBIAS_REXT signal. Modified IBIAS_REXT termination
circuit and added an programming sequence.
• In Table 3 removed note 3.
• In Table 9, modified typical and max I/O power numbers for USB PHY.
• In Table 5, modified “Maximum valid-to-high impedance time for actively driven POR configurations
with respect to negation of HRESET (max)” from 8 to 5.
• In Table 22, modified tDDKHDX, tDDKLDX (min) for 800MHz from 275 to 225 ns.
• In Table 32, modified note 4 to represent correct register fields.
• In note 4 of Table 48, replaced tLBOTOT with tIBOTOT.
• In Table 54, modified specifications for tJTDVKH and tJTKLDV.
• From Figure 31, removed tI2CR and tI2CF because those are not needed. These parameters are
not mentioned in table either.
• In Table 44, under conditions colum for total input jitter spec for USBPHY_CLK, changed “peak to
peak“ to “RMS“.
0
11/2011 Initial public release
P1014 QorIQ Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
99
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www.freescale.com
Web Support:
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implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
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Freescale Semiconductor reserves the right to make changes without further notice to
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Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
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Freescale and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. Reg. U.S. Pat. & Tm. Off. QorIQ is a trademark of
Freescale Semiconductor, Inc. All other product or service names are the
property of their respective owners. The Power Architecture and Power.org
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trademarks and service marks licensed by Power.org.
© 2011-2014 Freescale Semiconductor, Inc.
Document Number: P1014EC
Rev. 4
05/2014
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