概述
规格参数
数据手册P3Z22V10-DA 概述
3V zero power, TotalCMOS, universal PLD device 3V零功耗， TotalCMOS ，通用PLD器件 可编程逻辑器件
P3Z22V10-DA 规格参数
| 生命周期： | Obsolete | 零件包装代码： | QLCC |
| 包装说明： | QCCJ, | 针数： | 28 |
| Reach Compliance Code： | unknown | HTS代码： | 8542.39.00.01 |
| 风险等级： | 5.76 | 最大时钟频率： | 83 MHz |
| JESD-30 代码： | S-PQCC-J28 | 长度： | 11.5062 mm |
| 专用输入次数： | 11 | I/O 线路数量： | 10 |
| 端子数量： | 28 | 最高工作温度： | 70 °C |
| 最低工作温度： | 组织： | 11 DEDICATED INPUTS, 10 I/O | |
| 输出函数： | MACROCELL | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | QCCJ | 封装形状： | SQUARE |
| 封装形式： | CHIP CARRIER | 可编程逻辑类型： | EE PLD |
| 传播延迟： | 10 ns | 认证状态： | Not Qualified |
| 座面最大高度： | 4.57 mm | 最大供电电压： | 3.6 V |
| 最小供电电压： | 3 V | 标称供电电压： | 3.3 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | COMMERCIAL | 端子形式： | J BEND |
| 端子节距： | 1.27 mm | 端子位置： | QUAD |
| 宽度： | 11.5062 mm | Base Number Matches： | 1 |
P3Z22V10-DA 数据手册
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P3Z22V10
3V zero power, TotalCMOS , universal
PLD device
Product specification
1997 Jul 18
Supersedes data of 1997 May 15
IC27 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
3V zero power, TotalCMOS , universal PLD device
P3Z22V10
FEATURES
• Programmable output polarity
• Synchronous preset/asynchronous reset capability
• Industry’s first TotalCMOS 22V10 – both CMOS design and
process technologies
• Security bit prevents unauthorized access
• Fast Zero Power (FZP ) design technique provides ultra-low
power and high speed
• Electronic signature for identification
– Static current of less than 45µA
• Design entry and verification using industry standard CAE tools
• Reprogrammable using industry standard device programmers
– Dynamic current 1/10 to 1/1000 that of competitive devices
– Pin-to-pin delay of only 10ns
• True Zero Power device with no turbo bits or power down
schemes
DESCRIPTION
The P3Z22V10 is the first SPLD to combine high performance with
low power, without the need for “turbo bits” or other power down
schemes. To achieve this, Philips Semiconductors has used their
FZP design technique, which replaces conventional sense
amplifier methods for implementing product terms (a technique that
has been used in PLDs since the bipolar era) with a cascaded chain
of pure CMOS gates. This results in the combination of low power
and high speed that has previously been unattainable in the PLD
arena. For 5V operation, Philips Semiconductors offers the
P5Z22V10 that offers high speed and low power in a 5V
implementation.
• Function/JEDEC map compatible with
Bipolar, UVCMOS, EECMOS 22V10s
• Multiple packaging options featuring PCB-friendly flow-through
pinouts (SOL and TSSOP)
– 24-pin TSSOP—uses 93% less in-system space than a 28-pin
PLCC
– 24-pin SOL
– 28-pin PLCC with standard JEDEC pin-out
• Available in commercial and industrial operating ranges
• Supports mixed voltage systems–5V tolerant I/Os
The P3Z22V10 uses the familiar AND/OR logic array structure,
which allows direct implementation of sum-of-products equations.
This device has a programmable AND array which drives a fixed OR
array. The OR sum of products feeds an “Output Macro Cell”
(OMC), which can be individually configured as a dedicated input, a
combinatorial output, or a registered output with internal feedback.
2
• Advanced 0.5µ E CMOS process
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Varied product term distribution with up to 16 product terms per
output for complex functions
ORDERING INFORMATION
PROPAGATION
TEMPERATURE
RANGE
DRAWING
NUMBER
ORDER CODE
PACKAGE
28-pin PLCC
OPERATING RANGE
DELAY
10ns
10ns
10ns
15ns
15ns
15ns
15ns
15ns
15ns
P3Z22V10-DA
P3Z22V10-DD
P3Z22V10-DDH
P3Z22V10-BA
P3Z22V10-BD
P3Z22V10-BDH
P3Z22V10IBA
P3Z22V10IBD
P3Z22V10IBDH
0 to +70°C
0 to +70°C
0 to +70°C
0 to +70°C
0 to +70°C
0 to +70°C
–40 to +85°C
–40 to +85°C
–40 to +85°C
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.3V ±10%
= 3.3V ±10%
= 3.3V ±10%
= 3.3V ±10%
= 3.3V ±10%
= 3.3V ±10%
= 3.3V ±10%
= 3.3V ±10%
= 3.3V ±10%
SOT261-3
SOT137-1
SOT355-1
SOT261-3
SOT137-1
SOT355-1
SOT261-3
SOT137-1
SOT355-1
24-pin SOL
24-pin TSSOP
28-pin PLCC
24-pin SOL
24-pin TSSOP
28-pin PLCC
24-pin SOL
24-pin TSSOP
2
1997 Jul 18
853–2004 18193
Philips Semiconductors
Product specification
3V zero power, TotalCMOS , universal PLD device
P3Z22V10
PIN CONFIGURATIONS
28-Pin PLCC
PIN DESCRIPTIONS
PIN LABEL
I1 – I11
NC
DESCRIPTION
Dedicated Input
Not Connected
4
3
2
1
28 27 26
I3
I4
5
6
25 F7
24 F6
23 F5
22 NC
21 F4
20 F3
19 F2
F0 – F9
I0/CLK
Macrocell Input/Output
Dedicated Input/Clock Input
Supply Voltage
I5
7
V
CC
NC
I6
8
GND
Ground
9
I7
10
11
I8
12 13 14 15 16 17 18
SP00474
24-Pin SOL and 24-Pin TSSOP
IO/CLK
1
2
3
4
5
6
7
8
9
24 V
CC
I1
I2
I3
I4
I5
I6
I7
I8
23 F9
22 F8
21 F7
20 F6
19 F5
18 F4
17 F3
16 F2
15 F1
14 F0
13 I11
I9 10
I10 11
GND 12
AP00475
3
1997 Jul 18
Philips Semiconductors
Product specification
3V zero power, TotalCMOS , universal PLD device
P3Z22V10
LOGIC DIAGRAM
CLK/I0
1
24
V
CC
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43
AR
0
1
1
1
0
0
0
1
0
1
AR
D
23 F9
22 F8
21 F7
20 F6
19 F5
18 F4
17 F3
16 F2
15 F1
14 F0
Q
Q
9
SP
0
1
10
20
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
0
1
I1
I2
I3
I4
I5
I6
I7
I8
2
3
4
5
6
7
8
9
21
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
33
34
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
48
49
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
65
66
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
82
83
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
97
98
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
110
0
1
111
121
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
0
1
122
130
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
0
1
I9 10
I10 11
SP
131
13 I11
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43
GND 12
NOTE:
Programmable connection.
SP00059
4
1997 Jul 18
Philips Semiconductors
Product specification
3V zero power, TotalCMOS , universal PLD device
P3Z22V10
CLK/I0
I1 – I11
1
11
PROGRAMMABLE AND ARRAY
(44 × 132)
8
10
12
14
16
16
14
12
10
8
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
SP00060A
Figure 1.
Functional Diagram
132 product terms:
FUNCTIONAL DESCRIPTION
– 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16)
used to form logical sums
The P3Z22V10 implements logic functions as sum-of-products
expressions in a programmable-AND/fixed-OR logic array.
User-defined functions are created by programming the connections
of input signals into the array. User-configurable output structures in
the form of I/O macrocells further increase logic flexibility.
– 10 output enable terms (one for each I/O)
– 1 global synchronous preset product term
– 1 global asynchronous clear product term
At each input-line/product-term intersection there is an EEPROM
memory cell which determines whether or not there is a logical
connection at that intersection. Each product term is essentially a
44-input AND gate. A product term which is connected to both the
True and Complement of an input signal will always be FALSE, and
thus will not affect the OR function that it drives. When all the
connections on a product term are opened, a Don’t Care state exists
and that term will always be TRUE.
ARCHITECTURE OVERVIEW
The P3Z22V10 architecture is illustrated in Figure 1. Twelve
dedicated inputs and 10 I/Os provide up to 22 inputs and 10 outputs
for creation of logic functions. At the core of the device is a
programmable electrically-erasable AND array which drives a
fixed-OR array. With this structure, the P3Z22V10 can implement up
to 10 sum-of-products logic expressions.
Associated with each of the 10 OR functions is an I/O macrocell
which can be independently programmed to one of 4 different
configurations. The programmable macrocells allow each I/O to
create sequential or combinatorial logic functions with either
Active-High or Active-Low polarity.
Variable Product Term Distribution
The P3Z22V10 provides 120 product terms to drive the 10 OR
functions. These product terms are distributed among the outputs in
groups of 8, 10, 12, 14, and 16 to form logical sums (see Logic
Diagram). This distribution allows optimum use of device resources.
AND/OR Logic Array
The programmable AND array of the P3Z22V10 (shown in the Logic
Diagram) is formed by input lines intersecting product terms. The
input lines and product terms are used as follows:
44 input lines:
– 24 input lines carry the True and Complement of the signals
applied to the 12 input pins
– 20 additional lines carry the True and Complement values of
feedback or input signals from the 10 I/Os
5
1997 Jul 18
Philips Semiconductors
Product specification
3V zero power, TotalCMOS , universal PLD device
P3Z22V10
S
1
S
0
OUTPUT CONFIGURATION
1
1
0
0
0
1
0
1
0
0
1
1
0
Registered/Active-LOW/Macrocell feedback
Registered/Active-HIGH/Macrocell feedback
Combinatorial/Active-LOW/Pin feedback
Combinatorial/Active-HIGH/Pin feedback
AR
1
0
1
D
Q
F
CLK
Q
0 = Unprogrammed fuse
1 = Programmed fuse
SP
S
1
S
0
0
1
SP00484
Figure 2.
Output Macro Cell Logic Diagram
S
S
= 0
= 0
S
S
= 0
= 1
0
1
0
1
AR
D
Q
F
F
CLK
Q
SP
a. Registered/Active-LOW
c. Combinatorial/Active-LOW
S
S
= 1
= 0
S
S
= 1
= 1
0
1
0
1
AR
D
Q
Q
F
F
CLK
SP
b. Registered/Active-HIGH
Figure 3.
d. Combinatorial/Active-HIGH
Output Macro Cell Configurations
SP00376
Programmable I/O Macrocell
Output type
The output macrocell provides complete control over the
The signal from the OR array can be fed directly to the output pin
(combinatorial function) or latched in the D-type flip-flop (registered
function). The D-type flip-flop latches data on the rising edge of the
clock and is controlled by the global preset and clear terms. When
the synchronous preset term is satisfied, the Q output of the register
will be set HIGH at the next rising edge of the clock input. Satisfying
the asynchronous clear term will set Q LOW, regardless of the clock
state. If both terms are satisfied simultaneously, the clear will
override the preset.
architecture of each output. the ability to configure each output
independently permits users to tailor the configuration of the
P3Z22V10 to the precise requirements of their designs.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 2, consists of a D-type
flip-flop and two signal-select multiplexers. The configuration of each
macrocell of the P3Z22V10 is determined by the two EEPROM bits
controlling these multiplexers. These bits determine output polarity,
and output type (registered or non-registered). Equivalent circuits for
the macrocell configurations are illustrated in Figure 3.
6
1997 Jul 18
Philips Semiconductors
Product specification
3V zero power, TotalCMOS , universal PLD device
P3Z22V10
from the I/O pin. In this case, the pin can be used as a dedicated
input, a dedicated output, or a bi-directional I/O.
Program/Erase Cycles
The P3Z22V10 is 100% testable, erases/programs in seconds, and
guarantees 1000 program/erase cycles.
Power-On Reset
To ease system initialization, all flip-flops will power-up to a reset
condition and the Q output will be low. The actual output of the
P3Z22V10 will depend on the programmed output polarity. The V
rise must be monotonic.
Output Polarity
Each macrocell can be configured to implement Active-High or
Active-Low logic. Programmable polarity eliminates the need for
external inverters.
CC
Design Security
Output Enable
The P3Z22V10 provides a special EEPROM security bit that
The output of each I/O macrocell can be enabled or disabled under
the control of its associated programmable output enable product
term. When the logical conditions programmed on the output enable
term are satisfied, the output signal is propagated to the I/O pin.
Otherwise, the output buffer is driven into the high-impedance state.
prevents unauthorized reading or copying of designs programmed
into the device. The security bit is set by the PLD programmer,
either at the conclusion of the programming cycle or as a separate
step, after the device has been programmed. Once the security bit is
set, it is impossible to verify (read) or program the P3Z22V10 until
the entire device has first been erased with the bulk-erase function.
Under the control of the output enable term, the I/O pin can function
as a dedicated input, a dedicated output, or a bi-directional I/O.
Opening every connection on the output enable term will
permanently enable the output buffer and yield a dedicated output.
Conversely, if every connection is intact, the enable term will always
be logically FALSE and the I/O will function as a dedicated input.
TotalCMOS Design Technique
for Fast Zero Power
Philips is the first to offer a TotalCMOS SPLD, both in process
technology and design technique. Philips employs a cascade of
CMOS gates to implement its Sum of Products instead of the
traditional sense amp approach. This CMOS gate implementation
allows Philips to offer SPLDs which are both high performance and low
power, breaking the paradigm that to have low power, you must accept
Register Feedback Select
When the I/O macrocell is configured to implement a registered
function (S1 = 0) (Figures 3a or 3b), the feedback signal to the AND
array is taken from the Q output.
low performance. Refer to Figure 4 and Table 1 showing the I vs.
DD
Frequency of our P3Z22V10 TotalCMOS SPLD.
Bi-directional I/O Select
When configuring an I/O macrocell to implement a combinatorial
function (S1 = 1) (Figures 3c or 3d), the feedback signal is taken
30
25
20
TYPICAL
I
DD
15
10
5
(mA)
0
1
10
20
30
40
50
60
70
80
90
100
110
120
130
FREQUENCY (MHz)
SP00443
Figure 4.
Typical I vs. Frequency @ V = 3.3V, 25°C (10-bit counter)
DD DD
Table 1. Typical I vs. Frequency
DD
V
DD
= 3.3V@25°C
FREQ (MHz)
Typical I (mA)
1
10
20
30
40
50
60
8.9
70
80
90
100
14.5
110
120
130
0.2
1.5
3.0
4.5
6.0
7.4
10.4
11.8
13.2
15.8
17.0
18.2
DD
7
1997 Jul 18
Philips Semiconductors
Product specification
3V zero power, TotalCMOS , universal PLD device
P3Z22V10
1
ABSOLUTE MAXIMUM RATINGS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN.
–0.5
–0.5
–0.5
–30
–100
0
MAX.
4.6
V
V
V
Supply voltage
Input voltage
Output voltage
Input current
Output current
V
V
DD
2
5.5
5.5
I
2
V
OUT
I
I
30
100
75
mA
mA
°C
°C
°C
IN
OUT
T
T
T
Allowable thermal rise ambient to junction
Junction temperature range
R
–40
–65
150
150
J
Storage temperature range
STG
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at
these or any other condition above those indicated in the operational and programming specification of the device is not implied.
2. Except F7, where max = V + 0.5V.
DD
OPERATING RANGE
PRODUCT GRADE
Commercial
TEMPERATURE
0 to +70°C
VOLTAGE
3.3 ± 10% V
3.3 ± 10% V
Industrial
–40 to +85°C
8
1997 Jul 18
Philips Semiconductors
Product specification
3V zero power, TotalCMOS , universal PLD device
P3Z22V10
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0°C ≤ T
≤ +70°C; 3.0 ≤ V ≤ 3.6V
amb
DD
LIMITS
TYP.
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
MIN.
MAX.
0.8
V
V
V
V
V
Input voltage low
V
V
= 3.0V
= 3.6V
V
V
IL
DD
Input voltage high
Input clamp voltage
Output voltage low
Output voltage high
2
IH
I
DD
V
= 3.0V; I = –18mA
–1.2
0.5
V
DD
IN
V
DD
= 3.0V; I = 8mA
V
OL
OH
OL
V
= 3.0V; I = –4mA
2.4
–10
–10
–10
–10
V
DD
OH
V
IN
= 0 to V
10
10
10
10
45
2
µA
DD
I
I
Input leakage current
2
V
IN
= V to 5.5V
DD
V
IN
= 0 to V
µA
DD
I
I
I
3-Stated output leakage current
Standby current
OZ
2
V
IN
= V to 5.5V
DD
V
= 3.6V; T = 0°C
amb
25
.5
µA
mA
mA
DDQ
DDD
DD
V
= 3.6V; T
= 0°C @ 1MHz
= 0°C @ 50MHz
amb
DD
amb
1
Dynamic current
V
DD
= 3.6V; T
10
15
1 pin/time for no longer than 1 se-
cond
I
Short circuit output current
–15
5
–100
mA
SC
C
C
C
Input pin capacitance
Clock input capacitance
I/O pin capacitance
T
= 25°C; f = 1MHz
= 25°C; f = 1MHz
= 25°C; f = 1MHz
8
pF
pF
pF
IN
amb
T
12
10
CLK
I/O
amb
T
amb
NOTES:
1. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to V or ground. These
DD
parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where current may be
affected.
2. Does not apply to F7.
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0°C ≤ T
≤ +70°C; 3.0 ≤ V ≤ 3.6V
amb
DD
–B
–D
SYMBOL
PARAMETER
UNIT
MIN.
MAX.
MIN.
MAX.
t
t
t
t
t
t
t
t
t
t
t
t
t
f
f
f
t
t
Input or feedback to non-registered output
Setup time from input, feedback or SP to Clock
Clock to output
15
10
ns
ns
PD
4.5
3.5
SU
10
6
9
4.5
0
ns
CO
CF
1
Clock to feedback
ns
Hold time
0
ns
H
Asynchronous Reset to registered output
Asynchronous Reset width
Asynchronous Reset recovery time
Synchronous Preset recovery time
Width of Clock LOW
17
17
ns
AR
5
5
ns
ARW
ARR
SPR
WL
WH
R
6
6
6
6
ns
ns
3
3
3
3
ns
Width of Clock HIGH
ns
Input rise time
20
20
20
20
ns
Input fall time
ns
F
2
Maximum internal frequency (1/t + t
)
CF
95
69
125
80
MHz
MHz
MHz
ns
MAX1
MAX2
MAX3
EA
SU
1
Maximum external frequency (1/t + t
)
CO
SU
1
Maximum clock frequency (1/t + t
)
WH
167
167
WL
Input to Output Enable
Input to Output Disable
9
9
9
9
ns
ER
Capacitance
C
C
Input pin capacitance
Output capacitance
10
10
10
10
pF
pF
IN
OUT
NOTES:
1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency
may be affected.
2. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to V or ground. These
DD
parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be
affected.
9
1997 Jul 18
Philips Semiconductors
Product specification
3V zero power, TotalCMOS , universal PLD device
P3Z22V10
DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES
Industrial: –40°C ≤ T
≤ +85°C; 3.0 ≤ V ≤ 3.6V
amb
DD
LIMITS
TYP.
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
MIN.
MAX.
0.8
V
V
V
V
V
Input voltage low
V
V
= 3.0V
= 3.6V
V
V
IL
DD
Input voltage high
Input clamp voltage
Output voltage low
Output voltage high
2
IH
I
DD
V
= 3.0V; I = –18mA
–1.2
0.5
V
DD
IN
V
DD
= 3.0V; I = 8mA
V
OL
OH
OL
V
= 3.0V; I = –4mA
2.4
–10
–10
–10
–10
V
DD
OH
V
IN
= 0 to V
10
10
10
10
45
µA
µA
µA
µA
µA
DD
I
I
Input leakage current
2
V
IN
= V to 5.5V
DD
V
IN
= 0 to V
DD
I
I
3-Stated output leakage current
Standby current
OZ
2
V
IN
= V to 5.5V
DD
V
= 3.6V; T = –40°C
amb
30
.5
DDQ
DD
V
= 3.6V; T
= –40°C @
DD
amb
3
mA
mA
mA
1MHz
1
I
Dynamic current
DDD
SC
V
= 3.6V; T
= –40°C @
DD
amb
10
20
50MHz
1 pin/time for no longer than 1 se-
cond
I
Short circuit output current
–15
5
–100
C
C
C
Input pin capacitance
Clock input capacitance
I/O pin capacitance
T
= 25°C; f = 1MHz
= 25°C; f = 1MHz
= 25°C; f = 1MHz
8
pF
pF
pF
IN
amb
T
amb
12
10
CLK
I/O
T
amb
NOTES:
1. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to V or ground. These
DD
parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where current may be
affected.
2. Does not apply to F7.
AC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES
Industrial: –40°C ≤ T
≤ +85°C; 3.0 ≤ V ≤ 3.6V
amb
DD
LIMITS
SYMBOL
PARAMETER
UNIT
MIN.
MAX.
t
t
t
t
t
t
t
t
t
t
t
t
t
f
f
f
t
t
Input or feedback to non-registered output
Setup time from input, feedback or SP to Clock
Clock to output
15
ns
ns
PD
5
SU
10.5
6
ns
CO
CF
1
Clock to feedback
ns
Hold time
0
ns
H
Asynchronous Reset to registered output
Asynchronous Reset width
Asynchronous Reset recovery time
Synchronous Preset recovery time
Width of Clock LOW
17
ns
AR
5
ns
ARW
ARR
SPR
WL
WH
R
6
6
ns
ns
3
3
ns
Width of Clock HIGH
ns
Input rise time
20
20
ns
Input fall time
ns
F
2
Maximum internal frequency (1/t + t
)
91
65
MHz
MHz
MHz
ns
MAX1
MAX2
MAX3
EA
SU
CF
1
Maximum external frequency (1/t + t
)
SU
CO
1
Maximum clock frequency (1/t + t
)
WH
167
WL
Input to Output Enable
Input to Output Disable
11
11
ns
ER
Capacitance
C
C
Input pin capacitance
Output capacitance
10
12
pF
pF
IN
OUT
NOTES:
1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency
may be affected.
2. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to V or ground. These
DD
parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be
affected.
10
1997 Jul 18
Philips Semiconductors
Product specification
3V zero power, TotalCMOS , universal PLD device
P3Z22V10
TEST LOAD CIRCUIT
V
+3.3V
S
1
CC
C
C
2
R
1
1
I
0
F
0
C
R
L
2
DUT
INPUTS
F
I
n
n
OE
CK
GND
NOTE:
C
R
and C are to bypass V to GND.
1
1
2 CC
= 300Ω, R = 300Ω, C = 35pF.
2
L
SP00478
THEVENIN EQUIVALENT
V
L
= 1.65V
150Ω
DUT OUTPUT
35pF
SP00479A
VOLTAGE WAVEFORM
+3.0V
90%
10%
0V
t
R
t
F
1.5ns
1.5ns
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
Input Pulses
SP00368
11
1997 Jul 18
Philips Semiconductors
Product specification
3V zero power, TotalCMOS , universal PLD device
P3Z22V10
SWITCHING WAVEFORMS
INPUT OR
FEEDBACK
INPUT OR
FEEDBACK
V
V
T
T
t
t
t
H
PD
S
COMBINATORIAL
OUTPUT
CLOCK
V
V
T
T
t
CO
REGISTERED
OUTPUT
V
T
Combinatorial Output
Registered Output
INPUT
V
T
t
WH
t
t
ER
EA
CLOCK
V
T
V
– 0.5V
+ 0.5V
OH
OUTPUT
V
T
V
OL
t
WL
Clock Width
Input to Output Disable/Enable
t
ARW
INPUT ASSERTING
ASYNCHRONOUS
RESET
INPUT ASSERTING
SYNCHRONOUS
PRESET
V
V
T
T
t
t
t
t
SPR
AR
S
H
REGISTERED
OUTPUT
CLOCK
V
V
V
T
T
T
t
t
ARR
CO
REGISTERED
OUTPUT
CLOCK
V
T
V
T
Asynchronous Reset
Synchronous Preset
NOTES:
1. V = 1.5V.
T
2. Input pulse amplitude 0V to 3.0V.
3. Input rise and fall times 2.0ns max.
SP00065
“AND” ARRAY – (I, B)
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
P, D
P, D
P, D
P, D
STATE
CODE
STATE
TRUE
CODE
STATE
CODE
STATE
CODE
1
O
H
COMPLEMENT
L
DON’T CARE
—
INACTIVE
SP00008
NOTE:
1. This is the initial state.
12
1997 Jul 18
Philips Semiconductors
Product specification
3V zero power, TotalCMOS , universal PLD
device
P3Z22V10
PLCC28: plastic leaded chip carrer; 28 leads; pedestal
SOT261-3
13
1997 Jul 18
Philips Semiconductors
Product specification
3V zero power, TotalCMOS , universal PLD
device
P3Z22V10
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
14
1997 Jul 18
Philips Semiconductors
Product specification
3V zero power, TotalCMOS , universal PLD
device
P3Z22V10
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
15
1997 Jul 18
Philips Semiconductors
Product specification
3V zero power, TotalCMOS , universal PLD
device
P3Z22V10
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips
Semiconductors
P3Z22V10-DA 相关器件
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| P3Z22V10-DA-T | XILINX | EE PLD, 10ns, PQCC28 | 获取价格 |
|
| P3Z22V10-DD | NXP | 3V zero power, TotalCMOS, universal PLD device | 获取价格 |
|
| P3Z22V10-DD-T | XILINX | EE PLD, 10ns, CMOS, PDSO24, 7.50 MM, PLASTIC, MS-013AD, SOP-24 | 获取价格 |
|
| P3Z22V10-DDH | NXP | 3V zero power, TotalCMOS, universal PLD device | 获取价格 |
|
| P3Z22V10-DDH-T | NXP | EE PLD, 10ns, PDSO24 | 获取价格 |
|
| P3Z22V10IBA | NXP | 3V zero power, TotalCMOS, universal PLD device | 获取价格 |
|
| P3Z22V10IBA-T | NXP | EE PLD, 15ns, PQCC28 | 获取价格 |
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| P3Z22V10IBD | NXP | 3V zero power, TotalCMOS, universal PLD device | 获取价格 |
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| P3Z22V10IBDH | NXP | 3V zero power, TotalCMOS, universal PLD device | 获取价格 |
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| P3Z22V10IBDH-T | XILINX | EE PLD, 15ns, PDSO24 | 获取价格 |
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