P5CD040XD [NXP]

IC SPECIALTY MICROPROCESSOR CIRCUIT, Microprocessor IC:Other;


型号：	P5CD040XD
厂家：	NXP
描述：	IC SPECIALTY MICROPROCESSOR CIRCUIT, Microprocessor IC:Other 外围集成电路
文件：	总20页 (文件大小：151K)
中文：	中文翻译
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P5Cx012/02x/40/73/80/144

family

Secure dual interface and contact PKI smart card controller

Rev. 3.2 — 29 August 2011

136232

Product short data sheet

COMPANY PUBLIC

1. General description

1.1 CMOS14 SmartMX family features overview

The CMOS14 SmartMX family members are a modular set of devices featuring:

• 12 KB to 144 KB EEPROM

• 200 KB user ROM

• 6144 B RAM

• High-performance secure Public Key Infrastructure (PKI) coprocessor (RSA, ECC)

• Secure dual/triple-DES coprocessor

• Secure AES coprocessor

• Memory Management Unit (MMU)

• ISO/IEC 7816 contact interface

• Optional ISO/IEC 14443 A Contactless Interface Unit (CIU)

• Optional S²C interface for NFC communication link

• 5-metal layer 0.14 m CMOS technology

• EEPROM with typically 500000 cycles endurance and a minimum of 25 years

retention time

• Broad spectrum of delivery types

• Optional certified crypto library modules for RSA, ECC, DES, AES, SHA and PRNG

• Optional MIFARE 1K or MIFARE 4K functionality

1.2 CMOS14 SmartMX family properties

The long-established CMOS14 SmartMX family features a significantly enhanced secure

smart card IC architecture. Extended instructions for Java and C code, linear addressing,

high speed at low power and a universal memory management unit are among many

other improvements added to the classic 80C51 core architecture. The technology

transfer step from 5-metal layer 0.18 m to 5-metal layer 0.14 m CMOS technology

offers more advantages in terms of security features, memory resources, crypto

coprocessor calculation speed for RSA and ECC as well as availability of secure

hardware support for 2-key and 3-key Digital Encryption Standard (DES) and Advanced

Encryption Standard (AES) operations.

P5Cx012/02x/40/73/80/144 family

NXP Semiconductors

Secure dual interface and contact PKI smart card controller

The contact interface availability, the optional contactless interface and the optional S²C

interface enable the easy implementation of native or open platform and multi-application

operating systems in market segments such as banking, E-passports, ID cards, Health

cards, secure access, Java cards, Near Field Communication (NFC) connectable mobile

hand sets as well as Trusted Platform Modules (TPM).

1.3 Naming conventions

Table 1.

Naming conventions

P5xyzzz SmartMX platform

Type of category:

C = PKI controller + Triple-DES coprocessor + AES coprocessor on selected products

Interface options:

C = contact interface - ISO/IEC 7816

D = dual interface - ISO/IEC 7816 + ISO/IEC 14443 contactless interface

N = ISO/IEC 7816 + S²C interface for NFC

zzz

Amount of non-volatile memory in KB, increasing count for further product options

1.4 Cryptographic hardware coprocessors

1.4.1 FameXE coprocessor

The approved and modular FameXE architecture supports the trend of increasing RSA

keys with faster execution speeds as well as Elliptic Curve Cryptography (ECC) based on

GF(p) or GF(2ⁿ) at best performance. FameXE supports RSA with an operand length of

up to 8-kbit (up to 4-kbit with intermediate storage in RAM only).

The FameXE PKI coprocessor supports 192-bit ECC key length that offers the same level

of security as 2048-bit RSA. An ECC GF(2ⁿ) based signature, using a 163-bit key can be

executed in less than 30 ms providing a security level comparable to 1024-bit RSA. The

operand size for ECC, supported by FameXE, is only limited by the 2.5 KB size of the

FXRAM. FameXE is easy to use and the flexible interface provides programmers with the

freedom to implement their own cryptography solutions. A secure and CC EAL5+ certified

crypto library providing a large range of required functions will be available for all devices

in order to support customers in implementing public key-based solutions.

1.4.2 Triple-DES coprocessor

The DES widely used for symmetric encryption is supported by a dedicated, high

performance, highly attack-resistant hardware coprocessor. Single DES and triple-DES,

based on two or three DES keys, can be executed within less than 40 s. Relevant

standards (ISO/IEC, ANSI, FIPS) and Message Authentication Code (MAC) are fully

supported. A secure crypto library element for DES is available.

1.4.3 AES coprocessor

SmartMX is the first smart card microcontroller platform to provide a dedicated high

performance 128-bit parallel processing coprocessor to support secure AES. The

implementation is based on FIPS197 as standardized by the National Institute for

Standards and Technology (NIST), and supports key lengths of 128-bit, 192-bit, and

All information provided in this document is subject to legal disclaimers.

Product short data sheet

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Rev. 3.2 — 29 August 2011

136232

2 of 20

P5Cx012/02x/40/73/80/144 family

NXP Semiconductors

Secure dual interface and contact PKI smart card controller

256-bit with performance levels comparable to DES. AES is the next generation for

symmetric data encryption and recommended successor to DES providing a significantly

improved security level. A secure crypto library element for AES is available.

1.5 SmartMX interfaces

1.5.1 SmartMX contact interface

Operating in accordance with ISO/IEC 7816, the SmartMX contact interface is supported

by a built-in Universal Asynchronous Receiver/Transmitter (UART), which enables data

rates of up to 1 Mbit/s allowing for the automatic generation of all typical baud rates and

supports transmission protocols T = 0 and T = 1. Up to two additional I/Os are available.

1.5.2 SmartMX contactless interface

The optional contactless interface is fully compatible with ISO/IEC 14443 A as well as

NXP Semiconductors field proven MIFARE technology. A dedicated Contactless Interface

Unit (CIU) manages and supports communication using data rates up to 848 kbit/s. A true

anti-collision method (in accordance with ISO/IEC 14443-3) enables multiple cards to be

handled simultaneously.

The optional MIFARE functionality provided in configurations B1 (MIFARE 1K

implementation) and B4 (MIFARE 4K implementation) safeguard the interface

compatibility with any installed MIFARE infrastructure. The ability to run the MIFARE

protocol concurrently with other contactless transmission protocols implemented by the

user OS (T=CL or self defined) enables the combination of new services and existing

applications based on MIFARE (e.g. ticketing) on a single dual interface controller based

smart card.

The MIFARE implementation on the SmartMX makes use of the approved true random

number generator and thus is not susceptible to attacks based on the predictability of

random numbers. This emulation is separated from the rest of the SmartMX by a firewall

that is part of the Common Criteria evaluation.

A tutorial software library for ISO/IEC 14443-3 and ISO/IEC 14443-4 is available to

support NXP Semiconductors customers for easy integration of the contactless

technology into current system solutions.

1.5.3 SmartMX S²C interface

The S²C interface is intended for use with NXP Semiconductors NFC circuits (e.g. PN511,

PN531) in order to configure secure NFC systems, for example in mobile hand sets.

Operated both in Contact mode (ISO/IEC 7816) and in S²C mode, the user defines the

final function of the controller chip with its operating system. This allows the same level of

security, functionality and flexibility for the contact interface as well as for the S²C

interface.

The S²C interface is connected to the internal ISO/IEC 14443 CIU. The CIU handles the

demodulation and modulation of the S²C signals which enables full contactless

communication via this interface and the NFC IC. As the S²C interface is connected to the

CIU the power to the P5CN080 and P5CN144 must be supplied via the VDD and VSS

pads in order to use the S²C interface. The S²C interface does not need any software

adaptation compared to normal contactless operation.

All information provided in this document is subject to legal disclaimers.

Product short data sheet

COMPANY PUBLIC

Rev. 3.2 — 29 August 2011

136232

3 of 20

P5Cx012/02x/40/73/80/144 family

NXP Semiconductors

Secure dual interface and contact PKI smart card controller

When connected to the S²C interface of a NFC IC the device is compatible with existing

MIFARE reader infrastructure, and the optional emulation modes of MIFARE 1 K or

MIFARE 4 K enable fast system integration and backward compatibility to MIFARE based

cards. The communication on the S²C interface supports both the ISO/IEC 14443 A part 3

and the ISO/IEC 14443 part 4.

1.6 Security features

SmartMX incorporates a wide range of both inherent and OS-controlled security features

as countermeasure against all types of attack. NXP Semiconductors apply their extensive

knowledge of chip security, combined with handshaking circuit technology, very dense

5-metal layer 0.14 m technology, glue logic and active shielding methodology for

optimum results in CC EAL5+, EMVCo and other third-party certifications and approvals.

SmartMX Memory Management Unit (MMU), designed to define various memory

segments and assign security attributes accordingly, supports a strong firewall concept

that keeps different applications separate from each other. Only the System mode has full

access privileges to all memory space and on-chip peripherals, in User mode the

privileges are limited. User mode restrictions are configurable by software running in

System mode.

The SmartMX security features are acknowledged as having outstanding properties by

most NXP Semiconductors’ customers. The countermeasures against light attacks are

regarded as “best-in-class”.

1.7 Security evaluation and certificates

Hardware security certification in accordance with CC EAL5+ is attained. Also, third-party

approval such as EMVCo (VISA, CAST), ZKA and others, depending on the application

requirements, are available.

NXP Semiconductors continues to drive forward third-party security evaluations to provide

its customers with the relevant information and documentation needed to execute

subsequent composite evaluations of implemented applications.

1.8 Security licensing

In addition to the various intellectual properties regarding attack resistance of the NXP

Semiconductors’ owned SmartMX family, NXP Semiconductors has obtained a patent

license for SPA and DPA countermeasures from Cryptography Research Incorporated

(CRI). This license covers both hardware and software countermeasures. It is important to

customers that countermeasures within the operation system are covered under this

license agreement with CRI. Further details can be obtained on request.

1.9 Optional crypto library

NXP Semiconductors offer an optional crypto library for all family types:

• Various algorithms:

– AES encryption and decryption using the AES coprocessor

– DES and triple-DES encryption and decryption using the DES coprocessor

– RSA encryption and decryption, signature generation and verification for

straightforward and CRT keys up to 5024 bits

All information provided in this document is subject to legal disclaimers.

Product short data sheet

COMPANY PUBLIC

Rev. 3.2 — 29 August 2011

136232

4 of 20

P5Cx012/02x/40/73/80/144 family

NXP Semiconductors

Secure dual interface and contact PKI smart card controller

– RSA key generation

– ECC over GF(p) signature generation and verification (ECDSA) and Diffie-Hellman

key exchange for keys up to 544 bits

– ECC over GF(p) key generation

– ECC over GF(2ⁿ) signature generation and verification (ECDSA) and

Diffie-Hellman key exchange for keys up to 571 bits

– ECC over GF(2ⁿ) key generation

– SHA-1, SHA-224 and SHA-256 hash algorithm

– Pseudo-Random Number Generator (PRNG)

• Easy to use API for all algorithms

• Secure operation in contact as well as in the contactless mode

• Latest built-in security features to avoid power (SPA/DPA), timing and fault attacks

(DFA)

• Common criteria CC EAL5+ certification available [except ECC over GF(2ⁿ)] in

accordance with BSI-PP-0002 protection profile

2. Features and benefits

2.1 Standard family features

 EEPROM: choice of 12 KB, 20 KB, 40 KB, 72 KB, 80 KB or 144 KB

 Data retention time: 25 years minimum

 Endurance: 500000 cycles minimum

 ROM: 200 KB

 RAM: 6144 B

 256 B IRAM + 3.25 KB standard RAM usable for CPU

 2560 B FXRAM usable for FameXE

 Dedicated Secure_MX51 smart card CPU (Memory eXtended/enhanced 80C51)

 5-metal-layer 0.14 m CMOS technology

 Operating in Contact and Contactless mode (dependent on family type option)

 Featuring a 24-bit universal memory space, 24-bit program counter

 Combined universal program and data linear address range up to 16 MB

 Additional instructions to improve:

- pointer operations

- performance

- code density of both C and Java source code

 ISO/IEC 7816 contact interface

 PKI coprocessor FameXE

 Support of major Public Key Cryptography (PKC) systems such as RSA, Elgamel,

DSS, Diffie-Hellman, Guillou-Quisquater, Fiat-Shamir and Elliptic Curves

 8192 bits maximum key length for RSA with randomly chosen modulus

 4096 bits maximum key length for calculation within RAM

 32-bit interface

 Boolean operations for acceleration of standard, symmetric cipher algorithms

All information provided in this document is subject to legal disclaimers.

Product short data sheet

COMPANY PUBLIC

Rev. 3.2 — 29 August 2011

136232

5 of 20

P5Cx012/02x/40/73/80/144 family

NXP Semiconductors

Secure dual interface and contact PKI smart card controller

 High speed Triple-DES coprocessor (64-bit parallel processing DES engine)

 Two or three keys loadable

 DES3 performance < 40 s

 High speed AES coprocessor (128-bit parallel processing AES engine)

 Memory Management Unit (MMU)

 Low power and low voltage design using NXP Semiconductors’ handshaking

technology

 Multiple source vectorized interrupt system with four priority levels

 Watch exception provides software debugging facility

 Multiple source RESET system

 Two 16-bit timers

 Highly reliable EEPROM for both data storage and program execution

 Bytewise EEPROM programming and read access

 Versatile EEPROM programming of 1 B to 64 B at a time or, optionally 1 B to 128 B at

a time

 Typical EEPROM page erasing time: 1.7 ms

 Typical EEPROM page programming time: 1.0 ms

 Power-saving Idle mode

 Wake-up from Idle mode by RESET or any activated interrupt

 Power-saving Sleep (power-down) mode or Clockstop mode

 Wake-up from Sleep or Clockstop mode by RESET or external interrupt

 Contact configuration and serial interface in accordance with ISO/IEC 7816: GND,

VDD, CLK, RST_N, IO1

 ISO/IEC 7816 UART supporting standard protocols T = 0 and T = 1 as well as high

speed personalization up to 1 Mbit/s

 External or internally generated configurable CPU clock

 1 MHz to 10 MHz operating external clock frequency range

 Internal CPU clock up to 30 MHz with synchronous operation

 Internal clocking independent of externally applied frequency

 High speed 16-bit CRC engine in accordance with ITU-T polynomial definition

 Low power Random Number Generator (RNG) in hardware, AIS-31 compliant

 1.62 V to 5.5 V extended operating voltage range for class C, B and A

 Optional extended Class B operation mode (targeted for battery supplied applications)

 25 C to +85 C ambient temperature

 Broad spectrum of delivery types:

 Wafers

 Modules

2.2 Product specific family features

 P5CC021, P5CC040, P5CC073, P5CC080 and P5CC144

 ISO/IEC 7816 contact interface

 Two additional I/O ports: IO2 and IO3 for full-duplex serial data communication

 P5CD012, P5CD020, P5CD040, P5CD080 and P5CD144

 CIU fully compatible with ISO/IEC 14443A:

- 13.56 MHz operating frequency

All information provided in this document is subject to legal disclaimers.

Product short data sheet

COMPANY PUBLIC

Rev. 3.2 — 29 August 2011

136232

6 of 20

P5Cx012/02x/40/73/80/144 family

NXP Semiconductors

Secure dual interface and contact PKI smart card controller

- fully supports the T = CL protocol in accordance with ISO/IEC 14443-4

- supported data transfer rates: 106 kbit/s, 212 kbit/s, 424 kbit/s and 848 kbit/s

- MIFARE reader infrastructure compatibility via optional MIFARE 1 K or 4 K

emulation including built-in anticollision support

 Two additional I/O ports: IO2 and IO3 for full-duplex serial data communication

 P5CN080 and P5CN144

 S²C interface

 One additional I/O port: IO2 for full-duplex serial data communication

2.3 Security features

 Enhanced security sensors:

 Low and high clock frequency sensor

 Low and high temperature sensor

 Low and high supply voltage sensor

 Single Fault Injection (SFI) attack detection

 Light sensors (included integrated memory light sensor functionality)

 Electronic fuses for safeguarded mode control

 Active shielding

 Unique ID for each die

 Clock input filter for protection against spikes

 Power-up and power-down reset

 Optional programmable card disable feature

 Memory security (encryption and physical measures) for RAM, EEPROM and ROM

 Memory Management Unit (MMU) including memory protection:

 Secure multi-application operating systems via two different operation modes:

System mode and User mode

 OS-controlled access restriction mechanism to peripherals in User mode

 Memory mapping up to 8 MB code memory

 Memory mapping up to 8 MB (64-kbit) data memory

 Optional disabling of ROM read instructions by code executed in EEPROM

 Optional disabling of any code execution out of RAM

 EEPROM programming:

 No external clock

 Hardware sequencer controlled

 On-chip high voltage generation

 Enhanced error correction mechanism

 64 B or 128 B EEPROM for customer-defined security FabKey, featuring batch-,

wafer- or die-individual security data, included encrypted diversification features on

request

 14 B user write-protected security area in EEPROM (byte access, inhibit functionality

per byte)

 32 B write-once security area in EEPROM (bit access)

 32 B user read-only area in EEPROM (byte access)

 Customer-specific EEPROM initialization available

All information provided in this document is subject to legal disclaimers.

Product short data sheet

COMPANY PUBLIC

Rev. 3.2 — 29 August 2011

136232

7 of 20

P5Cx012/02x/40/73/80/144 family

NXP Semiconductors

Secure dual interface and contact PKI smart card controller

2.4 Design-in support

 Approved development tool chain:

 Keil PK51 development tool package including Vision3/dScope C51 simulator,

additional specific hardware drivers including simulation of contactless interface

and ISO/IEC 7816 card interface board. A SmartMX DBox allows software

debugging and integration tests.

 Ashling Ultra-Emulator platform, stand-alone ROM prototyping boards and

ISO/IEC 7816 and ISO/IEC 14443 card interface board. Code coverage and

performance measurement software tools for real-time software testing.

 Dual interface dummy modules OM6711 (PDM 1.1 - SOT658) with special antenna

bonding on C4 and C8 for testing the implanting process and antenna connection.

 Tutorial C source libraries for:

 contactless communication in accordance with ISO/IEC 14443, Part 3 and 4

 T = 1 communication in accordance with ISO/IEC 7816, Part 3

 EEPROM Read/Write routines

3. Applications

3.1 Application areas

 Banking

 Java cards

 E-passports

 ID cards

 Secure access

 Trusted platform modules

All information provided in this document is subject to legal disclaimers.

Product short data sheet

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Rev. 3.2 — 29 August 2011

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P5Cx012/02x/40/73/80/144 family

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Secure dual interface and contact PKI smart card controller

4. Quick reference data

Table 2.

Symbol

V_DD

Quick reference data

Parameter

Conditions

Min

4.5

Typ

5.0

3.0

1.8

Max

5.5

Unit

supply voltage

Class A: 5 V range

Class B: 3 V range

Class BE: 3 V range

Class C: 1.8 V range

2.7

3.3

[1]

2.2

3.3

1.62

1.98

EEPROM characteristics

t_ret

retention time

T_amb= +55 C

years

(EEPROM data)

write endurance

N_endu(W)

under all operating

conditions

5  10⁵

cycles

[1] In extended Class B (Class BE) operation mode (targeted for battery powered applications), Class C is not supported.

5. Ordering information

Table 3.

Ordering information

Type number

Package

Name

FFC

Description

Version

P5CC021UA

P5CC040UA

P5CC073UA

P5CC080UA

P5CC144UA

P5CD012UA

P5CD020UA

P5CD040UA

P5CD080UA

P5CD144UA

P5CN080UA

P5CN144UA

P5CD012UE

P5CD020UE

P5CD040UE

P5CD080UE

P5CD144UE

P5CC021TS

P5CC040TS

P5CC073TS

P5CC080TS

P5CC144TS

8 inch wafer (sawn; 150 m thickness; on film frame carrier;

electronic fail die marking according to SECSII format)

not applicable

FFC

8 inch wafer (sawn; 75 m thickness; on film frame carrier;

electronic fail die marking according to SECSII format)

not applicable

SOT266-1

SSOP20

plastic shrink small outline package; 20 leads; body width 4.4 mm

All information provided in this document is subject to legal disclaimers.

Product short data sheet

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Secure dual interface and contact PKI smart card controller

Table 3.

Ordering information …continued

Type number

Package

Name

Description

Version

P5CC021HN

P5CC040HN

P5CC073HN

P5CC080HN

P5CC144HN

P5CN080HN

P5CN144HN

P5CD012A4

P5CD020A4

P5CD040A4

P5CD080A4

P5CD144A4

P5CD012A6

P5CD020A6

P5CD040A6

P5CD080A6

P5CD144A6

P5CC021XS

P5CC040XS

P5CC073XS

P5CC080XS

P5CC144XS

P5CC021XD

P5CC040XD

P5CC080XD

P5CC144XD

P5CD012X1

P5CD020X1

P5CD040X1

P5CD080X1

P5CD144X1

P5CD012X0

P5CD020X0

P5CD040X0

P5CD080X0

P5CD144X0

HVQFN32

plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5  5  0.85 mm

SOT617-1

MOB4

MOB6

PCM1.1

contactless chip card module (super 35 mm tape format, module

thickness 320 m)

SOT500-2

SOT500-3

SOT658-1

contactless chip card module (super 35 mm tape format, module

thickness 250 m)

contact chip card module (super 35 mm tape format, 8-contact)

Pd-PCM1.1

PDM1.1

palladium plated contact chip card module (super 35 mm tape

format, 8-contact)

SOT658-1

SOT658-3

dual interface chip card module (Plug-in type; super 35 mm tape

format, 8-contact)

PDM1.1

dual interface chip card module (super 35 mm tape format,

8-contact)

SOT658-3

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Table 3.

Ordering information …continued

Type number

Package

Name

Description

Version

P5CD012XD

P5CD020XD

P5CD040XD

P5CD080XD

P5CD144XD

P5CC073XI

P5CD080XI

P5CD144XI

Pd-PDM1.1

palladium plated dual interface chip card module (super 35 mm tape SOT658-3

format, 8-contact)

P-M8.4-8-1

dual interface chip card module (super 35 mm tape format,

8-contact)

SOT708

Table 4.

Feature table

Product EEPROM User

Total CXRAM FXRAM

Coprocessor

FameXE DES

ISO/IEC 7816 Interface option

IO pads

type

[KB]

ROM

[KB]

RAM

[KB]

AES

P5CD012

P5CC021

P5CD020

P5CC040

P5CD040

P5CC073

P5CN080

200

3.5

2.5

yes

dual interface

contact

dual interface

contact

dual interface

contact

contact + S²C

interface for NFC

P5CC080

P5CD080

P5CN144

200

3.5

2.5

yes

contact

dual interface

contact + S²C

144

interface for NFC

P5CC144

P5CD144

144

200

3.5

2.5

yes

contact

dual interface

All information provided in this document is subject to legal disclaimers.

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6. Functional diagram

ROM

EEPROM

RAM

P5CC021 P5CC040 P5CC073 P5CC080

P5CC144

20 KB/40 KB/

72 KB/80 KB/

144 KB

DATA AND

PROGRAM

MEMORY

200 KB

PROGRAM

MEMORY

6144 B

DATA

MEMORY

FameXE

ENHANCED PUBLIC

KEY

COPROCESSOR e.g.

RSA, ECC

IO1

IO2

IO3

PROGRAMMABLE

UART

IO1, IO2, IO3

ISO 7816

MEMORY MANAGEMENT UNIT (MMU)

CLOCK

FILTER

CLOCK

GENERATION

CLK

SECURE_MX51 CPU

TRIPLE-DES

COPROCESSOR

AES

COPROCESSOR

TIMERS

SECURITY SENSORS

RESET GENERATION

RST_N

FAST

CRC16

RNG

16-bit 16-bit

VOLTAGE REGULATOR

VDD

VSS

001aae954

Fig 1. Functional diagram P5CC021/P5CC040/P5CC073/P5CC080/P5CC144

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

P5CD012 P5CD020 P5CD040 P5CD080 P5CD144

ROM

EEPROM

RAM

CIU

INTERFACE

ISO 14443

12 KB/ 20 KB/

40 KB/ 80 KB/

144 KB

DATA AND

PROGRAM

MEMORY

200 KB

PROGRAM

MEMORY

6144 B

DATA

MEMORY

FameXE

ENHANCED PUBLIC

KEY

IO1

IO2

IO3

PROGRAMMABLE

IO1, IO2, IO3

UART

ISO 7816

COPROCESSOR e.g.

RSA, ECC

MEMORY MANAGEMENT UNIT (MMU)

CLOCK

FILTER

CLOCK

GENERATION

CLK

SECURE_MX51 CPU

TRIPLE-DES

COPROCESSOR

AES

COPROCESSOR

TIMERS

SECURITY SENSORS

RESET GENERATION

RST_N

FAST

CRC16

RNG

16-bit 16-bit

VOLTAGE REGULATOR

VDD

VSS

001aae953

Fig 2. Functional diagram P5CD012/P5CD020/P5CD040/P5CD080/P5CD144

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

P5CN080 P5CN144

SIGIN

ROM

EEPROM

RAM

S C

CIU

INTERFACE

ISO 14443

SIGOUT

80 KB/

144 KB

DATA AND

PROGRAM

MEMORY

200 KB

PROGRAM

MEMORY

6144 B

DATA

MEMORY

FameXE

ENHANCED PUBLIC

KEY

COPROCESSOR e.g.

RSA, ECC

IO1

IO2

PROGRAMMABLE

IO1, IO2

UART

ISO 7816

MEMORY MANAGEMENT UNIT (MMU)

CLOCK

FILTER

CLOCK

GENERATION

CLK

SECURE_MX51 CPU

TRIPLE-DES

COPROCESSOR

AES

COPROCESSOR

TIMERS

SECURITY SENSORS

RESET GENERATION

RST_N

FAST

CRC16

RNG

16-bit 16-bit

VOLTAGE REGULATOR

VDD

VSS

001aae955

Fig 3. Functional diagram P5CN080/P5CN144

P5Cx012/02x/40/73/80/144 family

NXP Semiconductors

Secure dual interface and contact PKI smart card controller

7. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to

V_SS(ground = 0 V).

Symbol Parameter

Conditions

Min

0.5

Max

Unit

V_DD

V_I

supply voltage

input voltage

input current

+6.0

any signal pad

V_DD+ 0.5

15.0

I_I

pad IO1, IO2 or

IO3

I_O

output current

pad IO1, IO2 or

IO3

15.0

100

4.0

I_lu

latch-up current

V_I< 0 V

or V_I> V_DD

[1]

V_ESD

electrostatic discharge voltage pads VDD, VSS,

CLK, RST_N, IO1,

IO2, IO3

[1]

[2]

[3]

pads LA, LB

total power dissipation

2.0

P_tot

T_stg

storage temperature

C

[1] MIL Standard 883-D method 3015; human body model; C = 100 pF, R = 1.5 k; T_amb= 25 C to +85 C.

[2] Depending on appropriate thermal resistance of the package.

[3] Depending on delivery type, refer to NXP Semiconductors General Specification for 8 ” Wafers and to NXP

Semiconductors Contact & Dual Interface Chip Card Module Specification.

8. Abbreviations

Table 6.

Abbreviations

Description

Acronym

AES

Advanced Encryption Standard

Automatic Identification System

Application Programming Interface

Amplitude Shift Keying

AIS

API

ASK

Common Criteria

CIU

Contactless Interface Unit

CRC

CRT

Cyclic Redundancy Check

Chinese Remainder Theorem

Digital Encryption Standard

DES

DFA

Differential Fault Analysis

DPA

Differential Power Analysis

DSS

Digital Signature Standard

ECC

ECDSA

EEPROM

FIPS

Elliptic Curve Cryptography

Elliptic Curve Digital Signature Algorithm

Electrically Erasable Programmable Read-Only Memory

Federal Information Processing Standard

All information provided in this document is subject to legal disclaimers.

Product short data sheet

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Table 6.

Abbreviations …continued

Acronym

Description

IDentifier

I/O

Input/Output

IRAM

Intelligent Random Access Memory

Galois Function

MAC

MMU

NFC

Message Authentication Code

Memory Management Unit

Near Field Communication

Operating System

PKC

PKI

Public Key Cryptography

Public Key Infrastructure

Pseudo-Random Number Generator

Random Number Generator

Rivest, Shamir and Adleman

SigIn-SigOut-Connection

Single Fault Injection

PRNG

RNG

RSA

S²C

SFI

SHA

SMD

SPA

TPM

UART

Secure Hash Algorithm

Surface Mounted Device

Simple Power Analysis

Trusted Platform Module

Universal Asynchronous Receiver/Transmitter

All information provided in this document is subject to legal disclaimers.

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9. Revision history

Table 7.

Revision history

Document ID

Release date Data sheet status

Change notice Supersedes

P5CX012_02X_40_73_80_

144_FAM_SDS_3.1

P5CX012_02X_40_73_80_ 20110829

144_FAM_SDS_3.2

Product short data sheet

Modifications:

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Document version number revised

• Section Section 1.5.2: corrected MIFARE emulation to MIFARE implementation

• corrected endurance 500 000 typical to 500 000 minimum

• added SSOP package in ordering information

• added new Trademark

• corrected MIFARE emulation to MIFARE implementation

• corrected endurance 500 000 typical to 500 000 minimum

• added SSOP package in ordering information

• added new Trademark

P5CX012_02X_40_73_80_ 20100615

144_FAM_SDS_3.1

Product short data sheet

P5CX012_02X_40_73_80_

144_FAM_SDS_1.2

Modifications:

• Section 1.1: Retention time changed to 25 years and added new bullet item.

• Section 1.2: Second paragraph updated.

• Section 1.6: Second paragraph updated, added last paragraph.

• Section 1.8: New section.

• Section 2.1: Retention time changed to 25 years and changed minimum number of

cycles to 500000.

• Section 2.2: Product features for types P5CD012, P5CD020, P5CD040, P5CD080 and

P5CD144 updated.

• Section 2.4: Last bullet item updated.

• Section 10.5: Trademarks added.

P5CX012_02X_40_73_80_ 20080124

144_FAM_SDS_1.2

Objective short data sheet

P5CX02X_40_73_80_144_

FAM_SDS_1.1

P5CX02X_40_73_80_144_ 20070424

FAM_SDS_1.1

P5CX02X_40_80_144_FAM

_SDS_1.0

P5CX02X_40_80_144_FAM 20070216

_SDS_1.0

All information provided in this document is subject to legal disclaimers.

Product short data sheet

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10. Legal information

10.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

10.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

10.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

All information provided in this document is subject to legal disclaimers.

Product short data sheet

COMPANY PUBLIC

Rev. 3.2 — 29 August 2011

136232

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NXP Semiconductors

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Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

10.4 Licenses

ICs with DPA Countermeasures functionality

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

NXP ICs containing functionality

implementing countermeasures to

Differential Power Analysis and Simple

Power Analysis are produced and sold

under applicable license from

non-automotive qualified products in automotive equipment or applications.

Cryptography Research, Inc.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

10.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

FabKey — is a trademark of NXP B.V.

MIFARE — is a trademark of NXP B.V.

SmartMX — is a trademark of NXP B.V.

11. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

All information provided in this document is subject to legal disclaimers.

Product short data sheet

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12. Tables

Table 1. Naming conventions . . . . . . . . . . . . . . . . . . . . .2

Table 2. Quick reference data . . . . . . . . . . . . . . . . . . . . .9

Table 3. Ordering information . . . . . . . . . . . . . . . . . . . . .9

Table 4. Feature table . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 5. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 7. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17

13. Figures

Fig 1. Functional diagram P5CC021/

P5CC040/P5CC073/

P5CC080/P5CC144. . . . . . . . . . . . . . . . . . . . . . .12

Fig 2. Functional diagram P5CD012/

P5CD020/P5CD040/

P5CD080/P5CD144 . . . . . . . . . . . . . . . . . . . . . . 13

Fig 3. Functional diagram P5CN080/P5CN144 . . . . . . 14

14. Contents

1.1

1.2

1.3

General description. . . . . . . . . . . . . . . . . . . . . . 1

CMOS14 SmartMX family features overview . . 1

CMOS14 SmartMX family properties . . . . . . . . 1

Naming conventions . . . . . . . . . . . . . . . . . . . . . 2

Cryptographic hardware coprocessors. . . . . . . 2

FameXE coprocessor. . . . . . . . . . . . . . . . . . . . 2

Triple-DES coprocessor . . . . . . . . . . . . . . . . . . 2

AES coprocessor . . . . . . . . . . . . . . . . . . . . . . . 2

SmartMX interfaces . . . . . . . . . . . . . . . . . . . . . 3

SmartMX contact interface . . . . . . . . . . . . . . . . 3

SmartMX contactless interface. . . . . . . . . . . . . 3

SmartMX S²C interface . . . . . . . . . . . . . . . . . . 3

Security features. . . . . . . . . . . . . . . . . . . . . . . . 4

Security evaluation and certificates . . . . . . . . . 4

Security licensing . . . . . . . . . . . . . . . . . . . . . . . 4

Optional crypto library. . . . . . . . . . . . . . . . . . . . 4

10.1

10.2

10.3

10.4

10.5

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.4

1.4.1

1.4.2

1.4.3

1.5

1.5.1

1.5.2

1.5.3

1.6

Contact information . . . . . . . . . . . . . . . . . . . . 19

Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.7

1.8

1.9

Features and benefits . . . . . . . . . . . . . . . . . . . . 5

Standard family features. . . . . . . . . . . . . . . . . . 5

Product specific family features . . . . . . . . . . . . 6

Security features. . . . . . . . . . . . . . . . . . . . . . . . 7

Design-in support . . . . . . . . . . . . . . . . . . . . . . . 8

2.1

2.2

2.3

2.4

3.1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Application areas . . . . . . . . . . . . . . . . . . . . . . . 8

Quick reference data . . . . . . . . . . . . . . . . . . . . . 9

Ordering information. . . . . . . . . . . . . . . . . . . . . 9

Functional diagram . . . . . . . . . . . . . . . . . . . . . 12

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17

Legal information. . . . . . . . . . . . . . . . . . . . . . . 18

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 29 August 2011

136232

P5CD040XD [NXP]

相关型号：

P5CD041

P5CD041A4

P5CD041A6

P5CD041AI

P5CD041UA

P5CD041UE

P5CD041X0

P5CD041X1

P5CD041XD

P5CD041XE

P5CD051

P5CD051A4