P80C31SBAA,112 [NXP]
80C31/80C32 - 80C51 8-bit microcontroller family 128/256 byte RAM ROMless low voltage (2.7 V-5.5 V), low power, high speed (33 MHz) LCC 44-Pin;型号: | P80C31SBAA,112 |
厂家: | NXP |
描述: | 80C31/80C32 - 80C51 8-bit microcontroller family 128/256 byte RAM ROMless low voltage (2.7 V-5.5 V), low power, high speed (33 MHz) LCC 44-Pin |
文件: | 总32页 (文件大小:224K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz)
Product specification
IC28 Data Handbook
2000 Aug 07
Philips
Semiconductors
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
DESCRIPTION
FEATURES
The Philips 80C31/32 is a high-performance static 80C51 design
fabricated with Philips high-density CMOS technology with operation
from 2.7 V to 5.5 V.
• 8051 Central Processing Unit
– 128 × 8 RAM (80C31)
– 256 × 8 RAM (80C32)
– Three 16-bit counter/timers
– Boolean processor
The 80C31/32 ROMless devices contain a 128 × 8 RAM/256 × 8
RAM, 32 I/O lines, three 16-bit counter/timers, a six-source,
four-priority level nested interrupt structure, a serial I/O port for
either multi-processor communications, I/O expansion or full duplex
UART, and on-chip oscillator and clock circuits.
– Full static operation
– Low voltage (2.7 V to 5.5 V@ 16 MHz) operation
In addition, the device is a low power static design which offers a
wide range of operating frequencies down to zero. Two software
selectable modes of power reduction—idle mode and power-down
mode are available. The idle mode freezes the CPU while allowing
the RAM, timers, serial port, and interrupt system to continue
functioning. The power-down mode saves the RAM contents but
freezes the oscillator, causing all other chip functions to be
inoperative. Since the design is static, the clock can be stopped
without loss of user data and then the execution resumed from the
point the clock was stopped.
• Memory addressing capability
– 64k ROM and 64k RAM
• Power control modes:
– Clock can be stopped and resumed
– Idle mode
– Power-down mode
• CMOS and TTL compatible
• TWO speed ranges at V = 5 V
CC
– 0 to 16 MHz
SELECTION TABLE
For applications requiring more ROM and RAM, see the 8XC54/58
– 0 to 33 MHz
and 8XC51RA+/RB+/RC+/80C51RA+ data sheet.
• Three package styles
• Extended temperature ranges
• Dual Data Pointers
ROM/EPROM
Memory Size
(X by 8)
RAM Size
(X by 8)
Programmable
Timer Counter
(PCA)
Hardware
Watch Dog
Timer
80C31/8XC51
• 4 level priority interrupt
• 6 interrupt sources
0K/4K
128
No
No
No
No
80C32/8XC52/54/58
• Four 8-bit I/O ports
0K/8K/16K/32K
256
• Full–duplex enhanced UART
– Framing error detection
80C51RA+/8XC51RA+/RB+/RC+
– Automatic address recognition
0K/8K/16K/32K
8XC51RD+
64K
512
Yes
Yes
Yes
Yes
• Programmable clock out
• Asynchronous port reset
1024
• Low EMI (inhibit ALE)
• Wake-up from Power Down by an external interrupt
2
2000 Aug 07
853–2213 24293
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
80C51/87C51 AND 80C31 ORDERING INFORMATION
TEMPERATURE RANGE °C
VOLTAGE
RANGE
FREQ.
(MHz)
DRAWING
NUMBER
ROMless
AND PACKAGE
P80C31SBPN
P80C31SBAA
P80C31SBBB
P80C31SFPN
P80C31SFA A
P80C31SFBB
0 to +70, Plastic Dual In-line Package
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Plastic Quad Flat Pack
2.7 V to 5.5 V
2.7 V to 5.5 V
2.7 V to 5.5 V
2.7 V to 5.5 V
2.7 V to 5.5 V
2.7 V to 5.5 V
0 to 16
0 to 16
0 to 16
0 to 16
0 to 16
0 to 16
SOT129-1
SOT187-2
SOT307-2
SOT129-1
SOT187-2
SOT307-2
–40 to +85, Plastic Dual In-line Package
–40 to +85, Plastic Leaded Chip Carrier
–40 to +85, Plastic Quad Flat Pack
PART NUMBER DERIVATION
DEVICE NUMBER
OPERATING FREQUENCY, MAX (S)
TEMPERATURE RANGE (B)
B = 0_ to +70_C
PACKAGE (AA)
P80C31
S = 16 MHz
AA = PLCC
BB = PQFP
PN = PDIP
P80C32
U = 33 MHz
F = –40_C to +85_C
80C32 ORDERING INFORMATION
TEMPERATURE RANGE °C
FREQ
MHz
DRAWING
NUMBER
ROMless
AND PACKAGE
P80C32SBP N
P80C32SBA A
P80C32SBB B
P80C32SFP N
P80C32SFA A
P80C32SFB B
P80C32UBA A
P80C32UBP N
P80C32UBB B
P80C32UFA A
P80C32UFP N
P80C32UFB B
0 to +70, Plastic Dual In-line Package
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Plastic Quad Flat Pack
16
16
16
SOT129-1
SOT187-2
SOT307-2
SOT129-1
SOT187-2
SOT307-2
SOT187-2
SOT129-1
SOT307-2
SOT187-2
SOT129-1
SOT307-2
–40 to +85, Plastic Dual In-line Package
–40 to +85, Plastic Leaded Chip Carrier
–40 to +85, Plastic Quad Flat Pack
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Plastic Dual In-line Package
0 to +70, Plastic Quad Flat Pack
16
16
16
33
33
33
33
33
33
–40 to +85, Plastic Leaded Chip Carrier
–40 to +85, Plastic Dual In-line Package
–40 to +85, Plastic Quad Flat Pack
3
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
BLOCK DIAGRAM
P0.0–P0.7
P2.0–P2.7
PORT 0
DRIVERS
PORT 2
DRIVERS
V
CC
V
SS
RAM ADDR
REGISTER
PORT 0
LATCH
PORT 2
LATCH
ROM/EPROM
RAM
8
B
STACK
POINTER
ACC
REGISTER
PROGRAM
ADDRESS
REGISTER
TMP1
TMP2
BUFFER
ALU
SFRs
PC
INCRE-
MENTER
TIMERS
PSW
8
16
PROGRAM
COUNTER
PSEN
ALE/PROG
DPTR’S
MULTIPLE
TIMING
AND
CONTROL
EAV
PP
RST
PORT 1
LATCH
PORT 3
LATCH
PD
OSCILLATOR
PORT 1
DRIVERS
PORT 3
DRIVERS
XTAL1
XTAL2
P1.0–P1.7
P3.0–P3.7
SU00845
4
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
LOGIC SYMBOL
PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS
6
1
40
V
V
SS
CC
XTAL1
7
39
ADDRESS AND
DATA BUS
LCC
XTAL2
RST
17
29
T2
T2EX
18
28
EA/V
PP
PSEN
Pin Function
Pin Function
Pin Function
ALE/PROG
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P2.7/A15
PSEN
ALE
NIC*
EA/V
PP
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NIC*
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
RxD
TxD
INT0
INT1
T0
T1
WR
RD
ADDRESS BUS
SU00830
XTAL1
V
SS
NIC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
V
CC
PIN CONFIGURATIONS
* NO INTERNAL CONNECTION
SU01062
T2/P1.0
40
39
V
CC
1
2
3
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
T2EX/P1.1
P0.0/AD0
P1.2
P1.3
P1.4
38 P0.1/AD1
37
44
34
4
5
P0.2/AD2
36 P0.3/AD3
35
1
33
P1.5
P1.6
P1.7
RST
6
7
8
9
P0.4/AD4
34 P0.5/AD5
33
PQFP
P0.6/AD6
11
23
32 P0.7/AD7
DUAL
IN-LINE
PACKAGE
31 EA/V
PP
RxD/P3.0 10
TxD/P3.1 11
INT0/P3.2 12
12
22
30 ALE
Pin Function
Pin Function
Pin Function
29
PSEN
28 P2.7/A15
27
1
2
P1.5
P1.6
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
NIC*
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
SS
13
INT1/P3.3
3
P1.7
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
NIC*
EA/V
P0.7/AD7
P2.6/A14
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
XTAL1 19
4
RST
5
6
P3.0/RxD
NIC*
26 P2.5/A13
25 P2.4/A12
7
8
9
10
11
12
13
14
15
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
V
CC
NIC*
24
P2.3/A11
23 P2.2/A10
22
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
P2.1/A9
21 P2.0/A8
PP
V
20
SS
* NO INTERNAL CONNECTION
SU01063
SU01064
5
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC DIP
LCC
22
QFP
16
TYPE NAME AND FUNCTION
V
SS
V
CC
20
40
I
I
Ground: 0 V reference.
44
38
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
P0.0–0.7
39–32 43–36 37–30
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port with Schmitt trigger inputs. Port 0 pins
that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also
the multiplexed low-order address and data bus during accesses to external program and
data memory. In this application, it uses strong internal pull-ups when emitting 1s.
P1.0–P1.7
1–8
2–9
40–44,
1–3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger
inputs. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 1 pins that are externally pulled low will source
current because of the internal pull-ups. (See DC Electrical Characteristics: I ). Alternate
IL
functions for Port 1 include:
1
2
2
3
40
41
I/O
I
T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable Clock-Out)
T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control
P2.0–P2.7
21–28 24–31 18–25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger
inputs. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source
current because of the internal pull-ups. (See DC Electrical Characteristics: I ). Port 2 emits
IL
the high-order address byte during fetches from external program memory and during
accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this
application, it uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2
special function register.
P3.0–P3.7
10–17
11,
5,
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger
inputs. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source
13–19 7–13
current because of the pull-ups. (See DC Electrical Characteristics: I ). Port 3 also serves
IL
the special features of the 80C51 family, as listed below:
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
I
O
I
I
I
I
O
O
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
9
10
11
12
13
RST
ALE
9
10
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V permits a power-on reset using only an external
SS
capacitor to V
.
CC
30
33
27
O
Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or clocking. Note that one ALE
pulse is skipped during each access to external data memory. ALE can be disabled by
setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.
PSEN
29
31
32
35
26
29
O
I
Program Store Enable: The read strobe to external program memory. When the 80C31/32
is executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program memory.
EA/V
External Access Enable/Programming Supply Voltage: EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H to
0FFFH.
PP
XTAL1
19
18
21
20
15
14
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2
O
Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V + 0.5 V or V – 0.5 V, respectively.
CC
SS
6
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
Table 1.
8XC51/80C31 Special Function Registers
DIRECT
ADDRESS
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
LSB
E0
RESET
VALUE
SYMBOL
DESCRIPTION
MSB
E7
–
ACC*
AUXR#
AUXR1#
B*
Accumulator
E0H
8EH
A2H
F0H
E6
–
E5
–
E4
–
E3
–
E2
–
E1
–
00H
Auxiliary
AO
DPS
F0
xxxxxxx0B
xxx000x0B
00H
2
Auxiliary 1
B register
–
–
–
–
WUPD
F3
0
–
F7
F6
F5
F4
F2
F1
DPTR:
DPH
DPL
Data Pointer (2 bytes)
Data Pointer High
Data Pointer Low
83H
82H
00H
00H
AF
EA
BF
–
AE
–
AD
ET2
BD
AC
ES
BC
PS
B4
AB
ET1
BB
AA
EX1
BA
A9
ET0
B9
A8
EX0
B8
IE*
Interrupt Enable
Interrupt Priority
Interrupt Priority High
Port 0
A8H
B8H
B7H
80H
90H
A0H
B0H
87H
0x000000B
xx000000B
xx000000B
FFH
BE
–
IP*
PT2
B5
PT1
B3
PX1
B2
PT0
B1
PX0
B0
B7
–
B6
–
IPH#
P0*
P1*
P2*
P3*
PT2H
85
PSH
84
PT1H
83
PX1H PT0H
PX0H
80
87
86
82
AD2
92
81
AD1
91
AD7
97
AD6
96
AD5
95
AD4
94
AD3
93
AD0
90
Port 1
–
–
–
–
–
–
T2EX
A1
T2
FFH
A7
AD15
B7
RD
A6
AD14
B6
WR
A5
A4
A3
A2
A0
Port 2
AD13
B5
AD12
B4
AD11
B3
AD10
B2
AD9
B1
AD8
B0
FFH
Port 3
T1
T0
INT1
INT0
TxD
RxD
FFH
1
PCON#
Power Control
Program Status Word
SMOD1
D7
SMOD0
D6
–
POF
D4
GF1
D3
GF0
D2
PD
D1
–
IDL
D0
P
00xx0000B
D5
F0
PSW*
D0H
CBH
CAH
A9H
B9H
99H
CY
AC
RS1
RS0
OV
000000x0B
00H
00H
RACAP2H# Timer 2 Capture High
RACAP2L#
SADDR#
SADEN#
SBUF
Timer 2 Capture Low
Slave Address
Slave Address Mask
Serial Data Buffer
00H
00H
xxxxxxxxB
9F
9E
9D
9C
9B
9A
99
TI
98
RI
SM0/FE
SCON*
SP
Serial Control
Stack Pointer
98H
81H
SM1
SM2
REN
TB8
RB8
00H
07H
8F
TF1
CF
TF2
–
8E
TR1
CE
8D
TF0
CD
8C
TR0
CC
8B
IE1
CB
8A
IT1
CA
TR2
–
89
IE0
88
IT0
C8
TCON*
Timer Control
88H
00H
C9
T2CON*
Timer 2 Control
C8H
EXF2
–
RCLK
–
TCLK
–
EXEN2
–
C/T2
T2OE
CP/RL2 00H
DCEN xxxxxx00B
T2MOD#
TH0
TH1
TH2#
TL0
TL1
Timer 2 Mode Control
Timer High 0
Timer High 1
Timer High 2
Timer Low 0
C9H
8CH
8DH
CDH
8AH
8BH
CCH
00H
00H
00H
00H
00H
00H
Timer Low 1
Timer Low 2
TL2#
TMOD
Timer Mode
89H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
NOTE:
Unused register bits that are not defined should not be set by the user’s program. If violated, the device could function incorrectly.
*
SFRs are bit addressable.
#
–
SFRs are modified from or added to the 80C51 SFRs.
Reserved bits.
1. Reset value depends on reset source.
2. Not available on 80C31.
7
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
For the 80C31 or 80C32, either a hardware reset or external
OSCILLATOR CHARACTERISTICS
interrupt can be used to exit from Power Down. Reset redefines all
the SFRs but does not change the on-chip RAM. An external
interrupt allows both the SFRs and the on-chip RAM to retain their
values. WUPD (AUXR1.3–Wakeup from Power Down) enables or
disables the wakeup from power down with external interrupt.
Where:
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
WUPD = 0 Disable
WUPD = 1 Enable
To properly terminate Power Down the reset or external interrupt
should not be executed before V is restored to its normal
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10 ms).
CC
Reset
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles.
With an external interrupt, INT0 or INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the
oscillator but bringing the pin back high completes the exit. Once the
interrupt is serviced, the next instruction to be executed after RETI
will be the one following the instruction that put the device into
Power Down.
Stop Clock Mode
The static design enables the clock speed to be reduced down to
0 MHz (stopped). When the oscillator is stopped, the RAM and
Special Function Registers retain their values. This mode allows
step-by-step utilization and permits reduced system power
consumption by lowering the clock frequency down to any value. For
lowest power consumption the Power Down mode is suggested.
For the 80C31, wakeup from power down is always enabled.
Design Consideration
• When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is terminated by reset,
the instruction following the one that invokes Idle should not be
one that writes to a port pin or to external memory.
Idle Mode
In idle mode (see Table 2), the CPU puts itself to sleep while all of
the on-chip peripherals stay active. The instruction to invoke the idle
mode is the last instruction executed in the normal operating mode
before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during
this mode. The idle mode can be terminated either by any enabled
interrupt (at which time the process is picked up at the interrupt
service routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset.
ONCE Mode
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked by:
1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.
Power-Down Mode
To save even more power, a Power Down mode (see Table 2) can
be invoked by software. In this mode, the oscillator is stopped and
the instruction that invoked Power Down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the 80C31/32 is in
this mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
their values down to 2.0 V and care must be taken to return V to
the minimum specified operating voltages before the Power Down
Mode is terminated.
CC
Table 2. External Pin Status During Idle and Power-Down Modes
MODE
PROGRAM MEMORY
Internal
ALE
PSEN
PORT 0
Data
PORT 1
Data
PORT 2
Data
PORT 3
Data
Idle
Idle
1
1
0
0
1
1
0
0
External
Float
Data
Address
Data
Data
Power-down
Power-down
Internal
Data
Data
Data
External
Float
Data
Data
Data
8
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
TH2, to be captured into registers RCAP2L and RCAP2H,
Programmable Clock-Out
respectively. In addition, the transition at T2EX causes bit EXF2 in
T2CON to be set, and EXF2 like TF2 can generate an interrupt
(which vectors to the same location as Timer 2 overflow interrupt.
The Timer 2 interrupt service routine can interrogate TF2 and EXF2
to determine which event caused the interrupt). The capture mode is
illustrated in Figure 2 (There is no reload value for TL2 and TH2 in
this mode. Even when a capture event occurs from T2EX, the
counter keeps on counting T2EX pin transitions or osc/12 pulses.).
A 50% duty cycle clock can be programmed to come out on P1.0.
This pin, besides being a regular I/O pin, has two alternate
functions. It can be programmed:
1. to input the external clock for Timer/Counter 2, or
2. to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at
a 16 MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit
TR2 (T2CON.2) also must be set to start the timer.
Auto-Reload Mode (Up or Down Counter)
In the 16-bit auto-reload mode, Timer 2 can be configured (as either
a timer or counter (C/T2* in T2CON)) then programmed to count up
or down. The counting direction is determined by bit DCEN (Down
Counter Enable) which is located in the T2MOD register (see
Figure 3). When reset is applied the DCEN=0 which means Timer 2
will default to counting up. If DCEN bit is set, Timer 2 can count up
or down depending on the value of the T2EX pin.
The Clock-Out frequency depends on the oscillator frequency and
the reload value of Timer 2 capture registers (RCAP2H, RCAP2L)
as shown in this equation:
Oscillator Frequency
4 (65536 * RCAP2H, RCAP2L)
Where:
Figure 4 shows Timer 2 which will count up automatically since
DCEN=0. In this mode there are two options selected by bit EXEN2
in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH
and sets the TF2 (Overflow Flag) bit upon overflow. This causes the
Timer 2 registers to be reloaded with the 16-bit value in RCAP2L
and RCAP2H. The values in RCAP2L and RCAP2H are preset by
software means.
(RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L
taken as a 16-bit unsigned integer.
In the Clock-Out mode Timer 2 roll-overs will not generate an
interrupt. This is similar to when it is used as a baud-rate generator.
It is possible to use Timer 2 as a baud-rate generator and a clock
generator simultaneously. Note, however, that the baud-rate and the
Clock-Out frequency will be the same.
If EXEN2=1, then a 16-bit reload can be triggered either by an
overflow or by a 1-to-0 transition at input T2EX. This transition also
sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be
generated when either TF2 or EXF2 are 1.
TIMER 2 OPERATION
In Figure 5 DCEN=1 which enables Timer 2 to count up or down.
This mode allows pin T2EX to control the direction of count. When a
logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will
overflow at 0FFFFH and set the TF2 flag, which can then generate
an interrupt, if the interrupt is enabled. This timer overflow also
causes the 16–bit value in RCAP2L and RCAP2H to be reloaded
into the timer registers TL2 and TH2.
Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an
event timer or an event counter, as selected by C/T2* in the special
function register T2CON (see Figure 1). Timer 2 has three operating
modes:Capture, Auto-reload (up or down counting) ,and Baud Rate
Generator, which are selected by bits in the T2CON as shown in
Table 3.
When a logic 0 is applied at pin T2EX this causes Timer 2 to count
down. The timer will underflow when TL2 and TH2 become equal to
the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets
the TF2 flag and causes 0FFFFH to be reloaded into the timer
registers TL2 and TH2.
Capture Mode
In the capture mode there are two options which are selected by bit
EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or
counter (as selected by C/T2* in T2CON) which, upon overflowing
sets bit TF2, the timer 2 overflow bit. This bit can be used to
generate an interrupt (by enabling the Timer 2 interrupt bit in the
IE register). If EXEN2= 1, Timer 2 operates as described above, but
with the added feature that a 1- to -0 transition at external input
T2EX causes the current value in the Timer 2 registers, TL2 and
The external flag EXF2 toggles when Timer 2 underflows or
overflows. This EXF2 bit can be used as a 17th bit of resolution if
needed. The EXF2 flag does not generate an interrupt in this mode
of operation.
Table 3. Timer 2 Operating Modes
RCLK + TCLK
CP/RL2
TR2
1
MODE
16-bit Auto-reload
16-bit Capture
0
0
1
X
0
1
1
X
X
1
Baud rate generator
(off)
0
9
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
(MSB)
(LSB)
CP/RL2
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
Symbol
Position
Name and Significance
TF2
T2CON.7
T2CON.6
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set
when either RCLK or TCLK = 1.
EXF2
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2
interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down
counter mode (DCEN = 1).
RCLK
TCLK
T2CON.5
T2CON.4
T2CON.3
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock
in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock
in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.
TR2
T2CON.2
T2CON.1
Start/stop control for Timer 2. A logic 1 starts the timer.
C/T2
Timer or counter select. (Timer 2)
0 = Internal timer (OSC/12)
1 = External event counter (falling edge triggered).
CP/RL2
T2CON.0
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When
cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when
EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload
on Timer 2 overflow.
SU00728
Figure 1. Timer/Counter 2 (T2CON) Control Register
OSC
÷ 12
C/T2 = 0
TL2
(8-bits)
TH2
(8-bits)
TF2
C/T2 = 1
T2 Pin
Control
TR2
Capture
Transition
Detector
Timer 2
Interrupt
RCAP2L
RCAP2H
T2EX Pin
EXF2
Control
EXEN2
SU00066
Figure 2. Timer 2 in Capture Mode
10
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
T2MOD
Address = 0C9H
Not Bit Addressable
—
Reset Value = XXXX XX00B
—
6
—
5
—
4
—
3
—
2
T2OE
1
DCEN
0
Bit
7
Symbol
Function
—
Not implemented, reserved for future use.*
Timer 2 Output Enable bit.
T2OE
DCEN
Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.
*
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.
In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
SU00729
Figure 3. Timer 2 Mode (T2MOD) Control Register
OSC
÷ 12
C/T2 = 0
C/T2 = 1
TL2
(8-BITS)
TH2
(8-BITS)
T2 PIN
CONTROL
TR2
RELOAD
TRANSITION
DETECTOR
RCAP2L
RCAP2H
TF2
TIMER 2
INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
SU00067
Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)
11
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
(DOWN COUNTING RELOAD VALUE)
FFH
FFH
TOGGLE
EXF2
OSC
÷12
C/T2 = 0
C/T2 = 1
OVERFLOW
TL2
TH2
TF2
INTERRUPT
T2 PIN
CONTROL
TR2
COUNT
DIRECTION
1 = UP
0 = DOWN
RCAP2L
RCAP2H
(UP COUNTING RELOAD VALUE)
T2EX PIN
SU00730
Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)
Timer 1
Overflow
÷ 2
NOTE: OSC. Freq. is divided by 2, not 12.
“0”
“1”
OSC
÷ 2
C/T2 = 0
SMOD
RCLK
“1”
“0”
TL2
(8-bits)
TH2
(8-bits)
C/T2 = 1
T2 Pin
Control
÷ 16
RX Clock
“1”
“0”
TR2
Reload
TCLK
Transition
Detector
RCAP2L
RCAP2H
÷ 16
TX Clock
Timer 2
Interrupt
T2EX Pin
EXF2
Control
EXEN2
Note availability of additional external interrupt.
SU00068
Figure 6. Timer 2 in Baud Rate Generator Mode
12
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
under these conditions, a read or write of TH2 or TL2 may not be
accurate. The RCAP2 registers may be read, but should not be
written to, because a write might overlap a reload and cause write
and/or reload errors. The timer should be turned off (clear TR2)
before accessing the Timer 2 or RCAP2 registers.
Baud Rate Generator Mode
Bits TCLK and/or RCLK in T2CON (Table 3) allow the serial port
transmit and receive baud rates to be derived from either Timer 1 or
Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit
baud rate generator. When TCLK= 1, Timer 2 is used as the serial
port transmit baud rate generator. RCLK has the same effect for the
serial port receive baud rate. With these two bits, the serial port can
have different receive and transmit baud rates – one generated by
Timer 1, the other by Timer 2.
Table 4 shows commonly used baud rates and how they can be
obtained from Timer 2.
Table 4. Timer 2 Generated Commonly Used
Baud Rates
Figure 6 shows the Timer 2 in baud rate generation mode. The baud
rate generation mode is like the auto-reload mode, in that a rollover
in TH2 causes the Timer 2 registers to be reloaded with the 16-bit
value in registers RCAP2H and RCAP2L, which are preset by
software.
Timer 2
Baud Rate
Osc Freq
RCAP2H
RCAP2L
375 K
9.6 K
2.8 K
2.4 K
1.2 K
300
110
300
110
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
6 MHz
FF
FF
FF
FF
FE
FB
F2
FD
F9
FF
D9
B2
64
C8
1E
AF
8F
57
The baud rates in modes 1 and 3 are determined by Timer 2’s
overflow rate given below:
Timer 2 Overflow Rate
Modes 1 and 3 Baud Rates +
16
The timer can be configured for either “timer” or “counter” operation.
In many applications, it is configured for “timer” operation (C/T2*=0).
Timer operation is different for Timer 2 when it is being used as a
baud rate generator.
6 MHz
Usually, as a timer it would increment every machine cycle (i.e., 1/12
the oscillator frequency). As a baud rate generator, it increments
every state time (i.e., 1/2 the oscillator frequency). Thus the baud
rate formula is as follows:
Summary Of Baud Rate Equations
Timer 2 is in baud rate generating mode. If Timer 2 is being clocked
through pin T2(P1.0) the baud rate is:
Timer 2 Overflow Rate
Modes 1 and 3 Baud Rates =
Baud Rate +
16
Oscillator Frequency
If Timer 2 is being clocked internally, the baud rate is:
[32 [65536 * (RCAP2H, RCAP2L)]]
Where: (RCAP2H, RCAP2L)= The content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.
fOSC
Baud Rate +
[32 [65536 * (RCAP2H, RCAP2L)]]
The Timer 2 as a baud rate generator mode shown in Figure 6, is
valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a
rollover in TH2 does not set TF2, and will not generate an interrupt.
Thus, the Timer 2 interrupt does not have to be disabled when
Timer 2 is in the baud rate generator mode. Also if the EXEN2
(T2 external enable flag) is set, a 1-to-0 transition in T2EX
(Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but
will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2).
Therefore when Timer 2 is in use as a baud rate generator, T2EX
can be used as an additional external interrupt, if needed.
Where f
= Oscillator Frequency
OSC
To obtain the reload value for RCAP2H and RCAP2L, the above
equation can be rewritten as:
fOSC
RCAP2H, RCAP2L + 65536 * ǒ
Ǔ
32 Baud Rate
Timer/Counter 2 Set-up
Except for the baud rate generator mode, the values given for
T2CON do not include the setting of the TR2 bit. Therefore, bit TR2
must be set, separately, to turn the timer on. See Table 5 for set-up
of Timer 2 as a timer. Also see Table 6 for set-up of Timer 2 as a
counter.
When Timer 2 is in the baud rate generator mode, one should not try
to read or write TH2 and TL2. As a baud rate generator, Timer 2 is
incremented every state time (osc/2) or asynchronously from pin T2;
13
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
Table 5. Timer 2 as a Timer
T2CON
MODE
INTERNAL CONTROL (Note 1)
EXTERNAL CONTROL (Note 2)
16-bit Auto-Reload
00H
01H
34H
24H
14H
08H
09H
36H
26H
16H
16-bit Capture
Baud rate generator receive and transmit same baud rate
Receive only
Transmit only
Table 6. Timer 2 as a Counter
TMOD
MODE
INTERNAL CONTROL (Note 1)
EXTERNAL CONTROL (Note 2)
16-bit
02H
03H
0AH
0BH
Auto-Reload
NOTES:
1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate
generator mode.
SADDR are to b used and which bits are “don’t care”. The SADEN
mask can be logically ANDed with the SADDR to create the “Given”
Enhanced UART
The UART operates in all of the usual modes that are described in
address which the master will use for addressing each of the slaves.
the first section of Data Handbook IC20, 80C51-Based 8-Bit
Use of the Given address allows multiple slaves to be recognized
Microcontrollers. In addition the UART can perform framing error
while excluding others. The following examples will help to show the
detect by looking for missing stop bits, and automatic address
versatility of this scheme:
recognition. The 80C31/32 UART also fully supports multiprocessor
communication.
Slave 0
Slave 1
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1101
1100 00X0
When used for framing error detect the UART looks for missing stop
bits in the communication. A missing bit will set the FE bit in the
SCON register. The FE bit shares the SCON.7 bit with SM0 and the
function of SCON.7 is determined by PCON.6 (SMOD0) (see
Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7
functions as SM0 when SMOD0 is cleared. When used as FE
SCON.7 can only be cleared by software. Refer to Figure 8.
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1110
1100 000X
In the above example SADDR is the same and the SADEN data is
used to differentiate between the two slaves. Slave 0 requires a 0 in
bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is
ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be
selected at the same time by an address which has bit 0 = 0 (for
slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.
Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART
to recognize certain addresses in the serial bit stream by using
hardware to make the comparisons. This feature saves a great deal
of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART
modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be
automatically set when the received byte contains either the “Given”
address or the “Broadcast” address. The 9 bit mode requires that
the 9th information bit is a 1 to indicate that the received information
is an address and not data. Automatic address recognition is shown
in Figure 9.
In a more complex system the following could be used to select
slaves 1 and 2 while excluding slave 0:
Slave 0
Slave 1
Slave 2
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1001
1100 0XX0
SADDR
SADEN
Given
=
=
=
1110 0000
1111 1010
1110 0X0X
The 8 bit mode is called Mode 1. In this mode the RI flag will be set
if SM2 is enabled and the information received has a valid stop bit
following the 8 address bits and the information is either a Given or
Broadcast address.
SADDR
SADEN
Given
=
=
=
1110 0000
1111 1100
1110 00XX
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to
selectively communicate with one or more slaves by invoking the
Given slave address or addresses. All of the slaves may be
contacted by using the Broadcast address. Two special Function
Registers are used to define the slave’s address, SADDR, and the
address mask, SADEN. SADEN is used to define which bits in the
In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
14
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary to make bit 2 = 1 to exclude slave 2.
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR
address 0B9H) are leaded with 0s. This produces a given address
of all “don’t cares” as well as a Broadcast address of all “don’t
cares”. This effectively disables the Automatic Addressing mode and
allows the microcontroller to use standard 80C51 type UART drivers
which do not make use of this feature.
The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are trended
as don’t-cares. In most cases, interpreting the don’t-cares as ones,
the broadcast address will be FF hexadecimal.
SCON Address = 98H
Reset Value = 0000 0000B
Bit Addressable
SM0/FE
SM1
SM2
REN
TB8
RB8
Tl
Rl
Bit:
7
6
5
4
3
2
1
0
(SMOD0 = 0/1)*
Symbol
FE
Function
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
SM0
SM1
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
SM0
SM1
Mode
Description
Baud Rate**
f /12
OSC
0
0
1
1
0
1
0
1
0
1
2
3
shift register
8-bit UART
9-bit UART
9-bit UART
variable
/64 or f
f
/32
OSC
OSC
variable
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
REN
TB8
RB8
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Tl
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Rl
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
NOTE:
*SMOD0 is located at PCON6.
**f = oscillator frequency
OSC
SU00043
Figure 7. SCON: Serial Port Control Register
15
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
D0
D1
D2
D3
D4
D5
D6
D7
D8
START
BIT
DATA BYTE
ONLY IN
MODE 2, 3
STOP
BIT
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)
SM0 TO UART MODE CONTROL
SCON
(98H)
SM0 / FE
SMOD1
SM1
SM2
REN
POF
TB8
GF1
RB8
GF0
TI
RI
PCON
(87H)
SMOD0
–
PD
IDL
0 : SCON.7 = SM0
1 : SCON.7 = FE
SU01191
Figure 8. UART Framing Error Detection
D0
D1
D2
D3
D4
D5
D6
D7
D8
SCON
(98H)
SM0
SM1
SM2
REN
1
TB8
X
RB8
TI
RI
1
1
1
0
1
RECEIVED ADDRESS D0 TO D7
PROGRAMMED ADDRESS
COMPARATOR
IN UART MODE 2 OR MODE 3 AND SM2 = 1:
INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”
– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES
– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
SU00045
Figure 9. UART Multiprocessor Communication, Automatic Address Recognition
16
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
Interrupt Priority Structure
The 80C31 and 80C32 have a 6-source four-level interrupt
structure. They are the IE, IP and IPH. (See Figures 10, 11, and 12.)
The IPH (Interrupt Priority High) register that makes the four-level
interrupt structure possible. The IPH is located at SFR address B7H.
The structure of the IPH register and a description of its bits is
shown in Figure 12.
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPH.x
IP.x
0
0
0
1
1
Level 0 (lowest priority)
Level 1
1
0
Level 2
1
Level 3 (highest priority)
Table 7.
Interrupt Table
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR?
VECTOR ADDRESS
1
2
X0
T0
X1
T1
SP
T2
1
2
3
4
5
6
IE0
TP0
N (L) Y (T)
03H
0BH
13H
1BH
23H
2BH
Y
IE1
N (L) Y (T)
TF1
Y
N
N
RI, TI
TF2, EXF2
NOTES:
1. L = Level activated
2. T = Transition activated
7
6
5
4
3
2
1
0
IE (0A8H)
EA
—
ET2
ES
ET1
EX1
ET0
EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
SYMBOL FUNCTION
IE.7
EA
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
Not implemented. Reserved for future use.
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
—
ET2
ES
ET1
EX1
ET0
EX0
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
SU00571
Figure 10. IE Registers
17
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
7
6
5
4
3
2
1
0
IP (0B8H)
—
—
PT2
PS
PT1
PX1
PT0
PX0
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
SYMBOL FUNCTION
—
—
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit.
Serial Port interrupt priority bit.
Timer 1 interrupt priority bit.
PT2
PS
PT1
PX1
PT0
PX0
External interrupt 1 priority bit.
Timer 0 interrupt priority bit.
External interrupt 0 priority bit.
SU00572
Figure 11. IP Registers
7
6
5
4
3
2
1
0
IPH (B7H)
—
—
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT
SYMBOL FUNCTION
IPH.7
IPH.6
IPH.5
IPH.4
IPH.3
IPH.2
IPH.1
IPH.0
—
—
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit high.
Serial Port interrupt priority bit high.
Timer 1 interrupt priority bit high.
External interrupt 1 priority bit high.
Timer 0 interrupt priority bit high.
External interrupt 0 priority bit high.
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
SU01058
Figure 12. IPH Registers
18
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
Note that bit 2 is not writable and is always read as a zero. This
allows the DPS bit to be quickly toggled simply by executing an INC
DPTR instruction without affecting the WOPD or LPEP bits.
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output.
Reduced EMI Mode
AUXR (8EH)
DPS
BIT0
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
AUXR1
DPTR1
DPTR0
AO
AUXR.0
AO
Turns off ALE output.
DPH
DPL
(83H)
(82H)
EXTERNAL
DATA
MEMORY
Dual DPTR
SU00745A
The dual DPTR structure (see Figure 13) enables a way to specify
the address of an external data memory location. There are two
16-bit DPTR registers that address the external memory, and a
single bit called DPS = AUXR1/bit0 that allows the program code to
switch between them.
Figure 13.
DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
• New Register Name: AUXR1#
• SFR Address: A2H
• Reset Value: xxx000x0B
INC DPTR
Increments the data pointer by 1
AUXR1 (A2H)
MOV DPTR, #data16 Loads the DPTR with a 16-bit constant
7
–
6
–
5
–
4
–
3
2
0
1
–
0
MOV A, @ A+DPTR
MOVX A, @ DPTR
Move code byte relative to DPTR to ACC
WUPD
DPS
Move external RAM (16-bit address) to
ACC
Where:
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
MOVX @ DPTR , A
JMP @ A + DPTR
Move ACC to external RAM (16-bit
address)
Select Reg
DPS
Jump indirect relative to DPTR
DPTR0
DPTR1
0
1
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
19
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Operating temperature under bias
RATING
UNIT
°C
°C
V
0 to +70 or –40 to +85
–65 to +150
0 to +13.0
–0.5 to +6.5
15
Storage temperature range
Voltage on EA pin to V
SS
Voltage on any other pin to V
V
SS
Maximum I per I/O pin
mA
W
OL
Power dissipation (based on package heat transfer limitations, not device power consumption)
NOTES:
1.5
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise
SS
noted.
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C or –40°C to +85°C
CLOCK FREQUENCY
RANGE –f
SYMBOL
1/t
FIGURE
PARAMETER
MIN
MAX
UNIT
29
Oscillator frequency
CLCL
Speed versions : S (16 MHz)
U (33 MHz)
0
0
16
33
MHz
MHz
20
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C or –40°C to +85°C, V = 2.7 V to 5.5 V, V = 0 V (16 MHz devices)
CC SS
LIMITS
TEST
CONDITIONS
SYMBOL
PARAMETER
UNIT
MAX
1
MIN
–0.5
–0.5
TYP
4.0 V < V < 5.5 V
0.2 V –0.1
V
V
V
V
CC
CC
V
IL
Input low voltage
2.7 V<V < 4.0 V
0.7
CC
V
V
Input high voltage (ports 0, 1, 2, 3, EA)
Input high voltage, XTAL1, RST
0.2 V +0.9
V
V
+0.5
+0.5
IH
CC
CC
CC
0.7 V
IH1
CC
V
OL
= 2.7 V
= 1.6 mA
CC
8
V
Output low voltage, ports 1, 2,
0.4
V
V
V
V
OL
2
I
I
V
CC
= 2.7 V
8, 7
V
OL1
Output low voltage, port 0, ALE, PSEN
0.4
2
= 3.2 mA
OL
V
CC
= 2.7 V
= –20 µA
V
CC
V
CC
V
CC
– 0.7
– 0.7
– 0.7
I
OH
3
V
V
Output high voltage, ports 1, 2, 3
OH
V
CC
= 4.5 V
= –30 µA
I
OH
Output high voltage (port 0 in external bus
V
CC
= 2.7 V
= –3.2 mA
V
OH1
9
3
mode), ALE , PSEN
I
OH
I
I
Logical 0 input current, ports 1, 2, 3
Logical 1-to-0 transition current, ports 1, 2, 3
Input leakage current, port 0
V
V
= 0.4 V
= 2.0 V
–1
–50
–650
±10
µA
µA
µA
IL
IN
IN
6
TL
See note 4
I
I
0.45 < V < V – 0.3
LI
IN
CC
Power supply current (see Figure 21):
Active mode @ 16 MHz
Idle mode @ 16 MHz
Power-down mode or clock stopped (see
Figure 25 for conditions)
See note 5
CC
µA
µA
µA
µA
T
= 0°C to 70°C
3
50
75
amb
T
= –40°C to +85°C
amb
R
C
Internal reset pull-down resistor
40
225
15
kΩ
RST
IO
10
Pin capacitance (except EA)
pF
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due
OL
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no
OL
single output sinks more than 5 mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the V –0.7 specification when the
OH
CC
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V is approximately 2 V.
IN
5. See Figures 22 through 25 for I test conditions.
CC
Active mode:
Idle mode:
I
I
= 0.9 × FREQ. + 1.1 mA
= 0.18 × FREQ. +1.01 mA; See Figure 21.
CC
CC
6. This value applies to T
= 0°C to +70°C. For T = –40°C to +85°C, I = –750 µA.
amb TL
amb
7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin:
15 mA (*NOTE: This is 85°C specification.)
OL
Maximum I per 8-bit port:
26 mA
71 mA
OL
Maximum total I for all outputs:
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
9. ALE is tested to V
, except when ALE is off then V is the voltage specification.
OH
OH1
10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF.
21
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C or –40°C to +85°C, 33 MHz devices; 5 V ±10%; V = 0 V
SS
LIMITS
TEST
CONDITIONS
SYMBOL
PARAMETER
UNIT
MAX
1
MIN
TYP
V
V
V
Input low voltage
4.5 V < V < 5.5 V
–0.5
0.2 V –0.1
V
V
V
IL
CC
CC
Input high voltage (ports 0, 1, 2, 3, EA)
Input high voltage, XTAL1, RST
0.2 V +0.9
V
CC
V
CC
+0.5
+0.5
IH
CC
0.7 V
IH1
CC
V
= 4.5 V
= 1.6mA
CC
8
V
V
V
V
Output low voltage, ports 1, 2, 3
0.4
V
V
V
OL
2
I
OL
V
CC
= 4.5 V
7, 8
Output low voltage, port 0, ALE, PSEN
0.4
OL1
OH
2
I
OL
= 3.2mA
V
CC
= 4.5 V
= –30µA
3
Output high voltage, ports 1, 2, 3
V
V
– 0.7
– 0.7
CC
I
OH
Output high voltage (port 0 in external bus
V
CC
= 4.5 V
= –3.2mA
V
OH1
CC
9
3
mode), ALE , PSEN
I
OH
I
I
Logical 0 input current, ports 1, 2, 3
Logical 1-to-0 transition current, ports 1, 2, 3
Input leakage current, port 0
V
V
= 0.4 V
= 2.0 V
–1
–50
–650
±10
µA
µA
µA
IL
IN
IN
6
TL
See note 4
I
I
0.45 < V < V – 0.3
LI
IN
CC
Power supply current (see Figure 21):
Active mode (see Note 5)
See note 5
CC
Idle mode (see Note 5)
Power-down mode or clock stopped (see Fig-
ure 25 for conditions)
T
= 0°C to 70°C
= –40°C to +85°C
3
50
75
µA
µA
amb
T
amb
R
C
Internal reset pull-down resistor
40
225
15
kΩ
RST
IO
10
Pin capacitance (except EA)
pF
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due
OL
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no
OL
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the V –0.7 specification when the
OH
CC
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V is approximately 2 V.
IN
5. See Figures 22 through 25 for I test conditions.
CC
Active mode:
Idle mode:
I
I
= 0.9 × FREQ. + 1.1 mA
= 0.18 × FREQ. +1.0 mA; See Figure 21.
CC(MAX)
CC(MAX)
6. This value applies to T
= 0°C to +70°C. For T = –40°C to +85°C, I = –750 µA.
amb TL
amb
7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin:
15 mA (*NOTE: This is 85°C specification.)
OL
Maximum I per 8-bit port:
26 mA
71 mA
OL
Maximum total I for all outputs:
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
9. ALE is tested to V
, except when ALE is off then V is the voltage specification.
OH
OH1
10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF
(except EA is 25 pF).
22
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
AC ELECTRICAL CHARACTERISTICS
1, 2, 3
T
amb
= 0°C to +70°C or –40°C to +85°C, V = +2.7 V to +5.5 V, V = 0 V
CC SS
16 MHz CLOCK
VARIABLE CLOCK
MIN MAX
SYMBOL
1/t
FIGURE
PARAMETER
MIN
MAX
UNIT
5
14
Oscillator frequency
CLCL
3.5
16
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Speed versions :S
t
t
t
t
t
t
t
t
t
t
t
14
14
14
14
14
14
14
14
14
14
14
ALE pulse width
85
22
32
2t
–40
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
t
–40
–30
AVLL
LLAX
LLIV
CLCL
CLCL
150
82
4t
3t
–100
CLCL
32
t
–30
LLPL
PLPH
PLIV
PXIX
PXIZ
CLCL
PSEN pulse width
142
3t
–45
CLCL
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–105
CLCL
0
0
37
207
10
t
–25
CLCL
4
5t
–105
AVIV
CLCL
10
PLAZ
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
16
RD pulse width
275
275
6t
–100
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
147
5t
–165
CLCL
0
0
Data float after RD
65
2t
–60
CLCL
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
350
397
239
8t
CLCL
9t
CLCL
–150
–165
AVDV
LLWL
137
122
13
3t
–50
3t
+50
CLCL
CLCL
4t
t
–130
–50
AVWL
QVWX
WHQX
QVWH
RLAZ
WHLH
CLCL
CLCL
CLCL
CLCL
13
t
–50
Data valid to WR high
RD low to address float
RD or WR high to ALE high
287
7t
–150
15, 16
15, 16
0
0
23
103
t
–40
t
+40
CLCL
CLCL
External Clock
t
t
t
t
18
18
18
18
High time
Low time
Rise time
Fall time
20
20
20
20
t
–t
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
CLCL CLCX
t
–t
CLCL CHCX
20
20
20
20
Shift Register
t
t
t
t
t
17
17
17
17
17
Serial port clock cycle time
750
492
8
12t
ns
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10t
–133
QVXH
XHQX
XHDX
XHDV
CLCL
2t
CLCL
–117
0
0
492
10t
–133
CLCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the 80C31 and 80C32 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to
Port 0 drivers.
4. See application note AN457 for external memory interface.
5. Parts are guaranteed to operate down to 0 Hz. When an external clock source is used, the RST pin should be held high for a minimum of
20 µs for power-on or wakeup from power down.
23
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
AC ELECTRICAL CHARACTERISTICS
1, 2, 3
T
amb
= 0°C to +70°C or –40°C to +85°C, V = 5 V ±10%, V = 0 V
CC SS
4
VARIABLE CLOCK
16 MHz to f
33 MHz CLOCK
max
SYMBOL
FIGURE
14
PARAMETER
MIN
2t –40
CLCL
MAX
MIN
21
5
MAX
UNIT
ns
t
t
t
t
t
t
t
t
t
t
t
ALE pulse width
LHLL
AVLL
LLAX
LLIV
14
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
t
–25
–25
ns
CLCL
CLCL
14
ns
14
4t
3t
–65
55
30
ns
CLCL
14
t
–25
5
ns
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
14
PSEN pulse width
3t
CLCL
–45
45
ns
14
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–60
ns
CLCL
14
0
0
ns
14
t
–25
5
ns
CLCL
14
5t
–80
70
10
ns
CLCL
14
10
ns
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
16
RD pulse width
6t
–100
–100
82
82
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
5t
2t
–90
–28
60
CLCL
0
0
Data float after RD
32
90
CLCL
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
8t
–150
–165
CLCL
CLCL
9t
105
140
AVDV
LLWL
3t
–50
–75
3t
CLCL
+50
40
45
0
CLCL
4t
AVWL
QVWX
WHQX
QVWH
RLAZ
WHLH
CLCL
t
–30
CLCL
CLCL
CLCL
t
–25
5
Data valid to WR high
RD low to address float
RD or WR high to ALE high
7t
–130
80
15, 16
15, 16
0
0
t
–25
t
+25
5
55
CLCL
CLCL
External Clock
t
t
t
t
18
18
18
18
High time
Low time
Rise time
Fall time
0.38t
0.38t
t –t
CLCL CLCX
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
CLCL
t
–t
CLCL
CLCL CHCX
5
5
Shift Register
t
t
t
t
t
17
17
17
17
17
Serial port clock cycle time
12t
360
167
ns
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
10t
–133
–80
QVXH
XHQX
XHDX
XHDV
CLCL
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
2t
CLCL
0
0
10t
–133
167
CLCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the 80C31 and 80C32 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to
Port 0 drivers.
4. Variable clock is specified for oscillator frequencies greater than 16 MHz to 33 MHz. For frequencies equal or less than 16 MHz, see 16 MHz
“AC Electrical Characteristics”, page 23.
5. Parts are guaranteed to operate down to 0 Hz. When an external clock source is used, the RST pin should be held high for a minimum of
20 µs for power-on or wakeup from power down.
24
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
P – PSEN
Q – Output data
R – RD signal
t – Time
A – Address
V – Valid
C – Clock
D – Input data
H – Logic level high
W– WR signal
X – No longer a valid logic level
Z – Float
I – Instruction (program memory contents)
L – Logic level low, or ALE
Examples: t
= Time for address valid to ALE low.
=Time for ALE low to PSEN low.
AVLL
t
LLPL
t
LHLL
ALE
t
t
LLPL
AVLL
t
PLPH
t
LLIV
t
PLIV
PSEN
t
LLAX
t
PXIZ
t
PLAZ
t
PXIX
A0–A7
INSTR IN
A0–A7
PORT 0
PORT 2
t
AVIV
A0–A15
A8–A15
SU00006
Figure 14. External Program Memory Read Cycle
ALE
PSEN
RD
t
WHLH
t
LLDV
t
t
LLWL
RLRH
t
RHDZ
t
LLAX
t
t
RLDV
AVLL
t
RLAZ
t
RHDX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA IN
A0–A7 FROM PCL
INSTR IN
t
AVWL
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00025
Figure 15. External Data Memory Read Cycle
25
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
ALE
t
WHLH
PSEN
t
t
WLWH
LLWL
WR
t
LLAX
t
t
WHQX
t
AVLL
QVWX
t
QVWH
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA OUT
A0–A7 FROM PCL
INSTR IN
t
AVWL
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00026
Figure 16. External Data Memory Write Cycle
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
t
XLXL
CLOCK
t
XHQX
t
QVXH
OUTPUT DATA
0
1
2
3
4
5
6
7
WRITE TO SBUF
t
XHDX
t
SET TI
VALID
XHDV
INPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
SU00027
Figure 17. Shift Register Mode Timing
V
–0.5
CC
0.7V
CC
CC
0.45V
0.2V
–0.1
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
SU00009
Figure 18. External Clock Drive
26
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
V
–0.5
CC
V
V
+0.1V
LOAD
V
V
–0.1V
TIMING
REFERENCE
POINTS
OH
0.2V
0.2V
+0.9
–0.1
CC
V
LOAD
CC
–0.1V
LOAD
+0.1V
OL
0.45V
NOTE:
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from
load voltage occurs, and begins to float when a 100mV change from the loaded
AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.
CC
IH
IL
V
/V level occurs. I /I ≥ ±20mA.
OH OL
OH OL
SU00717
SU00718
Figure 19. AC Testing Input/Output
Figure 20. Float Waveform
35
30
25
20
15
10
5
MAX ACTIVE
MODE
I
MAX = 0.9 X FREQ. + 1.1
CC
TYP ACTIVE MODE
MAX IDLE MODE
TYP IDLE MODE
24 28 32
FREQ AT XTAL1 (MHz)
4
8
12
16
20
36
SU01413
Figure 21. I vs. FREQ
CC
Valid only within frequency specifications of the device under test
27
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
V
V
CC
CC
I
I
CC
CC
V
V
CC
CC
V
RST
V
V
CC
CC
CC
P0
EA
P0
EA
RST
(NC)
XTAL2
XTAL1
(NC)
XTAL2
XTAL1
CLOCK SIGNAL
CLOCK SIGNAL
V
V
SS
SS
SU00719
SU00720
Figure 22. I Test Condition, Active Mode
Figure 23. I Test Condition, Idle Mode
CC
CC
All other pins are disconnected
All other pins are disconnected
V
–0.5
CC
0.7V
CC
–0.1
0.45V
0.2V
CC
t
CHCX
t
t
t
CLCH
CHCL
CLCX
t
CLCL
SU00009
Figure 24. Clock Signal Waveform for I Tests in Active and Idle Modes
CC
t
= t
= 5ns
CHCL
CLCH
V
CC
CC
I
CC
V
CC
V
RST
P0
EA
(NC)
XTAL2
XTAL1
V
SS
SU00016
Figure 25. I Test Condition, Power Down Mode
CC
All other pins are disconnected. V = 2 V to 5.5 V
CC
28
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
29
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
30
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
31
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
80C31/80C32
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 08-00
Document order number:
9397 750 07403
Philips
Semiconductors
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