P80C453EBA [NXP]
IC MICROCONTROLLER, PQCC68, PLASTIC, SOT-168-3, MO-047AE, LCC-68, Microcontroller;
| 型号： | P80C453EBA |
| 厂家： | 
NXP |
| 描述： | IC MICROCONTROLLER, PQCC68, PLASTIC, SOT-168-3, MO-047AE, LCC-68, Microcontroller 微控制器和处理器 外围集成电路 装置 时钟 |
| 文件： | 总23页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
DESCRIPTION
LCC PIN FUNCTIONS
The Philips 8XC453 is an I/O expanded single-chip microcontroller
fabricated with Philips high-density CMOS technology. Philips
epitaxial substrate minimizes latch-up sensitivity.
9
1
61
10
60
44
The 8XC453 is a functional extension of the 87C51 microcontroller
with three additional I/O ports and four I/O control lines. The 8XC453
is available in 68-pin LCC packages. Four control lines associated
with port 6 facilitate high-speed asynchronous I/O functions.
LCC
26
The 87C453 includes an 8k × 8 EPROM, a 256 × 8 RAM, 56 I/O
lines, two 16-bit timer/counters, a seven source, two priority level,
nested interrupt structure, a serial I/O port for either a full duplex
UART, I/O expansion, or multi-processor communications, and
on-chip oscillator and clock circuits.
27
43
Pin
1
Function
EA/V
Pin
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Function
P4.2
Pin
Function
P5.3
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
PP
The 87C453 has two software selectable modes of reduced activity
for further power reduction; idle mode and power-down mode. Idle
mode freezes the CPU while allowing the RAM, timers, serial port,
and interrupt system to continue functioning. Power-down mode
freezes the oscillator, causing all other chip functions to be
inoperative while maintaining the RAM contents.
2
P2.0/A8
P4.1
P5.4
3
P2.1/A9
P4.0
P5.5
4
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
P1.0
P5.6
5
P1.1
P5.7
6
P1.2
XTAL2
XTAL1
7
P1.3
8
P1.4
V
SS
9
P1.5
ODS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
P1.6
IDS
FEATURES
P1.7
BFLAG
AFLAG
P6.0
RST
• 80C51 based architecture
P3.0/RxD
P3.1/TxD
P3.2/INTO
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
P5.0
P6.1
• Seven 8-bit I/O ports
P6.2
• Port 6 features:
– Eight data pins
P6.3
P6.4
V
P6.5
CC
– Four control pins
P4.7
P4.6
P4.5
P4.4
P4.3
P6.6
P6.7
– Direct MPU bus interface
– ISA Bus Interface
PSEN
ALE/PROG
P5.1
– Parallel printer interface
– IBF and OBF interrupts
– A flag latch on host write
P5.2
SU00157
• On the microcontroller:
– 8k × 8 EPROM
Quick pulse programming algorithm
Two-level program security system
– 256 × 8 RAM
– Two 16-bit counter/timers
– Two external interrupts
• External memory addressing capability
– 64k ROM and 64k RAM
• Low power consumption:
– Normal operation: less than 24mA at 5V, 16MHz
– Idle mode
– Power-down mode
• Reduced EMI
• Full-duplex enhanced UART
– Framing error detection
– Automatic address recognition
3-311
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
ORDERING INFORMATION
FREQ.
(MHz)
PKG.
DWG #
1
EPROM
ROMLESS
ROM
TEMPERATURE °C AND PACKAGE
P87C453EBAA
P87C453EFAA
OTP P80C453EBAA P83C453EBAA
OTP P80C453EFAA P83C453EFAA
68–Pin Plastic Leaded Chip Carrier, 0 to +70
68–Pin Plastic Leaded Chip Carrier, –40 to +85
3.5 to 16 SOT188-3
3.5 to 16 SOT188-3
68-Pin Ceramic Leaded Chip Carrier with window,
0 to +70
P87C453EBLKA UV
P87C453EFLKA UV
3.5 to 16
3.5 to 16
1473A
1473A
68-Pin Ceramic Leaded Chip Carrier with window,
–40 to +85
NOTE:
1. OTP = One-Time Programmable EPROM.
UV = Erasable EPROM.
LOGIC SYMBOL
V
V
SS
CC
XTAL1
ADDRESS AND
DATA BUS
XTAL2
RST
EA/V
PP
PSEN
ALE/PROG
RxD
TxD
INT0
INT1
T0
ADDRESS BUS
T1
WR
RD
ODS
IDS
PORT 6 CONTROL
BFLAG
AFLAG
SU00085
3-312
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
BLOCK DIAGRAM
P2.0–P2.7
P0.0–P0.7
P4.0–P4.7
P5.0–5.7
PORT 2
DRIVERS
PORT 0
DRIVERS
PORT 4
DRIVERS
PORT 5
DRIVERS
V
V
CC
SS
8K x 8
EPROM
PORT 2
LATCH
256 BYTES
RAM
RAM ADDR
REGISTER
PORT 0
LATCH
PORT 4
LATCH
PORT 5
LATCH
B
STACK
POINTER
ACC
REGISTER
PROGRAM
ADDRESS
REGISTER
TMP1
TMP2
BUFFER
PCON SCON TMOD TCON
ALU
PSW
TL1
TH0
DPH
TL0
DPL
IE
TH1
AUXR
IP
PC
CSR
SBUF
INCRE-
MENTER
PSW
INTERRUPT, SERIAL
PORT AND TIMER BLOCKS
PROGRAM
COUNTER
PSEN
ALE/PROG
TIMING
AND
CONTROL
DPTR
EAV
PP
RST
PORT 1
LATCH
PORT 6
LATCH
PD
PORT 3
LATCH
OSCILLATOR
PORT 6
CONTROL/STATUS
PORT 1
DRIVERS
PORT 6
DRIVERS
PORT 3
DRIVERS
XTAL1
XTAL2
IDS ODS BFLAG
AFLAG
P1.0–P1.7
P6.0–P6.7
P3.0–P3.7
SU00158
3-313
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
PIN DESCRIPTION
MNEMONIC
TYPE NAME AND FUNCTION
PIN NO.
V
SS
V
CC
54
I
I
Ground: 0V reference.
18
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
P0.0–0.7
17-10
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 is also the multiplexed data and low-order
address bus during accesses to external memory. External pull-ups are required during program
verification. Port 0 can sink/source eight LS TTL inputs.
P1.0–P1.7
P2.0–P2.7
27-34
2-9
I/O
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 receives the low-order address
bytes during program memory verification. Port 1 can sink/source three LS TTL inputs, and drive CMOS
inputs without external pull-ups.
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 emits the high-order address
bytes during access to external memory and receives the high-order address bits and control signals
during program verification. Port 2 can sink/source three LS TTL inputs, and drive CMOS inputs without
external pull-ups.
P3.0–P3.7
36-43
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 can sink/source three LS TTL
inputs, and drive CMOS inputs without external pull-ups. Port 3 also serves the special functions listed
below:
36
37
38
39
40
41
42
43
I
O
I
I
I
I
O
O
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
P4.0–P4.3
P4.0–P4.7
I/O
I/O
Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 4 can sink/source three LS TTL
inputs and drive CMOS inputs without external pull-ups.
26-19
44-51
P5.0–P5.7
I/O
Port 5: Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 5 can sink/source three LS TTL
inputs and drive CMOS inputs without external pull-ups.
P6.0–P6.7
59-66
I/O
Port 6: Port 6 is a specialized 8-bit bidirectional I/O port with internal pull-ups. This special port can
sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6 can be used in a
strobed or non-strobed mode of operation. Port 6 works in conjunction with four control pins that serve the
functions listed below:
ODS
55
56
57
58
35
I
I
ODS: Output data strobe
IDS
IDS: Input data strobe
BFLAG
AFLAG
RST
I/O
I/O
I
BFLAG: Bidirectional I/O pin with internal pull-ups
AFLAG: Bidirectional I/O pin with internal pull-ups
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An
internal pull-down resistor permits a power-on reset using only an external capacitor connected to V
.
CC
ALE/PROG
68
67
1
I/O
O
I
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an
access to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except during
an external data memory access, at which time one ALE is skipped. ALE can sink/source three LS TTL
inputs and drive CMOS inputs without external pull-ups. This pin is also the program pulse during EPROM
programming.
PSEN
Program Store Enable: The read strobe to external program memory. PSEN is activated twice each
machine cycle during fetches from external program memory. However, when executing out of external
program memory, two activations of PSEN are skipped during each access to external program memory.
PSEN is not activated during fetches from internal program memory. PSEN can sink/source eight LS TTL
inputs and drive CMOS inputs without an external pull-up. This pin should be tied low during programming.
EA/V
Instruction Execution Control/Programming Supply Voltage: When EA is held high, the CPU executes
out of internal program memory, unless the program counter exceeds 1FFFH. When EA is held low, the
CPU executes out of external program memory. EA must never be allowed to float. This pin also receives
PP
the 12.75V programming supply voltage (V ) during EPROM programming.
PP
XTAL1
XTAL2
53
52
I
Crystal 1: Input to the inverting oscillator amplifier that forms the oscillator. This input receives the external
oscillator when an external oscillator is used.
O
Crystal 2: An output of the inverting amplifier that forms the oscillator. This pin should be floated when an
external oscillator is used.
3-314
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
Table 1.
87C453 Special Function Registers
DIRECT
DESCRIPTION
BIT NAMES AND ADDRESSES
RESET
VALUE
SYMBOL
ADDRESS MSB
LSB
E0
ACC*
B*
Accumulator
B register
E0H
F0H
E7
F7
E6
F6
E5
F5
E4
F4
E3
F3
EB
E2
F2
EA
E1
F1
00H
F0
E8
00H
EF
EE
ED
EC
E9
CSR*#
DPTR
DPH
Port 6 command/status
Data pointer (2 bytes)
Data pointer high
E8H
MB1
MB0
MA1
MA0
OBFC IDSM
OBF
IBF
FCH
83H
82H
00H
00H
DPL
Data pointer low
BF
–
BE
BD
BC
PS
BB
BA
B9
B8
IP*
Interrupt priority
B8H
POB
PIB
PT1
PX1
PT0
PX0
x0000000B
AUXR#
IE*
Auxiliary register
Interrupt enable
8EH
A8H
–
–
–
–
–
–
AF
A9
AO
A8
x0000000B
00000000B
AF
EA
AE
IOB
AD
IIB
AC
ES
AB
ET1
AA
EX1
ET0
EX0
P0*
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
80H
90H
A0H
B0H
C0H
C8H
D8H
87
97
B6
96
85
95
84
94
83
93
82
92
81
91
80
90
FFH
FFH
FFH
FFH
FFH
FFH
FFH
P1*
P2*
A7
B7
C7
CF
DF
A6
B6
C6
CE
DE
A5
B5
C5
CD
DD
A4
B4
C4
CC
DC
A3
B3
C3
CB
DB
A2
B2
C2
CA
DA
A1
B1
C1
C9
D9
A0
B0
C0
C8
D8
P3*
P4*#
P5*#
P6*#
1
PCON
Power control
87H
SMOD1 SMOD0
–
POF
GF1
GF0
PD
IDL
00xx0000B
D7
CY
D6
AC
D5
F0
D4
D3
D2
D1
–
D0
P
PSW*
Program status word
Slave Address
D0H
A9H
B9H
99H
RS1
RS0
OV
00H
SADDR#
SADEN#
SBUF
00H
Slave Address Mask
Serial data buffer
00H
xxxxxxxxB
9F
9E
9D
9C
9B
9A
99
TI
98
RI
SCON*
SP
Serial port control
Stack pointer
98H
81H
SM0
SM1
SM2
REN
TB8
RB8
00H
07H
8F
8E
8D
8C
8B
8A
89
88
TCON*
TMOD
Timer/counter control
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00H
Timer/counter mode
Timer 0 high byte
Timer 1 high byte
Timer 0 low byte
Timer 1 low byte
89H
8CH
8DH
8AH
8BH
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
00H
00H
00H
00H
TH0
TH1
TL0
TL1
NOTES:
*
#
SFRs are bit addressable.
SFRs are modified from or added to the 80C51 SFRs.
1. REset value depends on reset source.
3-315
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
HIGH PRIORITY
INTERRUPT
IE REGISTER
IP REGISTER
0
IE.0
INT0
TF0
IT0
1
INTERRUPT
POLLING
SEQUENCE
IE.1
IE.2
0
1
INT1
TF1
IT1
IE.3
IE.4
RI
TI
IE.5
IE.6
IBF
OBF
LOW PRIORITY
INTERRUPT
INDIVIDUAL
ENABLES
GLOBAL
DISABLE
SU00562
Figure 1. 8XC453 Interrupt Control System
MSB
EA
LSB
IOB
IIB
ES
ET1
EX1
ET0
EX0
BIT
SYMBOL FUNCTION
IE.7
EA
Disables all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt
source is individually enabled or disabled by setting or clearing its enable bit.
IE.6
IOB
Enables or disables the Output Buffer Full (OBF) interrupt. If IOB=0, the interrupt is disabled,
If IOB=1, an interrupt will occur if EA is set and data has been read from the output buffer
register through Port 6 by the external host pulsing ODS low.
IE.5
IE.4
IIB
ES
Enables or disables the Input Buffer Full (IBF) interrupt. If IIB=0, the interrupt is disabled. If
IIB=1, an interrupt will occur if EA is set and data has been written into the Port 6 Input Data
Buffer by the host strobing IDS low.
Enables or disables the Serial Port Interrupt. If ES=0, the Serial Port Interrupt. If ES=0, the
Serial Port interrupt is disabled.
IE.3
IE.2
IE.1
IE.0
ET1
EX1
ET0
EX0
Enables or disables the Timer 1 Overflow interrupt. If ET1=0, the Timer 1 interrupt is disabled.
Enables or disables External Interrupt 1. If EX1=0, External Interrupt 1 is disabled.
Enables or disables the Timer 0 Overflow interrupt. If ET0=0, the Timer 0 interrupt is disabled.
Enables or disables External Interrupt 0. If EX0=0, external Interrupt 0 is disabled.
SU00563
Figure 2. 8XC453 Interrupt Enable (IE) Register
3-316
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
MSB
LSB
—
POB
PIB
PS
PT1
PX1
PT0
PX0
BIT
IP.7
IP.6
SYMBOL FUNCTION
—
Reserved.
POB
Defines the Output Buffer Full interrupt (IOB) priority level. POB=1 programs it to the higher
priority level.
IP.5
PIB
Defines the Input Buffer Full interrupt (IIB) priority level. PIB=1 programs it to the higher
priority level.
IP.4
IP.3
IP.2
IP.1
PS
Defines the Serial Port interrupt priority level. PS=1 programs it to the higher priority level.
Defines the Timer 1 interrupt priority level. PT1=1 programs it to the higher priority level.
Defines the External Interrupt 1 priority level. PX1=1 programs it to the higher priority level.
Enables or disables the Timer 0 interrupt priority level. PT0=1 programs it to the higher prior-
ity level.
PT1
PX1
PT0
IP.0
PX0
Defines the External Interrupt 0 priority level. PX0=1 programs it to the higher priority level.
SU00564
Figure 3. 8XC453 Interrupt Priority (IP) Register
7
6
5
4
3
2
1
0
PCON (87H)
SMOD1 SMOD2
—
POF
GF1
GF0
PD
IDL
BIT
SYMBOL FUNCTION
PCON.7
SMOD1
Double Baud rate bit. When set to a 1 and Timer 1 is used to generate baud rate, and the Serial Port
is used in modes 1, 2, or 3.
PCON.6
PCON.5
PCON.4
SMOD0
—
POF
If set to 1, SCON.7 will be the Framing Error bit (FE). If PCON.6 is cleared, SCON.7 will be SM0.
Reserved.
Power Off Flag is set during power on of V . If then cleared by software, it can be used to determine
CC
if a warm start has occurred.
PCON.3
PCON.2
PCON.1
PCON.0
GF1
GF0
PD
General-purpose flag bit.
General-purpose flag bit.
Power-Down bit. Setting this bit activates power-down mode. It can only be set if input EW is high.
Idle mode bit. Setting this bit activates the idle mode.
IDL
If logic 1s are written to PD and IDL at the same time, PD takes precedence.
Figure 4. Power Control Register (PCON)
SU00565
3-317
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
SCON Address = 98H
Reset Value = 0000 0000B
Bit Addressable
SM0/FE
SM1
SM2
REN
TB8
RB8
Tl
Rl
Bit:
7
6
5
4
3
2
1
0
(SMOD0 = 0/1)*
Symbol
FE
Function
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
SM0
SM1
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
SM0
SM1
Mode
Description
Baud Rate**
f /12
OSC
0
0
1
1
0
1
0
1
0
1
2
3
shift register
8-bit UART
9-bit UART
9-bit UART
variable
/64 or f
f
/32
OSC
OSC
variable
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
REN
TB8
RB8
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Tl
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Rl
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
NOTE:
*SMOD0 is located at PCON6.
**f = oscillator frequency
OSC
SU00043
Figure 5. Serial Port Control Register (SCON)
D0
D1
D2
D3
D4
D5
D6
D7
D8
START
BIT
DATA BYTE
ONLY IN
MODE 2, 3
STOP
BIT
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)
SM0 TO UART MODE CONTROL
SCON
(98H)
SM0 / FE
SMOD1
SM1
SM2
OSF
REN
POF
TB8
LVF
RB8
GF0
TI
RI
PCON
(87H)
SMOD0
GF1
IDL
0 : SCON.7 = SM0
1 : SCON.7 = FE
SU00044
Figure 6. UART Framing Error Detection
3-318
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
D0
D1
D2
D3
D4
D5
D6
D7
D8
SCON
(98H)
SM0
SM1
SM2
REN
1
TB8
X
RB8
TI
RI
1
1
1
0
1
RECEIVED ADDRESS D0 TO D7
PROGRAMMED ADDRESS
COMPARATOR
IN UART MODE 2 OR MODE 3 AND SM2 = 1:
INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”
– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES
– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
SU00045
Figure 7. UART Multiprocessor Communication, Automatic Address Recognition
Given slave address or addresses. All of the slaves may be
contacted by using the Broadcast address. Two special Function
Registers are used to define the slave’s address, SADDR, and the
address mask, SADEN. SADEN is used to define which bits in the
SADDR are to b used and which bits are “don’t care”. The SADEN
mask can be logically ANDed with the SADDR to create the “Given”
address which the master will use for addressing each of the slaves.
Use of the Given address allows multiple slaves to be recognized
while excluding others. The following examples will help to show the
versatility of this scheme:
SPECIAL FUNCTION REGISTER ADDRESSES
Special function register addresses for the device are identical to
those of the 80C51, except for the additional registers listed in
Table 2.
Enhanced UART
The UART operates in all of the usual modes that are described in
the first section of this book for the 80C51. In addition the UART can
perform framing error detect by looking for missing stop bits, and
automatic address recognition. The 87C453 UART also fully
supports multiprocessor communication as does the standard
80C51 UART.
Slave 0
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1101
1100 00X0
When used for framing error detect the UART looks for missing stop
bits in the communication. A missing bit will set the FE bit in the
SCON register. The FE bit shares the SCON.7 bit with SM0 and the
function of SCON.7 is determined by PCON.6 (SMOD0) (see
Figure 5). If SMOD0 is set then SCON.7 functions as FE. SCON.7
functions as SM0 when SMOD0 is cleared. When used as FE
SCON.7 can only be cleared by software. Refer to Figure 6.
Slave 1
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1110
1100 000X
In the above example SADDR is the same and the SADEN data is
used to differentiate between the two slaves. Slave 0 requires a 0 in
bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is
ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be
selected at the same time by an address which has bit 0 = 0 (for
slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.
Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART
to recognize certain addresses in the serial bit stream by using
hardware to make the comparisons. This feature saves a great deal
of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART
modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be
automatically set when the received byte contains either the “Given”
address or the “Broadcast” address. The 9 bit mode requires that
the 9th information bit is a 1 to indicate that the received information
is an address and not data. Automatic address recognition is shown
in Figure 7.
In a more complex system the following could be used to select
slaves 1 and 2 while excluding slave 0:
Slave 0
Slave 1
Slave 2
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1001
1100 0XX0
SADDR
SADEN
Given
=
=
=
1110 0000
1111 1010
1110 0X0X
The 8 bit mode is called Mode 1. In this mode the RI flag will be set
if SM2 is enabled and the information received has a valid stop bit
following the 8 address bits and the information is either a Given or
Broadcast address.
SADDR
SADEN
Given
=
=
=
1110 0000
1111 1100
1110 00XX
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to
selectively communicate with one or more slaves by invoking the
3-319
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary t make bit 2 = 1 to exclude slave 2.
does not change the on-chip RAM. An external interrupt allows both
the SFRs and the on-chip RAM to retain their values.
To properly terminate Power Down the reset or external interrupt
should not be executed before V is restored to its normal
CC
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10ms).
With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the
oscillator but bringing the pin back high completes the exit. Once the
interrupt is serviced, the next instruction to be executed after RETI
will be the one following the instruction that put the device into
Power Down.
The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are teated as
don’t-cares. In most cases, interpreting the don’t-cares as ones, the
broadcast address will be FF hexadecimal.
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR
address 0B9H) are leaded with 0s. This produces a given address
of all “don’t cares” as well as a Broadcast address of all “don’t
cares”. this effectively disables the Automatic Addressing mode and
allows the microcontroller to use standard 80C51 type UART drivers
which do not make use of this feature.
Power Off Flag
The Power Off Flag (POF) in PCON is set by on-chip circuitry when
the V level on the 87C453 rises from 0 to 5V. The POF bit can be
CC
set or cleared by software allowing a user to determine if the reset is
the result of a power-on or a warm start after powerdown. The V
CC
The 87C453 UART has all of the capabilities of the standard 80C51
UART plus Framing Error Detection and Automatic Address
Recognition. As in the 80C51, all four modes of operation are
supported as well as the 9th bit in modes 2 and 3 that can be used
to facilitate multiprocessor communication.
level must remain above 3V for the POF to remain unaffected by the
level.
V
CC
Design Consideration
• When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal rest algorithm takes
control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is terminated by reset,
the instruction following the one that invokes Idle should not be
one that writes to a port pin or to external memory.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
ONCE Mode
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems using the 87C453 without having to remove
the IC from the circuit. The ONCE Mode is invoked by:
1. Pull ALE low while the device is in reset and PSEN is high;
Reset
2. Hold ALE low as RST is deactivated.
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the 87C453 is in
this mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
V
CC
and RST must come up at the same time for a proper start-up.
PORTS 4 AND 5
Idle Mode
Ports 4 and 5 are bidirectional I/O ports with internal pull-ups. Port 4
is an 8-bit port. Port 4 and port 5 pins with ones written to them, are
pulled high by the internal pull-ups, and in that state can be used as
inputs. Ports 4 and 5 are addressed at the special function register
addresses shown in Table 2.
In the idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
PORT 6
Port 6 is a special 8-bit bidirectional I/O port with internal pull-ups
(see Figure 8). This port can be used as a standard I/O port, or in
strobed modes of operation in conjunction with four special control
lines: ODS, IDS, AFLAG, and BFLAG. Port 6 operating modes are
controlled by the port 6 control status register (CSR). Port 6 and the
CSR are addressed at the special function register addresses
shown in Table 2. The following four control pins are used in
conjunction with port 6:
Power-Down Mode
To save even more power, a Power Down mode can be invoked by
software. In this mode, the oscillator is stopped and the instruction
that invoked Power Down is the last instruction executed. The
on-chip RAM and Special Function Registers retain their values until
the Power Down mode is terminated.
ODS – Output data strobe for port 6. ODS can be programmed to
control the port 6 output drivers and the output buffer full flag (OBF),
or to clear only the OBF flag bit in the CSR (output-always mode).
On the 87C453 either a hardware reset or external interrupt can
cause an exit from Power Down. Reset redefines all the SFRs but
3-320
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
ODS is active low for output driver control. The OBF flag can be
programmed to be cleared on the negative or positive edge of ODS.
Can produce an IOB interrupt (see Figure 2).
CSR.3 Output Buffer Full Flag Clear Mode (OBFC) – When
CSR.3 = 1, the positive edge of the ODS input clears the OBF flag.
When CSR.3 = 0, the negative edge of the ODS input clears the
OBF flag.
IDS – Input data strobe for port 6. IDS is used to control the port 6
input latch and input buffer full flag (IBF) bit in the CSR. The input
data latch can be programmed to be transparent when IDS is low
and latched on the positive transition of IDS, or to latch only on the
positive transition of IDS. Correspondingly, the IBF flag is set on the
negative or positive transition of IDS. Can produce an IIB interrupt
(see Figure 2).
CSR.4, CSR.5 AFLAG Mode Select (MA0, MA1) – Bits 4 and 5
select the mode of operation for the AFLAG pin as follows:
MA1 MA0
AFLAG Function
Logic 0 output
Logic 1 output
OBF flag output (CSR.1)
Select (SEL) input mode
0
0
1
1
0
1
0
1
AFLAG – AFLAG is a bidirectional I/O pin which can be
programmed to be an output set high or low under program control,
or to output the state of the output buffer full flag. AFLAG can also
be programmed to be an input which selects whether the contents of
the output buffer, or the contents of the port 6 control status register
will output on port 6. This feature grants complete port 6 status to
external devices.
The select (SEL) input mode is used to determine whether the port 6
data register or the control status register is output on port 6. When
the select feature is enabled, the AFLAG input controls the source of
port 6 output data. A logic 0 on AFLAG input selects the port 6 data
register, and a logic 1 on AFLAG input selects the control status
register.
BFLAG – BFLAG is a bidirectional I/O pin which can be
programmed to be an output, set high or low under program control,
or to output the state of the input buffer full flag. BFLAG can also be
programmed to input an enable signal for port 6. When BFLAG is
used as an enable input, port 6 output drivers are in the
high-impedance state, and the input latch does not respond to the
IDS strobe when BFLAG is high. Both features are enabled when
BFLAG is low. This feature facilitates the use of the 87C453 in
bused multiprocessor systems.
The value of the AFLAG input is latched into the Auxiliary Register
(AUXR) bit 1 (AUXR.1). Checking this bit (AF) will allow the
87C453’s program to determine if Port 6 was loaded with data or a
UPI command.
CSR.6, CSR.7 BFLAG Mode Select (MB0, MB1) – Bits 6 and 7
select the mode operation as follows:
MB1 MB0
BFLAG Function
Logic 0 output
Logic 1 output
IBF flag output (CSR.0)
Port enable (PE)
0
0
1
1
0
1
0
1
CONTROL STATUS REGISTER
The control status register (CSR) establishes the mode of operation
for port 6 and indicates the current status of port 6 I/O registers. All
control status register bits can be read and written by the CPU,
except bits 0 and 1, which are read only. Reset writes ones to bits 2
through 7, and writes zeros to bits 0 and 1 (see Table 3).
In the port enable mode, IDS and ODS inputs are disabled when
BFLAG input is high. When the BFLAG input is low, the port is
enabled for I/O.
Reduced EMI Mode – The on–chip clock distribution drivers have
been identified as the cause of most of the EMI emissions from the
80C51 family. By tailoring the clock drivers properly, a compromise
between maximum operating speed and minimal EMI emissions can
be achieved. Typically, an order in magnitude of reduction is
possible over previous designs. This feature has been implemented
on this chip along with the additional capability of turning off the ALE
output. Setting the AO bit (AUXR.0) in the AUXR special function
register will disable the ALE output. Reset forces a 0 into AUXR.0 to
enable normal 80C51 type operation.
CSR.0 Input Buffer Full Flag (IBF) (Read Only) – The IBF bit is
set to a logic 1 when port 6 data is loaded into the input buffer under
control of IDS. This can occur on the negative or positive edge of
IDS, as determined by CSR.2. When IBF is set, the Interrupt Enable
Register bit IIB (IE.5) is set. The Interrupt Service Routine vector
address for this interrupt is 002BH. IBF is cleared when the CPU
reads the input buffer register.
CSR.1 Output Buffer Full Flag (OBF) (Read Only) – The OBF flag
is set to a logic 1 when the CPU writes to the port 6 output data
buffer. OBF is cleared by the positive or negative edge of ODS, as
determined by CSR.3. When OBF is cleared, the Interrupt Enable
Register bit IOB (IE.6) is set. The Interrupt Service Routine vector
address for this interrupt is 0033H.
Auxiliary Register (AUXR)
7
6
5
4
–
3
–
2
–
1
0
–
–
–
AF
AO
CSR.2 IDS Mode Select (IDSM) – When CSR.2 = 0, a low-to-high
transition on the IDS pin sets the IBF flag. The Port 6 input buffer is
loaded on the IDS positive edge. When CSR.2 = 1, a high-to-low
transition on the IDS pin sets the IBF flag. Port 6 input buffer is
transparent when IDS is low, and latched when IDS is high.
Latched value of AFLAG when Port 6
inputs data from IDS strobe
0 = ALE enabled
1 = ALE disabled
3-321
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
PORT 6
AFLAG
BFLAG ODS
IDS
BFLAG/ODS
MODE
(CSR.6/.7)
INPUT
BUFFER
(P6 READ)
IDS
MODE
OUTPUT
DRIVERS
INPUT BUFFER
FULL (CSR.0)
AFLAG
MODE
EDGE/LEVEL
SELECT (CSR.2)
MUX
(CSR.4/.5)
OUTPUT BUFFER
FULL (CSR.1)
CONTROL/STATUS
REGISTER (CSR)
OUTPUT BUFFER
(P6 WRITE)
INTERNAL BUS
SU00087
Figure 8. Port 6 Block Diagram
Table 2.
Special Function Register Addresses
REGISTER ADDRESS
BIT ADDRESS
Name
Symbol
Address
MSB
LSB
Port 4
Port 5
P4
P5
C0
C8
D8
E8
C7
CF
DF
EF
C6
CE
DE
EE
C5
CD
DD
ED
C4
CC
DC
EC
C3
CB
DB
EB
C2
CA
DA
EA
C1
C9
D9
E9
C0
C8
D8
E8
Port 6 data
P6
Port 6 control status
CSR
Slave address
Slave address mask
SADDR
SADEN
A9
B9
Auxiliary Register
AUXR
8E
Table 3.
Bit 7
Control Status Register (CSR)
Bit 6
Bit 5
Bit 4
MA0
Bit 3
OBFC
Bit 2
IDSM
Bit 1
OBF
Bit 0
IBF
MB1
MB0
MA1
BFLAG Mode Select
AFLAG Mode Select
Output Buffer
Flag Clear
Mode
Input Data
Strobe Mode
Output Buffer
Flag Full
Input Buffer
Flag Full
0/0 = Logic 0 output*
0/1 = Logic 1 output*
1/0 = IBF output
1/1 = PE input
0/0 = Logic 0 output*
0/1 = Logic 1 output*
1/0 = OBF output
1/1 = SEL input
0 = Negative
edge of ODS
1 = Positive
edge o ODS
0 = Positive
edge of IDS
1 = Low level
of IDS
0 = Output
data buffer
empty
1 = Output
data buffer full
0 = Input data
buffer empty
1 = Input data
buffer full
(0 = Select)
(0 = Select)
(1 = Disable I/O)
(1 = Control/status)
NOTE:
*
Output-always mode: MB1 = 0, MA1 = 1, and MA0 = 0. In this mode, port 6 is always enabled for output. ODS only clears the OBF flag.
3-322
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
Operating temperature under bias
0 to +70
°C
–40 to +85
Storage temperature range
–65 to +150
–0.5 to +6.5
1.5
°C
V
Voltage on any other pin to V
SS
Power dissipation (based on package heat transfer limitations, not device power consumption)
W
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. Voltages are with respect to V unless otherwise noted.
SS
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V
CC SS
TEST
LIMITS
1
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
0.2V –0.1
UNIT
V
IL
Input low voltage; ports 0, 1, 2, 3, 4, 5, 6, IDS, ODS,
AFLAG, BFLAG; except EA
–0.5
V
CC
V
V
V
V
Input low voltage to EA
0
0.2V –0.3
V
V
V
V
IL1
CC
Input high voltage; except XTAL1, RST
Input high voltage; XTAL1, RST
0.2V +0.9
V
CC
V
CC
+0.5
+0.5
IH
CC
0.7V
IH1
OL
CC
2
Output low voltage; ports 1, 2, 3, 4, 5, 6, AFLAG,
BFLAG
I
OL
= 1.6mA
0.45
2
V
V
Output low voltage; port 0, ALE, PSEN
I
I
I
I
= 3.2mA
0.45
V
OL1
OL
Output high voltage; ports 1, 2, 3, 4, 5, 6, AFLAG,
BFLAG
= –60µA,
= –25µA
= –10µA
2.4
V
V
V
OH
OH
0.75V
OH
OH
CC
CC
0.9V
V
OH1
Output high voltage (port 0 in external bus mode, ALE,
PSEN)
I
I
= –800µA,
= –300µA
2.4
V
V
V
OH
OH
I
3
0.75V
CC
CC
= –80µA
0.9V
OH
I
I
I
I
Logical 0 input current,; ports 1, 2, 3, 4, 5, 6
Logical 1-to-0 transition current; ports 1, 2, 3, 4, 5, 6
Input leakage current; port 0
V
= 0.45V
–50
–650
±10
µA
µA
µA
IL
IN
See note 4
= V or V
IH
TL
LI
V
IN
IL
Power supply current:
See note 6
CC
5
Active mode @ 16MHz
Idle mode @ 16MHz
11.5
1.3
3
25
4
50
mA
mA
µA
5
Power down mode
R
C
Internal reset pull-down resistor
50
300
kΩ
RST
IO
7
Pin capacitance – PLCC package
10
pF
NOTES:
1. Typical ratings are based on a limited number of samples from early manufacturing lots, and not guaranteed. Values are room temp., 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and the other ports. The noise is due
OL
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input..
3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9V specification when the
OH
CC
address bits are stabilizing.
4. Pins of ports 1, 2, 3, 4, 5 and 6 source a transition current when they are being externally driven from 1 to 0. The transition current reaches
its maximum value when V is approximately 2V.
IN
5. I MAX at other frequencies is given by:
CC
Active mode: I MAX = 0.94 X FREQ + 13.71
CC
Idle mode: I MAX = 0.14 X FREQ +2.31
CC
where FREQ is the external oscillator frequency in MHz. I MAX is given in mA. See Figure 20.
CC
6. See Figures 21 through 24 for I test conditions.
CC
7. C applies to ports 1 through 6, IDS, ODS, AFLAG, BFLAG, XTAL1, XTAL2.
IO
3-323
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V
CC SS
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
1/t
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
MHz
ns
Oscillator frequency
3.5
16
CLCL
t
t
t
t
t
t
t
t
t
t
t
9
9
9
9
9
9
9
9
9
9
9
ALE pulse width
85
22
32
2t
–40
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
–40
ns
AVLL
LLAX
LLIV
CLCL
CLCL
t
–30
ns
150
82
4t
3t
–100
ns
CLCL
32
t
–30
ns
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
PSEN pulse width
142
3t
–45
ns
CLCL
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–105
ns
CLCL
0
0
ns
37
207
10
t
–25
ns
CLCL
5t
–105
ns
CLCL
10
ns
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
RD pulse width
275
275
6t
–100
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
147
5t
–165
CLCL
0
0
65
2t
–60
CLCL
350
397
239
8t
–150
–165
CLCL
CLCL
9t
AVDV
LLWL
AVWL
QVWX
WHQX
RLAZ
WHLH
137
122
13
3t
–50
3t
+50
CLCL
CLCL
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
4t
t
–130
–50
CLCL
CLCL
CLCL
13
t
–50
RD low to address float
0
0
RD or WR high to ALE high
23
103
t
–40
t
+40
CLCL
CLCL
Shift Register
t
t
t
t
t
12
12
12
12
12
Serial port clock cycle time
750
492
8
12t
ns
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10t
–133
QVXH
XHQX
XHDX
XHDV
CLCL
2t
CLCL
–117
0
0
492
10t
–133
CLCL
Port 6 input (input rise and fall times = 5ns)
t
t
t
t
t
15
15
15
15
16
PE width
209
209
0
3t
+20
+20
ns
ns
ns
ns
ns
FLFH
ILIH
CLCL
IDS width
3t
CLCL
Data setup to IDS high or PE high
Data hold after IDS high or PE high
IDS to BFLAG (IBF) delay
0
DVIH
IHDZ
IVFV
30
30
130
130
3-324
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
AC ELECTRICAL CHARACTERISTICS (Continued)
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
Port 6 output
t
t
t
t
t
t
t
13
14
13
13
13
13
14
ODS width
209
3t
CLCL
+20
ns
ns
ns
ns
ns
ns
ns
OLOH
FVDV
OLDV
OHDZ
OVFV
FLDV
OHFH
SEL to data out delay
85
80
85
80
ODS to data out delay
ODS to data float delay
ODS to AFLAG (OBF) delay
PE to data out delay
35
35
100
120
100
120
ODS to AFLAG (SEL) delay
100
100
External Clock
t
t
t
t
17
17
17
17
High time
Low time
Rise time
Fall time
20
20
20
20
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
20
20
20
20
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3-325
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the
name of a signal or the logical status of that signal. The designations are:
A – Address
C – Clock
R – RD signal
– Time
t
D – Input data
H – Logic level high
V – Valid
W – WR signal
I
– Instruction (program memory contents)
X – No longer a valid logic level
Z – Float
L – Logic level low, or ALE
P – PSEN
Q – Output data
Examples: t
= Time for address valid to ALE low.
= Time for ALE low to PSEN low.
AVLL
LLPL
t
t
LHLL
ALE
t
t
LLPL
AVLL
t
PLPH
t
LLIV
PSEN
t
PLIV
t
PXIZ
t
PLAZ
t
t
PXIX
LLAX
A0–A7
INSTR IN
A0–A7
PORT 0
PORT 2
t
AVIV
A0–A15
A8–A15
SU00056
Figure 9. External Program Memory Read Cycle
ALE
PSEN
RD
t
WHLH
t
LLDV
t
t
LLWL
RLRH
t
RHDZ
t
LLAX
t
t
RLDV
AVLL
t
RLAZ
t
RHDX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA IN
A0–A7 FROM PCL
INSTR IN
t
AVWL
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPH
A0–A15 FROM PCH
SU00007
Figure 10. External Data Memory Read Cycle
3-326
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
ALE
t
WHLH
PSEN
t
t
WLWH
LLWL
WR
t
LLAX
t
t
WHQX
t
AVLL
QVWX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA OUT
A0–A7 FROM PCL
A0–A15 FROM PCH
INSTR IN
t
AVWL
P2.0–P2.7 OR A8–A15 FROM DPH
SU00008
Figure 11. External Data Memory Write Cycle
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
t
XLXL
CLOCK
t
XHQX
t
QVXH
OUTPUT DATA
0
1
2
3
4
5
6
7
WRITE TO SBUF
t
XHDX
t
SET TI
VALID
XHDV
INPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
SU00027
Figure 12. Shift Register Mode Timing
3-327
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
OBF (AFLAG)
t
OVFV
t
OVFV
PE (BFLAG)
t
OLOH
ODS
t
t
OHDZ
OLDV
PORT 6
t
FLDV
SU00088
Figure 13. Port 6 Output
ODS
t
OHFH
SEL (AFLAG)
t
t
FVDV
FVDV
PORT 6
DATA
CSR
DATA
SU00089
Figure 14. Port 6 Select Mode
t
FLFH
PE (BFLAG)
t
ILIH
IDS
t
IHDZ
t
DVIH
PORT 6
SU00090
Figure 15. Port 6 Input
IBF (BFLAG)
t
t
IVFV
IVFV
IDS
SU00091A
Figure 16. IBF Flag Output
3-328
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
V
–0.5
CC
0.7V
CC
–0.1
0.45V
0.2V
CC
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
SU00009
Figure 17. External Clock Drive
V
–0.5
CC
V
+0.1V
–0.1V
V
V
–0.1V
TIMING
REFERENCE
POINTS
LOAD
OH
+0.1V
OL
0.2V
0.2V
+0.9
–0.1
CC
V
LOAD
CC
V
LOAD
0.45V
NOTE:
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from
load voltage occurs, and begins to float when a 100mV change from the loaded
AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.
CC
IH
IL
V
/V level occurs. I /I ≥ ±20mA.
OH OL
OH OL
SU00717
SU00718
Figure 18. AC Testing Input/Output
Figure 19. Float Waveform
30
25
20
MAX ACTIVE MODE
15
10
5
TYP ACTIVE MODE
I
mA
CC
MAX IDLE MODE
TYP IDLE MODE
4MHz
8MHz
12MHz
16MHz
FREQ AT XTAL1
VALID ONLY WITHIN FREQUENCY SPECIFICATIONS OF THE DEVICE UNDER TEST.
SU00092
Figure 20. I vs. FREQ
CC
3-329
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
V
V
CC
CC
I
I
CC
CC
V
V
CC
CC
V
V
V
RST
CC
CC
CC
P0
P0
EA
RST
EA
V
(NC)
XTAL2
XTAL1
CC
(NC)
XTAL2
V
CC
CLOCK SIGNAL
CLOCK SIGNAL
XTAL1
V
IDS
V
SS
IDS
SS
ODS
ODS
SU00093
SU00094
Figure 21. I Test Condition, Active Mode
Figure 22. I Test Condition, Idle Mode
CC
CC
All other pins are disconnected
All other pins are disconnected
V
–0.5
CC
0.7V
CC
CC
0.45V
0.2V
–0.1
t
CHCX
t
t
t
CLCH
CHCL
CLCX
t
CLCL
SU00009
Figure 23. Clock Signal Waveform for I Tests in Active and Idle Modes
CC
t
= t
= 5ns
CHCL
CLCH
V
CC
CC
I
CC
V
CC
RST
V
V
P0
EA
(NC)
XTAL2
XTAL1
CC
V
IDS
SS
ODS
SU00095
Figure 24. I Test Condition, Power Down Mode
CC
All other pins are disconnected. V = 2V to 5.5V
CC
3-330
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
Program Verification
EPROM CHARACTERISTICS
If lock bit 2 has not been programmed, the on-chip program memory
can be read out for program verification. The address of the program
memory locations to be read is applied to ports 1 and 2 as shown in
Figure 27. The other pins are held at the ‘Verify Code Data’ levels
indicated in Table 4. The contents of the address location will be
emitted on port 0. External pull-ups are required on port 0 for this
operation.
The 87C453 is programmed by using a modified Quick-Pulse
Programming algorithm. It differs from older methods in the value
used for V (programming supply voltage) and in the width and
PP
number of the ALE/PROG pulses.
The 87C453 contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as an 87C453 manufactured by
Philips Semiconductors.
If the encryption table has been programmed, the data presented at
port 0 will be the exclusive NOR of the program byte with one of the
encryption bytes. The user will have to know the encryption table
contents in order to correctly decode the verification data. The
encryption table itself cannot be read out.
Table 4 shows the logic levels for reading the signature byte, and for
programming the program memory, the encryption table, and the
lock bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 25 and 26. Figure 27 shows the
circuit configuration for normal program memory verification.
Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031H, except that P3.6 and P3.7
need to be pulled to a logic low. The values are:
(030H) = 15H indicates manufactured by Philips
(031H) = B9H indicates 87C453
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in
Figure 26. Note that the 87C453 is running with a 4 to 6MHz
oscillator. The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 4, and
which satisfies the timing specifications, is suitable.
The address of the EPROM location to be programmed is applied to
ports 1 and 2, as shown in Figure 25. The code byte to be
programmed into that location is applied to port 0. RST, PSEN and
pins of ports 2 and 3 specified in Table 4 are held at the ‘Program
Code Data’ levels indicated in Table 4. The ALE/PROG is pulsed
low 15 to 25 times, as shown in Figure 26.
Erasure Characteristics
Erasure of the EPROM begins to occur when the chip is exposed to
light with wavelengths shorter than approximately 4,000 angstroms.
Since sunlight and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about
1 week in sunlight, or 3 years in room level fluorescent lighting)
could cause inadvertent erasure. For this and secondary effects,
it is recommended that an opaque label be placed over the
window. For elevated temperature or environments where solvents
are being used, apply Kapton tape Fluorglas part number 2345–5, or
equivalent.
To program the encryption table, repeat the 15 to 25 pulse
programming sequence for addresses 0 through 1FH, using the
‘Pgm Encryption Table’ levels. Do not forget that after the encryption
table is programmed, verification cycles will produce only encrypted
data.
To program the lock bits, repeat the 15 to 25 pulse programming
sequence using the ‘Pgm Lock Bit’ levels. After one lock bit is
programmed, further programming of the code memory and
encryption table is disabled. However, the other lock bit can still be
programmed.
The recommended erasure procedure is exposure to ultraviolet light
(at 2537 angstroms) to an integrated dose of at least 15W-sec/cm .
Exposing the EPROM to an ultraviolet lamp of 12,000µW/cm rating
for 20 to 39 minutes, at a distance of about 1 inch, should be
sufficient.
2
2
Note that the EA/V pin must not be allowed to go above the
PP
maximum specified V level for any amount of time. Even a narrow
PP
glitch above that voltage can cause permanent damage to the
Erasure leaves the array in an all 1s state.
device. The V source should be well regulated and free of glitches
PP
and overshoot.
Table 4.
EPROM Programming Modes
MODE
RST
PSEN
ALE/PROG
EA/V
P2.7
P2.6
P3.7
P3.6
PP
Read signature
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
0
1
1
0
1
0
Program code data
Verify code data
Pgm encryption table
Pgm lock bit 1
0*
1
V
PP
1
0*
0*
0*
V
PP
PP
PP
V
V
Pgm lock bit 2
NOTES:
1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. V = 12.75V ±0.25V.
PP
3. V = 5V ±10% during programming and verification.
CC
*
ALE/PROG receives 15 to 25 programming pulses while V is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high
PP
for a minimum of 10µs.
Trademark phrase of Intel Corporation.
3-331
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
+5V
V
CC
P0
A0–A7
PGM DATA
P1
1
1
1
RST
P3.6
+12.75V
EA/V
PP
15 TO 25 100µs PULSES TO GROUND
ALE/PROG
PSEN
0
1
87C453
P3.7
XTAL2
P2.7
0
P2.6
4–6MHz
XTAL1
A8–A12
P2.0–P2.4
V
SS
SU00159
Figure 25. Programming Configuration
15 TO 25 PULSES
1
0
ALE/PROG:
ALE/PROG:
10µs MIN
100µs+10
1
0
SU00160
Figure 26. PROG Waveform
+5V
V
CC
P0
A0–A7
PGM DATA
P1
1
1
1
RST
P3.6
1
1
EA/V
PP
ALE/PROG
PSEN
0
87C453
P3.7
0 ENABLE
XTAL2
P2.7
0
P2.6
4–6MHz
XTAL1
A8–A12
P2.0–P2.4
V
SS
SU00161
Figure 27. Program Verification
3-332
1996 Aug 15
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
80C453/83C453/87C453
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
T
amb
= 21°C to +27°C, V = 5V±10%, V = 0V (See Figure 28)
CC SS
SYMBOL
PARAMETER
MIN
MAX
13.0
50
UNIT
V
V
PP
Programming supply voltage
Programming supply current
Oscillator frequency
12.5
I
PP
mA
MHz
1/t
CLCL
4
6
t
t
t
t
t
t
t
t
t
t
t
t
Address setup to PROG low
Address hold after PROG
Data setup to PROG low
Data hold after PROG
48t
AVGL
CLCL
CLCL
CLCL
CLCL
CLCL
48t
48t
48t
48t
GHAX
DVGL
GHDX
EHSH
SHGL
GHSL
GLGH
AVQV
ELQZ
EHQZ
GHGL
P2.7 (ENABLE) high to V
PP
V
PP
V
PP
setup to PROG low
hold after PROG
10
10
90
µs
µs
µs
PROG width
110
Address to data valid
48t
CLCL
CLCL
CLCL
ENABLE low to data valid
Data float after ENABLE
PROG high to PROG low
48t
48t
0
10
µs
PROGRAMMING*
ADDRESS
VERIFICATION*
ADDRESS
P1.0–P1.7
P2.0–P2.4
t
AVQV
PORT 0
DATA IN
DATA OUT
t
t
t
DVGL
GHDX
GHAX
t
AVGL
ALE/PROG
t
t
GLGH
GHGL
t
t
SHGL
GHSL
LOGIC 1
LOGIC 1
EA/V
PP
LOGIC 0
t
t
t
EHSH
ELQV
EHQZ
P2.7
ENABLE
SU00020
NOTE:
*
FOR PROGRAMMING VERIFICATION SEE FIGURE 25.
FOR VERIFICATION CONDITIONS SEE FIGURE 27.
Figure 28. EPROM Programming and Verification
3-333
1996 Aug 15
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