P80C528FBA [NXP]
CMOS single-chip 8-bit microcontroller; CMOS单芯片8位微控制器
| 型号： | P80C528FBA |
| 厂家： | 
NXP |
| 描述： | CMOS single-chip 8-bit microcontroller |
| 文件： | 总26页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
80C528/83C528
CMOS single-chip 8-bit microcontroller
Product specification
IC20 Data Handbook
1995 Feb 02
Philips
Semiconductors
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
multi-source, two-priority-level, nested
DESCRIPTION
FEATURES
interrupt structure, two serial interfaces
The 8XC528 single-chip 8-bit microcontroller
• 80C51 instruction set
2
(UART and I C-bus), and on-chip oscillator
and timing circuits.
is manufactured in an advanced CMOS
process and is a derivative of the 80C51
microcontroller family. The 8XC528 has the
same instruction set as the 80C51. Three
versions of the derivative exist:
– 32k × 8 ROM (83C528)
– ROMless (80C528)
In addition, the 8XC528 has two software
selectable modes of power reduction — idle
mode and power-down mode. The idle mode
freezes the CPU while allowing the RAM,
timers, serial port, and interrupt system to
continue functioning. The power-down mode
saves the RAM contents but freezes the
oscillator, causing all other chip functions to
be inoperative.
– 512 × 8 RAM
– Memory addressing capability
64k ROM and 64k RAM
– Three 16-bit counter/timers
– On-chip watchdog timer with oscillator
– Full duplex UART
• 83C528 — 32k bytes mask programmable
ROM
• 80C528 — ROMless version of the
83C528
2
– I C serial interface
• 87C528 — 32k bytes EPROM (described
– Four 8-bit I/O ports
• Power control modes:
– Idle mode
in a separate data sheet)
This device provides architectural
enhancements that make it applicable in a
variety of applications in consumer, telecom
and general control systems, especially in
those systems which need large ROM and
RAM capacity on-chip.
– Power-down mode
– Warm start from power-down
• CMOS and TTL compatible
• Extended temperature ranges
• ROM code protection
The 8XC528 contains a 32k × 8 ROM
(83C528), a 512 × 8 RAM, four 8-bit I/O
ports, two 16-bit timer/event counters
• 7-source and 7-vector interrupt structure
with 2 priority levels
• Up to 3 external interrupt request inputs
(identical to the timers of the 80C51), a 16-bit
timer (identical to the timer 2 of the 80C52), a
watchdog timer with a separate oscillator, a
• Two programmable power reduction modes
(Idle and Power-down)
• Termination of Idle mode by any interrupt,
external or WDT (watchdog) reset
• XTAL frequency range: 1.2 MHz to 16 MHz
PIN CONFIGURATIONS
40
39
38
V
42
41
40
V
DD
1
2
3
1
2
3
DD
T2/P1.0
T2/P1.0
6
1
40
T2EX/P1.1
T2EX/P1.1
P0.0/AD0
P0.1/AD1
P0.0/AD0
P0.1/AD1
P1.2
P1.2
7
39
29
37 P0.2/AD2
36 P0.3/AD3
39 P0.2/AD2
38 P0.3/AD3
P1.3
P1.4
4
5
P1.3
P1.4
4
5
LEADED
CHIP
CARRIER
35
37
P1.5
SCL/P1.6
SDA/P1.7
RST
6
7
8
9
P0.4/AD4
34 P0.5/AD5
33
P1.5
SCL/P1.6
SDA/P1.7
RST
6
7
8
9
P0.4/AD4
36 P0.5/AD5
35
17
P0.6/AD6
32 P0.7/AD7
P0.6/AD6
34 P0.7/AD7
18
44
28
34
31
30
SHRINK
DUAL
IN-LINE
33
EA
EA
RxD/P3.0 10
TxD/P3.1 11
INT0/P3.2 12
INT1/P3.3 13
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
RxD/P3.0 10
DUAL
IN-LINE
PACKAGE
32
31
30
29
28
ALE
11
NC*
NC*
ALE
PACKAGE
29 PSEN
28
TxD/P3.1
INT0/P3.2
12
13
1
33
23
P2.7/A15
27 P2.6/A14
PSEN
QUAD
FLAT
PACK
INT1/P3.3 14
T0/P3.4 15
P2.7/A15
P2.6/A14
26
25
P2.5/A13
P2.4/A12
11
T1/P3.5
WR/P3.6
RD/P3.7
16
17
18
27 P2.5/A13
24 P2.3/A11
26
P2.4/A12
23
22
21
25
P2.2/A10
P2.1/A9
P2.0/A8
P2.3/A11
12
22
24
XTAL1 19
XTAL2 19
P2.2/A10
V
20
XTAL1
20
21
23
22
P2.1/A9
P2.0/A8
SS
V
SS
* DO NOT CONNECT
2
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
CERAMIC AND PLASTIC LEADED PLASTIC QUAD FLAT PACK
CHIP CARRIER PIN FUNCTIONS
PIN FUNCTIONS
44
34
6
1
40
7
39
29
1
33
23
PLCC
PQFP
11
17
18
28
12
22
Pin
1
Function
NC*
Pin
Function
NC*
Pin
1
Function
P1.5
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
2
P1.0/T2
P1.1/T2EX
P1.2
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
2
P1.6/SCL
P1.7/SDA
RST
3
3
4
4
5
P1.3
5
P3.0/RxD
NC*
ALE
6
P1.4
6
NC*
7
P1.5
7
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7RD
XTAL2
EA
8
P1.6/SCL
P1.7/SDA
RST
8
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
17
18
19
20
21
22
P3.0/RxD
NC*
ALE
NC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
XTAL1
V
V
DD
SS
NC*
NC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P1.0/T2
P1.1/T2EX
P1.2
XTAL1
P1.3
V
V
P1.4
SS
DD
* DO NOT CONNECT
* DO NOT CONNECT
LOGIC SYMBOL
V
V
SS
DD
XTAL1
ADDRESS AND
DATA BUS
XTAL2
T2
T2EX
RST
EA
PSEN
ALE
SCL
SDA
RxD
TxD
INT0
INT1
T0
ADDRESS BUS
T1
WR
RD
3
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
ORDERING INFORMATION
PHILIPS
PART ORDER NUMBER
PART MARKING
PHILIPS NORTH AMERICA
PART ORDER
NUMBER
o
Drawing
Number
TEMPERATURE C RANGE
FREQ
MHz
ROMless
ROM
ROMless
ROM
AND PACKAGE
P80C528FBP P83C528FBP/xxx P80C528FBP N P83C528FBP N SOT129-1
0 to +70, Plastic Dual In-line Package
16
P80C528FBA P83C528FBA/xxx P80C528FBA A P83C528FBA A SOT187-2
0 to +70, Plastic Leaded Chip Carrier
16
P80C528FBB P83C528FBB/xxx P80C528FBB B P83C528FBB B SOT307-2
P80C528FFP P83C528FFP/xxx P80C528FFP N P83C528FFP N SOT129-1
0 to +70, Plastic Quad Flat Pack
16
16
–40 to +85, Plastic Dual In-line Package
P80C528FFA P83C528FFA/xxx P80C528FFA A P83C528FFA A
SOT187-2
–40 to +85, Plastic Leaded Chip Carrier
16
P80C528FFB P83C528FFB/xxx P80C528FFB B P83C528FFB B
SOT307-2
–40 to +85, Plastic Quad Flat Pack
–40 to +125, Plastic Dual In-line Package
–40 to +125, Plastic Leaded Chip Carrier
–40 to +125, Plastic Quad Flat Pack
16
16
16
16
P80C528FHP P83C528FHP/xxx P80C528FHP N P83C528FHP N SOT129-1
P80C528FHA P83C528FHA/xxx P80C528FHA A P83C528FHA A SOT187-2
P80C528FHB P83C528FHB/xxx P80C528FHB B P83C528FHB B SOT307-2
P83C528FBR/xxx
SOT270-1 0 to +70, Plastic Shrink Dual In-Linr Package
16
NOTE:
1. xxx denotes the ROM code number.
4
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
o
Drawing
Number
TEMPERATURE C RANGE
AND PACKAGE
FREQ
MHz
EPROM
P87C528EBP N
P87C528EBF FA
P87C528EBA AA
P87C528EBL KA
SOT129-1
0590B
0 to +70, Plastic Dual In-line Package
16
16
16
16
0 to +70, Ceramic Dual In-line Package
w/Window
SOT187-2
1472A
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Ceramic Leaded Chip Carrier
w/Window
P87C528EBB B
P87C528EFP N
SOT307-2
SOT129-1
0 to +70, Plastic Quad Flat Pack
16
16
–40 to +85, Plastic Dual In-line Package
–40 to +85, Ceramic Dual In-line Package
w/Window
P87C528EFF FA
P87C528EFF FA
P87C528EFL KA
P87C528EFB B
0590B
SOT187-2
1472A
16
16
16
16
–40 to +85, Plastic Leaded Chip Carrier
–40 to +85, Ceramic Leaded Chip Carrier
w/Window
SOT307-2
–40 to +85, Plastic Quad Flat Pack
0 to +70, Plastic Dual In-line Package
P87C528GBP N
P87C528GBF FA
P87C528GBA A
P87C528GBL KA
P87C528GFP N
P87C528GFF FA
P87C528GFA A
P87C528GFL KA
SOT129-1
0590B
20
20
20
20
20
20
20
20
0 to +70, Ceramic Dual In-line Package
w/Window
SOT187-2
1472A
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Ceramic Leaded Chip Carrier
w/Window
SOT129-1
0590B
–40 to +85, Plastic Dual In-line Package
–40 to +85, Ceramic Dual In-line Package
w/Window
SOT187-2
1472A
–40 to +85, Plastic Leaded Chip Carrier
–40 to +85, Ceramic Leaded Chip Carrier
w/Window
5
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
BLOCK DIAGRAM
FREQUENCY
REFERENCE
COUNTERS
T0 T1
RST
XTAL2 XTAL1
T2
T2EX
RAM
AUX–RAM
PROGRAM
MEMORY
(32K x 8 ROM)
OSCILLATOR
AND
TIMING
DATA
MEMORY
(256 x 8)
DATA
MEMORY
(256 x 8)
TWO 16-BIT
TIMER/EVENT
COUNTERS
WATCHDOG
TIMER
16-BIT TIMER /
EVENT COUNTER
CPU
PROGRAMMABLE
SERIAL PORT
FULL DUPLEX UART
64K-BYTE BUS
EXPANSION
CONTROL
BIT-LEVEL
I C
INTERFACE
2
PROGRAMMABLE I/O
INTERNAL
INTERRUPTS
SYNCHRONOUS SHIFT
SERIAL IN
SERIAL OUT
INT0 INT1
CONTROL
PARALLEL PORTS,
ADDRESS/DATA BUS
AND I/O PINS
SDA
SCL
SHARED WITH
PORT 3
EXTERNAL
INTERRUPTS
6
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
PIN DESCRIPTION
PIN NO.
MNEMONIC
DIP
SDIL
LCC
QFP TYPE
NAME AND FUNCTION
Ground: circuit ground potential.
Power Supply: +5V power supply pin during normal operation, Idle mode and
V
V
20
40
21
42
22
44
16
38
I
I
SS
DD
Power-down mode.
P0.0–0.7
39–32 41–34 43–36 37–30
I/O
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high-impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during accesses to external program
and data memory. In this application, it uses strong internal pull-ups when emitting
1s.
P1.0–P1.7
1–8
1–8
2–9
40–44
1–3
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and
P1.7 which have open drain. Port 1 pins that have 1s written to them are pulled high
by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are
externally pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: I ). Port 1 can sink/source one TTL (4 LSTTL) inputs.
IL
1
2
7
8
1
2
7
8
2
3
8
9
40
41
2
I
I
T2 (P1.0): Timer/counter 2 external count input (following edge triggered).
T2EX (P1.1): Timer/counter 2 trigger input.
2
I/O
I/O
SCL (P1.6): I C serial port clock line.
2
3
SDA (P1.7): I C serial port data line.
P2.0–P2.7
21–28 22–29 24–31 18–25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 2 pins that are externally being pulled low will source current
because of the internal pull-ups. (See DC Electrical Characteristics: I ). Port 2
IL
emits the high-order address byte during fetches from external program memory
and during accesses to external data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s.
During accesses to external data memory that use 8-bit addresses (MOV @Ri), port
2 emits the contents of the P2 special function register.
P3.0–P3.7
10–17 10–18
11,
5,
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 3 pins that are externally being pulled low will source current
(11=NC) 13–19 7–13
because of the pull-ups. (See DC Electrical Characteristics: I ). Port 3 also serves
IL
the special features of the SC80C51 family, as listed below:
10
11
12
13
14
15
16
17
10
12
13
14
15
16
17
18
11
13
14
15
16
17
18
19
5
7
8
I
O
I
I
I
I
O
O
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
9
10
11
12
13
RST
ALE
9
9
10
4
I/O
Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to V permits a power-on reset
SS
using only an external capacitor to V . After a watchdog timer overflow, this pin is
DD
pulled high while the internal reset signal is active.
30
31
33
27
I/O
Address Latch Enable: Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or
clocking. Note that one ALE pulse is skipped during each access to external data
memory.
PSEN
EA
29
31
30
33
32
35
26
29
O
I
Program Store Enable: The read strobe to external program memory. When the
device is executing code from the external program memory, PSEN is activated
twice each machine cycle, except that two PSEN activations are skipped during
each access to external data memory. PSEN is not activated during fetches from
internal program memory.
External Access Enable: EA must be externally held low during RESET to enable
the device to fetch code from external program memory locations 0000H to 7FFFH.
If EA is held high during RESET, the device executes from internal program memory
unless the program counter contains an address greater than 7FFFH. EA is don’t
care after RESET.
XTAL1
XTAL2
19
18
20
19
21
20
15
14
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
O
Crystal 2: Output from the inverting oscillator amplifier.
7
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
Table 1.
8XC524/8XC528 Special Function Registers
DIRECT
DESCRIPTION
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
RESET
VALUE
SYMBOL
ADDRESS MSB
LSB
E0
ACC*
B*
Accumulator
B register
E0H
F0H
E7
F7
E6
F6
E5
F5
E4
F4
E3
F3
E2
F2
E1
F1
00H
F0
00H
DPTR:
DPH
DPL
Data pointer (2 bytes):
Data pointer high
Data pointer low
83H
82H
00H
00H
AF
EA
BF
–
AE
ES1
BE
AD
ET2
BD
AC
ES0
BC
AB
ET1
BB
AA
EX1
BA
A9
ET0
B9
A8
EX0
B8
IE*#
IP*#
Interrupt enable
Interrupt priority
A8H
B8H
00H
PS1
PT2
PS0
PT1
PX1
PT0
PX0
x0000000B
87
86
85
84
83
82
81
80
P0*
P1*
P2*
Port 0
Port 1
Port 2
80H
90H
A0H
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
FFH
FFH
FFH
97
96
95
–
94
–
93
–
92
–
91
90
T2
SDA
SEL
T2EX
A7
A6
A5
A4
A3
A2
A1
A9
A0
A8
A15
A14
A13
A12
A11
A10
B7
RD
B6
WR
–
B5
T1
–
B4
T0
–
B3
B2
B1
TxD
PD
B0
RxD
IDL
P3*
Port 3
B0H
87H
INT1
GF1
INT0
GF0
FFH
PCON
Power control
SMOD
0xxx0000B
D7
CY
D6
AC
D5
F0
D4
D3
D2
D1
F1
D0
P
PSW*
Program status word
D0H
RS1
RS0
OV
00H
RCAP2H# Capture high
RCAP2L# Capture low
CBH
CAH
99H
00H
00H
xxxxxxxxB
SBUF
Serial data buffer
9F
SM0
SDI
SD0
INT
DF
9E
SM1
0
9D
SM2
0
9C
REN
0
9B
TB8
0
9A
RB8
0
99
TI
98
RI
SCON*
S1BIT#
Serial controller
98H
D9H/RD
WR
00H
2
Serial I C data
0
0
x0000000B
0xxxxxxxB
0xxxxxxxB
X
X
X
X
X
X
X
2
S1INT#
S1SCS*#
SP
Serial I C interrupt
DAH
X
X
X
X
X
X
X
DE
SCI
SC0
DD
CLH
CLH
DC
BB
X
DB
RBF
X
DA
WBF
X
D9
STR
STR
D8
ENS
ENS
2
Serial I C control
D8H/RD
WR
SDI
SD0
xxxx0000B
00xxxx00B
07H
Stack pointer
Timer control
Timer 2 control
81H
8F
TF1
CF
8E
TR1
CE
8D
TF0
8C
TR0
CC
8B
IE1
8A
IT1
CA
89
IE0
C9
88
IT0
TCON*
T2CON*#
88H
C8H
00H
00H
CD
CB
C8
CP/RL2
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
TH0
TH1
TH2#
TL0
TL1
TL2#
T3#
Timer high 0
Timer high 1
Timer high 2
Timer low 0
Timer low 1
Timer low 2
Watchdog timer
8CH
8DH
CDH
8AH
8BH
CCH
FFH
00H
00H
00H
00H
00H
00H
00H
TMOD
Timer mode
89H
A5H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
A5H
WDCON# Watchdog control
*
SFRs are bit addressable.
#
SFRs are modified from or added to the 80C51 SFRs.
8
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
Table 2.
Internal and External Program Memory Access with Security Bit Set
ACCESS TO INTERNAL
PROGRAM MEMORY
ACCESS TO EXTERNAL
PROGRAM MEMORY
INSTRUCTION
MOVC in internal program memory
MOVC in external program memory
YES
NO
YES
YES
program has to reload the watchdog timer
within periods that are shorter than the
programmed watchdog timer internal. This
time interval is determined by an 8-bit value
that has to be loaded in register T3 while at
the same time the prescaler is cleared by
hardware.
ROM CODE PROTECTION
TIMER 2
By setting a mask programmable security bit,
the ROM content in the 83C528 is protected,
i.e., it cannot be read out by any test mode or
by any instruction in the external program
memory space. The MOVC instructions are
the only ones which have access to program
code in the internal or external program
memory. The EA input is latched during
RESET and is ‘don’t care’ after RESET (also
if security bit is not set). This implementation
prevents reading from internal program code
by switching from external program memory
to internal program memory during MOVC
instruction or an instruction that handles
immediate data. Table 2 lists the access to
the internal and external program memory by
the MOVC instructions when the security bit
has been set to logical one. If the security bit
has been set to a logical 0 there are no
restrictions for the MOVC instructions.
Timer 2 is functionally equal to the Timer 2 of
the 8052AH. Timer 2 is a 16-bit timer/counter.
These 16 bits are formed by two special
function registers TL2 and TH2. Another pair
of special function register RCAP2L and
RCAP2H form a 16-bit capture register or a
16-bit reload register. Like Timer 0 and 1, it
can operate either as a timer or as an event
counter. This is selected by bit C/T2N in the
special function register T2CON. It has three
operating modes: capture, autoload, and
baud rate generator mode which are selected
by bits in T2CON.
Watchdog timer interval =
[256 * (T3)] 2048
on * chip oscillator frequency
2
BIT-LEVEL I C INTERFACE
This bit-level serial I/O interface supports the
2
I C-bus. P1.6/SCL and P1.7/SDA are the
2
serial I/O pins. These two pins meet the I C
WATCHDOG TIMER T3
specification concerning the input levels and
output drive capability. Consequently, these
pins have an open drain output configuration.
The watchdog timer consists of an 11-bit
prescaler and an 8-bit timer formed by
special function register T3. The prescaler is
incremented by an on-chip oscillator with a
fixed frequency of 1MHz. The maximum
tolerance on this frequency is –50% and
+100%. The 8-bit timer increments every
2048 cycles of the on-chip oscillator. When a
timer overflow occurs, the microcontroller is
reset and a reset output pulse of 16 × 2048
cycles of the on-chip oscillator is generated
at pin RST. The internal RESET signal is not
inhibited when the external RST pin is kept
low by, for example, an external reset circuit.
The RESET signal drives port 1, 2, 3 into the
high state and port 0 into the high impedance
state.
2
All the four modes of the I C-bus are
supported:
– master transmitter
– master receiver
– slave transmitter
– slave receiver
INTERNAL DATA MEMORY
The internal data memory is divided into
three physically separated segments: 256
bytes of RAM, 256 bytes of AUX-RAM, and a
128 bytes special function area. These can
be addressed each in a different way.
– RAM 0 to 127 can be addressed directly
and indirectly as in the 80C51. Address
pointers are R0 and R1 of the selected
register bank.
2
The advantages of the bit-level I C hardware
2
compared with a full software I C
implementation are:
– the hardware can generate the SCL pulse
– Testing a single bit (RBF respectively,
WBF) is sufficient as a check for error free
transmission.
– RAM 128 to 255 can only be addressed
indirectly as in the 80C51. Address
pointers are R0 and R1 of the selected
register bank.
The watchdog timer is controlled by one
special function register WDCON with the
direct address location A5H. WDCON can be
read and written by software. A value of A5H
in WDCON halts the on-chip oscillator and
clears both the prescaler and timer T3. After
the RESET signal, WDCON contains A5H.
Every value other than A5H in WDCON
enables the watchdog timer. When the
watchdog timer is enabled, it runs
2
The bit-level I C hardware operates on serial
bit level and performs the following functions:
– filtering the incoming serial data and clock
signals
– AUX-RAM 0 to 255 is indirectly addressed
in the same way as external data memory
with the MOVX instructions. Address
pointers are R0, R1 of the selected register
bank and DPTR. An access to AUX-RAM 0
to 255 will not affect ports P0, P2, P3.6 and
P3.7.
– recognizing the START condition
– generating a serial interrupt request SI
after reception of a START condition and
the first falling edge of the serial clock
– recognizing the STOP condition
– recognizing a serial clock pulse on the SCL
line
independently of the XTAL-clock.
An access to external data memory locations
higher than 255 will be performed with the
MOVX DPTR instructions in the same way as
in the 8051 structure, so with P0 and P2 as
data/address bus and P3.6 and P3.7 as write
and read timing signals. Note that these
external data memory cannot be accessed
with R0 and R1 as address pointer.
Timer T3 can be read on the fly. Timer T3
can only be written if WDCON contains the
value 5AH. A successful write operation to
T3 will clear the prescaler and WDCON,
leaving the watchdog enabled and preventing
inadvertent changes of T3. To prevent an
overflow of the watchdog timer, the user
– latching a serial bit on the SDA line (SDI)
– stretching the SCL LOW period of the
serial clock to suspend the transfer of the
next serial data bit
9
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
2
– setting Read Bit Finished (RBF) when the
SCL clock pulse has finished and Write Bit
Finished (WBF) if there is no arbitration
loss detected (i.e., SDA = 0 while SDO = 1)
– setting a serial clock Low-to-High detected
(CLH) flag
– guarding the I C status if RBF or WBF = 0.
IP: Interrupt Priority Register
This register is located at address B8H. Refer
to Table 4.
Additionally, if acting as master:
– generating START and STOP conditions
– handling bus arbitration
IP SFR (B8H)
7
6
5
4
3
2
1
0
– generating serial clock pulses if S1BIT is
not used.
–
PS1
PT2
PS
PT1 PX1 PT0 PX0
– setting a Bus Busy (BB) flag on a START
condition and clearing this flag on a STOP
condition
2
Three SFRs control the bit-level I C interface:
S1INT, S1BIT and S1SCS.
The interrupt vector locations and the
interrupt priorities are:
– releasing the SCL line and clearing the
CLH, RBF and WBF flags to resume
transfer of the next serial data bit
Source
Vector
0003H
Priority within Level
INTERRUPT SYSTEM
Address
IE0
– generating an automatic clock if the single
bit data register S1BIT is used in master
mode.
The interrupt structure of the 8XC528 is the
same as that used in the 80C51, but includes
two additional interrupt sources: one for the
Highest
002BH TF2+EXF2
2
0053H
000BH TF0
0013H IE1
001BH TF1
0023H R1+T1
SI (I C)
2
third timer/counter, T2, and one for the I C
interface. The interrupt enable and interrupt
priority registers are IE and IP.
The following functions must be done in
software:
2
– handling the I C START interrupts
Lowest
– converting serial to parallel data when
receiving
IE: Interrupt Enable Register
This register is located at address A8H. Refer
to Table 3.
– converting parallel to serial data when
transmitting
IE SFR (A8H)
– comparing the received slave address with
its own
7
6
5
4
3
2
1
0
– interpreting the acknowledge information
EA
ES1
ET2
ES
ET1 EX1 ET0 EX0
Table 3. Description of IE Bits
MNEMONIC
BIT
FUNCTION
EA
IE.7
General enable/disable control:
0 = NO interrupt is enabled.
1 = ANY individually enabled interrupt will be accepted.
ES1
ET2
ES
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
Enable bit-level I C I/O interrupt
2
Enable Timer 2 interrupt
Enable Serial Port interrupt
Enable Timer 1 interrupt
Enable External interrupt 1
Enable Timer 0 interrupt
Enable External interrupt 0
ET1
EX1
ET0
EX0
Table 4. Description of IP Bits
MNEMONIC
–
BIT
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
FUNCTION
Reserved.
2
PS1
PT2
Bit-level I C interrupt priority level
Timer 2 interrupt priority level
Serial Port interrupt priority level
Timer 1 interrupt priority level
External Interrupt 1 priority level
Timer 0 interrupt priority level
External Interrupt 0 priority level
PS
PT1
PX1
PT0
PX0
10
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
signal INT0 and INT1 must be kept low until
the oscillator has restarted and stabilized. An
instruction following the instruction that puts
the device in the power-down mode will be
executed. A reset generated by the watchdog
timer terminates the power-down mode in the
same way as an external RESET, and only
the contents of the on-chip RAM are
OSCILLATOR
CHARACTERISTICS
XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol.
IDLE MODE
In idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.
To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.
preserved. The control bits for the reduced
power modes are in the special function
register PCON.
DESIGN CONSIDERATIONS
At power-on, the voltage on V and RST
DD
must come up at the same time for a proper
start-up.
POWER-DOWN MODE
In the power-down mode, the oscillator is
stopped and the instruction to invoke
RESET
When the idle mode is terminated by a
hardware reset, the device normally resumes
program execution, from where it left off, up
to two machine cycles before the internal
reset algorithm takes control. On-chip
hardware inhibits access to internal RAM in
this event, but access to the port pins is not
inhibited. To eliminate the possibility of an
unexpected write when idle is terminated by
reset, the instruction following the one that
invokes idle should not be one that writes to a
port pin or to external memory.
A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To insure a good power-up reset, the
RST pin must be high long enough to allow
the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At
power-down is the last instruction executed.
The power-down mode can be terminated by
a RESET in the same way as in the 80C51 or
in addition by one of two external interrupts,
INT0 or INT1. A termination with an external
interrupt does not affect the internal data
memory and does not affect the special
function registers. This makes it possible to
exit power-down without changing the port
output levels. To terminate the power-down
mode with an external interrupt INT0 or INT1
must be switched to level-sensitive and must
be enabled. The external interrupt input
power-up, the voltage on V and RST must
come up at the same time for a proper
start-up.
DD
Table 5 shows the state of I/O ports during
low current operating modes.
Table 5.
External Pin Status During Idle and Power-Down Modes
MODE
PROGRAM MEMORY
Internal
ALE
PSEN
PORT 0
Data
PORT 1
Data
PORT 2
Data
PORT 3
Data
Idle
Idle
1
1
0
0
1
1
0
0
External
Float
Data
Address
Data
Data
Power-down
Power-down
Internal
Data
Data
Data
External
Float
Data
Data
Data
11
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Operating temperature under bias
RATING
UNIT
°C
0 to +70, or –40 to +85, or –40 to +125
–65 to +150
Storage temperature range
°C
Voltage on any other pin to V
–0.5 to V +0.5
V
SS
DD
Input, output current on any two pins
±10
mA
Power dissipation
1.0
W
(based on package heat transfer limitations, not device power consumption)
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise
SS
noted.
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C (V = 5V ±20%), –40°C to +85°C (V = 5V ±20%), or –40°C to +125°C (V = 5V ±10%), V =0V
DD DD DD SS
TEST
LIMITS
SYMBOL
PARAMETER
PART TYPE
CONDITIONS
MIN
MAX
0.2V –0.1
UNIT
V
IL
Input low voltage,
0°C to 70°C
–40°C to +85°C
–40°C to +125°C
–0.5
–0.5
–0.5
V
V
V
DD
except EA, P1.6/SCL, P1.7/SDA
0.2V –0.15
DD
0.2V –0.25
DD
V
IL1
Input low voltage to EA
0°C to 70°C
–40°C to +85°C
–40°C to +125°C
–0.5
–0.5
–0.5
0.2V –0.3
V
V
V
DD
0.2V –0.35
DD
0.2V –0.45
DD
3
V
V
Input low voltage to P1.6/SCL, P1.7/SDA
Input high voltage,
–0.5
0.3V
V
IL2
DD
0°C to 70°C
–40°C to +85°C
–40°C to +125°C
0.2V +0.9
V
DD
V
DD
V
DD
+0.5
+0.5
+0.5
V
V
V
IH
DD
except XTAL1, RST, P1.6/SCL, P1.7/SDA
0.2V +1.0
DD
0.2V +1.0
DD
V
IH1
Input high voltage, XTAL1, RST
0°C to 70°C
–40°C to +85°C
–40°C to +125°C
0.7V
V
DD
V
DD
V
DD
+0.5
+0.5
+0.5
V
V
V
DD
0.7V +0.1
DD
0.7V +0.1
DD
3
V
V
Input high voltage, P1.6/SCL, P1.7/SDA
0.7V
6.0
V
V
IH2
DD
4
Output low voltage, ports 1, 2, 3, except
I
OL
= 1.6mA
0.45
OL
1
P1.6/SCL, P1.7/SDA
1
4
4
V
V
V
Output low voltage, port 0, ALE, PSEN
I
I
= 3.2mA
= 3.0mA
0.45
0.4
V
V
OL1
OL2
OH
OL
Output low voltage, P1.6/SCL, P1.7/SDA
Output high voltage, ports 1, 2, 3
OL
V
V
= 5V ±10%,
DD
I
I
I
= –60µA
= –25µA
= –10µA
2.4
V
V
V
OH
OH
OH
0.75V
DD
DD
0.9V
V
OH1
Output high voltage, Port 0 in external bus mode,
= 5V ±10%,
= –800µA
= –300µA
DD
2
ALE, PSEN, RST
I
I
2.4
0.75V
V
V
OH
OH
DD
I
= –80µA
0.9V
V
OH
DD
I
I
Logical 0 input current, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA
0°C to 70°C
–40°C to +85°C
–40°C to +125°C
V
= 0.45V
–50
–75
–75
µA
µA
µA
IL
IN
Logical 1-to-0 transition current, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA
0°C to 70°C
–40°C to +85°C
–40°C to +125°C
See note 5
–650
–750
–750
µA
µA
µA
TL
12
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
DC ELECTRICAL CHARACTERISTICS (Continued)
T
amb
= 0°C to +70°C (V = 5V ±20%), –40°C to +85°C (V = 5V ±20%), or –40°C to +125°C (V = 5V ±10%), V =0V
DD DD DD SS
TEST
LIMITS
SYMBOL
PARAMETER
PART TYPE
CONDITIONS
MIN
MAX
±10
UNIT
I
Input leakage current, port 0, EA
0.45<Vi<V
µA
IL1
DD
I
Input leakage current, P1.6/SCL, P1.7/SDA
0V<Vi<6.0V
µA
µA
±10
IL2
0V<V <6.0V
DD
I
Power supply current:
Active mode
See notes 6, 7
DD
35
6
mA
mA
Idle mode
Power down mode
Power down mode
100
150
µA
µA
–40°C to +125°C
R
C
Internal reset pull-down resistor
Capacitance of I/O buffer
50
150
10
kΩ
RST
IO
Freq.=1MHz
pF
T
= 25°C
amb
NOTES:
1. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW level ouput voltage of ALE, Port
1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make a 1-to-0
transition during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE line may exceed 0.8V. In such
cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
2. Capacitive loading on Port 0 and Port 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall below the 0.9V
DD
specification when the address bits are stabilizing.
3. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I C specification, so a voltage below 0.3V will be recognized as a logic 0
2
DD
while an input above 0.7V will be recognized as a logic 1.
DD
4. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin:
10mA
OL
Maximum I per 8–bit port: –
OL
Port 0: 26mA
Ports 1, 2, & 3: 15mA
Maximum total I for all output pins: 71mA
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
5. Pins of ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V is approximately 2V.
IN
6. See Figures 9 through 12 for I test conditions.
DD
7. I
I
at other frequencies can be derived from the figure below, where FREQ is the external oscillator frequency in MHz.
is given in mA.
DDMAX
DDMAX
35
30
25
20
15
10
5
MAX ACTIVE MODE
TYP ACTIVE MODE
MAX IDLE MODE
TYP IDLE MODE
0
4
8
12
FREQ. AT XTAL1 (MHz)
VALID ONLY WITHIN FREQUENCY SPECIFICATIONS OF DEVICE UNDER TEST.
16
I
vs. FREQUENCY
DD
13
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
1, 2
AC ELECTRICAL CHARACTERISTICS
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
1/t
FIGURE
PARAMETER
Oscillator frequency
MIN
MAX
MIN
MAX
UNIT
MHz
ns
1
1
1
1
1
1
1
1
1
1
1
1
1.2
16
CLCL
t
t
t
t
t
t
t
t
t
t
t
ALE pulse width
85
8
2t
–40
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
–55
ns
AVLL
LLAX
LLIV
CLCL
CLCL
28
t
–35
ns
150
83
4t
3t
–100
ns
CLCL
23
t
–40
ns
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
PSEN pulse width
143
3t
–45
ns
CLCL
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–105
ns
CLCL
0
0
ns
38
208
10
t
–25
ns
CLCL
5t
–105
ns
CLCL
10
ns
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
RD pulse width
275
275
6t
–100
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
148
5t
–165
CLCL
0
0
Data float after RD
55
2t
–70
CLCL
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
350
398
238
8t
CLCL
9t
CLCL
–150
–165
AVDV
LLWL
AVWL
QVWX
WHQX
RLAZ
WHLH
138
120
3
3t
–50
3t
+50
CLCL
CLCL
4t
t
–130
–60
CLCL
CLCL
CLCL
13
t
–50
RD low to address float
RD or WR high to ALE high
0
0
23
103
t
–40
t
+40
CLCL
CLCL
External Clock
t
t
t
t
6
6
6
6
High time
Low time
Rise time
Fall time
20
20
20
20
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
20
20
20
20
Shift Register
t
t
t
t
t
4
4
4
4
4
Serial port clock cycle time
750
492
8
12t
ns
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10t
–133
QVXH
XHQX
XHDX
XHDV
CLCL
2t
CLCL
–117
0
0
492
10t
–133
CLCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
14
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
2
AC ELECTRICAL CHARACTERISTICS – I C INTERFACE
2
SYMBOL
PARAMETER
INPUT
OUTPUT
I C SPECIFICATION
SCL TIMING CHARACTERISTICS
1
t
t
t
t
t
START condition hold time
SCL LOW time
≥ 14 t
Note 2
Note 2
≥ 4.0µs
≥ 4.7µs
≥ 4.0µs
≤ 1.0µs
≤ 0.3µs
HD;STA
LOW
HIGH
RC
CLCL
≥ 16 t
CLCL
1
3
SCL HIGH time
SCL rise time
≥ 14 t
≥ 80 t
CLCL
CLCL
4
≤ 1µs
Note 5
4
6
SCL fall time
≤ 0.3µs
≤ 0.3µs
FC
SDA TIMING CHARACTERISTICS
t
t
t
t
t
t
t
Data set-up time
≥ 250ns
≥ 0ns
Note 2
Note 2
Note 2
Note 2
Note 2
Note 5
≤ 0.3µs
≥ 250ns
≥ 0ns
SU;DAT1
HD;DAT
SU;STA
SU;STO
BUF
Data hold time
1
1
1
Repeated START set-up time
STOP condition set-up time
Bus free time
≥ 14 t
≥ 4.7µs
≥ 4.0µs
≥ 4.7µs
≤ 1.0µs
≤ 0.3µs
CLCL
CLCL
≥ 14 t
≥ 14 t
CLCL
4
SDA rise time
≤ 1µs
RD
4
6
SDA fall time
≤ 0.3µs
FD
NOTES:
1. At f
2
2
= 3.5MHz, this evaluates to 14 × 286ns = 4µs, i.e., the bit-level I C interface can respond to the I C protocol for f
≥ 3.5MHz.
CLK
CLK
2
2. This parameter is determined by the user software, it has to comply with the I C.
3. This value gives the autoclock pulse length which meets the I C specification for the specified XTAL clock frequency range. Alternatively, the
SCL pulse may be timed by software.
2
4. Spikes on SDA and SCL lines with a duration of less than 4 × f
will be filtered out.
CLK
5. The rise time is determined by the external bus line capacitance and pull-up resistor, it must be ≤ 1µs.
6. The maximum capacitance on bus lines SDA and SCL is 400pF.
15
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The
first character is always ‘t’ (= time). The other
characters, depending on their positions,
indicate the name of a signal or the logical
status of that signal. The designations are:
A – Address
Q – Output data
R – RD signal
t – Time
V – Valid
W– WR signal
X – No longer a valid logic level
Z – Float
C – Clock
D – Input data
H – Logic level high
Examples: t
= Time for address valid
to ALE low.
AVLL
I – Instruction (program memory contents)
L – Logic level low, or ALE
P – PSEN
t
= Time for ALE low to
PSEN low.
LLPL
t
LHLL
ALE
t
t
AVLL
PLPH
t
LLPL
LLIV
t
PSEN
t
PLIV
t
PXIZ
t
t
PLAZ
LLAX
t
PXIX
INSTR IN
A0–A7
A0–A7
PORT 0
PORT 2
t
AVIV
A8–A15
A8–A15
Figure 1. External Program Memory Read Cycle
ALE
PSEN
RD
t
WHLH
t
LLDV
t
t
LLWL
RLRH
t
t
RHDZ
LLAX
t
t
RLDV
AVLL
t
t
RLAZ
RHDX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA IN
A0–A7 FROM PCL
INSTR IN
t
AVWL
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPH
A8–A15 FROM PCH
Figure 2. External Data Memory Read Cycle
16
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
ALE
t
WHLH
PSEN
t
t
WLWH
LLWL
WR
t
LLAX
t
t
WHQX
t
AVLL
QVWX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA OUT
A0–A7 FROM PCL
INSTR IN
t
AVWL
P2.0–P2.7 OR A8–A15 FROM DPF
A8–A15 FROM PCH
Figure 3. External Data Memory Write Cycle
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
t
XLXL
CLOCK
t
XHQX
1
t
QVXH
OUTPUT DATA
0
2
3
4
5
6
7
WRITE TO SBUF
t
t
XHDX
XHDV
SET TI
INPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
Figure 4. Shift Register Mode Timing
repeated START condition
STOP condition
START or repeated START condition
START condition
t
SU;STA
t
RD
0.7 V
DD
SDA
(INPUT/OUTPUT)
0.3 V
DD
t
BUF
t
t
t
FC
FD
RC
t
SU; STO
0.7 V
DD
SCL
(INPUT/OUTPUT)
0.3 V
DD
t
SU;DAT3
t
t
t
t
SU;DAT1
t
t
HD;STA
LOW
HIGH
HD;DAT
SU;DAT2
2
Figure 5. Timing SIO1 (I C) Interface
17
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
V
–0.5
DD
0.7V
DD
–0.1
0.45V
0.2V
DD
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
Figure 6. External Clock Drive
V
–0.5
DD
V
+0.1V
–0.1V
V
V
–0.1V
TIMING
REFERENCE
POINTS
LOAD
OH
0.2V
0.2V
+0.9
–0.1
DD
V
LOAD
DD
V
+0.1V
OL
LOAD
0.45V
NOTE:
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from load
voltage occurs, and begins to float when a 100mV change from the loaded V
AC inputs during testing are driven at V
–0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
DD
/
OH
Timing measurements are made at V min for a logic ’1’ and V for a logic ’0’.
IH IL
V
level occurs. I ≥ ± 20mA.
/I
OL
OH OL
Figure 7. AC Testing Input/Output
Figure 8. Float Waveform
18
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
V
V
DD
DD
I
I
DD
DD
V
V
DD
DD
V
V
V
RST
EA
DD
DD
DD
P0
P0
RST
EA
(NC)
XTAL2
XTAL1
(NC)
XTAL2
XTAL1
P1.6
P1.7
P1.6
*
*
*
CLOCK SIGNAL
CLOCK SIGNAL
P1.7
*
V
V
SS
SS
Figure 9.
I
Test Condition, Active Mode
Figure 10.
I
Test Condition, Idle Mode
DD
DD
All other pins are disconnected
All other pins are disconnected
V
DD
I
DD
V
DD
P0
V
–0.5
DD
RST
EA
V
DD
0.7V
DD
0.45V
0.2V
–0.1
DD
t
CHCX
t
t
CHCL
t
CLCX
CLCH
(NC)
XTAL2
XTAL1
P1.6
P1.7
*
*
t
CLCL
V
SS
Figure 11. Clock Signal Waveform for
Tests in Active and Idle Modes
I
DD
Figure 12.
I
Test Condition, Power Down Mode
DD
t
= t
CHCL
= 5ns
CLCH
All other pins are disconnected. V = 2V to 5.5V
DD
NOTE:
Ports 1.6 and 1.6 should be connected to V through resistors of sufficiently high value such that the sink current into these pins does not
*
DD
exceed the I
specifications.
OL1
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent
2
to use the components in the I C system provided the system conforms to the
I C specifications defined by Philips. This specification can be ordered using the
2
code 9398 393 40011.
19
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
20
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
21
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
22
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)
SOT270-1
23
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
0590B
40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE)
853–0590B 06688
24
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
1472A
44-PIN CERQUAD J-BEND (K) PACKAGE
853-1472A 05854
25
1995 Feb 02
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C528/83C528
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1996
All rights reserved. Printed in U.S.A.
Philips
Semiconductors
相关型号：
P80C528FBBA
IC 8-BIT, 16 MHz, MICROCONTROLLER, PQCC44, PLASTIC, SOT-187, LCC-44, Microcontroller
NXP
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