P80C851FBB [NXP]
CMOS single-chip 8-bit microcontroller with on-chip EEPROM; CMOS单芯片8位微控制器的片上EEPROM
| 型号： | P80C851FBB |
| 厂家： | 
NXP |
| 描述： | CMOS single-chip 8-bit microcontroller with on-chip EEPROM |
| 文件： | 总22页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
Product specification
1998 Jul 03
Supersedes data of 1992 Nov 25
IC20 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
DESCRIPTION
FEATURES
• 80C51 based architecture
– 4k × 8 ROM
The Philips 80C851/83C851 is a
high-performance microcontroller fabricated
with Philips high-density CMOS technology.
The 80C851/83C851 has the same
instruction set as the 80C51. The Philips
CMOS technology combines the high speed
and density characteristics of HMOS with the
low power attributes of CMOS. The Philips
epitaxial substrate minimizes latch-up
sensitivity.
– 128 × 8 RAM
– Two 16-bit counter/timers
– Full duplex serial channel
– Boolean processor
• Non-volatile 256 × 8-bit EEPROM
(electrically erasable programmable read
only memory)
The 80C851/83C851 contains a 4k × 8 ROM
with mask-programmable ROM code
– On-chip voltage multiplier for erase/write
– 10,000 erase/write cycles per byte
– 10 years non-volatile data retention
– Infinite number of read cycles
– User selectable security mode
– Block erase capability
protection, a 128 × 8 RAM, 256 × 8
EEPROM, 32 I/O lines, two 16-bit
counter/timers, a seven-source, five vector,
two-priority level nested interrupt structure,
a serial I/O port for either multi-processor
communications, I/O expansion or full duplex
UART, and on-chip oscillator and clock
circuits.
• Mask-programmable ROM code protection
• Memory addressing capability
– 64k ROM and 64k RAM
In addition, the 80C851/83C851 has two
software selectable modes of power
reduction — idle mode and power-down
mode. The idle mode freezes the CPU while
allowing the RAM, timers, serial port, and
interrupt system to continue functioning. The
power-down mode saves the RAM and
EEPROM contents but freezes the oscillator,
causing all other chip functions to be
inoperative.
• Power control modes:
– Idle mode
– Power-down mode
• CMOS and TTL compatible
• 1.2 to 16MHz or 3.5 to 24MHz
• Three package styles
• Three temperature ranges
• ROM code protection
ORDERING INFORMATION
PHILIPS
PART ORDER NUMBER
PART MARKING
NORTH AMERICA PHILIPS
PART ORDER NUMBER
°
TEMPERATURE RANGE C
AND PACKAGE
ROMless
Version
ROM Version
ROMless
Version
ROM Version
FREQ.
(MHz)
DRAWING
NUMBER
P80C851 FBP P83C851 FBP S80C851-4N40 S83C851-4N40
P80C851 IBP P83C851 IBP
P80C851 FBA P83C851 FBA S80C851-4A44 S83C851-4A44
P80C851 IBA P83C851 IBA
P80C851 FBB P83C851 FBB S80C851-4B44 S83C851-4B44
0 to +70, Plastic Dual In-line Package
0 to +70, Plastic Dual In-line Package
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Plastic Quad Flat Pack
1.2 to 16
3.5 to 24
1.2 to 16
3.5 to 24
1.2 to 16
3.5 to 24
SOT129-1
SOT129-1
SOT187-1
SOT187-1
SOT307-2
SOT307-2
SOT129-1
SOT187-1
SOT307-2
SOT129-1
SOT187-1
SOT307-2
P80C851 IBB
P80C851 FFP
P80C851 FFA
P80C851 FFB
P83C851 IBB
P83C851 FFP
P83C851 FFA
P83C851 FFB
0 to +70, Plastic Quad Flat Pack
S80C851-5N40 S83C851-5N40 –40 to +85, Plastic Dual In-line Package 1.2 to 16
S80C851-5A44 S83C851-5A44
S80C851-5B44 S83C851-5B44
–40 to +85, Plastic Leaded Chip Carrier
–40 to +85, Plastic Quad Flat Pack
1.2 to 16
1.2 to 16
P80C851 FHP P83C851 FHP S80C851-6N40 S83C851-6N40 –40 to +125, Plastic Dual In-line Package 1.2 to 16
P80C851 FHA P83C851 FHA S80C851-6A44 S83C851-6A44 –40 to +125, Plastic Leaded Chip Carrier 1.2 to 16
P80C851 FHB P83C851 FHB S80C851-6B44 S83C851-6B44
–40 to +125, Plastic Quad Flat Pack
1.2 to 16
2
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
BLOCK DIAGRAM
FREQUENCY
REFERENCE
COUNTERS
T0 T1
XTAL2
XTAL1
OSCILLATOR
PROGRAM
MEMORY
(4K x 8 ROM)
DATA
TWO 16-BIT
TIMER/EVENT
COUNTERS
EEPROM
(256 x 8)
AND
MEMORY
TIMING
(128 x 8 RAM)
CPU
INTERNAL
INTERRUPTS
64K BYTE BUS
EXPANSION
CONTRTOL
PROG SERIAL PORT
FULL DUPLEX UART
SYNCHRONOUS SHIFT
PROGRAMMABLE I/O
SERIAL IN
SERIAL OUT
INT0
INT1
CONTROL
PARALLEL PORTS,
ADDRESS/DATA BUS
AND I/O PINS
SHARED WITH
PORT 3
EXTERNAL
INTERRUPTS
LOGIC SYMBOL
V
V
SS
DD
XTAL1
ADDRESS AND
DATA BUS
XTAL2
RST
EA
PSEN
ALE
RxD
TxD
INT0
INT1
T0
ADDRESS BUS
T1
WR
RD
3
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
PIN CONFIGURATIONS
PLASTIC LEADED CHIP
CARRIER PIN FUNCTIONS
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
44
34
P1.0
P1.1
40
39
V
DD
6
1
40
1
2
3
P0.0/AD0
7
39
29
1
33
23
P1.2
P1.3
P1.4
38 P0.1/AD1
37
4
5
P0.2/AD2
36 P0.3/AD3
35
PLCC
PQFP
P1.5
P1.6
P1.7
RST
6
7
8
9
P0.4/AD4
34 P0.5/AD5
33
11
17
18
28
P0.6/AD6
12
22
32 P0.7/AD7
EA
Pin
1
Function
NC*
Pin
Function
NC*
Pin
1
Function
P1.5
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
31
DUAL
IN-LINE
PACKAGE
RxD/P3.0 10
TxD/P3.1 11
INT0/P3.2 12
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
2
P1.0
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
2
P1.6
30 ALE
29
3
P1.1
3
P1.7
PSEN
28 P2.7/A15
27
4
P1.2
4
RST
5
P1.3
5
P3.0/RxD
NC*
ALE
13
INT1/P3.3
6
P1.4
6
NC*
P2.6/A14
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
XTAL1 19
7
P1.5
7
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7RD
XTAL2
XTAL1
EA
8
P1.6
8
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
26 P2.5/A13
25 P2.4/A12
9
P1.7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
RST
10
11
12
13
14
15
16
17
18
19
20
21
22
P3.0/RxD
NC*
ALE
24
P2.3/A11
23 P2.2/A10
22
NC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
P2.1/A9
21 P2.0/A8
V
20
SS
V
V
V
SS
DD
SS
NC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P1.0
P1.1
P1.2
P1.3
P1.4
6
1
40
7
39
V
V
DD
SS
* NO INTERNAL CONNECTION
* NO INTERNAL CONNECTION
PLASTIC
LEADED
CHIP
CARRIER
17
29
18
28
44
34
1
33
PLASTIC
QUAD
FLAT
PACK
11
23
12
22
4
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
PIN DESCRIPTION
PIN NO.
MNEMONIC
DIP
20
LCC
22
QFP
16, 39
38
TYPE
NAME AND FUNCTION
V
SS
V
DD
I
I
Ground: 0V reference.
40
44
Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
P0.0–0.7
39–32 43–36 37–30
I/O
I/O
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory.
In this application, it uses strong internal pull-ups when emitting 1s.
P1.0–P1.7
P2.0–P2.7
1–8
2–9
40–44,
1–3
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 1 pins that are externally pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: I ).
IL
21–28 24–31 18–25
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: I ). Port 2 emits the high-order
IL
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.
P3.0–P3.7
10–17
11,
13–19
5,
7–13
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: I ). Port 3 also serves the special features
IL
of the SC80C51 family, as listed below:
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
I
O
I
I
I
I
O
O
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
9
10
11
12
13
RST
ALE
9
10
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V permits a power-on reset using only an
SS
external capacitor to V
.
DD
30
33
27
I/O
Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency, and can be used for external timing or clocking. Note that one
ALE pulse is skipped during each access to external data memory.
PSEN
EA
29
31
32
35
26
29
O
I
Program Store Enable: The read strobe to external program memory. When the device
is executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
External Access Enable: If during a RESET, EA is held at TTL, level HIGH, the CPU
executes out of the internal program memory ROM provided the Program Counter is less
than 4096. If during a RESET, EA is held a TTL LOW level, the CPU executes out of
external program memory. EA is not allowed to float.
XTAL1
XTAL2
19
18
21
20
15
14
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
O
Crystal 2: Output from the inverting oscillator amplifier.
5
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
Table 1.
8XC851 Special Function Registers
DIRECT
DESCRIPTION
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
ADDRESS MSB
RESET
VALUE
SYMBOL
LSB
E0
ACC*
B*
Accumulator
B register
E0H
F0H
E7
F7
EF
E6
F6
EE
E5
F5
E4
F4
E3
F3
EB
E2
F2
EA
E1
F1
E9
00H
F0
00H
ED
EC
E8
DPTR:
Data pointer
(2 bytes):
High byte
Low byte
DPH
DPL
83H
82H
00H
00H
EADRH#
EEPROM addr
reg-high
F3H
F2H
F6H
F4H
F5H
80H
EADRL#
EEPROM addr
reg-low
00H
ECNTRL# EEPROM control reg
IFE
EEINT
EWP
–
ECNTR ECNTR ECNTR ECNTR 00H
L3
L2
L1
L0
EDAT#
ETIM#
EEPROM data
register
xxH
08H
EEPROM timer
register
BF
–
BE
–
BD
–
BC
PS
BB
BA
B9
B8
IP*
Interrupt priority
B8H
PT1
PX1
PT0
PX0
xxx00000B
AF
EA
AE
–
AD
–
AC
ES
84
94
A4
B4
–
AB
ET1
83
AA
EX1
82
A9
ET0
81
A8
EX0
80
IE*
Interrupt enable
Port 0
A8H
80H
90H
A0H
B0H
87H
0xx00000B
FFH
P0*
87
86
96
A6
B6
–
85
95
A5
B5
–
P1*
Port 1
97
93
92
91
90
FFH
P2*
Port 2
A7
A3
A2
A1
A0
FFH
P3*
Port 3
B7
B3
B2
B1
B0
FFH
PCON
Power control
SMOD
GF1
GF0
PD
IDL
0xxx0000B
D7
CY
D6
AC
D5
F0
D4
D3
D2
D1
–
D0
P
PSW*
SBUF
Program status word
Serial data buffer
D0H
99H
RS1
RS0
OV
00H
xxxxxxxxB
9F
9E
9D
9C
9B
9A
99
TI
98
RI
SCON*
SP
Serial port control
Stack pointer
98H
81H
SM0
SM1
SM2
REN
TB8
RB8
00H
07H
00H
00H
8F
8E
8D
8C
8B
8A
89
88
TCON*
Timer/counter con-
trol
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TMOD
TH0
TH1
TL0
Timer/counter mode
Timer 0 high byte
Timer 1 high byte
Timer 0 low byte
Timer 1 low byte
89H
8CH
8DH
8AH
8BH
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
00H
00H
00H
00H
TL1
*
#
SFRs are bit addressable.
SFRs are modified from or added to the 80C51 SFRs.
6
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
EADRH register address is F3H. The EADRL
register address is F2H.
The ETIM register address is F5H. Table 2
contains the values which must be written to
the ETIM register by software for various
oscillator frequencies (the default value is
08H after RESET).
EEPROM
Communications between the CPU and the
EEPROM is accomplished via 5 special
function registers; 2 address registers (high
and low byte), 1 data register for read and
write operations, 1 control register, and 1
timer register to adapt the erase/write time to
the clock frequency. All registers can be read
and written. Figure 1 shows a block diagram
of the CPU, the EEPROM and the interface.
Data Register (EDAT)
This register is required for read and write
operations and also for row/block erase. In
write mode, its contents are written to the
addressed byte (for “row erase” and “block
erase” the contents are don’t care). The write
pulse starts all operations, except read. In
read mode, EDAT contains the data of the
addressed byte. The EDAT register address
is F4H.
The general formula is:
2ms Write time:
fXTAL1 [kHz]
Value (decimal,
to be rounded up)
+
* 2
512
Register and Functional
Description
Address Register (EADRH, EADRL)
10ms Write time:
fXTAL1 [kHz]
96
Value (decimal)
+
* 2
Timer Register (ETIM)
The timer register is required to adapt the
erase/write time to the oscillator frequency.
The user has to ensure that the erase or
write (program) time is neither too short or
too long.
The lower byte contains the address of one
of the 256 bytes. The higher byte (EADRH) is
for future extensions and for addressing the
security bits (see Security Facilities). The
Control Register (ECNTRL)
See Figure 2 for a description of this register.
The ECNTRL register address is F6H.
Table 2.
Values for the Timer Register (ETIM)
VALUES FOR ETIM
10ms WRITE TIME
f
2ms WRITE TIME
HEX DEC
XTAL1
HEX
DEC
1.0MHz
–
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
–
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
08
13
1D
28
32
3C
47
51
5C
66
71
7B
8
19
29
40
50
60
71
81
92
2.0MHz
3.0MHz
4.0MHz
5.0MHz
6.0MHz
7.0MHz
8.0MHz
9.0MHz
10.0MHz
11.0MHz
12.0MHz
13.0MHz
14.0MHz
15.0MHz
102
113
123
16.0MHz
.
.
24.0MHz
2C
4745
INTERRUPT
CONTROL
LOGIC
8
SEQUENCER
MATRIX
POWER-DOWN IDLE
EEPROM
CLOCK
GENERATOR
RESET
CLK
3
5
COLUMN
ROW
ECNTRL
ETIM
DECODER
DECODER
CPU
8
3
8
EDATA
EADRH
EADRL
INTERNAL BUS
Figure 1. EEPROM Interface Block Diagram
7
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
7
6
5
4
3
2
1
0
EWP
– –
IFE
EEINT
ECNTRL3 ECNTRL2 ECNTRL1 ECNTRL0
Bit
ECNTRL.7
Symbol
IFE
Function
Active high EEPROM interrupt flag: set by the sequencer or by software;
reset by software.
When set and enabled, this flag forces an interrupt to the same vector as the
serial port interrupt (see Interrupt section).
EEPROM interrupt enable: set and reset by software (active high).
Erase/write in progress flag: set and reset by the sequencer (active high).
When EWP is set, access to the EEPROM is not possible. EWP cannot be set or
reset by software.
ECNTRL.6
ECNTRL.5
EEINT
EWP
ECNTRL.4
ECCTRL.3–
ECNTRL.0
Reserved.
See table below.
Operation
ECNTRL.3 ECNTRL.2 ECNTRL.1 ECNTRL.0
Byte mode
Row erase
Page write*
Page erase/write*
block erase
0
1
–
–
1
0
1
–
–
0
0
0
–
–
1
0
0
–
–
0
*Future products.
Byte mode:
Read mode:
Write mode:
Normal EEPROM mode, default mode after reset. In this mode, data can be read and
written to one byte at a time.
This is the default mode when byte mode is selected. This means that the contents of the
addressed byte are available in the data register.
This mode is activated by writing to the data register. The address register must be loaded
first. Since the old contents are read first (by default), this allows the sequencer to decide
whether an erase/write or write cycle only (data = 00H) is required.
Row erase:
In this mode, the addressed row is cleared. The three LSBs of EADRL are not significant,
i.e. the 8 bytes addressed by EADRL are cleared in the same time normally needed to clear
one byte (t
= t = t ). For the following write modes, only the write and not the
E W
ROWERASE
erase/write cycle is required. For example, using the row erase mode, programming 8 bytes
takes t = t + 8 × t compared to t = 8 × t + 8 × t (t = t = t ).
t
TOTOAL
E
W
TOTAL
E
W
E
ERASE
W
WRITE
Page write:
For future products.
Page erase/write: For future products.
Block erase: In this mode all 256 bytes are cleared. The byte containing the security bits is also cleared.
= t . The contents of EADRH, EADRL and EDAT are insignificant.
t
BLOCKERASE
E
Program Sequences and Register Contents after Reset
The contents of the EEPROM registers after a Reset are the default values:
EADRH
EADRL
ETIM
ECNTRL
EDAT
= 1xxxxxxxB
= 00H
= 08H
= 00H
= xxH
(security bit address)
(security bit address)
(minimum erase time with the lowest permissible oscillator frequency)
(Byte mode, read)
(security bit)
Initialize:
MOV ETIM, ..
MOV EADRH, ..
Read:
MOV EADRL, ..
MOV .., EDAT
Write:
MOV EADRL, ..
MOV EDAT, ..
Erase row: MOV EADRL, ..
MOV ECNTRL, #0CH
Row address. 3LSBs don’t care
Erase row mode
MOV EDAT, .. (EDAT) don’t care
Erase block: MOV ECNTRL, 0AH
Erase block mode
MOV EDAT, .. (EDAT) don’t care
If the security bit is to be altered, the program generally starts as follows:
MOV EADRH, #80H
MOV EADRL, #00H
Figure 2. Control Register (ECNTRL)
8
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
the EA pin low or by passing the 4K
mode to internal access within the MOVC
cycle.
Security Facilities
boundary). For SB = 1 and “external access”
only, the “block erase” mode is enabled. The
program sequence has to be as follows:
EEPROM Protection
Additionally, a mask-programmable ROM
code protection facility is available. When the
program memory passes the 4K boundary
using both the internal and external ROMs, it
is not possible to access the internal ROM
from the external program memory if the
mask-programmable ROM security bit is set.
An access to the lower 4K bytes of program
memory using the MOVC instruction is only
possible while executing internal program
memory.
The EEPROM is protected using four security
bits which are contained in an extra
EEPROM byte at address 8000H
(EADRH/EADRL). They can be set or cleared
by software. To activate the EEPROM
protection, the program sequence in byte
mode must be as follows:
MOV EADRH, #80H (security byte address)
MOV EADRL, #00H (security byte address)
MOV ECNTRL, #0AH (block erase mode)
MOV EDAT, #xxH
(start block erase)
All 256 data bytes, the security bits, and SB
will be cleared after completing this mode
(EWP = 0). SB will also be affected in byte
mode when writing to the security byte (not
for SB = 1 and “external access”). Figure 3
illustrates the access to SB.
MOV EADRH, #80H
MOV EADRL, #00H
MOV EDAT, #FFH
If two or more of these bits are reset, SB = 0,
the security mode is disabled and the
EEPROM is not protected. If three or four bits
are set, SB = 1 and the EA mode differs from
the internal access mode.
Also the verification mode (test-mode which
writes the ROM contents to a port for
comparison with a reference code) is not
implemented for security reasons. A different
test-mode is implemented for test purposes.
This mode allows every bit to be tested.
However, the internal code cannot be
accessed via a port.
ROM Code Protection
Since the external access mode can only be
selected by pulling the EA pin low during
reset, it is not possible to read the internal
program memory using the MOVC instruction
while executing external program memory.
Furthermore, it is not possible to change this
In this case, access to the EEPROM is only
possible in one mode regardless of how the
external access mode is reached (by pulling
EADRH
EADRL
EA
RESET
RESET
8
REGISTERS EADRH AND
EADRL CONTAIN THE
ADDRESS OF THE
EEPROM
SECURITY BYTE
RESET
EDATA
n
RESET
SECURITY BYTE ADDRESS
AND BLOCK ERASE FINISHED
EAQ
SECURITY BYTE ADDRESS
AND BYTE MODE FINISHED
L
SB
NO
SB = 1
YES
NO
EXTERNAL
ACCESS
YES
INHIBIT ‘READ DATA REGISTER’
INHIBIT ‘WRITE DATA REGISTER’
EXCEPT (ECNTRL) = BLOCK ERASE
Figure 3. EEPROM Protection (Functional and Flowchart)
9
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
(i.e., the EWP bit has to be reset before
OSCILLATOR
CHARACTERISTICS
XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol,
page 3.
INTERRUPT SYSTEM
activating the idle or power-down modes;
otherwise EEPROM accesses will be
aborted).
External events and the real-time-driven
on-chip peripherals require service by the
CPU asynchronous to the execution of any
particular section of code. To tie the
IDLE MODE
asynchronous activities of these functions to
normal program execution, a multiple-source,
two-priority-level, nested interrupt system is
provided. Interrupt response latency is from
In idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.
To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.
3µs to 7µs when using a 12MHz crystal. The
S83C851 acknowledges interrupt requests
from 7 sources as follows:
– INT0 and INT1: externally via pins 12 and
13, respectively,
– Timer 0 and timer 1: from the two internal
counters,
– Serial port: from the internal serial I/O port
or EEPROM (1 vector).
RESET
A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To insure a good power-up reset, the
RST pin must be high long enough to allow
the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At
Each interrupt vectors to a separate location
in program memory for its service program.
Each source can be individually enabled (the
EEPROM interrupt can only be enabled when
the serial port interrupt is enabled) or
disabled and can be programmed to a high or
low priority level. All enabled sources can
also be globally disabled or enabled. Both
external interrupts can be programmed to be
level-activated and are active low to allow
“wire-ORing” of several interrupt sources to
one input pin.
POWER-DOWN MODE
In the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM and
EEPROM are preserved. A hardware reset is
the only way to terminate the power-down
mode. The control bits for the reduced power
modes are in the special function register
PCON. Table 3 shows the state of the I/O
ports during low current operating modes.
power-up, the voltage on V and RST must
come up at the same time for a proper
start-up.
DD
Note: Before entering the idle or power-down
modes, the user has to ensure that there is
no EEPROM erase/write cycle in progress
Note: The serial port and EEPROM interrupt
flags must be cleared by software; all other
flags are cleared by hardware.
Table 3.
External Pin Status During Idle and Power-Down Modes
MODE
PROGRAM MEMORY
Internal
ALE
PSEN
PORT 0
Data
PORT 1
Data
PORT 2
Data
PORT 3
Data
Idle
Idle
1
1
0
0
1
1
0
0
External
Float
Data
Address
Data
Data
Power-down
Power-down
Internal
Data
Data
Data
External
Float
Data
Data
Data
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
°C
V
Storage temperature range
–65 to +150
Voltage on any other pin to V
–0.5 to +6.5
SS
Input or output DC current on any single I/O pin
mA
W
±5
Power dissipation (based on package heat transfer limitations, not device power consumption)
1.0
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise
SS
noted.
10
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C (V = 5V ±10%), –40°C to +85°C (V = 5V ±10%), or –40°C to +125°C (V = 5V ±10%), V = 0V
DD DD DD SS
PART
TYPE
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
IL
Input low voltage, except EA
0 to +70°C
–40 to +85°C
–40 to +125°C
–0.5
–0.5
–0.5
0.2V –0.1
V
V
V
DD
0.2V –0.15
DD
0.2V –0.25
DD
V
V
V
Input low voltage to EA
0 to +70°C
–40 to +85°C
–40 to +125°C
–0.5
–0.5
–0.5
0.2V –0.3
V
V
V
IL1
IH
DD
0.2V –0.35
DD
0.2V –0.45
DD
Input high voltage, except XTAL1, RST
Input high voltage, XTAL1, RST
0 to +70°C
–40 to +85°C
–40 to +125°C
0.2V +0.9
V
DD
V
DD
V
DD
+0.5
+0.5
+0.5
V
V
V
DD
0.2V +1.0
DD
0.2V +1.0
DD
0 to +70°C
–40 to +85°C
–40 to +125°C
0.7V
V
DD
V
DD
V
DD
+0.5
+0.5
+0.5
IH1
DD
0.7V +0.1
DD
0.7V +0.1
D
6
4
V
V
V
Output low voltage, ports 1, 2, 3
I
I
= 1.6mA
= 3.2mA
0.45
0.45
V
V
OL
OL
6
4
Output low voltage, port 0, ALE, PSEN
OL1
OH
OL
Output high voltage, ports 1, 2, 3, ALE, PSEN
I
I
I
= –60µA,
= –25µA,
= –10µA
2.4
V
V
V
OH
OH
0.75V
DD
DD
0.9V
OH
V
OH1
Output high voltage, port 0 in external bus
mode
I
I
= –800µA,
= –300µA,
2.4
V
V
V
OH
OH
I
5
0.75V
DD
DD
= –80µA
0.9V
OH
I
I
Logical 0 input current, ports 1, 2, 3
0 to +70°C
–40 to +85°C
–40 to +125°C
V
= 0.45V
–50
–75
–75
µA
µA
µA
IL
IN
Logical 1-to-0 transition current, ports 1, 2, 3
0 to +70°C
–40 to +85°C
–40 to +125°C
V
= 2.0V
–650
–750
–750
µA
µA
µA
TL
IN
I
I
Input leakage current, port 0, EA
Power supply current:
0.45V<V<V
DD
µA
±10
L1
i
See note 7
DD
1
Active mode @ 16MHz
19
29
3.7
5.6
50
mA
mA
mA
mA
µA
1
Active mode @ 24MHz
2
2
Idle mode @ 16MHz
Idle mode @ 24MHz
3
Power down mode
R
C
Internal reset pull-down resistor
Pin capacitance
50
150
10
kΩ
RST
IO
f = 1MHz
pF
NOTES:
1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 5ns; V = V +0.5V;
r
f
IL
SS
V
IH
= V – 0.5V; XTAL2 not connected; EA = RST = Port 0 = V
.
DD
DD
2. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 5ns; V = V +0.5V;
r
f
IL
SS
V
IH
= V – 0.5V; XTAL2 not connected; EA = Port 0 = V ; RST = V
.
DD
DD
SS
3. The power-down current is measured with all output pins disconnected; XTAL2 not connected; EA = Port 0 = V ; RST = XTAL1 = V
.
DD
SS
4. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW level output voltage of ALE, Port
1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make a 1-to-0
transition during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE line may exceed 0.8V. In such
cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
5. Capacitive loading on Port 0 and Port 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall below the 0.9V
specification when the address bits are stabilizing.
DD
6. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
10mA
Maximum I per Port pin:
OL
Maximum I per 8-bit port –
OL
Port 0: 26mA
Ports 1, 2, and 3:
Maximum total I for all output pins:
15mA
71mA.
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
7. See Figures 11 through 14 for I test conditions.
DD
11
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
1, 2
AC ELECTRICAL CHARACTERISTICS
16 MHz Version
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
1/t
FIGURE
PARAMETER
Oscillator frequency
MIN
MAX
MIN
MAX
UNIT
MHz
ns
4
4
4
4
4
4
4
4
4
4
4
4
1.2
16
CLCL
t
t
t
t
t
t
t
t
t
t
t
ALE pulse width
85
8
2t
–40
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
t
–55
ns
AVLL
LLAX
LLIV
CLCL
CLCL
28
–35
ns
150
83
4t
3t
–100
ns
CLCL
23
t
–40
ns
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
PSEN pulse width
143
3t
–45
ns
CLCL
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–105
ns
CLCL
0
0
ns
38
208
10
t
–25
ns
CLCL
5t
–105
ns
CLCL
10
ns
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
5
5
RD pulse width
275
275
6t
–100
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
CLCL
WR pulse width
6t
CLCL
5
RD low to valid data in
Data hold after RD
148
5t
–165
CLCL
5
0
0
5
Data float after RD
55
2t
–70
CLCL
5
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to RD or WR low
Data setup time before WR
Data valid to WR transition
Data hold after WR
350
398
238
8t
CLCL
9t
CLCL
–150
–165
5
AVDV
LLWL
5, 6
5, 6
6
138
120
288
3
3t
–50
3t
+50
CLCL
CLCL
4t
7t
t
–130
–150
–60
AVWL
QVWH
QVWX
WHQX
RLAZ
WHLH
CLCL
CLCL
CLCL
CLCL
6
6
13
t
–50
5
RD low to address float
RD or WR high to ALE high
0
0
5, 6
23
103
t
–40
t
+40
CLCL
CLCL
External Clock
t
t
t
t
8
8
8
8
High time
Low time
Rise time
20
20
20
20
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
20
20
20
20
Fall time
3
Erase/write timer constant
t
t
t
t
Erase/write cycle time
Erase time
4
20
10
10
4
20
10
10
ms
ms
E/W
E
2
2
2
2
Write time
ms
W
4
Data retention time
10
10
years
cycles
S
5
NE/W
Erase/write cycles
10,000
10,000
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. The power-off fall-time of V must be less than 1ms to prevent an overwrite pulse from being generated in the EEPROM which can cause
DD
spurious parasitic writing to EEPROM cells. If the V power-off full-time is greater than 1ms, a power-off reset signal should be generated
DD
to prevent this condition from occurring.
4. Test condition: T
= +55°C.
amb
5. Number of erase/write cycles for each EEPROM byte.
12
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
1, 2
AC ELECTRICAL CHARACTERISTICS
24 MHz Version
24MHz CLOCK
VARIABLE CLOCK
SYMBOL
1/t
FIGURE
PARAMETER
Oscillator frequency
MIN
MAX
MIN
MAX
UNIT
MHz
ns
4
4
4
4
4
4
4
4
4
4
4
4
3.5
24
CLCL
t
t
t
t
t
t
t
t
t
t
t
ALE pulse width
43
17
17
2t
–40
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
t
–25
ns
AVLL
LLAX
LLIV
CLCL
CLCL
–25
ns
102
65
4t
3t
–65
ns
CLCL
17
80
t
–25
ns
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
PSEN pulse width
3t
–45
ns
CLCL
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–60
–25
ns
CLCL
0
0
ns
17
128
10
t
ns
CLCL
5t
–80
ns
CLCL
10
ns
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
5
5
RD pulse width
150
150
6t
–100
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
CLCL
WR pulse width
6t
CLCL
5
RD low to valid data in
Data hold after RD
118
5t
2t
–90
–28
CLCL
5
0
0
5
Data float after RD
55
CLCL
5
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to RD or WR low
Data setup time before WR
Data valid to WR transition
Data hold after WR
183
210
175
8t
–150
–165
CLCL
CLCL
5
9t
AVDV
LLWL
5, 6
5, 6
6
75
92
3t
–50
–75
3t
CLCL
+50
CLCL
4t
AVWL
QVWH
QVWX
WHQX
RLAZ
WHLH
CLCL
162
12
7t
t
–130
–30
CLCL
CLCL
CLCL
6
6
17
t
–25
5
RD low to address float
RD or WR high to ALE high
0
0
5, 6
17
67
t
–25
t
+25
CLCL
CLCL
External Clock
t
t
t
t
8
8
8
8
High time
Low time
Rise time
17
17
17
17
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
5
5
20
20
Fall time
3
Erase/write timer constant
t
t
t
t
Erase/write cycle time
Erase time
4
20
10
10
4
20
10
10
ms
ms
E/W
E
2
2
2
2
Write time
ms
W
4
Data retention time
10
10
years
cycles
S
5
NE/W
Erase/write cycles
10,000
10,000
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. The power-off fall-time of V must be less than 1ms to prevent an overwrite pulse from being generated in the EEPROM which can cause
DD
spurious parasitic writing to EEPROM cells. If the V power-off full-time is greater than 1ms, a power-off reset signal should be generated
DD
to prevent this condition from occurring.
4. Test condition: T
= +55°C.
amb
5. Number of erase/write cycles for each EEPROM byte.
13
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
L – Logic level low, or ALE
P – PSEN
Q – Output data
R – RD signal
t – Time
V – Valid
W– WR signal
EXPLANATION OF THE
AC SYMBOLS
Each timing symbol has five characters. The
first character is always ‘t’ (= time). The other
characters, depending on their positions,
indicate the name of a signal or the logical
status of that signal. The designations are:
X – No longer a valid logic level
A – Address
Z – Float
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
Examples: t
= Time for address valid to
ALE low.
AVLL
t
= Time for ALE low to
PSEN low.
LLPL
t
LHLL
ALE
t
PLPH
t
t
LLPL
AVLL
t
LLIV
t
PLIV
PSEN
t
LLAX
t
PXIZ
t
PLAZ
t
PXIX
A0–A7
INSTR IN
A0–A7
PORT 0
PORT 2
t
AVIV
A8–A15
A8–A15
Figure 4. External Program Memory Read Cycle
ALE
PSEN
RD
t
WHLH
t
LLDV
t
t
LLWL
RLRH
t
RHDZ
t
t
t
RLDV
AVLL
LLAX
t
t
RLAZ
RHDX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA IN
A0–A7 FROM PCL
INSTR IN
t
AVWL
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPH
A8–A15 FROM PCH
Figure 5. External Data Memory Read Cycle
14
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
ALE
t
WHLH
PSEN
t
t
WLWH
LLWL
WR
t
AW
t
t
t
WHQX
t
LLAX
AVLL
QVWX
t
QVWH
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA OUT
A0–A7 FROM PCL
INSTR IN
t
AVWL
P2.0–P2.7 OR A8–A15 FROM DPH
A8–A15 FROM PCH
Figure 6. External Data Memory Write Cycle
ONE MACHINE CYCLE
S3 S4
P2
ONE MACHINE CYCLE
S1
P2
S2
P2
S5
P2
S6
P2
S1
P2
S2
P2
S3
P2
S4
S5
P2
S6
P1
P1
P1
P1
P2
P1
P1
P1
P1
P1
P1
P2
P1
P1
P2
XTAL1
INPUT
ALE
PSEN
RD
WR
BUS
PORT 0
FLOAT
FLOAT
FLOAT
FLOAT
DATA
DATA
DATA
DATA
ADDRESS
ADDRESS
ADDRESS
ADDRESS
EXTERNAL
PROGRAM
MEMORY
FETCH
FLOAT
FLOAT
FLOAT
FLOAT
PORT 2
(EXTERNAL)
ADDRESS TRANSITIONS
PORT
OUTPUT
OLD DATA
NEW DATA
PORT
INPUT
SAMPLING TIME OF I/O PORT PINS DURING INPUT (INCLUDING INT0 AND INT1)
SERIAL
PORT
(SHIFT CLOCK)
Figure 7. Instruction Timing
15
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
Table 4.
External Clock Drive XTAL1
VARIABLE CLOCK
f = 1.2 – 16MHz
VARIABLE CLOCK
f = 3.5 – 24MHz
SYMBOL
PARAMETER
Oscillator clock period
HIGH time
MIN
MAX
MIN
MAX
UNIT
ns
t
t
t
t
t
t
63
20
20
–
833
42
17
17
–
286
CLCL
HIGH
LOW
r
t
– t
t
– t
ns
CLCL
LOW
CLCL
LOW
LOW time
t
– t
t
– t
5
ns
CLCL
HIGH
CLCL
HIGH
Rise time
20
ns
Fall time
–
20
10
–
5
ns
f
1
Cycle time
0.75
0.5
3.43
ms
CY
NOTE:
1. t = 12 t
.
CLCL
CY
2.4V
V
–0.5
DD
2.0V
0.8V
0.7V
DD
–0.1
0.45V
0.2V
DD
t
CHCX
0.45V
NOTE:
t
t
t
CHCL
CLCX
CLCH
t
CLCL
AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at 2.0V min for a logic ‘1’ and 0.8V for a logic ‘0’.
Figure 8. External Clock Drive
Figure 9. AC Testing Input/Output
V
V
+0.1V
LOAD
V
V
–0.1V
TIMING
REFERENCE
POINTS
OH
V
LOAD
–0.1V
LOAD
+0.1V
OL
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change
from the loaded V /V
level occurs. IOH/IOL ≥ ± 20mA.
OH OL
Figure 10. Float Waveform
16
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
V
V
DD
DD
I
I
DD
DD
V
V
DD
DD
V
V
V
RST
DD
DD
DD
P0
P0
RST
EA
EA
(NC)
XTAL2
XTAL1
(NC)
XTAL2
XTAL1
CLOCK SIGNAL
CLOCK SIGNAL
V
V
SS
SS
Figure 11.
I
Test Condition, Active Mode
Figure 12.
I
Test Condition, Idle Mode
DD
DD
All other pins are disconnected
All other pins are disconnected
V
DD
DD
I
DD
V
DD
RST
V
V
–0.5
DD
0.5V
P0
t
CHCX
t
EA
t
CHCL
t
CLCX
CLCH
(NC)
XTAL2
XTAL1
t
CLCL
V
SS
Figure 13. Clock Signal Waveform for I Tests
Figure 14.
All other pins are disconnected.
= 2V to 5.5V
I
Test Condition, Power Down Mode
DD
DD
in Active and Idle Modes
t
= t
= 5ns
V
DD
CLCH
CHCL
17
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller with on-chip
EEPROM
80C851/83C851
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
18
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller with on-chip
EEPROM
80C851/83C851
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
19
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller with on-chip
EEPROM
80C851/83C851
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
20
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller with on-chip
EEPROM
80C851/83C851
NOTES
21
1998 Jul 03
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller with on-chip
EEPROM
80C851/83C851
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 09-98
Document order number:
9397 750 04368
Philips
Semiconductors
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