P80CL410HFPN [NXP]
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| 型号： | P80CL410HFPN |
| 厂家： | 
NXP |
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INTEGRATED CIRCUITS
DATA SHEET
P80CL410; P83CL410
Low voltage 8-bit microcontrollers
with I2C-bus
1997 Apr 10
Product specification
Supersedes data of 1995 Jan 20
File under Integrated circuits, IC20
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
CONTENTS
14.3.2
Interrupt Enable Register (IEN1)
14.3.3
14.3.4
14.3.5
14.3.6
Interrupt Priority Register (IP0)
Interrupt Priority Register (IP1)
Interrupt Polarity Register (IX1)
Interrupt Request Flag Register (IRQ1)
1
FEATURES
2
GENERAL DESCRIPTION
ROMless version: P80CL410
APPLICATIONS
2.1
3
15
16
OSCILLATOR CIRCUITRY
RESET
4
ORDERING INFORMATION
BLOCK DIAGRAM
16.1
16.2
External reset using the RST pin
Power-on-reset
5
6
FUNCTIONAL DIAGRAM
PINNING INFORMATION
17
SPECIAL FUNCTION REGISTERS
OVERVIEW
7
7.1
7.2
Pinning
Pin description
18
19
20
21
22
INSTRUCTION SET
LIMITING VALUES
8
FUNCTIONAL DESCRIPTION OVERVIEW
DC CHARACTERISTICS
AC CHARACTERISTICS
8.1
8.2
General
CPU timing
P85CL000HFZ ‘PIGGY-BACK’
SPECIFICATION
9
MEMORY ORGANIZATION
9.1
9.2
9.3
9.4
Program Memory
Data Memory
Special Function Registers (SFRs)
Addressing
22.1
22.2
General description
Feature differences/additional features of
P85CL000HFZ with respect to P83CL410
Common specification/feature differences
between P85CL000HFZ and
22.3
10
I/O FACILITIES
10.1
Ports
P83CL410/P80CL51
10.2
10.3
10.3.1
10.3.2
10.4
Port options
Port 0 options
External memory accesses
I/O Accesses
SET/RESET options
23
24
PACKAGE OUTLINES
SOLDERING
24.1
24.2
Introduction
DIP
24.2.1
24.2.2
24.3
Soldering by dipping or by wave
Repairing soldered joints
QFP
11
12
TIMERS/EVENT COUNTERS
REDUCED POWER MODES
12.1
12.2
12.3
12.3.1
12.3.2
12.4
Idle mode
Power-down mode
24.3.1
24.3.2
24.3.3
24.4
24.5
24.6
Reflow soldering
Wave soldering
Repairing soldered joints
Reflow soldering
Wave soldering
Wake-up from Power-down mode
Wake-up using INT2 to INT9
Wake-up using RST
Power Control Register (PCON)
Status of external pins
Repairing soldered joints
12.5
25
26
27
DEFINITIONS
13
I2C-BUS SERIAL I/O
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
13.1
13.2
13.3
13.4
Serial Control Register (S1CON)
Serial Status Register (S1STA)
Data Shift Register (S1DAT)
Address Register (S1ADR)
14
INTERRUPT SYSTEM
14.1
14.2
External interrupts INT2 to INT9
Interrupt priority
14.3
Interrupt registers
14.3.1
Interrupt Enable Register (IEN0)
1997 Apr 10
2
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
The 8xCL410 has two reduced power modes that are the
same as those on the standard 80C51.
1
FEATURES
• Full static 80C51 Central Processing Unit
The special reduced power feature of this device is that it
can be stopped and then restarted. Running from an
external clock source, the clock can be stopped and after
a period of time restarted. The 8xCL410 will resume
operation from where it was when the code stopped with
no loss of internal state, RAM contents, or Special
Function Register contents.
• 8-bit CPU, ROM, RAM, I/O in a 40-lead DIP,
40-lead VSO or 44-lead QFP package
• 128 bytes on-chip RAM Data Memory
• 4 kbytes on-chip ROM Program Memory for P83CL410
• External memory expandable up to 128 kbytes: RAM up
to 64 kbytes and ROM up to 64 kbytes
If the internal oscillator is used the device cannot be
stopped and started, but the Power-down mode can be
used to achieve similar power savings, without loss of
on-chip RAM and Special Function Register values.
The Power-down mode can be terminated via an interrupt.
• Four 8-bit ports; 32 I/O lines
• Two 16-bit Timer/Event counters
• On-chip oscillator suitable for RC, LC, quartz crystal or
ceramic resonator
• Thirteen source, thirteen vector, nested interrupt
structure with two priority levels
• I2C-bus interface for serial transfer on two lines
This data sheet details the specific properties of the
P80CL410; P83CL410. For details of the 80C51 core see
“Data Handbook IC20”.
For emulation purposes, the P85CL000 (piggy-back
version) with 256 bytes of RAM is recommended. Details
are given in Chapter 22.
• Enhanced architecture with:
– non-page oriented instructions
– direct addressing
– four 8-byte RAM register banks
2.1
ROMless version: P80CL410
– stack depth limited only by available internal RAM
(maximum 128 bytes)
The P80CL410 is the ROMless version of the P83CL410.
The mask options on the P80CL410 are fixed as follows:
– multiply, divide, subtract and compare instructions
• All ports have option ‘1S’ (standard port, HIGH after
reset), except ports P1.6 and P1.7 which have option
‘2S’ (open-drain, HIGH after reset)
• Reduced power consumption through Power-down and
Idle modes
• Wake-up via external interrupts at Port 1
• Frequency range: DC to 12 MHz
• Oscillator option: Oscillator 3
• Power-on-reset option: OFF.
• Supply voltage: 1.8 to 6.0 V
3
APPLICATIONS
• Very low current consumption
• Operating ambient temperature range: −40 to +85 °C.
The P8xCL410 is an 8-bit general purpose microcontroller
especially suited for battery-powered applications.
The P8xCL410 also functions as an arithmetic processor
having facilities for both binary and BCD arithmetic plus
bit-handling capabilities.
2
GENERAL DESCRIPTION
The P80CL410; P83CL410 (hereafter generally referred to
as the P8xCL410) is manufactured in an advanced CMOS
technology that allows the device to operate at voltages
down to 1.8 V and at frequencies down to DC.
The P8xCL410 has the same instruction set as the 80C51.
The P8xCL410 features 4 kbyte ROM (83CL410),
128 bytes RAM (both ROM and RAM are externally
expandable to 64 kbytes), four 8-bit ports, two 16-bit
timer/counter, an I2C serial interface, a thirteen source two
priority level nested interrupt structure, and on-chip
oscillator circuitry suitable for quartz crystal, ceramic
resonator, RC, or LC. The device operates over a wide
range of supply voltages and has low power consumption.
1997 Apr 10
3
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
4
ORDERING INFORMATION
TYPE NUMBER(1)
PACKAGE
DESCRIPTION
ROMless
ROM
NAME
VERSION
P80CL410HFP P83CL410HFP DIP40 plastic dual in-line package; 40 leads (600 mil)
P80CL410HFT P83CL410HFT VSO40 plastic very small outline package; 40 leads
SOT129-1
SOT158-1
SOT307-2
−
P83CL410HFH QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 × 10 × 1.75 mm
Note
1. Refer to the Order Entry Form (OEF) for this device for the full type number, including options/program.
5
BLOCK DIAGRAM
frequency
reference
counter (1)
XTAL2
XTAL1
T0
T1
PROGRAM
MEMORY
(4K x 8 ROM)
OSCILLATOR
DATA
MEMORY
(128 x 8 RAM)
TWO 16-BIT
TIMER/EVENT
COUNTERS
AND
TIMING
P80CL410
P83CL410
CPU
10
3
64 kbyte BUS
EXPANSION
CONTROL
2
I C-BUS
PROGRAMMABLE I/O
SERIAL I/O
internal
interrupts
external interrupts (1)
SDA
SCL
control
parallel ports,
address/data bus
and I/O pins
(1)
MBK018
(1) Pins shared with parallel port pins.
Fig.1 Block diagram.
1997 Apr 10
4
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
6
FUNCTIONAL DIAGRAM
V
V
DD
RST
SS
XTAL1
XTAL2
address and
data bus
port 0
EA
INT2
INT3
PSEN
ALE
INT4
INT5
P80CL410
P83CL410
port 1
INT6
INT7
INT8/SCL
INT9/SDA
INT0
INT1
T0
alternative
functions
port 3
port 2
address bus
T1
WR
RD
MBK019
Fig.2 Functional diagram.
5
1997 Apr 10
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
7
PINNING INFORMATION
Pinning
7.1
handbook, halfpage
V
P1.0/INT2
1
2
3
4
5
6
7
8
9
40
DD
P1.1/INT3
P1.2/INT4
39 P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
P1.3/INT5
P1.4/INT6
36
P0.3/AD3
P1.5/INT7
35 P0.4/AD4
34 P0.5/AD5
P1.6/INT8/SCL
P1.7/INT9/SDA
RST
33
32 P0.7/AD7
P0.6/AD6
P3.0 10
P3.1 11
31
30
EA
P80CL410
P83CL410
ALE
12
P3.2/INT0
29 PSEN
P3.3/INT1 13
P3.4/T0 14
28 P2.7/A15
27
26
25
24
23
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
15
16
17
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2 18
XTAL1 19
22 P2.1/A9
21 P2.0/A8
V
20
SS
MBK017
Fig.3 Pin configuration for DIP40 and VSO40 packages.
6
1997 Apr 10
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
P1.5/INT7
P1.6/INT8/SCL
P1.7/INT9/SDA
RST
1
2
33 P0.4/AD4
32
P0.5/AD5
3
31 P0.6/AD6
30 P0.7/AD7
4
P3.0
5
29
28
27
EA
P83CL410HFH
n.c.
n.c.
6
P3.1
7
ALE
P3.2/INT0
8
26 PSEN
9
25
24
P2.7/A15
P2.6/A14
P3.3/INT1
P3.4/T0
P3.5/T1
10
11
23 P2.5/A13
MBK016
Fig.4 Pin configuration for QFP44 package.
7
1997 Apr 10
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
7.2
Pin description
Table 1 Pin description for DIP40 (SOT190-1), VSO40 (SOT319-2) and QFP44 (SOT307-2) packages
For more extensive description of the port pins see Chapter 10 “I/O facilities”.
PIN
SYMBOL
DESCRIPTION
DIP40
VSO40
QFP44
P1.0/INT2
1
2
3
4
5
6
7
8
9
40
41
42
43
44
1
• Port 1: 8-bit bidirectional I/O port (P1.0 to P1.7). Port pins that have
logic 1s written to them are pulled HIGH by internal pull-ups, and in this
state can be used as inputs. As inputs, Port 1 pins that are externally
pulled LOW will source current (IIL, see Chapter 20) due to the internal
pull-ups. Port 1 output buffers can sink/source 4 LS TTL loads.
P1.1/INT3
P1.2/INT4
P1.3/INT5
P1.4/INT6
P1.5/INT7
P1.6/INT8/SCL
P1.7/INT9/SDA
RST
• Alternative functions:
– INT2 to INT9 are external interrupt inputs
– SCL and SDA are the I2C-bus clock and data lines.
2
3
4
Reset: a HIGH level on this pin for two machine cycles while the oscillator
is running resets the device.
P3.0
10
11
12
13
14
15
16
17
18
5
7
• Port 3: 8-bit bidirectional I/O port (P3.0 to P3.7).
Same characteristics as Port 1.
P3.1
• Alternative functions:
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
8
– INT0 and INT1 are external interrupts 0 and 1
– T0 and T1 are external inputs for timers 0 and 1
– WR is the external Data Memory write strobe
– RD is the external Data Memory read strobe.
9
10
11
12
13
14
Crystal oscillator output: output of the inverting amplifier of the oscillator.
Left open when external clock is used.
XTAL1
VSS
19
15
16
Crystal oscillator input: input to the inverting amplifier of the oscillator,
also the input for an externally generated clock source.
20
Ground: circuit ground potential.
P2.0 to P2.7
A8 to A15
21 to 28
18 to 25 • Port 2: 8-bit bidirectional I/O port (P2.0 to P2.7) with internal pull-ups.
Same characteristics as Port 1.
• High-order addressing: Port 2 emits the high-order address byte
(A8 to A15) during accesses to external memory that use 16-bit
addresses (MOVX @DPTR). In this application it uses the strong internal
pull-ups when emitting logic 1s. During accesses to external memory that
use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2
Special Function Register.
PSEN
29
26
Program Store Enable. Output read strobe to external Program Memory.
When executing code out of external Program Memory, PSEN is activated
twice each machine cycle. However, during each access to external Data
Memory two PSEN activations are skipped.
1997 Apr 10
8
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
PIN
SYMBOL
DIP40
DESCRIPTION
QFP44
VSO40
ALE
30
27
Address Latch Enable. Output pulse for latching the low byte of the
address during access to external memory. ALE is emitted at a constant
rate of 1⁄6 × fosc, and may be used for external timing or clocking purposes
(assuming MOVX instructions are not used).
EA
31
29
External Access. When EA is held HIGH the CPU executes out of internal
program memory (unless the program counter exceeds 0FFFH). Holding
EA LOW forces the CPU to execute out of external memory regardless of
the value of the program counter.
P0.0 to P0.7
AD0 to AD7
39 to 32
30 to 37 • Port 0: 8-bit open-drain bidirectional I/O port. As an open-drain output
port it can sink 8 LS TTL loads. Port 0 pins that have logic 1s written to
them float, and in that state will function as high impedance inputs.
• Low-order addressing: Port 0 is also the multiplexed low-order address
and data bus during access to external memory. The strong internal
pull-ups are used while emitting logic 1s within the low order address.
VDD
n.c.
40
38
Power supply.
−
6, 17, 28 Not connected.
and 39
1997 Apr 10
9
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
8
FUNCTIONAL DESCRIPTION OVERVIEW
9
MEMORY ORGANIZATION
This chapter gives a brief overview of the device.
The detailed functional description is in the following
chapters:
The P8xCL410 has 4 kbytes of Program Memory (ROM;
P83CL410 only) plus 128 bytes of Data Memory (RAM) on
board. The device has separate address spaces for
Program and Data Memory (see Fig.5). Using Port latches
P0 and P2, the P8xCL410 can address a maximum of
64 kbytes of program memory and a maximum of
64 kbytes of data memory. The CPU generates. The CPU
generates both read (RD) and write (WR) signals for
external Data Memory accesses, and the read strobe
(PSEN) for external Program Memory.
Chapter 9 “Memory organization”
Chapter 10 “I/O facilities”
Chapter 11 “Timers/event counters”
Chapter 12 “Reduced power modes”
Chapter 13 “I2C-bus serial I/O”
Chapter 14 “Interrupt system”
Chapter 15 “Oscillator circuitry”
Chapter 16 “Reset”.
9.1
Program Memory
After reset the CPU begins program execution at location
0000H. The lower 4 kbytes of Program Memory can be
implemented in the on-chip ROM (P83CL410 only) or in
external Program Memory.
8.1
General
The P8xCL410 is a stand-alone high-performance CMOS
microcontroller designed for use in real-time applications
such as instrumentation, industrial control, intelligent
computer peripherals and consumer products.
If the EA pin is tied to VDD, then Program Memory fetches
from addresses 0000H to 0FFFH are directed to the
internal ROM. Fetches from addresses 1000H to FFFFH
are directed to external ROM. Program Counter values
greater than 0FFFH are automatically addressed to
external memory regardless of the state of the EA pin.
The device provides hardware features, architectural
enhancements and new instructions to function as a
controller for applications requiring up to 64 kbytes of
Program Memory and/or up to 64 kbytes of Data Memory.
9.2
Data Memory
The P8xCL410 contains a 4 kbytes Program Memory
(ROM; P83CL410); a static 128 bytes Data Memory
(RAM); 32 I/O lines; two16-bit timer/event counters;
a thirteen-source, two priority-level, nested interrupt
structure and on-chip oscillator and timing circuit.
An I2C-bus serial interface is also provided.
The P8xCL410 contains128 bytes of internal RAM and 27
Special Function Registers (SFR). The memory map
(Fig.5) shows the internal Data Memory space divided into
the lower 128, the upper 128, and the SFR space.
The lower 128 bytes of the internal RAM are organized as
mapped in Fig.6. The lowest 32 bytes are grouped into 4
banks of 8 registers. Program instructions refer to these
registers within a register bank as R0 through R7. Two bits
in the Program Status Word select which register bank is
in use. The next 16 bytes above the register banks form a
block of bit-addressable memory space. The 128 bits in
this area can be directly addressed by the single-bit
manipulation instructions. The remaining registers
The device has two software-selectable modes of reduced
activity for power reduction:
• Idle mode; freezes the CPU while allowing the timers,
serial I/O and interrupt system to continue functioning.
• Power-down mode; saves the RAM contents but
freezes the oscillator causing all other chip functions to
be inoperative.
(30H to 7FH) are directly and indirectly byte addressable.
8.2
CPU timing
A machine cycle consists of a sequence of 6 states. Each
state lasts for two oscillator periods, thus a machine cycle
takes 12 oscillator periods or 1 µs if the oscillator
frequency (fosc) is 12 MHz.
1997 Apr 10
10
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
64K
EXTERNAL
64K
4096
4095
4095
OVERLAPPED SPACE
255
127
0
INTERNAL
(EA = 1)
SPECIAL
FUNCTION
REGISTERS
EXTERNAL
(EA = 0)
INTERNAL
DATA RAM
0
EXTERNAL
DATA MEMORY
INTERNAL DATA MEMORY
PROGRAM MEMORY
MLA559
Fig.5 Memory map.
1997 Apr 10
11
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
handbook, halfpage
7FH
30H
2FH
bit-addressable space
(bit addresses 0 to 7F)
20H
1FH
R7
R0
R7
18H
17H
R0
R7
10H
0FH
4 banks of 8 registers
(R0 to R7)
R0
R7
08H
07H
R0
0
MLA560 - 1
Fig.6 The lower 128 bytes of internal RAM.
The first three methods can be used for addressing
9.3
Special Function Registers (SFRs)
destination operands. Most instructions have a
‘destination/source’ field that specifies the data type,
addressing methods and operands involved.
For operations other than MOVs, the destination operand
is also a source operand.
The upper 128 bytes are the address locations of the
SFRs. Figure 7 shows the SFR space. The SFRs include
the port latches, timers, peripheral control, serial I/O
registers, etc. These registers can only be accessed by
direct addressing. There are 128 directly addressable
locations in the SFR address space (SFRs with addresses
divisible by eight).
Access to memory addressing is as follows:
• Registers in one of the four register banks through
register, direct or register-indirect
9.4
Addressing
• Internal RAM (128 bytes) through direct or
The P8xCL410 has five methods for addressing source
operands:
register-indirect
• Special Function Registers through direct
• Register
• External data memory through register-indirect
• Direct
• Program Memory look-up tables through base-register
• Register-indirect
plus index-register-indirect.
• Immediate
• Base-register plus index-register-indirect.
1997 Apr 10
12
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
DIRECT
BYTE
ADDRESS (HEX)
REGISTER
MNEMONIC
BIT ADDRESS
FFH
IP1
B
FF FE FD FC FB FA F9 F8
F7 F6 F5 F4 F3 F2 F1 F0
F8H
F0H
E9H
IX1
IEN1
EF EE ED EC EB EA E9 E8 E8H
ACC
E7 E6 E5 E4 E3 E2 E1 E0 E0H
S1ADR
S1DAT
S1STA
S1CON
DBH
DAH
D9H
DF DE DD DC DB DA D9 D8
D8H
PSW
IRQ1
IP0
D7 D6 D5 D4 D3 D2 D1 D0 D0H
C7 C6 C5 C4 C3 C2 C1 C0
C0H
BE BD BC BB BA B9 B8 B8H
B7 B6 B5 B4 B3 B2 B1 B0 B0H
AF AE AD AC AB AA A9 A8 A8H
A7 A6 A5 A4 A3 A2 A1 A0 A0H
97 96 95 94 93 92 91 90 90H
SFRs containing
directly addressable
bits
P3
IEN0
P2
P1
TH1
TH0
8DH
8CH
TL1
8BH
8AH
89H
TL0
TMOD
TCON
PCON
8F 8E 8D 8C 8B 8A 89 88
88H
87H
DPH
DPL
SP
83H
82H
81H
80H
P0
87 86 85 84 83 82 81 80
MBK020
Fig.7 Special Function Register memory map.
1997 Apr 10
13
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
Option 3 Push-pull; output with drive capability in both
polarities. Under this option, pins can only be
used as outputs; see Fig.8(c).
10 I/O FACILITIES
10.1 Ports
The P8xCL410 has 32 I/O lines treated as 32 individually
addressable bits or as four parallel 8-bit addressable ports.
Ports 0, 1, 2 and 3 perform the alternative functions
detailed below. To enable a port pin alternate function, the
port bit latch in its SFR must contain a logic 1.
10.3 Port 0 options
The definition of port options for Port 0 is slightly different.
Two cases are considered. First, access to external
memory (EA = 0 or access above the built-in memory
boundary) and second, I/O accesses.
Port 0 Provides the multiplexed low-order address and
data bus for expanding the device with standard
memories and peripherals.
10.3.1 EXTERNAL MEMORY ACCESSES
Port 1 Used for the external interrupts INT2 to INT9, and
the I2C-bus interface lines SCL and SDA.
Option 1 True logic 0 and logic 1 are written as address to
the external memory (strong pull-up to be used).
Port 2 Provides the high-order address when expanding
the device with external Program or Data Memory.
Option 2 An external pull-up resistor is required for
external accesses.
Port 3 Pins can be configured individually to provide:
Option 3 Not allowed for external memory accesses as
the port can only be used as output.
• External interrupt request inputs: INT1 and INT0
• Timer/counter inputs: T1 and T0
10.3.2 I/O ACCESSES
• Control signals to read and write to external
memories: RD and WR.
Option 1 When writing a logic 1 to the port latch, the
strong pull-up ‘p1’ will be on for 2 oscillator
periods. No weak pull-up exists. Without an
external pull-up, this option can be used as a
high-impedance input.
Each port consists of a latch (SFRs P0 to P3), an output
driver and input buffer. Ports 1, 2, and 3 have internal
pull-ups Figure 8(a) shows that the strong transistor ‘p1’ is
turned on for only 2 oscillator periods after a LOW-to-HIGH
transition in the port latch. When on, it turns on ‘p3’ (a weak
pull-up) through the inverter. This inverter and ‘p3’ form a
latch which holds the logic 1. In Port 0 the pull-up ‘p1’ is
only on when emitting logic 1s for external memory
access. Writing a logic 1 to a Port 0 bit latch leaves both
output transistors switched off so that the pin can be used
as a high-impedance input.
Option 2 Open-drain; quasi-directional I/O with n-channel
open-drain output. Use as an output requires the
connection of an external pull-up resistor.
See Fig.8(b).
Option 3 Push-Pull; output with drive capability in both
polarities. Under this option pins can only be
used as outputs. See Fig.8(c).
10.4 SET/RESET options
10.2 Port options
Individual mask selection of the post-reset state is
available with any of the above pins. The required
selection is made by appending ‘S’ or ‘R’ to Options 1, 2,
or 3 above.
The pins of port 1 (except P1.6 and P1.7; with option 2S
only), port 2 and port 3 may be individually configured with
one of the following options. These options are also shown
in Fig.8.
Option R RESET, at reset this pin will be initialized LOW.
Option S SET, at reset this pin will be initialized HIGH.
Option 1 Standard Port; quasi-bidirectional I/O with
pull-up. The strong booster pull-up ‘p1’ is turned
on for two oscillator periods after a
LOW-to-HIGH transition in the port latch;
Fig.8(a).
Option 2 Open-drain; quasi-bidirectional I/O with
n-channel open-drain output. Use as an output
requires the connection of an external pull-up
resistor; see Fig.8(b).
1997 Apr 10
14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
strong pull-up
+5 V
2 oscillator
periods
p2
p3
p1
n
I/O pin
Q
from port latch
input data
INPUT
BUFFER
read port pin
(a) Standard
+5 V
external
pull-up
I/O pin
Q
from port latch
n
input data
read port pin
INPUT
BUFFER
(b) Open-drain
strong pull-up
+5 V
p1
I/O pin
Q
from port latch
n
MGD677
(c) Push-pull
Fig.8 Port configuration options.
1997 Apr 10
15
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
The following functions remain active during the Idle
mode:
11 TIMERS/EVENT COUNTERS
The P8xCL410 contains two16-bit timer/event counter
registers; Timer 0 and Timer 1, which can perform the
following functions:
• Timer 0 and Timer 1
• I2C-bus
• Measure time intervals and pulse durations
• Count events
• External interrupt.
These functions may generate an interrupt or reset; thus
ending the Idle mode.
• Generate interrupt requests.
There are two ways to terminate the Idle mode:
In the ‘Timer’ operating mode the register is incremented
every machine cycle. Since a machine cycle consists of 12
1. Activation of any enabled interrupt will cause IDL
(PCON.0) to be cleared by hardware thus terminating
the Idle mode. The interrupt is serviced, and following
the RETI instruction, the next instruction to be
executed will be the one following the instruction that
put the device in the Idle mode. The flag bits GF0
(PCON.2) and GF1 (PCON.3) may be used to
determine whether the interrupt was received during
normal execution or during the Idle mode.
oscillator periods, the count rate is 1⁄12 × fosc
.
In the ‘Counter’ operating mode, the register is
incremented in response to a HIGH-to-LOW transition.
Since it takes 2 machine cycles (24 oscillator periods) to
recognize a HIGH-to-LOW transition, the maximum count
rate is 1⁄24 × fosc. To ensure a given level is sampled, it
should be held for at least one complete machine cycle.
Timer 0 and Timer 1 can be programmed independently to
operate in four modes:
For example, the instruction that writes to PCON.0 can
also set or clear one or both flag bits. When the Idle
mode is terminated by an interrupt, the service routine
can examine the status of the flag bits.
Mode 0 8-bit timer or 8-bit counter each with divide-by-32
prescaler.
2. The second way of terminating the Idle mode is with an
external hardware reset. Since the oscillator is still
running, the hardware reset is required to be active for
two machine cycles (24 oscillator periods) to complete
the reset operation. Reset redefines all SFRs but does
not affect the on-chip RAM.
Mode 1 16-bit time-interval or event counter.
Mode 2 8-bit time-interval or event counter with automatic
reload upon overflow.
Mode 3 Timer 0 establishes TL0 and TH0 as two
separate counters.
12.2 Power-down mode
12 REDUCED POWER MODES
Operation in Power-down mode freezes the oscillator.
The internal connections which link both Idle and
Power-down signals to the clock generation circuit are
shown in Fig.9.
There are two software selectable modes of reduced
activity for further power reduction: Idle and Power-down.
12.1 Idle mode
Power-down mode is entered by setting the PD bit in the
Power Control Register (PCON.1, see Table 2).
The instruction that sets PD is the last executed prior to
going into the Power-down mode.
Idle mode operation permits the external interrupts,
I2C-bus, and timer blocks to continue to function while the
clock to the CPU is halted.
Idle mode is entered by setting the IDL bit in the Power
Control Register (PCON.0, see Table 3). The instruction
that sets IDL is the last instruction executed in the normal
operating mode before the Idle mode is activated
Once in the Power-down mode, the oscillator is stopped.
The contents of the on-chip RAM and the SFRs are
preserved. The port pins output the value held by their
respective SFRs. ALE and PSEN are held LOW.
Once in Idle mode, the CPU status is preserved along with
the Stack Pointer, Program Counter, Program Status
Word and Accumulator. The RAM and all other registers
maintain their data during Idle mode. The status of the
external pins during Idle mode is shown in Table 4.
In the Power-down mode, VDD may be reduced to
minimize circuit power consumption. The supply voltage
must not be reduced until the Power-down mode is
entered, and must be restored before the hardware reset
is applied which will free the oscillator. Reset should not be
released until the oscillator has restarted and stabilized.
1997 Apr 10
16
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
12.3 Wake-up from Power-down mode
12.4 Power Control Register (PCON)
When in Power-down mode the controller can be
woken-up with either the external interrupts INT2 to INT9,
or a reset operation. The wake-up operation has two basic
approaches as explained in Section 12.3.1; 12.3.2 and
illustrated in Fig.10.
See Tables 2 and 3. Idle and Power-down modes are
activated by software using this SFR. PCON is not
bit-addressable.
12.5 Status of external pins
The status of the external pins during Idle and Power-down
mode is shown in Table 3. If the Power-down mode is
activated whilst accessing external Program Memory, the
port data that is held in the Special Function Register P2 is
restored to Port 2.
12.3.1 WAKE-UP USING INT2 TO INT9
If any of the interrupts INT2 to INT9 are enabled, the
device can be woken-up from the Power-down mode with
the external interrupts. To ensure that the oscillator is
stable before the controller restarts, the internal clock will
remain inactive for 1536 oscillator periods. This is
controlled by an on-chip delay counter.
If the data is a logic 1, the port pin is held HIGH during the
Power-down mode by the strong pull-up transistor ‘p1’;
see Fig.8(a).
12.3.2 WAKE-UP USING RST
To wake-up the P8xCL410, the RST pin must be kept
HIGH for a minimum of 24 periods. The on-chip delay
counter is inactive. The user must ensure that the oscillator
is stable before any operation is attempted.
Table 2 Power Control Register (address 87H)
7
6
5
4
3
2
1
0
−
−
−
−
GF1
GF0
PD
IDL
Table 3 Description of PCON bits
BIT
7, 6, 5, 4
3 and 2
1
SYMBOL
DESCRIPTION
−
reserved
GF1 and GF0 General purpose flag bits
PD
Power-down bit; setting this bit activates the Power-down mode
Idle mode bit; setting this bit activates the Idle mode
0
IDL
Table 4 Status of external pins during Idle and Power-down modes
MODE
MEMORY
internal
ALE
PSEN
PORT 0
port data
floating
PORT 1
port data
port data
port data
port data
PORT 2
port data
address
port data
port data
PORT 3
port data
port data
port data
port data
PORT 4
port data
port data
port data
port data
Idle
1
1
0
0
1
1
0
0
external
internal
Power-down
port data
floating
external
1997 Apr 10
17
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
d
XTAL2
XTAL1
OSCILLATOR
interrupts
serial ports
timer blocks
CLOCK
GENERATOR
CPU
PD
IDL
MLA563
Fig.9 Internal clock control in Idle and Power-down mode.
power-down
RST pin
external
interrupt
oscillator
MGD679
24 periods
delay counter
1536 periods
Fig.10 Wake-up operation.
1997 Apr 10
18
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
13 I2C-BUS SERIAL I/O
These functions are controlled by the Serial Control
Register S1CON. S1STA is the Status Register whose
contents may also be used as a vector to various service
routines. S1DAT is the Data Shift Register and S1ADR is
the Slave Address Register. Slave address recognition is
performed by on-chip hardware.
The serial port supports the twin line I2C-bus, which
consists of a serial data line (SDA) and a serial clock line
(SCL). These lines also function as the I/O port lines P1.7
and P1.6 respectively.
The system is unique because data transport, clock
generation, address recognition and bus control arbitration
are all controlled by hardware.
Figure 11 is the block diagram of the I2C-bus serial I/O.
The I2C-bus serial I/O has complete autonomy in byte
handling and operates in 4 modes:
• Master transmitter
• Master receiver
• Slave transmitter
• Slave receiver.
7
0
GC
SLAVE ADDRESS
S1ADR
7
0
SHIFT REGISTER
S1DAT
SDA
ARBITRATION SYNC LOGIC
SCL
BUS CLOCK GENERATOR
7
0
CONTROL REGISTER
STATUS REGISTER
S1CON
7
0
MLB199
S1STA
Fig.11 Block diagram of I2C-bus serial I/O.
1997 Apr 10
19
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
13.1 Serial Control Register (S1CON)
Table 5 Serial Control Register (SFR address D8H)
7
6
5
4
3
2
1
0
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
Table 6 Description of S1CON bits
BIT
SYMBOL
DESCRIPTION
7
CR2
This bit along with bits CR1 (S1CON.1) and CR0 (S1CON.0) determines the serial clock
frequency when SIO is in the Master mode. See Table 7.
6
5
4
ENS1
STA
ENABLE serial I/O. When ENS1 = 0, the serial I/O is disabled. SDA and SCL outputs
are in the high impedance state; P1.6 and P1.7 function as open-drain ports. When
ENS1 = 1, the serial I/O is enabled. Output port latches P1.6 and P1.7 must be set to
logic 1.
START flag. When this bit is set in Slave mode, the SIO hardware checks the status of
the I2C-bus and generates a START condition if the bus is free or after the bus becomes
free. If STA is set while the SIO is in Master mode, SIO will generate a repeated START
condition.
STO
STOP flag. With this bit set while in Master mode a STOP condition is generated. When
a STOP condition is detected on the I2C-bus, the SIO hardware clears the STO flag.
STO may also be set in Slave mode in order to recover from an error condition. In this
case no STOP condition is transmitted to the I2C-bus. However, the SIO hardware
behaves as if a STOP condition has been received and releases the SDA and SCL.
The SIO then switches to the not addressed slave receiver mode. The STOP flag is
cleared by the hardware.
3
SI
SIO interrupt flag. This flag is set, and an interrupt is generated, after any of the
following events occur:
• A START condition is generated in Master mode
• Own slave address has been received during AA = 1
• The general call address has been received while GC (S1ADR.0) = 1 and AA = 1
• A data byte has been received or transmitted in Master mode (even if arbitration is lost)
• A data byte has been received or transmitted as selected slave
• A STOP or START condition is received as selected slave receiver or transmitter.
2
AA
Assert Acknowledge. When this bit is set, an acknowledge (low level to SDA) is
returned during the acknowledge clock pulse on the SCL line when:
• Own slave address is received
• General call address is received; GC (S1ADR.0) = 1
• A data byte is received while the device is programmed to be a Master Receiver
• A data byte is received while the device is a selected Slave Receiver.
When this bit is reset, no acknowledge is returned. Consequently, no interrupt is
requested when the own slave address or general call address is received.
1
0
CR1
CR0
These two bits along with the CR2 (S1CON.7) bit determine the serial clock frequency
when SIO is in the Master mode. See Table 7.
1997 Apr 10
20
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
Table 7 Selection of the serial clock frequency SCL in a Master mode of operation
BIT RATE (kHz) at fosc
CR2
CR1
CR0
fosc DIVISOR
3.58 MHz
6 MHz
12 MHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
256
224
14.0
16.0
18.6
22.4
3.73
29.8
59.7
−
23.4
26.8
31.3
37.5
6.25
50.0
100.0
−
46.9
53.6
62.5
75.0
12.5
100.0
−
192
160
960
120
60
not allowed
−
13.2 Serial Status Register (S1STA)
S1STA is a read-only register. The contents of this register may be used as a vector to a service routine. This optimizes
the response time of the software and consequently that of the I2C-bus. The status codes for all possible modes of the
I2C-bus interface are given in Tables 10 to 14.
Table 8 Serial Status Register (address D9H)
7
6
5
4
3
2
1
0
SC4
SC3
SC2
SC1
SC0
0
0
0
Table 9 Description of S1STA bits
BIT
SYMBOL
DESCRIPTION
3 to 7
0 to 2
SC4 to SC0 5-bit status code
−
these three bits are always zero
Table 10 MST/TRX mode
S1STA VALUE
DESCRIPTION
08H
10H
18H
20H
28H
30H
38H
a START condition has been transmitted
a repeated START condition has been transmitted
SLA and W have been transmitted, ACK has been received
SLA and W have been transmitted, ACK received
DATA of S1DAT has been transmitted, ACK received
DATA of S1DAT has been transmitted, ACK received
arbitration lost in SLA, R/W or DATA
1997 Apr 10
21
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
Table 11 MST/REC mode
S1STA VALUE
DESCRIPTION
08H
10H
38H
40H
48H
50H
58H
a START condition has been transmitted
a repeated START condition has been transmitted
arbitration lost while returning ACK
SLA and R have been transmitted, ACK received
SLA and R have been transmitted, ACK received
DATA has been received, ACK returned
DATA has been received, ACK returned
Table 12 SLV/REC mode
S1STA VALUE
DESCRIPTION
own SLA and W have been received, ACK returned
60H
68H
70H
78H
80H
88H
90H
98H
A0H
arbitration lost in SLA, R/W as MST. Own SLA and W have been received, ACK returned
general CALL has been received, ACK returned
arbitration lost in SLA, R/W as MST; general CALL has been received
previously addressed with own SLA; DATA byte received, ACK returned
previously addressed with own SLA; DATA byte received, ACK returned
previously addressed with general CALL; DATA byte has been received, ACK has been returned
previously addressed with general CALL; DATA byte has been received, ACK has been returned
a STOP condition or repeated START condition has been received while still addressed as SLV/REC
or SLV/TRX
Table 13 SLV/TRX mode
S1STA VALUE
DESCRIPTION
A8H
B0H
B8H
C0H
C8H
own SLA and R have been received, ACK returned
arbitration lost in SLA, R/W as MST; own SLA and R have been received, ACK returned
DATA byte has been transmitted, ACK received
DATA byte has been transmitted, ACK received
last DATA byte has been transmitted (AA = 0), ACK received
Table 14 Miscellaneous
S1STA VALUE
DESCRIPTION
00H
F8H
bus error during MST mode or selected SLV mode, due to an erroneous START or STOP condition
no relevant state information available, SI = 0
1997 Apr 10
22
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
Table 15 Symbols used in Tables 10 to 14
SYMBOL
DESCRIPTION
SLA
R
7-bit slave address
read bit
W
write bit
ACK
ACK
DATA
MST
SLV
TRX
REC
acknowledgement (acknowledge bit is logic 0)
no acknowledgement (acknowledge bit is logic 1)
8-bit data byte to or from I2C-bus
master
slave
transmitter
receiver
13.3 Data Shift Register (S1DAT)
S1DAT contains the serial data to be transmitted or data which has just been received. The MSB (bit 7) is transmitted or
received first; i.e. data shifted from right to left.
Table 16 Data Shift Register (SFR address DAH)
7
6
5
4
3
2
1
0
S1DAT.7
S1DAT.6
S1DAT.5
S1DAT.4
S1DAT.3
S1DAT.2
S1DAT.1
S1DAT.0
13.4 Address Register (S1ADR)
This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as
a slave receiver/transmitter.
Table 17 Address Register (SFR address DBH)
7
6
5
4
3
2
1
0
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
GC
Table 18 Description of S1ADR bits
BIT
SYMBOL
SLA6 to SLA0 own slave address
DESCRIPTION
7 to 1
0
GC
this bit is used to determine whether the general call address is recognized; when
GC = 0, the general call address is not recognized; when GC = 1, the general call
address is recognized
1997 Apr 10
23
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
14 INTERRUPT SYSTEM
14.2 Interrupt priority
External events and the real-time-driven on-chip
peripherals require service by the CPU at unpredictable
times. To tie the asynchronous activities of these functions
to normal program execution a multiple-source,
two-priority-level, nested interrupt system is provided.
The system is shown in Fig.12. The P8xCL410
acknowledges interrupt requests from thirteen sources as
follows:
Each interrupt source can be set to either a high priority or
to a low priority. If a low priority interrupt is received
simultaneously with a high priority interrupt, the high
priority interrupt will be dealt with first.
If interrupts of the same priority are requested
simultaneously, the processor will branch to the interrupt
polled first, according to the sequence shown in Table 19
and in Fig.12. The ‘vector address’ is the ROM location
where the appropriate interrupt service routine starts.
• INT0 and INT1
• Timer 0 and Timer 1
• I2C-bus
Table 19 Interrupt vector polling sequence
VECTOR
ADDRESS (HEX)
• INT2 to INT9.
SYMBOL
SOURCE
External 0
I2C port
Each interrupt vectors to a separate location in Program
Memory for its service routine. Each source can be
individually enabled or disabled by corresponding bits in
the Interrupt Enable Registers (IEN0 and IEN1).
The priority level is selected via the Interrupt Priority
Registers (IP0 and IP1). All enabled sources can be
globally disabled or enabled. Figure 12 shows the interrupt
system.
X0 (first)
S1
0003
002B
X5
0053
External 5
Timer 0
T0
000B
X6
005B
External 6
External 1
External 2
External 7
Timer 1
X1
0013
X2
003B
14.1 External interrupts INT2 to INT9
X7
0063
Port 1 lines serve an alternative purpose as eight
additional interrupts INT2 to INT9. When enabled, each of
these lines may wake-up the device from the Power-down
mode. Using the Interrupt Polarity Register (IX1), each pin
may be initialized to be either active HIGH or active LOW.
IRQ1 is the Interrupt Request Flag Register. If the interrupt
is enabled, each flag will be set on an interrupt request but
must be cleared by software, i.e. via the interrupt software
or when the interrupt is disabled.
T1
001B
X3
0043
External 3
External 8
External 4
External 9
X8
006B
X4
004B
X9 (last)
xt0073
A low priority interrupt routine can only be interrupted by a
high priority interrupt. A high priority interrupt routine
cannot be interrupted.
Port 1 interrupts are level sensitive. A Port 1 interrupt will
be recognized when a level (HIGH or LOW depending on
the Interrupt Polarity Register) on P1.n is held active for at
least one machine cycle. The interrupt request is not
serviced until the next machine cycle. Figure 13 shows the
external interrupt configuration.
1997 Apr 10
24
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
INTERRUPT
SOURCES
IEN0/1
IP0/1
PRIORITY
REGISTERS
HIGH
LOW
X0
S1
X5
T0
X6
X1
X2
X7
T1
X3
X8
X4
X9
MBK022
GLOBAL
ENABLE
Fig.12 Interrupt system.
25
1997 Apr 10
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
IX1
IRQ1
IEN1
X9
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
X8
X7
X6
X5
X4
X3
X2
P1.0
MLA575
WAKE-UP
Fig.13 External interrupt configuration.
14.3 Interrupt registers
The registers used in the interrupt system are listed in Table 20. Tables 21 to 32 describe the contents of these registers.
Table 20 Special Function Registers related to the interrupt system
ADDRESS
A8H
REGISTER
IEN0
IEN1
IP0
DESCRIPTION
Interrupt Enable Register
E8H
Interrupt Enable Register (INT2 to INT9)
Interrupt Priority Register
B8H
F8H
IP1
Interrupt Priority Register (INT2 to INT9)
Interrupt Polarity Register
E9H
IX1
C0H
IRQ1
Interrupt Request Flag Register
1997 Apr 10
26
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
14.3.1 INTERRUPT ENABLE REGISTER (IEN0)
Bit values: 0 = interrupt disabled; 1 = interrupt enabled.
Table 21 Interrupt Enable Register (SFR address A8H)
7
6
5
4
3
2
1
0
EA
−
ES1
−
ET1
EX1
ET0
EX0
Table 22 Description of IEN0 bits
BIT
SYMBOL
DESCRIPTION
7
EA
general enable/disable control. If EA = 0, no interrupt is enabled. If EA = 1, any
individually enabled interrupt will be accepted
6
5
4
3
2
1
0
−
reserved
enable I2C-bus SIO interrupt
ES1
−
reserved
ET1
EX1
ET0
EX0
enable Timer 1 interrupt (T1)
enable external interrupt 1
enable Timer 0 interrupt (T0)
enable external interrupt 0
14.3.2 INTERRUPT ENABLE REGISTER (IEN1)
Bit values: 0 = interrupt disabled; 1 = interrupt enabled.
Table 23 Interrupt Enable Register (SFR address E8H)
7
6
5
4
3
2
1
0
EX9
EX8
EX7
EX6
EX5
EX4
EX3
EX2
Table 24 Description of IEN1 bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
EX9
EX8
EX7
EX7
EX5
EX4
EX3
EX2
enable external interrupt 9
enable external interrupt 8
enable external interrupt 7
enable external interrupt 6
enable external interrupt 5
enable external interrupt 4
enable external interrupt 3
enable external interrupt 2
1997 Apr 10
27
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
14.3.3 INTERRUPT PRIORITY REGISTER (IP0)
Bit values: 0 = low priority; 1 = high priority.
Table 25 Interrupt Priority Register (SFR address B8H)
7
6
5
4
3
2
1
0
−
−
PS1
−
PT1
PX1
PT0
PX0
Table 26 Description of IP0 bits
BIT
7
SYMBOL
−
DESCRIPTION
reserved
reserved
6
−
5
PS1
−
I2C-bus SIO interrupt priority level
4
reserved
3
PT1
PX1
PT0
PX0
Timer 1 interrupt priority level
external interrupt 1 priority level
Timer 0 interrupt priority level
external interrupt 0 priority level
2
1
0
14.3.4 INTERRUPT PRIORITY REGISTER (IP1)
Bit values: 0 = low priority; 1 = high priority.
Table 27 Interrupt Priority Register (SFR address F8H)
7
6
5
4
3
2
1
0
PX9
PX8
PX7
PX6
PX5
PX4
PX3
PX2
Table 28 Description of IP1 bits
BIT
7
SYMBOL
PX9
DESCRIPTION
external interrupt 9 priority level
external interrupt 8 priority level
external interrupt 7 priority level
external interrupt 6 priority level
external interrupt 5 priority level
external interrupt 4 priority level
external interrupt 3 priority level
external interrupt 2 priority level
6
PX8
5
PX7
4
PX6
3
PX5
2
PX4
1
PX3
0
PX2
1997 Apr 10
28
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
14.3.5 INTERRUPT POLARITY REGISTER (IX1)
Writing either a logic 1 or logic 0 to any Interrupt Polarity Register bit sets the polarity level of the corresponding external
interrupt to an active HIGH or active LOW respectively.
Table 29 Interrupt Polarity Register (SFR address E9H)
7
6
5
4
3
2
1
0
IL9
IL8
IL7
IL6
IL5
IL4
IL3
IL2
Table 30 Description of IX1 bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
IL9
IL8
IL7
IL6
IL5
IL4
IL3
IL2
external interrupt 9 polarity level
external interrupt 8 polarity level
external interrupt 7 polarity level
external interrupt 6 polarity level
external interrupt 5 polarity level
external interrupt 4 polarity level
external interrupt 3 polarity level
external interrupt 2 polarity level
14.3.6 INTERRUPT REQUEST FLAG REGISTER (IRQ1)
Table 31 Interrupt Request Flag Register (SFR address C0H)
7
6
5
4
3
2
1
0
IQ9
IQ8
IQ7
IQ6
IQ5
IQ4
IQ3
IQ2
Table 32 Description of IRQ1 bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
IQ9
IQ8
IQ7
IQ6
IQ5
IQ4
IQ3
IQ2
external interrupt 9 request flag
external interrupt 8 request flag
external interrupt 7 request flag
external interrupt 6 request flag
external interrupt 5 request flag
external interrupt 4 request flag
external interrupt 3 request flag
external interrupt 2 request flag
1997 Apr 10
29
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
To drive the device with an external clock source, apply the
external clock signal to XTAL1, and leave XTAL2 to float,
as shown in Fig.14(f). There are no requirements on the
duty cycle of the external clock, since the input to the
internal clocking circuitry is buffered by a flip-flop.
15 OSCILLATOR CIRCUITRY
The on-chip oscillator circuitry of the P8xCL410 is a
single-stage inverting amplifier biased by an internal
feedback resistor. The oscillator circuit is shown in Fig.15.
For operation as a standard quartz oscillator, no external
components are needed, except for the 32 kHz option.
When using external capacitors, ceramic resonators, coils
and RC networks to drive the oscillator, five different
configurations are supported (see Table 33 and Fig.14).
Various oscillator options are provided for optimum
on-chip oscillator performance; these are specified in
Table 33 and shown in Fig.14. The required option should
be stated when ordering.
In the Power-down mode the oscillator is stopped and
XTAL1 is pulled HIGH. The oscillator inverter is switched
off to ensure no current will flow regardless of the voltage
at XTAL1, for configurations (a), (b), (c), (d), (e) and (g) of
Fig.14.
Table 33 Oscillator options
OPTION
APPLICATION
Oscillator 1
for 32 kHz clock applications with external trimmer for frequency adjustment; a 4.7 MΩ bias resistor
is needed for use in parallel with the crystal; see Fig.14(c)
Oscillator 2
Oscillator 3
Oscillator 4
RC oscillator
low-power, low-frequency operations using LC components; see Fig.14(e)
medium frequency range applications
high frequency range applications
RC oscillator configuration; see Figs 14(g) and 16
QUARTZ OSCILLATOR
WITH EXTERNAL
CAPACITORS
STANDARD
QUARTZ
OSCILLATOR
32 kHz
OSCILLATOR
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
(a)
(b)
(c)
CERAMIC
RESONATOR
LC - OSCILLATOR
EXTERNAL CLOCK
RC - OSCILLATOR
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
n.c.
XTAL1
n.c.
XTAL2
V
DD
(d)
(e)
(f)
(g)
MLA577
Fig.14 Oscillator configurations.
30
1997 Apr 10
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
V
DD
P80CL410
P83CL410
to internal
timing circuits
PD
V
V
DD
DD
C1
C2
R
i
i
bias
MBK025
XTAL1
XTAL2
Fig.15 Standard oscillator.
MLA579
600
handbook, halfpage
f
osc
(kHz)
400
200
0
0
2
4
6
RC (µs)
RC oscillator frequency is externally adjustable; 100 kHz ≤ fosc ≤ 500 kHz.
Fig.16 RC oscillator frequency as a function of RC.
31
1997 Apr 10
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
Table 34 Oscillator type selection guide
C1 EXT. (pF)
C2 EXT. (pF)
FREQUENCY
(MHz)
OPTION
(see Table 33)
RESONATOR MAX.
SERIES RESISTANCE
RESONATOR
MIN.
MAX.
MIN.
MAX.
Quartz
0.032
1.0
Oscillator 1
Oscillator 2
Oscillator 3
Oscillator 4
0
0
0
5
0
15
30
15
20
10
15
10
15
50
50
40
40
20
15
40
90
15 kΩ(1)
600 Ω
100 Ω
75 Ω
30
15
20
10
15
10
15
50
50
40
40
20
15
40
90
3.58
4.0
0
0
0
0
6.0
0
0
60 Ω
10.0
12.0
16.0
0.455
1.0
0
0
60 Ω
0
0
40Ω
0
0
20 Ω
PXE
40
15
0
40
15
0
10 Ω
100 Ω
10 Ω
3.58
4.0
Oscillator 2
0
0
10 Ω
6.0
0
0
5 Ω
10.0
12.0
−
Oscillator 3
Oscillator 4
Oscillator 2
0
0
6 Ω
10
20
10
20
6 Ω
LC
10 µH = 1 Ω
100 µH = 5 Ω
1 mH = 75 Ω
Note
1. 32 kHz quartz crystals with a series resistance >15 kΩ will reduce the guaranteed supply voltage range to
2.5 to 3.5 V.
1997 Apr 10
32
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
R
f
XTAL1
XTAL2
g
C1
V
C2
i
R
m
1
i
2
MLA578
Fig.17 Oscillator equivalent circuit diagram.
Table 35 Oscillator equivalent circuit parameters
The equivalent circuit data of the internal oscillator compares with that of matched crystals.
SYMBOL
gm
PARAMETER
OPTION
CONDITION
MIN.
TYP.
15
MAX. UNIT
transconductance
Oscillator 1; 32 kHz
Oscillator 2
Tamb = +25 °C;
VDD = 4.5 V
−
−
µS
µS
µS
200
400
1000
−
600
1500
4000
3.0
8.0
8.0
8.0
23
1000
4000
Oscillator 3
Oscillator 4
10000 µS
C1i
C2i
R2
input capacitance
output capacitance
output resistance
Oscillator 1; 32 kHz
Oscillator 2
−
−
−
−
−
−
−
−
−
−
−
−
pF
pF
pF
pF
pF
pF
pF
pF
kΩ
kΩ
kΩ
kΩ
−
Oscillator 3
−
Oscillator 4
−
Oscillator 1; 32 kHz
Oscillator 2
−
−
8.0
8.0
8.0
3800
65
Oscillator 3
−
Oscillator 4
−
Oscillator 1; 32 kHz
Oscillator 2
−
−
Oscillator 3
−
18
Oscillator 4
−
5.0
1997 Apr 10
33
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
16 RESET
16.2 Power-on-reset
To initialize the P8xCL410 a reset is performed by either of
three methods:
The device contains on-chip circuitry which switches the
port pins to the customer defined logic level as soon as
VDD exceeds 1.3 V; if the mask option ‘ON’ has been
chosen. As soon as the minimum supply voltage is
reached, the oscillator will start up. However, to ensure
that the oscillator is stable before the controller starts, the
clock signals are gated away from the CPU for a further
1536 oscillator periods. During that time the CPU is held in
a reset state. A hysteresis of approximately 50 mV at a
typical power-on switching level of 1.3 V will ensure
correct operation (see Fig.20).
• Applying an external signal to the RST pin
• Via Power-on-reset circuitry.
A reset leaves the internal registers as shown in
Chapter 17. The reset state of the port pins is
mask-programmable and can be defined by the user.
16.1 External reset using the RST pin
The reset input for the P8xCL410 is RST. A Schmitt trigger
is used at the input for noise rejection. The output of the
Schmitt trigger is sampled by the reset circuitry every
machine cycle. A reset is accomplished by holding the
RST pin HIGH for at least two machine cycles
(24 oscillator periods) while the oscillator is running.
The CPU responds by executing an internal reset. Port
pins adopt their reset state immediately after the RST goes
HIGH. During reset, ALE and PSEN are held HIGH.
The on-chip Power-on-reset circuitry can also be switched
off via the mask option ‘OFF’. This option reduces the
Power-down current to typically 800 nA and can be
chosen if external reset circuitry is used. For applications
not requiring the internal reset, option ‘OFF’ should be
chosen.
An automatic reset can be obtained by connecting the RST
pin to VDD via a 10 µF capacitor. At power-on, the voltage
on the RST pin is equal to VDD minus the capacitor voltage,
and decreases from VDD as the capacitor charges through
the internal resistor (RRST) to ground. The larger the
capacitor, the more slowly VRST decreases. VRST must
remain above the lower threshold of the Schmitt trigger
long enough to effect a complete reset. The time required
is the oscillator start-up time, plus 2 machine cycles.
The Power-on-reset circuitry is shown in Fig.19.
The external reset is asynchronous to the internal clock.
The RST pin is sampled during state 5, phase 2 of every
machine cycle. After a HIGH is detected at the RST pin, an
internal reset is repeated until RST goes LOW.
The internal RAM is not affected by reset. When VDD is
turned on, the RAM contents are indeterminate.
V
handbook, halfpage
DD
V
DD
SCHMITT
TRIGGER
handbook, halfpage
RST
10 µF
P80CL410
P83CL410
RESET
CIRCUITRY
RST
MLA580
R
RST
MBK024
Fig.18 Reset configuration.
Fig.19 Recommended Power-on-reset circuitry.
1997 Apr 10
34
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
switching level
POR
SUPPLY
hysteresis
VOLTAGE
POWER-ON-RESET
(INTERNAL)
OSCILLATOR
CPU RUNNING
MLA581
Start-up 1536 oscillator
time
periods delay
Fig.20 Power-on-reset switching level.
1997 Apr 10
35
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
17 SPECIAL FUNCTION REGISTERS OVERVIEW
The P8xCL410 has 27 SFRs available to the user.
ADDRESS
(HEX)
RESET VALUE
(B)
NAME
IP1(1)
B(1)
FUNCTION
F8
F0
E9
E8
E0
DB
DA
D9
D8
D0
C0
B8
B0
A8
A0
90
8D
8C
8B
8A
89
88
87
83
82
81
80
00000000
00000000
00000000
00000000
00000000
00000000
00000000
11111000
00000000
00000000
00000000
XX000000
Interrupt Priority Register INT2 to INT9)
B Register
IX1
Interrupt Polarity Register
Interrupt Enable Register 1
Accumulator
IEN1(1)
ACC(1)
S1ADR
S1DAT
S1STA
S1CON(1)
PSW(1)
IRQ1(1)
IP0(1)
P3(1)
I2C-bus Slave Address Register
I2C-bus Data Shift Register
I2C-bus Serial Status Register
I2C-bus Serial Control Register
Program Status Word
Interrupt Request Flag Register
Interrupt Priority Register 0
Digital I/O Port Register 3
Interrupt Enable Register
Digital I/O Port Register 2
Digital I/O Port Register 1
Timer 1 High byte
(2)
XXXXXXXX
IEN0(1)
P2(1)
P1(1)
00000000
(2)
XXXXXXXX
(2)
XXXXXXXX
TH1
00000000
00000000
00000000
00000000
00000000
00000000
0XXX0000
00000000
00000000
00000111
TH0
Timer 0 High byte
TL1
Timer 1 Low byte
TL0
Timer 0 Low byte
TMOD
TCON(1)
PCON
DPH
Timer 0 and 1 Mode Control Register
Timer 0 and 1 Control/External Interrupt Control Register
Power Control Register
Data Pointer High byte
DPL
Data Pointer Low byte
SP
P0(1)
Stack Pointer
(2)
XXXXXXXX
Digital I/O Port Register 0
Notes
1. Bit addressable register.
2. Port reset state determined by the customer.
1997 Apr 10
36
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
49 single-byte, 46 two-byte and 16 three-byte instructions.
When using a 12 MHz oscillator, 64 instructions execute in
1 µs and 45 instructions execute in 2 µs. Multiply and
divide instructions execute in 4 µs.
18 INSTRUCTION SET
The P8xCL410 uses a powerful instruction set which
permits the expansion of on-chip CPU peripherals and
optimizes byte efficiency and execution speed. Assigned
opcodes add new high-power operation and permit new
addressing modes. The instruction set consists of
For the description of the Data Addressing modes and
Hexadecimal opcode cross-reference see Table 40.
Table 36 Instruction set description: Arithmetic operations
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES
CYCLES
Arithmetic operations
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
INC
A,Rr
add register to A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
2*
A,direct
A,@Ri
A,#data
A,Rr
add direct byte to A
25
add indirect RAM to A
26, 27
24
add immediate data to A
add register to A with carry flag
add direct byte to A with carry flag
add indirect RAM to A with carry flag
add immediate data to A with carry flag
subtract register from A with borrow
subtract direct byte from A with borrow
subtract indirect RAM from A with borrow
subtract immediate data from A with borrow
increment A
3*
A,direct
A,@Ri
A,#data
A,Rr
35
36, 37
34
9*
A,direct
A,@Ri
A,#data
A
95
96, 97
94
04
INC
Rr
increment register
0*
INC
direct
@Ri
increment direct byte
05
INC
increment indirect RAM
decrement A
06, 07
14
DEC
DEC
DEC
DEC
INC
A
Rr
decrement register
1*
direct
@Ri
decrement direct byte
15
decrement indirect RAM
increment data pointer
16, 17
A3
DPTR
AB
MUL
DIV
multiply A and B
A4
AB
divide A by B
84
DA
A
decimal adjust A
D4
1997 Apr 10
37
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
Table 37 Instruction set description: Logic operations
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES
CYCLES
Logic operations
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
A,Rr
AND register to A
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
5*
A,direct
A,@Ri
A,#data
direct,A
AND direct byte to A
AND indirect RAM to A
AND immediate data to A
AND A to direct byte
55
56, 57
54
52
direct,#data AND immediate data to direct byte
53
A,Rr
OR register to A
4*
A,direct
A,@Ri
A,#data
direct,A
OR direct byte to A
OR indirect RAM to A
OR immediate data to A
OR A to direct byte
45
46, 47
44
42
direct,#data OR immediate data to direct byte
43
A,Rr
exclusive-OR register to A
6*
A,direct
A,@Ri
A,#data
direct,A
exclusive-OR direct byte to A
exclusive-OR indirect RAM to A
exclusive-OR immediate data to A
exclusive-OR A to direct byte
65
66, 67
64
62
direct,#data exclusive-OR immediate data to direct byte
63
A
A
A
A
A
A
A
clear A
E4
F4
complement A
rotate A left
23
RLC
RR
rotate A left through the carry flag
rotate A right
33
03
RRC
SWAP
rotate A right through the carry flag
swap nibbles within A
13
C4
1997 Apr 10
38
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
Table 38 Instruction set description: Data transfer
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES
CYCLES
Data transfer
A,Rr
A,direct (note 1) move direct byte to A
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVC
MOVC
MOVX
MOVX
MOVX
MOVX
PUSH
POP
move register to A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
E*
E5
A,@Ri
move indirect RAM to A
E6, E7
74
A,#data
move immediate data to A
move A to register
Rr,A
F*
Rr,direct
Rr,#data
direct,A
move direct byte to register
move immediate data to register
move A to direct byte
A*
7*
F5
direct,Rr
direct,direct
direct,@Ri
direct,#data
@Ri,A
move register to direct byte
move direct byte to direct
8*
85
move indirect RAM to direct byte
move immediate data to direct byte
move A to indirect RAM
86, 87
75
F6, F7
A6, A7
76, 77
90
@Ri,direct
@Ri,#data
move direct byte to indirect RAM
move immediate data to indirect RAM
DPTR,#data 16 load data pointer with a 16-bit constant
A,@A+DPTR
A,@A+PC
A,@Ri
move code byte relative to DPTR to A
move code byte relative to PC to A
move external RAM (8-bit address) to A
move external RAM (16-bit address) to A
move A to external RAM (8-bit address)
move A to external RAM (16-bit address)
push direct byte onto stack
93
83
E2, E3
E0
A,@DPTR
@Ri,A
F2, F3
F0
@DPTR,A
direct
C0
direct
pop direct byte from stack
D0
XCH
A,Rr
exchange register with A
C*
XCH
A,direct
A,@Ri
exchange direct byte with A
C5
XCH
exchange indirect RAM with A
C6, C7
D6, D7
XCHD
A,@Ri
exchange LOW-order digit indirect RAM with A
Note
1. MOV A,ACC is not permitted.
1997 Apr 10
39
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
Table 39 Instruction set description: Boolean variable manipulation, Program and machine control
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES
CYCLES
Boolean variable manipulation
CLR
CLR
SETB
SETB
CPL
CPL
ANL
ANL
ORL
ORL
MOV
MOV
C
clear carry flag
clear direct bit
set carry flag
set direct bit
1
2
1
2
1
2
2
2
2
2
2
2
1
1
1
1
1
1
2
2
2
2
1
2
C3
C2
D3
D2
B3
B2
82
B0
72
A0
A2
92
bit
C
bit
C
complement carry flag
bit
complement direct bit
C,bit
C,/bit
C,bit
C,/bit
C,bit
bit,C
AND direct bit to carry flag
AND complement of direct bit to carry flag
OR direct bit to carry flag
OR complement of direct bit to carry flag
move direct bit to carry flag
move carry flag to direct bit
Program and machine control
ACALL
LCALL
RET
RETI
AJMP
LJMP
SJMP
JMP
JZ
addr11
addr16
absolute subroutine call
long subroutine call
2
3
1
1
2
3
2
1
2
2
2
2
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
•1
12
22
32
♦ 1
02
80
73
60
70
40
50
20
30
10
B5
B4
B*
return from subroutine
return from interrupt
addr11
addr16
rel
absolute jump
long jump
short jump (relative address)
jump indirect relative to the DPTR
jump if A is zero
@A+DPTR
rel
JNZ
rel
jump if A is not zero
JC
rel
jump if carry flag is set
JNC
rel
jump if carry flag is not set
jump if direct bit is set
JB
bit,rel
JNB
bit,rel
jump if direct bit is not set
jump if direct bit is set and clear bit
compare direct to A and jump if not equal
compare immediate to A and jump if not equal
JBC
bit,rel
CJNE
CJNE
CJNE
A,direct,rel
A,#data,rel
Rr,#data,rel
compare immediate to register and jump if not
equal
CJNE
@Ri,#data,rel
compare immediate to indirect and jump if not
equal
3
2
B6, B7
DJNZ
DJNZ
NOP
Rr,rel
decrement register and jump if not zero
decrement direct and jump if not zero
no operation
2
3
1
2
2
1
D*
D5
00
direct,rel
1997 Apr 10
40
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
Table 40 Description of the mnemonics in the Instruction set
MNEMONIC
DESCRIPTION
Data addressing modes
Rr
working register R0-R7
direct
@Ri
128 internal RAM locations and any special function register (SFR)
indirect internal RAM location addressed by register R0 or R1 of the actual register bank
8-bit constant included in instruction
#data
#data 16
bit
16-bit constant included as bytes 2 and 3 of instruction
direct addressed bit in internal RAM or SFR
addr16
16-bit destination address. Used by LCALL and LJMP;
the branch will be anywhere within the 64 kbytes Program Memory address space
addr11
rel
111-bit destination address. Used by ACALL and AJMP; the branch will be within the
same 2 kbytes page of Program Memory as the first byte of the following instruction
signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps;
range is −128 to +127 bytes relative to first byte of the following instruction
Hexadecimal opcode cross-reference
*
•
8, 9, A, B, C, D, E, F
1, 3, 5, 7, 9, B, D, F
0, 2, 4, 6, 8, A, C, E
♦
1997 Apr 10
41
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
1997 Apr 10
42
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
19 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
PARAMETER
MIN.
−0.5
MAX.
+6.5
VDD + 0.5 V
UNIT
supply voltage
V
VI
input voltage on any pin with respect to ground (VSS
DC current on any input
)
−0.5
−5.0
−5.0
−
II
+5.0
+5.0
300
mA
mA
IO
DC current on any output
Ptot
Tstg
Tamb
Tj
total power dissipation
mW
°C
storage temperature
−65
−40
−
+150
+85
operating ambient temperature
operating junction temperature
°C
+125
°C
20 DC CHARACTERISTICS
VSS = 0 V; Tamb = −40 to +85 °C; all voltages with respect to VSS unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN.
VDD supply voltage
MAX.
UNIT
operating
VSS = 0 V
1.8
6.0
V
V
RAM retention in Power-down mode
1.0
−
Operating supply current (note 1, note 2)
IDD operating supply current
Oscillator 1; fclk = 32 kHz;
VDD = 1.8 V; Tamb = 25 °C
−
−
−
−
−
50
2.5
14
16
20
µA
Oscillator 2; fclk = 3.58 MHz;
VDD = 3 V
mA
mA
mA
mA
Oscillator 2; fclk = 10 MHz;
VDD = 5 V
Oscillator 3; fclk = 12 MHz;
VDD = 5 V
Oscillator 4; fclk = 12 MHz;
VDD = 5 V
Supply current (Idle mode) (note 2, note 3)
IDD(idle)
supply current (Idle mode)
Oscillator 1; fclk = 32 kHz;
VDD = 1.8 V; Tamb = 25 °C
−
−
−
−
−
25
µA
Oscillator 2; fclk = 3.58 MHz;
VDD = 3 V
1.0
5.0
7.0
8.5
mA
mA
mA
mA
Oscillator 2; fclk = 10 MHz;
VDD = 5 V
Oscillator 3; fclk = 12 MHz;
VDD = 5 V
Oscillator 4; fclk = 12 MHz;
VDD = 5 V
1997 Apr 10
43
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Supply current (Power-down mode) (note 2, note 4)
IDD(pd)
supply current (Power-down mode)
VDD = 1.8 V; Tamb = 25 °C
−
10
µA
Inputs
VIL
VIH
IIL
LOW level input voltage
VSS
0.3VDD
V
HIGH level input voltage
input current logic 0 (port 1,2,3)
0.7VDD VDD
V
VDD = 5 V; VI = 0.4 V
VDD = 2.5 V; VI = 0.4 V
VDD = 5 V; VI = 0.5VDD
VDD = 2.5 V; VI = 0.5VDD
VSS < VI < VDD
−
−
−
−
−
−100
−50
µA
µA
mA
µA
µA
IITL
input current logic 0, HIGH- to-LOW
transition (port 1,2,3)
−1.0
−500
10
ILI
input leakage current (port 0, EA)
Port outputs
IOL
LOW level output current (except SDA;
SCL)
VDD = 5 V; VOL = 0.4 V
VDD = 2.5 V; VOL = 0.4 V
VDD = 5 V; VOL = 0.4 V
VDD = 5 V; VOH = VDD − 0.4 V
1.6
0.7
3.0
−1.6
−
mA
mA
mA
mA
mA
kΩ
−
IOL
IOH
LOW level output current (SDA; SCL)
−
HIGH level output current (push-pull
options)
−
VDD = 2.5 V; VOH = VDD − 0.4 V −0.7
−
RRST
RST pull-down resistor
10
200
Notes
1. The operating supply current is measured with all output pins disconnected; XTAL 1 driven with tr = tf = 10 ns;
VIL = VSS; VIH = VDD; XTAL 2 not connected; EA = RST = Port 0 = VDD; all open drain outputs connected to VSS
.
2. Circuits with Power-on-reset option ‘OFF’ are tested at VDD(min) = 1.8 V; within option ‘ON’ (typically 1.3 V) they are
tested at VDD(min) = 2.3 V. Please note, option ‘ON’ is only available on P83CL410.
3. The Idle mode supply current is measured with all output pins disconnected; XTAL 1 driven with tr = tf = 10 ns;
VIL = VSS. XTAL 2 not connected; EA = Port 0 = VDD; RST = VSS; all open drain outputs connected to VSS
4. The Power-down current is measured with all output pins disconnected; XTAL 1 not connected; EA = Port 0 = VDD
RST = VSS; all open drain outputs connected to VSS
.
;
.
1997 Apr 10
44
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
MBK047
MBK026
2
2.0
10
handbook, halfpage
handbook, halfpage
I
DD
(mA)
1.6
f
XTAL
(MHz)
10
1.2
1.2 MHz
1
0.8
0.4
−1
10
32 kHz
−2
0
0
10
2
4
6
0
2
4
6
8
V
(V)
DD
V
(V)
V
MIN = 1.8 V
DD
DD
Tamb = 25 °C.
Fig.22 Typical operating current as a function of
frequency and VDD (32 kHz and 1.2 MHz).
Fig.21 Frequency operating range.
MBK027
MBK028
5
16
handbook, halfpage
handbook, halfpage
I
I
DD
DD(idle)
(mA)
(mA)
4
12
3
12 MHz
12 MHz
8
4
2
8 MHz
8 MHz
1
3.58 MHz
2
3.58 MHz
0
0
0
4
6
0
2
4
6
V
(V)
V
(V)
DD
DD
Tamb = 25 °C.
Tamb = 25 °C.
Fig.23 Typical operating current as a function of
frequency and VDD (3.58, 8 and 12 MHz).
Fig.24 Typical Idle current as a function of
frequency and VDD
.
1997 Apr 10
45
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
MBK029
8
handbook, halfpage
I
DD(pd)
(µA)
6
4
2
0
0
2
4
6
V
(V)
DD
Tamb = 25 °C.
Fig.25 Typical Power-down current as a function of
VDD
.
1997 Apr 10
46
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
21 AC CHARACTERISTICS
VDD = 5 V; VSS = 0 V; Tamb = −40 to +85 °C; CL = 50 pF for Port 0, ALE and PSEN; CL = 40 pF for all other outputs
unless specified; tCLK = 1/ fCLK
.
fosc = 12 MHz
MIN. MAX.
fosc = VARIABLE
UNIT
SYMBOL
PARAMETER
MIN.
MAX.
Program Memory (Fig.26)
tLHLL
tAVLL
tLLAX
tLLIV
ALE pulse width
127
43
48
−
−
2tCLK − 40
−
−
−
ns
ns
ns
address valid to ALE LOW
address hold after ALE LOW
ALE LOW to valid instruction in
ALE LOW to PSEN LOW
PSEN pulse width
−
t
CLK − 40
CLK − 35
−
t
233
−
−
4tCLK − 100 ns
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tPXAV
tAVIV
tPLAZ
58
215
−
tCLK − 25
−
−
ns
ns
−
3tCLK − 35
PSEN LOW to valid instruction in
input instruction hold after PSEN
input instruction float after PSEN
PSEN to address valid
125
−
−
0
−
3tCLK − 125 ns
0
−
ns
ns
ns
−
63
−
tCLK − 20
75
−
tCLK − 8
−
address to valid instruction in
PSEN LOW to address float
302
−
−
5tCLK − 115 ns
12
0
−
ns
External Data Memory (Figs 27 and 28)
tRLRH
tWLWH
tLLAX
RD pulse width
400
400
48
−
−
6tCLK − 100 −
6tCLK − 100 −
ns
ns
ns
WR pulse width
−
address hold after ALE LOW
RD LOW to valid data in
data float after RD
−
tCLK − 35
−
tRLDV
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
150
97
517
585
300
−
−
−
5tCLK − 165 ns
2tCLK − 70 ns
8tCLK − 150 ns
9tCLK − 165 ns
−
ALE LOW to valid data in
address to valid data in
ALE LOW to RD or WR LOW
address valid to RD or WR LOW
RD or WR HIGH to ALE HIGH
data valid to WR transition
data valid time WR HIGH
data hold after WR
−
−
−
200
203
43
23
433
33
−
3tCLK − 50 3tCLK + 50 ns
4
−
ns
ns
ns
ns
ns
ns
123
−
t
CLK − 40
CLK − 60
tCLK + 40
t
−
−
7tCLK − 150 −
−
tCLK −50
−
RD LOW to address float
12
−
12
1997 Apr 10
47
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
t
CY
a
t
t
LLIV
LHLL
ALE
PSEN
t
LLPL
t
PLPH
t
t
LLAX
PXAV
t
t
t
PXIZ
AVLL
PLIV
PORT 0
PORT 2
A0 to A7
inst. input
A0 to A7
inst. input
t
t
PXIX
PLAZ
t
AVIV
address A8 to A15
address A8 to A15
MGD680
Fig.26 Read from Program Memory.
t
CY
ALE
t
t
t
LHLL
LLDV
WHLH
PSEN
RD
t
t
RLRH
LLWL
t
t
t
RHDZ
AVLL
LLAX
t
t
t
RHDX
AVWL
RLDV
PORT 0
PORT 2
A0 to A7
data input
t
RLAZ
t
AVDV
address A8 to A15 (DPH) or Port 2
MGA177
Fig.27 Read from Data Memory.
48
1997 Apr 10
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
t
CY
t
t
LHLL
WHLH
ALE
PSEN
t
t
WLWH
LLWL
WR
t
AVWL
t
t
t
t
AVLL
LLAX
QVWH
WHQX
t
QVWX
PORT 0
PORT 2
A0 to A7
data output
address A8 to A15 (DPH) or Port 2
MGA178
Fig.28 Write to Data Memory.
1997 Apr 10
49
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
one machine cycle
one machine cycle
h
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
P1 P2
P1 P2
P1 P2 P1 P2 P1 P2
P1 P2 P1 P2 P1 P2
P1 P2 P1 P2 P1 P2
P1 P2
XTAL1
INPUT
dotted lines
are valid when
RD or WR are
active
ALE
PSEN
RD
only active
during a read
from external
data memory
only active
during a write
to external
data memory
WR
BUS
(PORT 0)
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
external
program
memory
fetch
address A8 - A15
address A8 - A15
address A8 - A15
address A8 - A15
PORT 2
BUS
(PORT 0)
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
address
A0 - A7
data output or data input
read or
write of
external data
memory
address A8 - A15
address A8 - A15 or Port 2 output
address A8 - A15
PORT 2
PORT 0, 2, 3
OUTPUT
old data
old data
new data
new data
PORT 1
OUTPUT
PORT 0, 2, 3
INPUT
sampling time of I/O port pins during input
SERIAL PORT
SHIFT CLOCK
(MODE 0)
MGD681
Fig.29 Instruction cycle timing.
50
1997 Apr 10
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
0.7 V
0.7 V
DD
DD
handbook, halfpage
0.9 V
DD
test points
0.4 V
DD
MLA586
0.3 V
DD
0.3 V
DD
Fig.30 AC testing input waveform.
MBK023
500 µA
I
IL(T)
I
I
I
100 µA
IL
0
0.5 V
DD
V
DD
Fig.31 Input current.
1997 Apr 10
51
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
22 P85CL000HFZ ‘PIGGY-BACK’ SPECIFICATION
22.2 Feature differences/additional features of
P85CL000HFZ with respect to P83CL410
The differences between the masked version and the
piggy-back are described below.
• No internal ROM
• 8-bit CPU, RAM, I/O in a single 40-lead package with
DIP pin-out
22.1 General description
The P85CL000HFZ is a piggy-back version with 256 bytes
of RAM used for emulation of the P83CL410 and the
P80CL51 microcontrollers. The P85CL000HFZ is
manufactured in an advanced CMOS technology.
The instruction set of the P85CL000HFZ is based on that
of the 8051. The device has low power consumption and a
wide supply voltage range. The P85CL000HFZ has two
software selectable modes of reduced activity for further
power reduction: Idle and Power-down. For timing and
AC/DC characteristics, please refer to the P83CL410
specifications.
• Socket for up to 16 kbytes external EPROM
• 256 bytes RAM, expandable externally to 64 kbytes
• UART interface
• On-chip oscillator: Oscillator 4 option only.
22.3 Common specification/feature differences between P85CL000HFZ and P83CL410/P80CL51
PARAMETER
P83CL410/P80CL51
P85CL000HFZ ‘PIGGY-BACK’
256
RAM size
ROM size
Port options
128
4K
EPROM size dependent (max. 16K)
1, 2, 3
1
Oscillator options
Oscillator 1, 2, 3, 4, RC
Oscillator 4
Mechanical dimensions
standard dual in-line, small outline
same pin-out as SOT129-1, but larger
package size
Current consumption
Voltage range
ESD
IDD
IDD (Oscillator 4) + IEPROM
full, limited by EPROM
full
specification
not tested (different package)
1997 Apr 10
52
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
23 PACKAGE OUTLINES
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
D
M
E
A
2
A
L
A
1
c
e
w M
Z
b
1
(e )
1
b
M
H
40
21
pin 1 index
E
1
20
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
w
UNIT
mm
b
b
c
D
E
e
e
L
M
M
1
1
E
H
max.
min.
max.
max.
1.70
1.14
0.53
0.38
0.36
0.23
52.50
51.50
14.1
13.7
3.60
3.05
15.80
15.24
17.42
15.90
4.7
0.51
4.0
2.54
0.10
15.24
0.60
0.254
0.01
2.25
0.067
0.045
0.021
0.015
0.014
0.009
2.067
2.028
0.56
0.54
0.14
0.12
0.62
0.60
0.69
0.63
inches
0.19
0.020
0.16
0.089
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-14
SOT129-1
051G08
MO-015AJ
1997 Apr 10
53
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
VSO40: plastic very small outline package; 40 leads
SOT158-1
D
E
A
X
c
y
H
v
M
A
E
Z
40
21
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
20
w
M
b
p
e
0
5
scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(2)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
0.3
0.1
2.45
2.25
0.42
0.30
0.22
0.14
15.6
15.2
7.6
7.5
12.3
11.8
1.7
1.5
1.15
1.05
0.6
0.3
2.70
0.11
0.25
0.762
0.03
2.25
0.089
0.2
0.1
0.1
7o
0o
0.012 0.096
0.004 0.089
0.017 0.0087 0.61
0.012 0.0055 0.60
0.30
0.29
0.48
0.46
0.067 0.045
0.059 0.041
0.024
0.012
inches
0.010
0.008 0.004 0.004
Notes
1. Plastic or metal protrusions of 0.4 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-24
SOT158-1
1997 Apr 10
54
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
y
X
A
33
23
34
22
Z
E
e
Q
H
E
E
A
2
A
(A )
3
A
1
w M
θ
b
p
L
p
pin 1 index
L
12
44
detail X
1
11
w M
Z
v
M
A
D
b
p
e
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
10o
0o
0.25 1.85
0.05 1.65
0.40 0.25 10.1 10.1
0.20 0.14 9.9 9.9
12.9 12.9
12.3 12.3
0.95 0.85
0.55 0.75
1.2
0.8
1.2
0.8
mm
2.10
0.25
0.8
1.3
0.15 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT307-2
1997 Apr 10
55
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
24 SOLDERING
24.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary from
50 to 300 seconds depending on heating method. Typical
reflow temperatures range from 215 to 250 °C.
24.2 DIP
24.2.1 SOLDERING BY DIPPING OR BY WAVE
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheat for 45 minutes at 45 °C.
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
24.3.2 WAVE SOLDERING
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
24.2.2 REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
24.3 QFP
24.3.1 REFLOW SOLDERING
Reflow soldering techniques are suitable for all QFP
packages.
1997 Apr 10
56
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured. Maximum permissible solder
temperature is 260 °C, and maximum duration of package
immersion in solder is 10 seconds, if cooled to less than
150 °C within 6 seconds. Typical dwell time is 4 seconds
at 250 °C.
24.5 Wave soldering
Wave soldering techniques can be used for all VSO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
24.3.3 REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
24.4 Reflow soldering
Reflow soldering techniques are suitable for all VSO
packages.
24.6 Repairing soldered joints
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1997 Apr 10
57
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
25 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
26 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
27 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Apr 10
58
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I2C-bus
P80CL410; P83CL410
NOTES
1997 Apr 10
59
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
457047/1200/02/pp60
Date of release: 1997 Apr 10
Document order number: 9397 750 01518
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