P80CL580HFT [NXP]
IC 8-BIT, 6 MHz, MICROCONTROLLER, PDSO56, PLASTIC, VSOP-56, Microcontroller;
| 型号： | P80CL580HFT |
| 厂家： | 
NXP |
| 描述： | IC 8-BIT, 6 MHz, MICROCONTROLLER, PDSO56, PLASTIC, VSOP-56, Microcontroller 微控制器 |
| 文件： | 总80页 (文件大小：361K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
P80CL580; P83CL580
Low voltage 8-bit microcontrollers
with UART, I2C-bus and ADC
1997 Mar 14
Product specification
Supersedes data of 1996 Oct 04
File under Integrated circuits, IC20
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
CONTENTS
15
I2C-BUS SERIAL I/O
15.1
15.2
15.3
15.4
Serial Control Register (S1CON)
Serial Status Register (S1STA)
Data Shift Register (S1DAT)
Address Register (S1ADR)
1
FEATURES
2
GENERAL DESCRIPTION
ROMless version: P80CL580
APPLICATIONS
2.1
3
16
STANDARD SERIAL INTERFACE SIO0: UART
16.1
16.2
Multiprocessor communications
Serial Port Control and Status Register
(S0CON)
4
ORDERING INFORMATION
BLOCK DIAGRAM
5
6
FUNCTIONAL DIAGRAM
PINNING INFORMATION
16.3
17
Baud rates
7
INTERRUPT SYSTEM
7.1
7.2
Pinning
Pin description
17.1
17.2
17.3
External interrupts INT2 to INT8
Interrupt priority
Interrupt registers
8
FUNCTIONAL DESCRIPTION OVERVIEW
8.1
8.2
General
CPU timing
18
19
OSCILLATOR CIRCUITRY
RESET
9
MEMORY ORGANIZATION
19.1
19.2
External reset using the RST pin
Power-on-reset
9.1
9.2
9.3
9.4
Program Memory
Data Memory
Special Function Registers (SFRs)
Addressing
20
SPECIAL FUNCTION REGISTERS
OVERVIEW
21
22
23
24
25
26
INSTRUCTION SET
LIMITING VALUES
DC CHARACTERISTICS
AC CHARACTERISTICS
PACKAGE OUTLINES
SOLDERING
10
I/O FACILITIES
10.1
10.2
10.3
10.4
Ports
Port options
Port 0 options
SET/RESET options
11
TIMERS/EVENT COUNTERS
11.1
11.2
11.3
11.4
Timer 0 and Timer 1
Timer T2
Timer/Counter 2 Control Register (T2CON)
Watchdog Timer
26.1
26.2
26.3
26.4
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
12
PULSE WIDTH MODULATED OUTPUT
27
28
29
DEFINITIONS
12.1
12.2
Prescaler Frequency Control Register (PWMP)
Pulse Width Register (PWM0)
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
13
ANALOG-TO-DIGITAL CONVERTER (ADC)
ADC Control Register (ADCON)
13.1
14
REDUCED POWER MODES
14.1
14.2
14.3
14.4
14.5
Idle mode
Power-down mode
Wake-up from Power-down mode
Status of external pins
Power Control Register (PCON)
1997 Mar 14
2
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
• Very low current consumption:
1
FEATURES
typically 4.5 mA at 2.5 V and 8 MHz
• Full static 80C51 Central Processing Unit
• Operating ambient temperature range: −40 to +85 °C.
• 8-bit CPU, ROM, RAM, I/O in a 56-lead VSO or 64-lead
QFP package
2
GENERAL DESCRIPTION
• 256 bytes on-chip RAM Data Memory
The P80CL580; P83CL580 (hereafter generally referred to
as P8xCL580) is manufactured in an advanced CMOS
technology. The P8xCL580 has the same instruction set
as the 80C51, consisting of over 100 instructions:
49 one-byte, 46 two-byte, and 16 three-byte. The device
operates over a wide range of supply voltages and has low
power consumption; there are two software selectable
modes for power reduction: Idle and Power-down.
For emulation purposes, the P85CL580 (piggy-back
version) with 256 bytes of RAM is recommended.
• 6 kbytes on-chip ROM Program Memory for P83CL580
• External memory expandable up to 128 kbytes: RAM up
to 64 kbytes and ROM up to 64 kbytes
• Five 8-bit ports; 40 I/O lines
• Three 16-bit Timers/Event counters
• On-chip oscillator suitable for RC, LC, quartz crystal or
ceramic resonator
• Fifteen source, fifteen vector, nested interrupt structure
with two priority levels
This data sheet details the specific properties of the
P80CL580; P83CL580. For details of the 80C51 core and
the I2C-bus see “Data Handbook IC20”.
• Full duplex serial port (UART)
• I2C-bus interface for serial transfer on two lines
• Analog-to-digital converter (ADC) with Power-down
mode; 4 input channels and 8-bit ADC
2.1
ROMless version: P80CL580
• Pulse Width Modulated (PWM) output (8-bit resolution)
• Watchdog Timer
The P80CL580 is the ROMless version of the P83CL580.
The mask options on the P80CL580 are fixed as follows:
• All ports have option ‘1S’ (standard port, HIGH after
reset), except ports P1.6 and P1.7 which have option
‘2S’ (open-drain, HIGH after reset)
• Enhanced architecture with:
– non-page oriented instructions
– direct addressing
• Oscillator option: Oscillator 3
• Power-on-reset option: off.
– four 8-byte RAM register banks
– stack depth limited only by available internal RAM
(maximum 256 bytes)
3
APPLICATIONS
– multiply, divide, subtract and compare instructions
The P8xCL580 is an 8-bit general purpose microcontroller
especially suited for cordless telephone and mobile
communication applications. The P8xCL580 also
functions as an arithmetic processor having facilities for
both binary and BCD arithmetic plus bit-handling
capabilities.
• Reduced power consumption through Power-down and
Idle modes
• Wake-up via external interrupts at Port 1
• Frequency range: 0 to 12 MHz. For ADC operation
minimum 250 kHz at 2.7 V
• Supply voltage: 2.5 to 6.0 V
4
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER(1)
NAME
DESCRIPTION
VERSION
SOT190-1
SOT319-2
P8xCL580HFT VSO56 plastic very small outline package; 56 leads
P8xCL580HFH QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm);
body 14 x 20 x 2.8 mm
Note
1. ‘x’ = 0 or 3. Refer to the Order Entry Form (OEF) for this device for the full type number, including options/program.
1997 Mar 14
3
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
5
BLOCK DIAGRAM
BM450
1997 Mar 14
4
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
6
FUNCTIONAL DIAGRAM
XTAL1
XTAL2
LOW ORDER
ADDRESS
AND
PORT 0
PORT 1
PORT 2
PORT 3
DATA BUS
EA
PSEN
ALE
T2
T2EX
INT2
INT3
PWM0
STADC INT4
INT5
V
SSA
INT6
INT7
V
ref(p)(A)
INT8
SCL
SDA
P80CL580
P83CL580
ADC3
ADC2
ADC1
ADC0
HIGH ORDER
ADDRESS
BUS
RXD
TXD
INT0
INT1
T0
PORT 4
T1
WR
RD
V
V
RST
EWN
SS
DD
MBB541
Fig.2 Functional diagram.
5
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
7
PINNING INFORMATION
Pinning
7.1
handbook, halfpage
V
1
2
3
4
5
6
56
55
54
53
52
51
50
49
ADC3
ADC2
DD
P2.0
P2.1
P2.2
ADC1
ADC0
V
ref(p)(A)
PSEN
ALE
V
SSA
P4.0
P4.1
P4.2
7
8
9
EA
P2.3
P2.4
48
P4.3 10
P4.4 11
47 P2.5
46
45
P2.6
P2.7
12
13
14
P4.5
P4.6
P4.7
44
43
42
P0.7
P0.6
P0.5
P0.4
P80CL580
P83CL580
RST 15
16
41
P1.0/INT2/T2
P1.1/INT3/T2EX 17
18
40 P0.3
39 P0.2
P1.2/INT4/STADC
P1.3/INT5 19
20
38
P0.1
37
36
35
P0.0
P1.4/INT6
P1.5/INT7 21
P3.7/RD
P3.6/WR
P1.6/INT8/SCL 22
P1.7/SDA
PWM0 24
23
34
33
32
P3.5/T1
P3.4/T0
25
26
EWN
P3.3/INT1
XTAL2
31 P3.2/INT0
30
XTAL1 27
P3.1/TXD
29 P3.0/RXD
V
28
SS
MBB542
Fig.3 Pin configuration for VSO56 package.
6
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
P4.0
1
2
51 EA
50
49
P4.1
n.c.
3
n.c.
P2.3
P4.2
P4.3
4
48 P2.4
5
47
46
45
44
43
42
41
40
39
38
37
P2.5
P2.6
P2.7
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
6
P4.4
7
P4.5
8
P4.6
9
n.c.
10
11
12
13
14
15
P80CL580
P83CL580
P4.7
RST
P1.0/INT2/T2
P1.1/INT3/T2EX
P1.2/INT4/STADC
P1.3/INT5
P1.4/INT6 16
17
36 n.c.
35
n.c.
n.c.
n.c. 18
34 P3.7/RD
33 P3.6/WR
P1.5/INT7 19
MGC765
Fig.4 Pin configuration for QFP64 package.
7
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
7.2
Pin description
Table 1 Pin description for VSO56 (SOT190-1) and QFP64 (SOT319-2)
For more extensive description of the port pins see Chapter 10 “I/O facilities”.
PIN
SYMBOL
DESCRIPTION
4 input channels to the ADC.
VSO56
QFP64
ADC3 to ADC0
Vref(p)(A)
1 to 4
59 to 62
63
5
6
Positive potential of analog-to-digital conversion reference resistor.
Analog part ground.
VSSA
64
P4.0 to P4.7
7 to 14
1, 2, 4 to 8, Port 4: 8-bit bidirectional I/O port. (P4.0 to P4.7). Port pins that have
10
logic 1s written to them are pulled HIGH by internal pull-ups, and in this
state can be used as inputs. As inputs, Port 4 pins that are externally
pulled LOW will source current (IIL, see Chapter 23) due to the internal
pull-ups. Port 4 output buffers can sink/source 4 LS TTL loads.
RST
15
11
Reset: a HIGH level on this pin for two machine cycles while the
oscillator is running resets the device.
P1.0/INT2/T2
P1.1/INT3/T2EX
P1.2/INT4/STADC
P1.3/INT5
16
17
18
19
20
21
22
23
24
25
12
13
14
15
16
19
20
21
22
23
• Port 1: 8-bit bidirectional I/O port (P1.0 to P1.7). Same characteristics
as Port 4, but note that P1.6 and P1.7 are open-drain only.
• Alternative functions:
– INT2 to INT8 are external interrupt inputs
– STADC is the external trigger of the analog-to-digital converter
– T2 and T2EX are the Timer/event counter 2 inputs
– SCL and SDA are the I2C-bus clock and data lines.
P1.4/INT6
P1.5/INT7
P1.6/INT8/SCL
P1.7/SDA
PWM0
Pulse Width Modulation output 0.
EWN
Enable Watchdog Timer: enable for Watchdog Timer and enable
Power-down mode.
XTAL2
XTAL1
26
27
24
25
Crystal oscillator output: output of the inverting amplifier of the
oscillator. Left open when external clock is used.
Crystal oscillator input: input to the inverting amplifier of the oscillator,
also the input for an externally generated clock source.
VSS
28
29
30
31
32
33
34
35
36
26
27
28
29
30
31
32
33
34
Ground: circuit ground potential.
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
• Port 3: 8-bit bidirectional I/O port (P3.0 to P3.7).
Same characteristics as Port 4
• Alternative functions:
– RXD is the UART serial data input (asynchronous) or data
input/output (synchronous)
– TXD is the UART serial data output (asynchronous) or clock output
(synchronous)
– INT0 and INT1 are external interrupts 0 and 1
– T0 and T1 are external inputs for timers 0 and 1.
1997 Mar 14
8
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
PIN
SYMBOL
DESCRIPTION
VSO56
QFP64
P0.0 to P0.7
37 to 44
37 to 44
• Port 0: 8-bit open-drain bidirectional I/O port. As an open-drain output
port it can sink 8 LS TTL loads. Port 0 pins that have logic 1s written
to them float, and in that state will function as high impedance inputs.
• Low-order addressing: Port 0 is also the multiplexed low-order
address and data bus during access to external memory. The strong
internal pull-ups are used while emitting logic 1s within the low order
address.
P2.0 to P2.7
55 to 53,
49 to 45
56 to 54,
49 to 45
• Port 2: 8-bit bidirectional I/O port with internal pull-ups.
Same characteristics as Port 4.
• High-order addressing: Port 2 emits the high-order address byte
during accesses to external memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses the strong internal
pull-ups when emitting logic 1s. During accesses to external memory
that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the
P2 Special Function Register.
EA
50
51
52
51
52
53
57
External Access. When EA is held HIGH the CPU executes out of
internal Program Memory (unless the program counter exceeds
17FFH). Holding EA LOW forces the CPU to execute out of external
memory regardless of the value of the Program Counter.
ALE
PSEN
Address Latch Enable. Output pulse for latching the low byte of the
address during access to external memory. ALE is emitted at a constant
rate of 1⁄6 × fosc, and may be used for external timing or clocking
purposes (assuming MOVX instructions are not used).
Program Store Enable. Output read strobe to external Program
Memory. When executing code out of external Program Memory, PSEN
is activated twice each machine cycle. However, during each access to
external Data Memory two PSEN activations are skipped.
VDD
n.c.
56
Power supply.
−
3, 9, 17, 18, Not connected.
35, 36, 50
and 58
1997 Mar 14
9
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
The device has two software-selectable modes of reduced
activity for power reduction:
8
FUNCTIONAL DESCRIPTION OVERVIEW
This chapter gives a brief overview of the device.
The detailed functional description is in the following
chapters:
• Idle mode; freezes the CPU while allowing the
derivative functions (timers, serial I/O, ADC, PWM) and
interrupt system to continue functioning.
Chapter 9 “Memory organization”
Chapter 10 “I/O facilities”
• Power-down mode; saves the RAM contents but
freezes the oscillator causing all other chip functions to
be inoperative.
Chapter 11 “Timers/event counters”
Chapter 12 “Pulse Width Modulated output”
Chapter 13 “Analog-to-digital converter (ADC)”
Chapter 14 “Reduced power modes”
Chapter 15 “I2C-bus serial I/O”
In addition, two serial interfaces are provided on-chip:
• A standard UART serial interface, and
• A standard I2C-bus serial interface. The I2C-bus serial
interface has byte-oriented master and slave functions
allowing communication with the whole family of I2C-bus
compatible devices.
Chapter 16 “Standard serial interface SIO0: UART”
Chapter 17 “Interrupt system”
Chapter 18 “Oscillator circuitry”
8.2
CPU timing
Chapter 19 “Reset”.
A machine cycle consists of a sequence of 6 states. Each
state lasts for two oscillator periods, thus a machine cycle
takes 12 oscillator periods or 1 µs if the oscillator
frequency (fosc) is 12 MHz.
8.1
General
The P8xCL580 is a stand-alone high-performance CMOS
microcontroller designed for use in real-time applications
such as cordless telephone and mobile communications,
instrumentation, industrial control, intelligent computer
peripherals and consumer products.
The device provides hardware features, architectural
enhancements and new instructions to function as a
controller for applications requiring up to 64 kbytes of
Program Memory and/or up to 64 kbytes of Data Memory.
The P8xCL580 contains a 6 kbytes Program Memory
(ROM; P83CL580); a static 256 bytes Data Memory
(RAM); 40 I/O lines; three 16-bit timer/event counters; a
fifteen-source two priority-level, nested interrupt structure
and on-chip oscillator and timing circuit, 4-channel 8-bit
A/D converter, Watchdog Timer and Pulse Width
Modulation output.
1997 Mar 14
10
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
9
MEMORY ORGANIZATION
9.4
Addressing
The P8xCL580 has 6 kbytes of Program Memory (ROM;
P83CL580 only) plus 256 bytes of Data Memory (RAM) on
board.The device has separate address spaces for
The P8xCL580 has five methods for addressing source
operands:
• Register
Program and Data Memory (see Fig.6). Using Port latches
P0 and P2, the P8xCL580 can address up to 128 kbytes of
external memory. The CPU generates both read (RD) and
write (WR) signals for external Data Memory accesses,
and the read strobe (PSEN) for external Program Memory.
• Direct
• Register-indirect
• Immediate
• Base-register plus index-register-indirect.
The first three methods can be used for addressing
destination operands. Most instructions have a
‘destination/source’ field that specifies the data type,
addressing methods and operands involved. For
operations other than MOVs, the destination operand is
also a source operand.
9.1
Program Memory
The P83CL580 contains 6 kbytes of internal ROM. After
reset the CPU begins execution at location 0000H.
The lower 6 kbytes of Program Memory can be
implemented in either on-chip ROM or external Program
Memory.
If the EA pin is tied to VDD, then Program Memory fetches
from addresses 0000H to 17FFH are directed to the
internal ROM. Fetches from addresses 1800H to FFFFH
are directed to external ROM. Program Counter values
greater than 17FFH are automatically addressed to
external memory regardless of the state of the EA pin.
halfpage
7FH
30H
2FH
9.2
Data Memory
The P8xCL580 contains 256 bytes of internal RAM and
40 Special Function Registers (SFRs). Figure 6 shows the
internal Data Memory space divided into the lower
128 bytes, the upper 128 bytes, and the SFRs space.
Internal RAM locations 0 to 127 are directly and indirectly
addressable. Internal RAM locations 128 to 255 are only
indirectly addressable. The Special Function Register
locations 128 to 255 bytes are only directly addressable.
bit-addressable space
(bit addresses 0 to 7F)
20H
1FH
R7
R0
R7
18H
17H
R0
R7
10H
0FH
4 banks of 8 registers
(R0 to R7)
9.3
Special Function Registers (SFRs)
The upper 128 bytes are the address locations of the
SFRs. Figures 7 and 8 show the Special Function
Registers space. The SFRs include the port latches,
timers, peripheral control, serial I/O registers, etc. These
registers can only be accessed by direct addressing.
There are 128 directly addressable locations in the SFR
address space. Bit addressable SFRs are those that end
in 000B.
R0
R7
08H
07H
R0
0
MLA560 - 1
Fig.5 The lower 128 bytes of internal RAM.
1997 Mar 14
11
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
Access to memory addressing is as follows:
The P8xCL580 is classified as an 8-bit device since the
internal ROM, RAM, Special Function Registers,
Arithmetic Logic Unit and external data bus are all 8-bits
wide. It performs operations on bit, nibble, byte and
double-byte data types.
• Registers in one of the four register banks through
register, direct or register-indirect
• Lower 128 bytes of internal RAM through direct or
register-indirect; upper 128 bytes of internal RAM
through direct
Facilities are available for byte transfer, logic and integer
arithmetic operations. Data transfer, logic and conditional
branch operations can be performed directly on Boolean
variables to provide excellent bit handling.
• Special Function Registers through direct
• External Data Memory through register-indirect
• Program Memory look-up tables through base-register
plus index-register-indirect.
64 kbytes
h
EXTERNAL
64 kbytes
6 kbytes
6 kbytes
6 kbytes
OVERLAPPED SPACE
255
INTERNAL
(EA = 1)
EXTERNAL
(EA = 0)
SPECIAL
FUNCTION
REGISTERS
INTERNAL
DATA RAM
(1)
(2)
(3)
127
0
0
EXTERNAL
DATA MEMORY
INTERNAL DATA MEMORY
PROGRAM MEMORY
MGD676
(1) Accessible via indirect addressing only.
(2) Accessible via direct and indirect addressing.
(3) Accessible via direct addressing.
Fig.6 Memory map.
1997 Mar 14
12
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
DIRECT
BYTE
ADDRESS (HEX)
REGISTER
MNEMONIC
BIT ADDRESS
T3
FFH
FEH
FDH
FCH
PWMP
PWM0
IP1
FF FE FD FC FB FA F9 F8
F7 F6 F5 F4 F3 F2 F1 F0
F8H
F0H
EFH
EEH
EDH
ECH
EBH
EAH
E9H
B
IX1
IEN1
EF EE ED EC EB EA E9 E8 E8H
ACC
E7 E6 E5 E4 E3 E2 E1 E0 E0H
SFRs containing
directly addressable
bits
S1ADR
S1DAT
S1STA
S1CON
DBH
DAH
D9H
DF DE DD DC DB DA D9 D8
D8H
PSW
D7 D6 D5 D4 D3 D2 D1 D0 D0H
CFH
CEH
CDH
TH2
TL2
CCH
CBH
CAH
C9H
RCAP2H
RCAP2L
C8H
T2CON
CF CE CD CC CB CA C9 C8
ADCH
C5H
C4H
ADCON
P4
C1H
C0H
IRQ1
C7 C6 C5 C4 C3 C2 C1 C0
MGC749
Fig.7 Special Function Register memory map (continued in Fig.8).
13
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
DIRECT
BYTE
ADDRESS (HEX)
REGISTER
MNEMONIC
BIT ADDRESS
IP0
P3
BE BD BC BB BA B9 B8 B8H
B7 B6 B5 B4 B3 B2 B1 B0 B0H
AFH
AEH
ADH
ACH
ABH
AAH
A9H
IEN0
P2
AF AE AD AC AB AA A9 A8 A8H
A7 A6 A5 A4 A3 A2 A1 A0 A0H
SFRs containing
directly addressable
bits
S0BUF
S0CON
99H
98H
9F 9E 9D 9C 9B 9A 99 98
P1
97 96 95 94 93 92 91 90 90H
TH1
TH0
8DH
8CH
TL1
8BH
8AH
89H
TL0
TMOD
TCON
PCON
8F 8E 8D 8C 8B 8A 89 88
88H
87H
DPH
DPL
SP
83H
82H
81H
80H
P0
87 86 85 84 83 82 81 80
MLA607
Fig.8 Special Function Register memory map (continued from Fig.7).
14
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
LOW-to-HIGH transition in the port latch;
Fig.9(a).
10 I/O FACILITIES
10.1 Ports
Option 2 Open-drain; quasi-bidirectional I/O with
n-channel open-drain output. Use as an output
requires the connection of an external pull-up
resistor; see Fig.9(b).
The P8xCL580 has 40 I/O lines treated as one 8-bit port
plus 32 individually addressable bits or as five parallel 8-bit
addressable ports.
Port 4 has no alternative functions. To enable a port pin
alternative function for Ports 0, 1, 2 and 3, the port bit
latch in its SFR must contain a logic 1. The alternative
functions are detailed below:
Option 3 Push-pull; output with drive capability in both
polarities. Under this option, pins can only be
used as outputs; see Fig.9(c).
10.3 Port 0 options
Port 0 Provides the multiplexed low-order address and
data bus for expanding the device with standard
memories and peripherals.
The definition of port options for Port 0 is slightly different.
Two cases are considered. First, access to external
memory (EA = 0 or access above the built-in memory
boundary) and second, I/O accesses.
Port 1 Used for a number of special functions:
• Provides the inputs for the external interrupts:
INT2 to INT8.
10.3.1 EXTERNAL MEMORY ACCESSES
• External activation of Timer 2: T2.
• External trigger of the ADC: STADC.
• The I2C-bus interface: SCL and SDA.
Option 1 True logic 0 and logic 1 are written as address to
the external memory (strong pull-up to be used).
Option 2 An external pull-up resistor is required for
external accesses.
Port 2 Provides the high-order address when expanding
the device with external Program or Data Memory.
Option 3 Not allowed for external memory accesses as
the port can only be used as output.
Port 3 Pins can be configured individually to provide:
• External interrupt request inputs: INT1 and INT0.
• Counter input: T1 and T0.
10.3.2 I/O ACCESSES
Option 1 When writing a logic 1 to the port latch, the
strong pull-up ‘p1’ will be on for 2 oscillator
periods. No weak pull-up exists. Without an
external pull-up, this option can be used as a
high-impedance input.
• Control signals to read and write to external
memories: RD and WR.
• UART input and output: RXD and TXD.
Each port consists of a latch (SFRs P0 to P4), an output
driver and input buffer. Ports 1, 2, 3 and 4 have internal
pull-ups (except P1.6 and P1.7). Figure 9(a) shows that
the strong transistor ‘p1’ is turned on for only 2 oscillator
periods after a LOW-to-HIGH transition in the port latch.
When on, it turns on ‘p3’ (a weak pull-up) through the
inverter. This inverter and ‘p3’ form a latch which holds the
logic 1. In Port 0 the pull-up ‘p1’ is only on when emitting
logic 1s for external memory access. Writing a logic 1 to a
Port 0 bit latch leaves both output transistors switched off
so that the pin can be used as an high-impedance input.
Option 2 Open-drain; quasi-directional I/O with n-channel
open-drain output. Use as an output requires the
connection of an external pull-up resistor. See
Fig.9(b).
Option 3 Push-Pull; output with drive capability in both
polarities. Under this option pins can only be
used as outputs. See Fig.9(c).
10.4 SET/RESET options
Individual mask selection of the post-reset state is
available with any of the above pins. The selection is made
by appending ‘S’ or ‘R’ to Options 1, 2, or 3 above.
10.2 Port options
38 of the 40 port pins (excluding P1.6 and P1.7 with option
2S only) may be individually configured with one of the
following options. These options are also shown in Fig.9.
Option R RESET, at reset this pin will be initialized LOW.
Option S SET, at reset this pin will be initialized HIGH.
Option 1 Standard Port; quasi-bidirectional I/O with
pull-up. The strong booster pull-up ‘p1’ is turned
on for two oscillator periods after a
1997 Mar 14
15
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
strong pull-up
+5 V
2 oscillator
periods
p2
p3
p1
n
I/O pin
Q
from port latch
input data
INPUT
BUFFER
read port pin
(a) Standard
+5 V
external
pull-up
I/O pin
Q
from port latch
n
input data
read port pin
INPUT
BUFFER
(b) Open-drain
strong pull-up
+5 V
p1
I/O pin
Q
from port latch
n
MGD677
(c) Push-pull
Fig.9 Port configuration options.
16
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
11 TIMERS/EVENT COUNTERS
11.2.1 CAPTURE MODE
The P8xCL580 contains three 16-bit timer/event counter
registers; Timer 0, Timer 1 and Timer 2 which can perform
the following functions:
Figure 10 shows the Capture mode. Two options in this
mode, may be selected by the EXEN2 bit in T2CON:
• If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter
which upon overflowing sets the Timer 2 overflow bit
TF2, this may then be used to generate an interrupt.
• Measure time intervals and pulse durations
• Count events
• If EXEN2 = 1, Timer 2 operates as described above but
with the additional feature that a HIGH-to-LOW
• Generate interrupt requests.
In the ‘Timer’ operating mode the register is incremented
every machine cycle. Since a machine cycle consists of 12
oscillator periods, the count rate is 1⁄12 × fosc
transition at external input T2EX causes the current
value in TL2 and TH2 to be captured into registers
RCAP2L and RCAP2H respectively. In addition, the
transition at T2EX causes the EXF2 bit in T2CON to be
set; this may also be used to generate an interrupt.
.
In the ‘Counter’ operating mode, the register is
incremented in response to a HIGH-to-LOW transition.
Since it takes 2 machine cycles (24 oscillator periods) to
recognize a HIGH-to-LOW transition, the maximum count
rate is 1⁄24 × fosc. To ensure a given level is sampled, it
should be held for at least one complete machine cycle.
11.2.2 AUTO-RELOAD MODE
Figure 11 shows the Auto-reload mode. Also two options
in this mode are selected by the EXEN2 bit in T2CON:
• If EXEN2 = 0, then when Timer 2 rolls over, it sets the
TF2 bit but also causes the Timer 2 registers to be
reloaded with the 16-bit value held in registers RCAP2L
and RCAP2H. The 16-bit value held in these registers is
preset by software.
11.1 Timer 0 and Timer 1
Timer 0 and Timer 1 can be programmed independently to
operate in four modes:
Mode 0 8-bit timer or 8-bit counter each with divide-by-32
prescaler.
• If EXEN2 = 1, Timer 2 operates as described above but
with the additional feature that a HIGH-to-LOW
transition at external input T2EX will also trigger the
16-bit reload and set the EXF2 bit.
Mode 1 16-bit time-interval or event counter.
Mode 2 8-bit time-interval or event counter with automatic
reload upon overflow.
11.2.3 BAUD RATE GENERATOR MODE
Mode 3 Timer 0 establishes TL0 and TH0 as two
separate counters.
The Baud Rate Generator mode is selected when
RTCLK = 1. It will be described in conjunction with the
serial port (UART); see Section 16.3.2.
11.2 Timer T2
Timer T2 is a 16-bit timer/counter that can operate (like
Timer 0 and 1) either as a timer or as an event counter.
These functions are selected by the state of the C/T2 bit in
the T2CON register; see Tables 2 and 3.
Three operating modes are available Capture, Auto-reload
and Baud Rate Generator, which also are selected via the
T2CON register; see Table 4.
1997 Mar 14
17
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
OSC
12
C/T2 = 0
C/T2 = 1
TL2
(8 BITS)
TH2
(8 BITS)
TF2
control
TR2
T2 PIN
Timer 2
interrupt
capture
transition
detector
RCAP2L
RCAP2H
T2EX PIN
EXF2
MLA608
control
EXEN2
Fig.10 Timer 2 in Capture mode.
OSC
12
C/T2 = 0
TL2
(8 BITS)
TH2
(8 BITS)
TF2
C/T2 = 1
control
TR2
T2 PIN
Timer 2
interrupt
reload
RCAP2L
RCAP2H
transition
detector
T2EX PIN
EXF2
MLA609
control
EXEN2
Fig.11 Timer 2 in Auto-Reload mode.
18
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
11.3 Timer/Counter 2 Control Register (T2CON)
Table 2 Timer/Counter 2 Control Register (SFR address C8H)
7
6
5
4
3
2
1
0
TF2
EXF2
GF2
RTCLK
EXEN2
TR2
C/T2
CP/RL2
Table 3 Description of T2CON bits.
BIT
SYMBOL
DESCRIPTION
7
TF2
Timer 2 overflow flag. Set by a Timer 2 overflow and must be cleared by software. TF2
will not be set when RTCLK = 1.
6
EXF2
Timer 2 external flag. Set when either a capture or reload is caused by a negative
transition on T2EX and when EXEN2 = 1. When Timer T2 interrupt is enabled,
EXF2 = 1 will cause the CPU to vector to Timer 2 interrupt routine. EXF2 must be
cleared by software.
5
4
GF2
General purpose flag bit.
RTCLK
Receive/transmit clock flag. When set, causes the UART serial port to use Timer 2
overflow pulses for its receive and transmit clock in Modes 1 and 3. RTCLK = 0 causes
Timer 1 overflows to be used for the receive and transmit clock.
3
EXEN2
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result
of a negative transition on T2EX, if Timer 2 is not being used to clock the serial port.
EXEN2 = 0, causes Timer 2 to ignore events at T2EX.
2
1
TR2
Start/stop control for Timer 2. TR2 = 1 starts the timer.
C/T2
Timer or counter select for Timer 2. C/T2 = 0 selects the internal timer with a clock
frequency of 1⁄12 × fosc. C/T2 = 1 selects the external event counter; negative edge
triggered.
0
CP/RL2
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX, if
EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or
negative transitions at T2EX when EXEN2 = 1. When RTCLK = 1, this bit is ignored and
the timer is forced to auto-reload on a Timer 2 overflow.
Table 4 Timer 2 operating modes; X = don’t care.
RTCLK
CP/RL2
TR2
1
MODE
0
0
1
X
0
1
16-bit Auto-reload
16-bit Capture
Baud Rate Generator
Off
1
X
X
1
0
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
When a timer overflow occurs, the microcontroller is reset
and a reset output pulse is generated at the RST pin. To
prevent a system reset the timer must be reloaded in time
by the application software. If the processor suffers a
hardware/software malfunction, the software will fail to
reload the timer. This failure will produce a reset upon
overflow thus preventing the processor running out of
control.
11.4 Watchdog Timer
In addition to Timer T2 and the standard timers, a
Watchdog Timer (consisting of an 11-bit prescaler and an
8-bit timer) is also incorporated.
The Watchdog Timer is controlled by the Watchdog
Enable pin (EWN). When EWN = 0, the timer is enabled
and the Power-down mode is disabled. When EWN = 1,
the timer is disabled and the Power-down mode is
enabled. In the Idle mode the Watchdog Timer and reset
circuitry remain active.
The Watchdog Timer can only be reloaded if the condition
flag WLE (PCON.4) has been previously set by software.
At the moment the counter is loaded the condition flag is
automatically cleared.
The Watchdog Timer is shown in Fig. 12.
The time interval between the timer reloading and the
occurrence of a reset is dependent upon the reloaded
value. For example, this time period may range from 2 ms
to 500 ms when using an oscillator frequency
fosc = 12 MHz.
The timer frequency is derived from the oscillator
frequency using the following formula:
fosc
ftimer
=
--------------------------------
(12 × 2048)
INTERNAL BUS
V
DD
PRESCALER
11-BIT
overflow
f
/12
P
osc
TIMER T3 (8-BIT)
LOAD
LOADEN
CLEAR
RST
internal
reset
CLEAR
R
write
T3
RST
WLE
PD
LOADEN
PCON.4
PCON.1
EWN
INTERNAL BUS
MGD678
Fig.12 Functional diagram of the T3 Watchdog Timer.
1997 Mar 14
20
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
12 PULSE WIDTH MODULATED OUTPUT
The repetition frequency (fPWM) at the PWM0 output is
given by:
One Pulse Width Modulated output channel (PWM0) is
provided which outputs pulses of programmable length
and interval. The repetition frequency is defined by an 8-bit
prescaler (PWMP) that generates the clock for the
counter. The 8-bit counter counts modulo 255, i.e. from
0 to 254 inclusive. The value held in the 8-bit counter is
compared to the contents of the register PWM0.
fosc
----------------------------------------------------------------------------
{2 × (1 + PWMP ) × 255 }
fPWM
=
For fosc = 12 MHz the above formula gives a repetition
frequency range of 92 Hz to 23.5 kHz.
By loading the PWM0 register with either 00H or FFH, the
PWM0 output can be retained at a constant HIGH or LOW
level respectively. When loading FFH into the PWM0
register, the 8-bit counter will never actually reach this
value.
Provided the contents of this register are greater than the
counter value, the PWM0 output is set LOW. If the
contents of register PWM0 are equal to, or less than the
counter value, the PWM0 output is set HIGH.
The pulse-width-ratio is therefore defined by the contents
of register PWM0. The pulse-width-ratio will be in the
The PWM0 output pin is driven by push-pull drivers and is
not shared with any other function.
range 0 to 255
of 1⁄255
⁄255 and may be programmed in increments
.
12.1 Prescaler Frequency Control Register (PWMP)
Table 5 Prescaler Frequency Control Register (address FEH)
7
6
5
4
3
2
1
0
PWMP.7
PWMP.6
PWMP.5
PWMP.4
PWMP.3
PWMP.2
PWMP.1
PWMP.0
Table 6 Description of PWMP bits
BIT
SYMBOL
DESCRIPTION
7 to 1
PWMP.7 to PWMP.0
Prescaler division factor = (PWMP) + 1.
12.2 Pulse Width Register (PWM0)
Table 7 Pulse Width Register (address FCH)
7
6
5
4
3
2
1
0
PWM0.7
PWM0.6
PWM0.5
PWM0.4
PWM0.3
PWM0.2
PWM0.1
PWM0.0
Table 8 Description of PWM0 bits
BIT
SYMBOL
DESCRIPTION
(PWM0)
--------------------------------------------------
{255 – (PWM0) }
LOW/HIGH ratio of PWM0 signal =
7 to 1
PWM0.7 to PWM0.0
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
PWM0
I
N
T
E
R
N
A
L
OUTPUT
BUFFER
PWM0
8-BIT COMPARATOR
8-BIT COUNTER
f
osc
B
U
S
1/2
PRESCALER
PWMP
MGC750
Fig.13 Functional diagram of Pulse Width Modulated output (PWM0).
1997 Mar 14
22
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
The result of a completed conversion remains unaffected
provided ADCI = 1. While ADCS = 1 or ADCI = 1, a new
ADC start will be blocked and consequently lost.
13 ANALOG-TO-DIGITAL CONVERTER (ADC)
The analog input circuitry consists of a 4-bit analog
multiplexer and an ADC with 8-bit resolution. The analog
reference voltage (Vref(p)(A)) and analog ground (VSSA) are
connected via separate input pins. The conversion is
selectable from 24 machine cycles (24 µs at
An ADC conversion already in progress is aborted when
the Power-down mode is entered. The result of a
completed conversion (ADCI = 1) remains unaffected
when entering the Idle or Power-down mode.
fosc = 12 MHz) to 48 machine cycles. The functional
diagram of the ADC is shown in Fig. 14.
The analog-to-digital conversion can be started in 3 ways:
The ADC is controlled using the ADC Control Register
(ADCON). Input channels are selected by the analog
multiplexer via the ADCON register bits AADR0 and
AADR1. The completion of the 8-bit ADC conversion is
flagged by ADCI in the ADCON register and the result is
stored in the Special Function Register ADCH (address
C5H).
• Start in operating mode, continue in operating mode
• Start in operating mode, by setting the ADCS bit, then go
to Idle mode
• Set the ADEX bit, go to the Idle mode and start
conversion externally via the STADC pin.
For the three cases mentioned above the internal flag
ADCI is set upon completion of the conversion.
An ADC conversion in progress is unaffected by an
external software ADC start.
STADC
ADEX
+
V
ref(p)(A)
ADC0
8-BIT ADC
(succesive approximation)
ADC1
ANALOG INPUT
MULTIPLEXER
ADC2
ADC3
V
SSA
START
END
ADCON
(1)
0
1
2
3
4
5
6
-
0
1
2
3
4
5
6
7
ADCH
INTERNAL BUS
MGC751
(1) For the descriptions of ADCON bits see Table 10.
Fig.14 Functional diagram of analog input.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
13.1 ADC Control Register (ADCON)
Table 9 ADC Control Register (address C4H)
7
6
5
4
3
2
1
0
−
ADPD
ADEX
ADCI
ADCS
CKDIV
AADR1
AADR0
Table 10 Description of ADCON bits
BIT
SYMBOL
DESCRIPTION
7
6
−
Reserved.
ADPD
Power-down. This bit switches off the resistor reference to save power even when the
CPU is operating.
5
ADEX
Enable external start of conversion. This bit determines whether a conversion can be
started using the external pin STADC. When ADEX = 0, a conversion cannot be started
externally using STADC. When ADEX = 1, a conversion can be started externally using
STADC.
4
3
ADCI
ADC interrupt flag. This flag is set when an ADC conversion result is ready to be read.
An interrupt is invoked if this is enabled. This flag must be cleared by software (it cannot
be set by software); see Table 11.
ADCS
ADC start and status flag. When this bit is set an ADC conversion is started. ADCS
may be set by software or by the external signal STADC. The ADC logic ensures that
this signal is HIGH while the ADC is busy. On completion of the conversion ADCS is
reset and after that the interrupt flag ADCI is set. ADCS cannot be reset by software;
see Table 11.
2
CKDIV
This bit selects the conversion time, in terms of instruction cycles. This allows the CPU
to be run at the maximum frequency (12 MHz) yet keeping the ADC timing at low
frequency. When CKDIV = 0, the conversion time is equivalent to 24 instruction cycles.
When CKDIV = 1, the conversion time is equivalent to 48 instruction cycles.
The conversion time includes a sampling time of 6 cycles.
1
0
AADR1
AADR0
Analog input select. These bits are used to select one of the four analog inputs; see
Table 12. They only can be changed when ADCI and ADCS are both LOW.
Table 11 Analog-to-digital operation
ADCI ADCS OPERATION
Table 12 Selection of analog input channel
AADR1 AADR0 SELECTED CHANNEL
0
0
1
1
0
1
0
1
ADC not busy; a conversion can be
started.
0
0
1
1
0
1
0
1
AD0
AD1
AD2
AD3
ADC busy; start of a new conversion is
blocked.
Conversion completed; start of a new
conversion is blocked.
Intermediate status for a maximum of
one machine cycle before conversion is
completed (ADCI = 1, ADCS = 0).
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
14 REDUCED POWER MODES
14.2 Power-down mode
There are two software selectable modes of reduced
activity for further power reduction: Idle and Power-down.
Operation in Power-down mode freezes the oscillator.
The internal connections which link both Idle and
Power-down signals to the clock generation circuit are
shown in Fig.15.
14.1 Idle mode
Power-down mode is entered by setting the PD bit in the
Power Control Register (PCON.1, see Table 14).
The instruction that sets PD is the last executed prior to
going into the Power-down mode.
Idle mode operation permits the interrupt, serial ports,
timer blocks, PWM and ADC to continue to function while
the clock to the CPU is halted.
Idle mode is entered by setting the IDL bit in the Power
Control Register (PCON.0, see Table 14). The instruction
that sets IDL is the last instruction executed in the normal
operating mode before the Idle mode is activated
Once in the Power-down mode, the oscillator is stopped.
The contents of the on-chip RAM and the SFRs are
preserved. The port pins output the value held by their
respective SFRs. ALE and PSEN are held LOW.
Once in Idle mode, the CPU status is preserved along with
the Stack Pointer, Program Counter, Program Status
Word and Accumulator. The RAM and all other registers
maintain their data during Idle mode. The status of the
external pins during Idle mode is shown in Table 13.
In the Power-down mode, VDD may be reduced to
minimize circuit power consumption. The supply voltage
must not be reduced until the Power-down mode is
entered, and must be restored before the hardware reset
is applied which will free the oscillator. Reset should not be
released until the oscillator has restarted and stabilized.
The following functions remain active during the Idle
mode:
• Timer 0, Timer 1, Timer 2 and Timer 3
• UART, I2C-bus interface
• External interrupt
14.3 Wake-up from Power-down mode
When in Power-down mode the controller can be
woken-up with either the external interrupts INT2 to INT8,
or a reset operation. The wake-up operation has two basic
approaches as explained in Section 14.3.1; 14.3.2 and
illustrated in Fig.16.
• PWM0 (reset; output = HIGH)
• ADC.
These functions may generate an interrupt or reset; thus
ending the Idle mode.
14.3.1 WAKE-UP USING INT2 TO INT8
There are two ways to terminate the Idle mode:
If any of the interrupts INT2 to INT8 are enabled, the
device can be woken-up from the Power-down mode with
the external interrupts. To ensure that the oscillator is
stable before the controller restarts, the internal clock will
remain inactive for 1536 oscillator periods. This is
controlled by an on-chip delay counter.
1. Activation of any enabled interrupt will cause IDL
(PCON.0) to be cleared by hardware thus terminating
the Idle mode. The interrupt is serviced, and following
the RETI instruction, the next instruction to be
executed will be the one following the instruction that
put the device in the Idle mode. The flag bits GF0
(PCON.2) and GF1 (PCON.3) may be used to
determine whether the interrupt was received during
normal execution or during the Idle mode.
14.3.2 WAKE-UP USING RST
To wake-up the P8xCL580, the RST pin must be kept
HIGH for a minimum of 24 periods. The on-chip delay
counter is inactive. The user must ensure that the oscillator
is stable before any operation is attempted.
For example, the instruction that writes to PCON.0 can
also set or clear one or both flag bits. When the Idle
mode is terminated by an interrupt, the service routine
can examine the status of the flag bits.
2. The second way of terminating the Idle mode is with an
external hardware reset, or an internal reset caused by
an overflow of Timer T2. Since the oscillator is still
running, the hardware reset is required to be active for
two machine cycles (24 oscillator periods) to complete
the reset operation. Reset redefines all SFRs but does
not affect the on-chip RAM.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
If the data is a logic 1, the port pin is held HIGH during the
Power-down mode by the strong pull-up transistor ‘p1’;
see Fig.9(a).
14.4 Status of external pins
The status of the external pins during Idle and Power-down
mode is shown in Table 13. If the Power-down mode is
activated whilst accessing external Program Memory, the
port data that is held in the Special Function Register P2 is
restored to Port 2.
Table 13 Status of external pins during Idle and Power-down modes
MODE
Idle
MEMORY
internal
ALE
PSEN
PWM0
PORT 0 PORT 1 PORT 2 PORT 3 PORT 4
1
1
0
0
1
1
0
0
active
active
HIGH
HIGH
port data port data port data port data port data
floating port data address port data port data
port data port data port data port data port data
floating port data port data port data port data
external
internal
Power-down
external
14.5 Power Control Register (PCON)
Idle and Power-down modes are activated by software using this SFR. PCON is not bit addressable, the reset value of
PCON is 0XX00000B.
Table 14 Power Control Register (address 87H)
7
6
5
4
3
2
1
0
SMOD
−
−
WLE
GF1
GF0
PD
IDL
Table 15 Description of PCON bits
BIT
SYMBOL
DESCRIPTION
7
SMOD
Double Baud rate bit. When set to a logic 1 the baud rate is doubled when the serial
port SIO0 is being used in modes 1, 2 or 3.
6 and 5
4
−
Reserved.
WLE
Watchdog Load Enable. This flag must be set by software prior to loading the
Watchdog Timer (T3). It is cleared when T3 is loaded.
3 and 2
1
GF1 and GF0 General purpose flag bits.
PD
Power-down bit. Setting this bit activates the Power-down mode. This bit can only be
set if input EWN is HIGH. If a logic 1 is written to both PD and IDL at the same time, PD
takes precedence.
0
IDL
Idle mode bit. Setting this bit activates the Idle mode.
1997 Mar 14
26
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
XTAL2
XTAL1
OSCILLATOR
interrupts
serial ports
timer blocks
CLOCK
GENERATOR
CPU
P80CL580
P83CL580
PD
IDL
MGL102
Fig.15 Internal clock control in Idle and Power-down modes.
power-down
RST pin
external
interrupt
oscillator
MGD679
24 periods
delay counter
1536 periods
Fig.16 Wake-up operation.
1997 Mar 14
27
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
15 I2C-BUS SERIAL I/O
These functions are controlled by the Serial Control
Register S1CON. S1STA is the Status Register whose
contents may also be used as a vector to various service
routines. S1DAT is the Data Shift Register and S1ADR is
the Slave Address Register. Slave address recognition is
performed by on-chip hardware.
The serial port supports the twin line I2C-bus, which
consists of a serial data line (SDA) and a serial clock line
(SCL). These lines also function as the I/O port lines P1.7
and P1.6 respectively.
The system is unique because data transport, clock
generation, address recognition and bus control arbitration
are all controlled by hardware.
Figure 17 is the block diagram of the I2C-bus serial I/O.
The I2C-bus serial I/O has complete autonomy in byte
handling and operates in 4 modes:
• Master transmitter
• Master receiver
• Slave transmitter
• Slave receiver.
7
0
GC
SLAVE ADDRESS
S1ADR
7
0
SHIFT REGISTER
S1DAT
SDA
ARBITRATION SYNC LOGIC
SCL
BUS CLOCK GENERATOR
7
0
CONTROL REGISTER
STATUS REGISTER
S1CON
7
0
MLB199
S1STA
Fig.17 Block diagram of I2C-bus serial I/O.
1997 Mar 14
28
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
15.1 Serial Control Register (S1CON)
Table 16 Serial Control Register (SFR address D8H)
7
6
5
4
3
2
1
0
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
Table 17 Description of S1CON bits
BIT
SYMBOL
DESCRIPTION
7
CR2
This bit along with bits CR1 (S1CON.1) and CR0 (S1CON.0) determines the serial clock
frequency when SIO is in the Master mode. See Table 18.
6
5
4
ENS1
STA
ENABLE serial I/O. When ENS1 = 0, the serial I/O is disabled. SDA and SCL outputs
are in the high impedance state; P1.6 and P1.7 function as open-drain ports. When
ENS1 = 1, the serial I/O is enabled. Output port latches P1.6 and P1.7 must be set to
logic 1.
START flag. When this bit is set in Slave mode, the SIO hardware checks the status of
the I2C-bus and generates a START condition if the bus is free or after the bus becomes
free. If STA is set while the SIO is in Master mode, SIO will generate a repeated START
condition.
STO
STOP flag. With this bit set while in Master mode a STOP condition is generated. When
a STOP condition is detected on the I2C-bus, the SIO hardware clears the STO flag.
STO may also be set in Slave mode in order to recover from an error condition. In this
case no STOP condition is transmitted to the I2C-bus. However, the SIO hardware
behaves as if a STOP condition has been received and releases the SDA and SCL.
The SIO then switches to the not addressed slave receiver mode. The STOP flag is
cleared by the hardware.
3
SI
SIO interrupt flag. This flag is set, and an interrupt is generated, after any of the
following events occur:
• A start condition is generated in Master mode
• Own slave address has been received during AA = 1
• The general call address has been received while GC (S1ADR.0) = 1 and AA = 1
• A data byte has been received or transmitted in Master mode (even if arbitration is lost)
• A data byte has been received or transmitted as selected slave
• A Stop or Start condition is received as selected slave receiver or transmitter.
2
AA
Assert Acknowledge. When this bit is set, an acknowledge (low level to SDA) is
returned during the acknowledge clock pulse on the SCL line when:
• Own slave address is received
• General call address is received; GC (S1ADR.0) = 1
• A data byte is received while the device is programmed to be a Master Receiver
• A data byte is received while the device is a selected Slave Receiver.
When this bit is reset, no acknowledge is returned. Consequently, no interrupt is
requested when the own slave address or general call address is received.
1
0
CR1
CR0
These two bits along with the CR2 (S1CON.7) bit determine the serial clock frequency
when SIO is in the Master mode. See Table 18.
1997 Mar 14
29
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
Table 18 Selection of the serial clock frequency SCL in a Master mode of operation
BIT RATE(kHz) AT fosc
CR2
CR1
CR0
fosc DIVISOR
3.58 MHz
6 MHz
12 MHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
256
224
14.0
16.0
18.6
22.4
3.73
29.8
59.7
−
23.4
26.8
31.3
37.5
6.25
50.0
100.0
−
46.9
53.6
62.5
75.0
12.5
100.0
−
192
160
960
120
60
not allowed
−
15.2 Serial Status Register (S1STA)
S1STA is a read-only register.The contents of this register may be used as a vector to a service routine. This optimizes
the response time of the software and consequently that of the I2C-bus. The status codes for all possible modes of the
I2C-bus interface are given in Tables 21 to 25.
Table 19 Serial Status Register (address D9H)
7
6
5
4
3
2
1
0
SC4
SC3
SC2
SC1
SC0
0
0
0
Table 20 Description of S1STA bits
BIT
SYMBOL
DESCRIPTION
3 to 7
0 to 2
SC4 to SC0 5-bit status code.
−
These three bits are always zero.
Table 21 MST/TRX mode
S1STA VALUE
DESCRIPTION
08H
10H
18H
20H
28H
30H
38H
A START condition has been transmitted.
A repeated START condition has been transmitted.
SLA and W have been transmitted, ACK has been received.
SLA and W have been transmitted, ACK received.
DATA of S1DAT has been transmitted, ACK received.
DATA of S1DAT has been transmitted, ACK received.
Arbitration lost in SLA, R/W or DATA.
1997 Mar 14
30
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
Table 22 MST/REC mode
S1STA VALUE
DESCRIPTION
08H
10H
38H
40H
48H
50H
58H
A START condition has been transmitted.
A repeated START condition has been transmitted.
Arbitration lost while returning ACK.
SLA and R have been transmitted, ACK received.
SLA and R have been transmitted, ACK received.
DATA has been received, ACK returned.
DATA has been received, ACK returned.
Table 23 SLV/REC mode
S1STA VALUE
DESCRIPTION
Own SLA and W have been received, ACK returned.
60H
68H
70H
78H
80H
88H
90H
98H
A0H
Arbitration lost in SLA, R/W as MST. Own SLA and W have been received, ACK returned.
General CALL has been received, ACK returned.
Arbitration lost in SLA, R/W as MST. General CALL has been received.
Previously addressed with own SLA. DATA byte received, ACK returned.
Previously addressed with own SLA. DATA byte received, ACK returned.
Previously addressed with general CALL. DATA byte has been received, ACK has been returned.
Previously addressed with general CALL. DATA byte has been received, ACK has been returned.
A STOP condition or repeated START condition has been received while still addressed as SLV/REC
or SLV/TRX.
Table 24 SLV/TRX mode
S1STA VALUE
DESCRIPTION
A8H
B0H
B8H
C0H
C8H
Own SLA and R have been received, ACK returned.
Arbitration lost in SLA, R/W as MST. Own SLA and R have been received, ACK returned.
DATA byte has been transmitted, ACK received.
DATA byte has been transmitted, ACK received.
Last DATA byte has been transmitted (AA = 0), ACK received.
Table 25 Miscellaneous.
S1STA VALUE
DESCRIPTION
00H
F8H
Bus error during MST mode or selected SLV mode, due to an erroneous START or STOP condition.
No relevant state information available, SI = 0.
1997 Mar 14
31
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
Table 26 Symbols used in Tables 21 to 25
SYMBOL
DESCRIPTION
SLA
R
7-bit slave address
Read bit
W
Write bit
ACK
ACK
DATA
MST
SLV
TRX
REC
Acknowledgement (acknowledge bit is logic 0)
No acknowledgement (acknowledge bit is logic 1)
8-bit data byte to or from I2C-bus
Master
Slave
Transmitter
Receiver
15.3 Data Shift Register (S1DAT)
S1DAT contains the serial data to be transmitted or data which has just been received. The MSB (bit 7) is transmitted or
received first; i.e. data shifted from right to left.
Table 27 Data Shift Register (SFR address DAH)
7
6
5
4
3
2
1
0
S1DAT.7
S1DAT.6
S1DAT.5
S1DAT.4
S1DAT.3
S1DAT.2
S1DAT.1
S1DAT.0
15.4 Address Register (S1ADR)
This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as
a slave receiver/transmitter.
Table 28 Address Register (SFR address DBH)
7
6
5
4
3
2
1
0
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
GC
Table 29 Description of S1ADR bits
BIT
SYMBOL
SLA6 to SLA0 Own slave address.
DESCRIPTION
7 to 1
0
GC
This bit is used to determine whether the general call address is recognized. When
GC = 0, the general call address is not recognized; when GC = 1, the general call
address is recognized.
1997 Mar 14
32
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
16 STANDARD SERIAL INTERFACE SIO0: UART
16.1 Multiprocessor communications
This serial port is full duplex which means that it can
transmit and receive simultaneously. It is also
Modes 2 and 3 have a special provision for multiprocessor
communications. In these modes, 9 data bits are received.
The 9th bit goes into RB8. The following bit is the stop bit.
The port can be programmed such that when the stop bit
is received, the serial port interrupt will be activated, but
only if RB8 = 1. This feature is enabled by setting bit SM2
in S0CON. One use of this feature, in multiprocessor
systems, is as follows.
receive-buffered and can commence reception of a
second byte before a previously received byte has been
read from the register. (However, if the first byte has not
been read by the time the reception of the second byte is
complete, one of the bytes will be lost). The serial port
receive and transmit registers are both accessed via the
Special Function Register S0BUF. Writing to S0BUF loads
the transmit register and reading S0BUF accesses a
physically separate receive register.
When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an address
byte which identifies the target slave. An address byte
differs from a data byte in that the 9th bit is HIGH in an
address byte and LOW in a data byte. With SM2 = 1, no
slave will be interrupted by a data byte. An address byte,
however, will interrupt all slaves, so that each slave can
examine the received byte and see if it is being addressed.
The addressed slave will clear its SM2 bit and prepare to
receive the data bytes that will be sent. The slaves that
were not being addressed leave their SM2 bits set and go
on about their business, ignoring the coming data bytes.
The serial port can operate in 4 modes:
Mode 0 Serial data enters and exits through RXD.
TXD outputs the shift clock. Eight bits are
transmitted/received (LSB first). The baud rate is
fixed at 1⁄12 × fosc. See Figs 19 and 20.
Mode 1 10 bits are transmitted (through TXD) or received
(through RXD): a start bit (logic 0), 8 data bits
(LSB first), and a stop bit (logic 1). On receive,
the stop bit goes into RB8 in Special Function
Register S0CON. The baud rate is variable.
See Figs 21 and 22.
SM2 has no effect in Mode 0, and in Mode 1 can be used
to check the validity of the stop bit. In a Mode 1 reception,
if SM2 = 1, the receive interrupt will not be activated unless
a valid stop bit is received.
Mode 2 11 bits are transmitted (through TXD) or received
(through RXD): start bit (logic 0), 8 data bits (LSB
first), a programmable 9th data bit, and a stop bit
(logic 1). On transmit, the 9th data bit (TB8 in
S0CON) can be assigned the value of a logic 0 or
logic 1. Or, for example, the parity bit (P, in the
PSW) could be moved into TB8. On receive, the
9th data bit goes into RB8 in S0CON, while the
stop bit is ignored. The baud rate is
programmable to either 1⁄32 or 1⁄64 × fosc
.
See Figs 23 and 24.
Mode 3 11 bits are transmitted (through TXD) or received
(through RXD): a start bit (logic 0), 8 data bits
(LSB first), a programmable 9th data bit and a
stop bit (logic 1). In fact, Mode 3 is the same as
Mode 2 in all respects except baud rate.
The baud rate in Mode 3 is variable.
See Figs 25 and 26.
In all four modes, transmission is initiated by any
instruction that uses S0BUF as a destination register.
Reception is initiated in Mode 0 by the condition RI = 0 and
REN = 1. Reception is initiated in the other modes by the
incoming start bit if REN = 1.
1997 Mar 14
33
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
16.2 Serial Port Control and Status Register (S0CON)
The Serial Port Control and Status Register is the Special Function Register S0CON. The register contains not only the
mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits
(TI and RI).
Table 30 Serial Port Control Register (address 98H)
7
6
5
4
3
2
1
0
SMO
SM1
SM2
REN
TB8
RB8
TI
RI
Table 31 Description of S0CON bits
BIT
SYMBOL
DESCRIPTION
These bits are used to select the serial port mode; see Table 32.
7
6
5
SM0
SM1
SM2
Enables the multiprocessor communication feature in Modes 2 and 3. In these modes,
if SM2 = 1, then RI will not be activated if the received 9th data bit (RB8) is a logic 0.
In Mode 1, if SM2 = 1, then RI will not be activated unless a valid stop bit was received.
In Mode 0, SM2 should be a logic 0.
4
3
2
1
REN
TB8
RB8
TI
Enables serial reception and is set by software to enable reception, and cleared by
software to disable reception.
Is the 9th data bit that will be transmitted in Modes 2 and 3. Set or cleared by software as
desired.
In Modes 2 and 3, is the 9th data bit received. In Mode 1, if SM2 = 0 then RB8 is the stop
bit that was received. In Mode 0, RB8 is not used.
The transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or
at the beginning of the stop bit time in the other modes, in any serial transmission. Must
be cleared by software.
0
RI
The receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or
halfway through the stop bit time in the other modes, in any serial transmission (except
see SM2). Must be cleared by software.
Table 32 Selection of the serial port modes
SMO
SM1
MODE
Mode 0
Mode 1
Mode 2
Mode 3
DESCRIPTION
Shift register
8-bit UART
BAUD RATE
1
0
0
1
1
0
1
0
1
⁄12 × fosc
variable
32 or 1⁄64 × fosc
variable
1
9-bit UART
⁄
9-bit UART
1997 Mar 14
34
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
Timer 1 overflow rate and the value of the SMOD bit as
follows:
16.3 Baud rates
The baud rate in Mode 0 is fixed and may be calculated as:
fosc
2SMOD
Baud Rate =
× Timer 1 Overflow Rate.
----------------
Baud Rate =
--------
12
32
The Timer 1 interrupt should be disabled in this
application. The Timer itself can be configured for either
‘timer’ or ‘counter’ operation in any of its 3 running modes.
In most typical applications, it is configured for ‘timer’
operation, in the Auto-reload mode (high nibble of
TMOD = 0010B). In this case the baud rate is given by the
formula:
The baud rate in Mode 2 depends on the value of the
SMOD bit in Special Function Register PCON and may be
calculated as:
2SMOD
64
Baud Rate =
× f
osc
----------------
• If SMOD = 0 (value on reset), the baud rate is 1⁄64 × fosc
• If SMOD = 1, the baud rate is 1⁄32 × fosc
2SMOD
f osc
---------------- --------------------------------------------------------
32 {12 × (256 – TH1) }
Baud Rate =
×
The baud rates in Modes 1 and 3 are determined by the
Timer 1 or Timer 2 overflow rate.
By configuring Timer 1 to run as a 16-bit timer (high nibble
of TMOD = 0001B), and using the Timer 1 interrupt to do
a 16-bit software reload, very low baud rates can be
achieved. Table 33 lists commonly used baud rates and
how they can be obtained from Timer 1.
16.3.1 USING TIMER 1 TO GENERATE BAUD RATES
When Timer 1 is used as the Baud Rate Generator, the
baud rates in Modes 1 and 3 are determined by the
Table 33 Commonly used baud rates generated by Timer 1
BAUD RATE(kb/s)
f
osc (MHz)
12.000
12.000
12.000
11.059
11.059
11.059
11.059
11.059
11.986
6.000
SMOD
C/T
X
X
0
TIMER 1 MODE
X
RELOAD VALUE
1000.0(1)
375.0(3)
62.5(4)
19.2
X(2)
1
X
X
X
1
Mode 2
Mode 2
Mode 2
Mode 2
Mode 2
Mode 2
Mode 2
Mode 2
Mode 1
FFH
FDH
FDH
FAH
F4H
E8H
1DH
72H
FEEBH
1
0
9.6
0
0
4.8
0
0
2.4
0
0
1.2
0
0
137.5
110.0
110.0
0
0
0
0
12.000
0
0
Notes
1. Maximum in Mode 0.
2. X = don’t care.
3. Maximum in Mode 2.
4. Maximum in Modes 1 and 3.
1997 Mar 14
35
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
16.3.2 USING TIMER 2 TO GENERATE BAUD RATES
Where (RCAP2H; RCAP2L) is the content of registers
RCAP2H and RCAP2L taken as a 16-bit unsigned integer.
Timer 2 is selected as a Baud Rate Generator by setting
the RTCLK bit in T2CON. The Baud Rate Generator mode
is similar to the Auto-reload mode, in that a roll-over in TH2
causes Timer 2 registers to be reloaded with the 16-bit
value held in the registers RCAP2H and RCAP2L, which
are preset by software. Baud rates in Modes 1 and 3 are
determined by Timer 2's overflow rate as specified below.
The Baud Rate Generator mode for Timer 2 is shown in
Fig.18. This figure is only valid if RTCLK = 1. At roll-over
TH2 does not set the TF2 bit in T2CON and therefore, will
not generate an interrupt. Consequently, the Timer 2
interrupt does not need to be disabled when in the Baud
Rate Generator mode. If EXEN2 is set, a HIGH-to-LOW
transition on T2EX will set the EXF2 bit, also in T2CON,
but will not cause a reload from (RCAP2H; RCAP2L) to
(TH2, TL2). Therefore, in this mode T2EX may be used as
an additional external interrupt.
Timer 2 Overflow Rate
Baud Rate =
----------------------------------------------------------
16
The Timer 2 can be configured for either ‘timer’ or ‘counter’
operation. In the most typical applications, it is configured
for ‘timer’ operation (C/T2 = 0). ‘Timer’ operation is slightly
different for Timer 2 when it is being used as a Baud Rate
Generator. Normally, as a timer it would increment every
machine cycle at a frequency of 1⁄12 × fosc. However, as a
Baud Rate Generator it increments every state time at a
frequency of 1⁄2 × fosc. In this case the baud rate in
Modes 1 and 3 is determined as:
When Timer 2 is operating as a timer (TR2 = 1), in the
Baud Rate Generator mode, registers TH2 and TL2 should
not be accessed (read or write). Under these conditions
the timer is being incremented every state time and
therefore the results of a read or write may not be
accurate. The registers RCAP2H and RCAP2L however,
may be read but not written to. A write might overlap a
reload and cause write and/or reload errors. If a write
operation is required, Timer 2 or RCAP2H/RCAP2L
should first be turned off by clearing the TR2 bit.
fosc
Baud Rate =
----------------------------------------------------------------------------------------------------
32 × {65536 – (RCAP2H; RCAP2L) }
TIMER 1
overflow
2
(note: divided by 2
not by 12)
0
1
OSC
2
SMOD
RTCLK
C/T2 = 0
1
0
TL2
(8 BITS)
TH2
(8 BITS)
C/T2 = 1
control
TR2
T2 PIN
16
CLK
RELOAD
UART receive/
transmit clock
RCAP2L
EXF2
RCAP2H
transition
detector
TIMER 2 interrupt
(additional external interrupt)
T2EX PIN
MGD622
control
EXEN2
Fig.18 Timer 2 in Baud Rate Generator mode.
1997 Mar 14
36
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
INTERNAL BUS
write to
SBUF
RXD
P3.0 ALT
output
S
D
Q
S0 BUFFER
function
CL
SHIFT
ZERO DETECTOR
START
SHIFT
TX CONTROL
S6
TX CLOCK
SEND
T1
serial port
interrupt
TXD
P3.1 ALT
output
function
SHIFT
CLOCK
R1
RX CLOCK
START
RECEIVE
SHIFT
REN
RI
RX CONTROL
1
1
1 1 1 1 1
0
RXD
P3.0 ALT
input
INPUT SHIFT
REGISTER
function
SHIFT
LOAD
SBUF
S0 BUFFER
READ
SBUF
INTERNAL BUS
MGC752
Fig.19 Serial port Mode 0.
37
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
LM5A67
a n d b o o k g e w i d t h
1997 Mar 14
38
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
INTERNAL BUS
TB8
write to
SBUF
Timer 1
overflow
Timer 2
overflow
S
D
TXD
Q
S0 BUFFER
CL
2
0
1
SHIFT
0
1
ZERO DETECTOR
SMOD
RTCLK
SHIFT
START
DATA
TX CONTROL
16
TX CLOCK
SEND
T1
serial port
interrupt
16
sample
RX CLOCK
R1
LOAD
SBUF
HIGH-TO-LOW
TRANSITION
DETECTOR
START
RX CONTROL
SHIFT
INPUT SHIFT
REGISTER
(9-BITS)
BIT
DETECTOR
RXD
SHIFT
LOAD
SBUF
S0 BUFFER
READ
SBUF
INTERNAL BUS
MGC755
Fig.21 Serial port Mode 1.
39
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
LM5A69
a n d b o o k , f u l l p a g e w i d t h
1997 Mar 14
40
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
INTERNAL BUS
TB8
write to
SBUF
phase 2 clock
(f
/ 2)
osc
S
D
TXD
Q
S0 BUFFER
CL
2
SHIFT
0
1
ZERO DETECTOR
CSMOD at
PCON.7
STOP BIT
START
SHIFT
DATA
TX CONTROL
16
TX CLOCK
SEND
T1
serial port
interrupt
16
sample
RX CLOCK
R1
LOAD
SBUF
HIGH-TO-LOW
TRANSITION
DETECTOR
RX CONTROL
START
SHIFT
INPUT SHIFT
REGISTER
(9-BITS)
BIT
DETECTOR
SHIFT
RXD
LOAD
SBUF
S0 BUFFER
READ
SBUF
INTERNAL BUS
MGC754
Fig.23 Serial port Mode 2.
41
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
LM5A71
a n d b o o k g e w i d t h
1997 Mar 14
42
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
h
INTERNAL BUS
TB8
write to
SBUF
Timer 1
overflow
Timer 2
overflow
S
D
TXD
Q
S0 BUFFER
CL
2
0
SHIFT
1
ZERO DETECTOR
0
1
SMOD
RTCLK
SHIFT
START
DATA
TX CONTROL
16
TX CLOCK
SEND
T1
serial port
interrupt
16
sample
RX CLOCK
R1
LOAD
SBUF
HIGH-TO-LOW
TRANSITION
DETECTOR
RX CONTROL
START
SHIFT
INPUT SHIFT
REGISTER
(9-BITS)
BIT
DETECTOR
RXD
SHIFT
LOAD
SBUF
S0 BUFFER
READ
SBUF
INTERNAL BUS
MGC753
Fig.25 Serial port Mode 3.
43
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
LM5A73
a n d b o o k , f u l l p a g e w i d t h
1997 Mar 14
44
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
17 INTERRUPT SYSTEM
17.2 Interrupt priority
External events and the real-time-driven on-chip
peripherals require service by the CPU at unpredictable
times. To tie the asynchronous activities of these functions
to normal program execution a multiple-source,
two-priority-level, nested interrupt system is provided.
The system is shown in Fig.27. The P8xCL580
acknowledges interrupt requests from fifteen sources as
follows:
Each interrupt source can be set to either a high priority or
to a low priority. If a low priority interrupt is received
simultaneously with a high priority interrupt, the high
priority interrupt will be dealt with first.
If interrupts of the same priority are requested
simultaneously, the processor will branch to the interrupt
polled first, according to the sequence shown in Table 34
and in Fig.27. The ‘vector address’ is the ROM location
where the appropriate interrupt service routine starts.
• INT0 to INT8
• Timer 0, Timer 1 and Timer 2
• I2C-bus serial I/O
• UART
Table 34 Interrupt vector polling sequence
VECTOR
ADDRESS (HEX)
SYMBOL
SOURCE
External 0
• ADC.
X0 (first)
0003
002B
0053
000B
0033
005B
0013
003B
0063
001B
0043
006B
0023
004B
0073
Each interrupt vectors to a separate location in Program
Memory for its service routine. Each source can be
individually enabled or disabled by corresponding bits in
the Interrupt Enable Registers (IEN0 and IEN1).
The priority level is selected via the Interrupt Priority
Registers (IP0 and IP1). All enabled sources can be
globally disabled or enabled. Figure 27 shows the interrupt
system.
S1
X5
I2C port
External 5
Timer 0
T0
T2
Timer 2
X6
External 6
External 1
External 2
External 7
Timer 1
X1
X2
17.1 External interrupts INT2 to INT8
X7
Port 1 lines serve an alternative purpose as seven
additional interrupts INT2 to INT8. When enabled, each of
these lines may wake-up the device from the Power-down
mode. Using the Interrupt Polarity Register (IX1), each pin
may be initialized to be either active HIGH or active LOW.
IRQ1 is the Interrupt Request Flag Register. If the interrupt
is enabled, each flag will be set on an interrupt request but
must be cleared by software, i.e. via the interrupt software
or when the interrupt is disabled.
T1
X3
External 3
External 8
UART
X8
SO
X4
External 4
ADC
ADC (last)
A low priority interrupt routine can only be interrupted by a
high priority interrupt. A high priority interrupt routine
cannot be interrupted.
Port 1 interrupts are level sensitive. A Port 1 interrupt will
be recognized when a level (HIGH or LOW depending on
the Interrupt Polarity Register) on P1.n is held active for at
least one machine cycle. The interrupt request is not
serviced until the next machine cycle. Figure 28 shows the
external interrupt system.
1997 Mar 14
45
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
INTERRUPT
SOURCES
IEN0/1
IP0/1
PRIORITY
REGISTERS
HIGH
LOW
X0
S1
X5
T0
T2
X6
X1
X2
X7
T1
X3
X8
SO
X4
ADC
GLOBAL
ENABLE
MGD623
Fig.27 Interrupt system.
46
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
IX1
IRQ1
IEN1
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
X8
X7
X6
X5
X4
X3
X2
P1.0
MGD626
WAKE-UP
Fig.28 External interrupt configuration.
17.3 Interrupt registers
The registers used in the interrupt system are listed in Table 35. Tables 36 to 47 describe the contents of these registers.
Table 35 Special Function Registers related to the interrupt system
ADDRESS
REGISTER
DESCRIPTION
A8H
E8H
B8H
F8H
E9H
C0H
IEN0
IEN1
IP0
Interrupt Enable Register
Interrupt Enable Register (INT2 to INT8)
Interrupt Priority Register
IP1
Interrupt Priority Register (INT2 to INT8, ADC)
Interrupt Polarity Register
IX1
IRQ1
Interrupt Request Flag Register
1997 Mar 14
47
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
17.3.1 INTERRUPT ENABLE REGISTER (IEN0)
Bit values: 0 = interrupt disabled; 1 = interrupt enabled.
Table 36 Interrupt Enable Register (SFR address A8H)
7
6
5
4
3
2
1
0
EA
ET2
ES1
ES0
ET1
EX1
ET0
EX0
Table 37 Description of IEN0 bits
BIT
SYMBOL
DESCRIPTION
7
EA
General enable/disable control. If EA = 0, no interrupt is enabled. If EA = 1, any
individually enabled interrupt will be accepted.
6
5
4
3
2
1
0
ET2
ES1
ES0
ET1
EX1
ET0
EX0
enable T2 interrupt
enable I2C interrupt
enable UART SIO interrupt
enable Timer 1 interrupt (T1)
enable external interrupt 1
enable Timer 0 interrupt (T0)
enable external interrupt 0
17.3.2 INTERRUPT ENABLE REGISTER (IEN1)
Bit values: 0 = interrupt disabled; 1 = interrupt enabled.
Table 38 Interrupt Enable Register (SFR address E8H)
7
6
5
4
3
2
1
0
EAD
EX8
EX7
EX6
EX5
EX4
EX3
EX2
Table 39 Description of IEN1 bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
EAD
EX8
EX7
EX7
EX5
EX4
EX3
EX2
Enable ADC interrupt.
enable external interrupt 8
enable external interrupt 7
enable external interrupt 6
enable external interrupt 5
enable external interrupt 4
enable external interrupt 3
enable external interrupt 2
1997 Mar 14
48
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
17.3.3 INTERRUPT PRIORITY REGISTER (IP0)
Bit values: 0 = low priority; 1 = high priority.
Table 40 Interrupt Priority Register (SFR address B8H)
7
6
5
4
3
2
1
0
−
PT2
PS1
PS0
PT1
PX1
PT0
PX0
Table 41 Description of IP0 bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
−
reserved
PT2
PS1
PS0
PT1
PX1
PT0
PX0
Timer 2 interrupt priority level
I2C interrupt priority level
UART SIO interrupt priority level
Timer 1 interrupt priority level
external interrupt 1 priority level
Timer 0 interrupt priority level
external interrupt 0 priority level
17.3.4 INTERRUPT PRIORITY REGISTER (IP1)
Bit values: 0 = low priority; 1 = high priority.
Table 42 Interrupt Priority Register (SFR address F8H)
7
6
5
4
3
2
1
0
PADC
PX8
PX7
PX6
PX5
PX4
PX3
PX2
Table 43 Description of IP1 bits
BIT
7
SYMBOL
PADC
PX8
DESCRIPTION
ADC interrupt priority level
6
external interrupt 8 priority level
external interrupt 7 priority level
external interrupt 6 priority level
external interrupt 5 priority level
external interrupt 4 priority level
external interrupt 3 priority level
external interrupt 2 priority level
5
PX7
4
PX6
3
PX5
2
PX4
1
PX3
0
PX2
1997 Mar 14
49
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
17.3.5 INTERRUPT POLARITY REGISTER (IX1)
Writing either a logic 1 or logic 0 to any Interrupt Polarity Register bit sets the polarity level of the corresponding external
interrupt to an active HIGH or active LOW respectively.
Table 44 Interrupt Polarity Register (SFR address E9H)
7
6
5
4
3
2
1
0
−
IL8
IL7
IL6
IL5
IL4
IL3
IL2
Table 45 Description of IX1 bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
−
reserved
IL8
IL7
IL6
IL5
IL4
IL3
IL2
external interrupt 8 polarity level
external interrupt 7 polarity level
external interrupt 6 polarity level
external interrupt 5 polarity level
external interrupt 4 polarity level
external interrupt 3 polarity level
external interrupt 2 polarity level
17.3.6 INTERRUPT REQUEST FLAG REGISTER (IRQ1)
Table 46 Interrupt Request Flag Register (SFR address C0H)
7
6
5
4
3
2
1
0
−
IQ8
IQ7
IQ6
IQ5
IQ4
IQ3
IQ2
Table 47 Description of IRQ1 bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
−
reserved
IQ8
IQ7
IQ6
IQ5
IQ4
IQ3
IQ2
external interrupt 8 request flag
external interrupt 7 request flag
external interrupt 6 request flag
external interrupt 5 request flag
external interrupt 4 request flag
external interrupt 3 request flag
external interrupt 2 request flag
1997 Mar 14
50
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
To drive the device with an external clock source, apply the
external clock signal to XTAL1, and leave XTAL2 to float,
as shown in Fig.29(f). There are no requirements on the
duty cycle of the external clock, since the input to the
internal clocking circuitry is buffered by a flip-flop.
18 OSCILLATOR CIRCUITRY
The on-chip oscillator circuitry of the P8xCL580 is a
single-stage inverting amplifier biased by an internal
feedback resistor. The oscillator circuit is shown in Fig.30.
For operation as a standard quartz oscillator, no external
components are needed, except for the 32 kHz option.
When using external capacitors, ceramic resonators, coils
and RC networks to drive the oscillator, five different
configurations are supported (see Table 48 and Fig.29).
Various oscillator options are provided for optimum
on-chip oscillator performance; these are specified in
Table 48 and shown in Fig.29. The required option should
be stated when ordering.
In the Power-down mode the oscillator is stopped and
XTAL1 is pulled HIGH. The oscillator invertor is switched
off to ensure no current will flow regardless of the voltage
at XTAL1, for configurations (a), (b), (c), (d), (e) and (g) of
Fig.29.
Table 48 Oscillator options
OPTION
APPLICATION
Oscillator 1
For 32 kHz clock applications with external trimmer for frequency adjustment. A 4.7 MΩ bias resistor
is needed for use in parallel with the crystal; see Fig.29(c).
Oscillator 2
Oscillator 3
Oscillator 4
RC oscillator
Low-power, low-frequency operations using LC components; see Fig.29(e).
Medium frequency range applications.
High frequency range applications.
RC oscillator configuration; see Figs 29(g) and 31.
QUARTZ OSCILLATOR
WITH EXTERNAL
CAPACITORS
STANDARD
QUARTZ
OSCILLATOR
h
32 kHz
OSCILLATOR
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
(a)
(b)
(c)
CERAMIC
RESONATOR
LC - OSCILLATOR
EXTERNAL CLOCK
RC - OSCILLATOR
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
n.c.
XTAL1
n.c.
XTAL2
V
DD
(d)
(e)
(f)
(g)
MLA577
Fig.29 Oscillator configurations.
51
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
V
DD
to internal
timing circuits
P80CL580
P83CL580
V
V
PD
DD
DD
C1
C2
R
i
i
bias
MGC756
XTAL1
XTAL2
Fig.30 Standard oscillator.
MLA579
600
handbook, halfpage
f
osc
(kHz)
400
200
0
0
2
4
6
RC (µs)
RC oscillator frequency is externally adjustable; 100 kHz ≤ fosc ≤ 500 kHz.
Fig.31 RC oscillator; frequency as a function of RC.
52
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
Table 49 Oscillator type selection guide
C1 EXT. (pF)
C2 EXT. (pF)
FREQUENCY
(MHz)
OPTION
(see Table 48)
RESONATOR MAX.
SERIES RESISTANCE
RESONATOR
MIN.
MAX.
MIN.
MAX.
Quartz
0.032
1.0
Oscillator 1
Oscillator 2
Oscillator 3
Oscillator 4
0
0
0
5
0
15
30
15
20
10
15
10
15
50
50
40
40
20
15
40
90
15 kΩ; note 1
600 Ω
100 Ω
75 Ω
30
15
20
10
15
10
15
50
50
40
40
20
15
40
90
3.58
4.0
0
0
0
0
6.0
0
0
60 Ω
10.0
12.0
16.0
0.455
1.0
0
0
60 Ω
0
0
40Ω
0
0
20 Ω
PXE
40
15
0
40
15
0
10 Ω
100 Ω
10 Ω
3.58
4.0
Oscillator 2
0
0
10 Ω
6.0
0
0
5 Ω
10.0
12.0
Oscillator 3
Oscillator 4
Oscillator 2
0
0
6 Ω
10
20
10
20
6 Ω
LC
10 µH = 1 Ω
100 µH = 5 Ω
1 mH = 75 Ω
Note
1. 32 kHz quartz crystals with a series resistance >15 kΩ will reduce the guaranteed supply voltage range to
2.5 to 3.5 V.
1997 Mar 14
53
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
R
f
XTAL1
XTAL2
g
C1
V
C2
i
R
m
1
i
2
MLA578
Fig.32 Oscillator equivalent circuit diagram.
Table 50 Oscillator equivalent circuit parameters
The equivalent circuit data of the internal oscillator compares with that of matched crystals.
SYMBOL
gm
PARAMETER
OPTION
CONDITION
MIN.
TYP.
15
MAX.
UNIT
µS
transconductance
Oscillator 1; 32 kHz
Oscillator 2
Tamb = +25 °C;
VDD = 4.5 V
−
−
200
600
1 500
4000
3.0
1000
4000
µS
µS
Oscillator 3
400
Oscillator 4
1000
10000 µS
C1i
C2i
R2
input capacitance
output capacitance
output resistance
Oscillator 1; 32 kHz
Oscillator 2
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
pF
pF
pF
pF
pF
pF
pF
pF
kΩ
kΩ
kΩ
kΩ
8.0
Oscillator 3
8.0
Oscillator 4
8.0
Oscillator 1; 32 kHz
Oscillator 2
23
8.0
Oscillator 3
8.0
Oscillator 4
8.0
Oscillator 1; 32 kHz
Oscillator 2
3800
65
Oscillator 3
18
Oscillator 4
5.0
1997 Mar 14
54
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
19 RESET
19.2 Power-on-reset
To initialize the P8xCL580 a reset is performed by either of
three methods:
The device contains on-chip circuitry which switches the
port pins to the customer defined logic level as soon as
V
DD exceeds 1.3 V; if the mask option ‘ON’ has been
• Applying an external signal to the RST pin
• Via Power-on-reset circuitry
• Watchdog Timer.
chosen. As soon as the minimum supply voltage is
reached, the oscillator will start up. However, to ensure
that the oscillator is stable before the controller starts, the
clock signals are gated away from the CPU for a further
1536 oscillator periods. During that time the CPU is held in
a reset state. A hysteresis of approximately 50 mV at a
typical power-on switching level of 1.3 V will ensure
correct operation (see Fig.35).
A reset leaves the internal registers as shown in
Chapter 20. The reset state of the port pins is
mask-programmable and can be defined by the user.
19.1 External reset using the RST pin
The on-chip Power-on reset circuitry can also be switched
off via the mask option ‘OFF’. This option reduces the
Power-down current to typically 800 nA and can be
chosen if external reset circuitry is used. For applications
not requiring the internal reset, option ‘OFF’ should be
chosen.
The reset input for the P8xCL580 is RST. A Schmitt trigger
is used at the input for noise rejection. The output of the
Schmitt trigger is sampled by the reset circuitry every
machine cycle. A reset is accomplished by holding the
RST pin HIGH for at least two machine cycles
(24 oscillator periods) while the oscillator is running.
The CPU responds by executing an internal reset. Port
pins adopt their reset state immediately after the RST goes
HIGH. During reset, ALE and PSEN are held HIGH.
An automatic reset can be obtained by connecting the RST
pin to VDD via a 10 µF capacitor. At power-on, the voltage
on the RST pin is equal to VDD minus the capacitor voltage,
and decreases from VDD as the capacitor charges through
the internal resistor (RRST) to ground. The larger the
capacitor, the more slowly VRST decreases. VRST must
remain above the lower threshold of the Schmitt trigger
long enough to effect a complete reset. The time required
is the oscillator start-up time, plus 2 machine cycles.
The Power-on-reset circuitry is shown in Fig.34.
The external reset is asynchronous to the internal clock.
The RST pin is sampled during state 5, phase 2 of every
machine cycle. After a HIGH is detected at the RST pin, an
internal reset is repeated until RST goes LOW. The reset
circuitry is also affected by the Watchdog timer; see
Section 11.4. The internal RAM is not affected by reset.
When VDD is turned on, the RAM contents are
indeterminate.
V
handbook, halfpage
V
DD
DD
handbook, halfpage
T3 overflow
P
10 µF
V
P80CL580
P83CL580
DD
RST
RESET
CIRCUITRY
RST
R
RST
SCHMITT
TRIGGER
R
RST
POR
MGC757
MGC760
Fig.33 Reset configuration.
Fig.34 Recommended Power-on-reset circuitry.
1997 Mar 14
55
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
switching level
POR
SUPPLY
hysteresis
VOLTAGE
POWER-ON-RESET
(INTERNAL)
OSCILLATOR
CPU RUNNING
MLA581
Start-up 1536 oscillator
time
periods delay
Fig.35 Power-on-reset switching level.
1997 Mar 14
56
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
20 SPECIAL FUNCTION REGISTERS OVERVIEW
The P8xCL580 has 40 SFRs available to the user.
ADDRESS
(HEX)
RESET VALUE
(B)
NAME
FUNCTION
FF
FE
FC
F8
T3
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
11111000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
11111111
X0000000
Watchdog Timer
PWMP
PWM0
IP1
Prescaler Frequency Control Register
Pulse Width Register 0
Interrupt Priority Register (INT2 to INT8, ADC)
B Register
F0
B(1)
E9
E8
E0
DB
DA
D9
D8
D0
CD
CC
CB
CA
C8
C5
C4
C1
C0
IX1
Interrupt Polarity Register
Interrupt Enable Register 1
Accumulator
I2C-bus Slave Address Register
I2C-bus Data Shift Register
I2C-bus Serial Status Register
I2C-bus Serial Control Register
Program Status Word
IEN1(1)
ACC(1)
S1ADR
S1DAT
S1STA
S1CON(1)
PSW(1)
TH2
Timer 2 High byte
TL2
Timer 2 Low byte
RCAP2H
RCAP2L
T2CON(1)
ADCH
ADCON
P4
Timer 2 Reload/Capture Register High byte
Timer 2 Reload/Capture Register Low byte
Timer/Counter 2 Control Register
ADC Result Register
ADC Control Register
(2)
XXXXXXXX
Digital I/O Port Register 4
Interrupt Request Flag Register
IRQ1(1)
00000000
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
ADDRESS
(HEX)
RESET VALUE
(B)
NAME
IP0(1)
P3(1)
IEN0(1)
P2(1)
FUNCTION
B8
B0
A8
A0
99
98
90
8D
8C
8B
8A
89
88
87
83
82
81
80
X0000000
Interrupt Priority Register 0
Digital I/O Port Register 3
Interrupt Enable Register
Digital I/O Port Register 2
Serial Data Buffer Register 0
Serial Port Control Register 0
Digital I/O Port Register 1
Timer 1 High byte
(2)
XXXXXXXX
00000000
(2)
XXXXXXXX
S0BUF
S0CON(1)
P1(1)
XXXXXXXX
00000000
(2)
XXXXXXXX
TH1
00000000
00000000
00000000
00000000
00000000
00000000
0XX00000
00000000
00000000
00000111
TH0
Timer 0 High byte
TL1
Timer 1 Low byte
TL0
Timer 0 Low byte
TMOD
TCON(1)
PCON
DPH
Timer 0 and 1 Mode Control Register
Timer 0 and 1 Control/External Interrupt Control Register
Power Control Register
Data Pointer High byte
DPL
Data Pointer Low byte
SP
P0(1)
Stack Pointer
(2)
XXXXXXXX
Digital I/O Port Register 0
Notes
1. Bit addressable register.
2. Port reset state determined by the customer.
1997 Mar 14
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
21 INSTRUCTION SET
The P8xCL580 uses a powerful instruction set which permits the expansion of on-chip CPU peripherals and optimizes
byte efficiency and execution speed. Assigned opcodes add new high-power operation and permit new addressing
modes. The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 12 MHz
oscillator, 64 instructions execute in 1 µs and 45 instructions execute in 2 µs. Multiply and divide instructions execute in
4 µs.
For the description of the Data Addressing modes and Hexadecimal opcode cross-reference see Table 55.
Table 51 Instruction set description: Arithmetic operations
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES CYCLES
Arithmetic operations
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
INC
A,Rr
Add register to A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
2*
A,direct
A,@Ri
A,#data
A,Rr
Add direct byte to A
25
Add indirect RAM to A
26, 27
24
Add immediate data to A
Add register to A with carry flag
Add direct byte to A with carry flag
Add indirect RAM to A with carry flag
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment A
3*
A,direct
A,@Ri
A,#data
A,Rr
35
36, 37
34
9*
A,direct
A,@Ri
A,#data
A
95
96, 97
94
04
INC
Rr
Increment register
0*
INC
direct
@Ri
Increment direct byte
05
INC
Increment indirect RAM
Decrement A
06, 07
14
DEC
DEC
DEC
DEC
INC
A
Rr
Decrement register
1*
direct
@Ri
Decrement direct byte
15
Decrement indirect RAM
Increment data pointer
16, 17
A3
DPTR
AB
MUL
DIV
Multiply A and B
A4
AB
Divide A by B
84
DA
A
Decimal adjust A
D4
1997 Mar 14
59
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
Table 52 Instruction set description: Logic operations
OPCODE
BYTES CYCLES
(HEX)
MNEMONIC
DESCRIPTION
Logic operations
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
A,Rr
AND register to A
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
5*
A,direct
A,@Ri
A,#data
direct,A
AND direct byte to A
AND indirect RAM to A
AND immediate data to A
AND A to direct byte
55
56, 57
54
52
direct,#data AND immediate data to direct byte
53
A,Rr
OR register to A
4*
A,direct
A,@Ri
A,#data
direct,A
OR direct byte to A
OR indirect RAM to A
OR immediate data to A
OR A to direct byte
45
46, 47
44
42
direct,#data OR immediate data to direct byte
43
A,Rr
Exclusive-OR register to A
6*
A,direct
A,@Ri
A,#data
direct,A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate data to A
Exclusive-OR A to direct byte
65
66, 67
64
62
direct,#data Exclusive-OR immediate data to direct byte
63
A
A
A
A
A
A
A
Clear A
E4
F4
Complement A
Rotate A left
23
RLC
RR
Rotate A left through the carry flag
Rotate A right
33
03
RRC
SWAP
Rotate A right through the carry flag
Swap nibbles within A
13
C4
1997 Mar 14
60
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
Table 53 Instruction set description: Data transfer
OPCODE
BYTES CYCLES
(HEX)
MNEMONIC
DESCRIPTION
Data transfer
A,Rr
A,direct (note 1) Move direct byte to A
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVC
MOVC
MOVX
MOVX
MOVX
MOVX
PUSH
POP
Move register to A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
E*
E5
A,@Ri
Move indirect RAM to A
E6, E7
74
A,#data
Move immediate data to A
Move A to register
Rr,A
F*
Rr,direct
Rr,#data
direct,A
Move direct byte to register
Move immediate data to register
Move A to direct byte
A*
7*
F5
direct,Rr
direct,direct
direct,@Ri
direct,#data
@Ri,A
Move register to direct byte
Move direct byte to direct
8*
85
Move indirect RAM to direct byte
Move immediate data to direct byte
Move A to indirect RAM
86, 87
75
F6, F7
A6, A7
76, 77
90
@Ri,direct
@Ri,#data
Move direct byte to indirect RAM
Move immediate data to indirect RAM
DPTR,#data 16 Load data pointer with a 16-bit constant
A,@A+DPTR
A,@A+PC
A,@Ri
Move code byte relative to DPTR to A
Move code byte relative to PC to A
Move external RAM (8-bit address) to A
Move external RAM (16-bit address) to A
Move A to external RAM (8-bit address)
Move A to external RAM (16-bit address)
Push direct byte onto stack
93
83
E2, E3
E0
A,@DPTR
@Ri,A
F2, F3
F0
@DPTR,A
direct
C0
direct
Pop direct byte from stack
D0
XCH
A,Rr
Exchange register with A
C*
XCH
A,direct
A,@Ri
Exchange direct byte with A
C5
XCH
Exchange indirect RAM with A
C6, C7
D6, D7
XCHD
A,@Ri
Exchange LOW-order digit indirect RAM with A
Note
1. MOV A,ACC is not permitted.
1997 Mar 14
61
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
Table 54 Instruction set description: Boolean variable manipulation, Program and machine control
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES CYCLES
Boolean variable manipulation
CLR
CLR
SETB
SETB
CPL
CPL
ANL
ANL
ORL
ORL
MOV
MOV
C
Clear carry flag
Clear direct bit
Set carry flag
Set direct bit
1
2
1
2
1
2
2
2
2
2
2
2
1
1
1
1
1
1
2
2
2
2
1
2
C3
bit
C2
D3
D2
B3
B2
82
B0
72
A0
A2
92
C
bit
C
Complement carry flag
bit
Complement direct bit
C,bit
C,/bit
C,bit
C,/bit
C,bit
bit,C
AND direct bit to carry flag
AND complement of direct bit to carry flag
OR direct bit to carry flag
OR complement of direct bit to carry flag
Move direct bit to carry flag
Move carry flag to direct bit
Program and machine control
ACALL
LCALL
RET
addr11
addr16
Absolute subroutine call
2
3
1
1
2
3
2
1
2
2
2
2
3
3
3
3
3
3
3
2
3
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
•1
Long subroutine call
12
22
32
♦ 1
02
80
73
60
70
40
50
20
30
10
B5
B4
B*
Return from subroutine
RETI
AJMP
LJMP
SJMP
JMP
Return from interrupt
addr11
addr16
rel
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to the DPTR
Jump if A is zero
@A+DPTR
rel
JZ
JNZ
rel
Jump if A is not zero
JC
rel
Jump if carry flag is set
JNC
rel
Jump if carry flag is not set
Jump if direct bit is set
JB
bit,rel
JNB
bit,rel
Jump if direct bit is not set
Jump if direct bit is set and clear bit
Compare direct to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to register and jump if not equal
JBC
bit,rel
CJNE
CJNE
CJNE
CJNE
DJNZ
DJNZ
NOP
A,direct,rel
A,#data,rel
Rr,#data,rel
@Ri,#data,rel Compare immediate to indirect and jump if not equal
B6, B7
D*
D5
00
Rr,rel
Decrement register and jump if not zero
Decrement direct and jump if not zero
No operation
direct,rel
1997 Mar 14
62
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
Table 55 Description of the mnemonics in the Instruction set
MNEMONIC
DESCRIPTION
Data addressing modes
Rr
Working register R0-R7.
128 internal RAM locations and any special function register (SFR).
direct
@Ri
Indirect internal RAM location addressed by register R0 or R1 of the actual register bank.
8-bit constant included in instruction.
#data
#data 16
bit
16-bit constant included as bytes 2 and 3 of instruction.
Direct addressed bit in internal RAM or SFR.
addr16
16-bit destination address. Used by LCALL and LJMP.
The branch will be anywhere within the 64 kbytes Program Memory address space.
addr11
rel
111-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes
page of Program Memory as the first byte of the following instruction.
Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps.
Range is −128 to +127 bytes relative to first byte of the following instruction.
Hexadecimal opcode cross-reference
*
•
8, 9, A, B, C, D, E, F.
1, 3, 5, 7, 9, B, D, F.
0, 2, 4, 6, 8, A, C, E.
♦
1997 Mar 14
63
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
1997 Mar 14
64
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
22 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
−0.5
MAX.
+6.5
VDD + 0.5 V
UNIT
VDD
VI
supply voltage
V
input voltage on any pin with respect to ground (VSS
)
−0.5
−5.0
−5.0
−
II
DC current on any input
+5.0
+5.0
300
mA
mA
IO
DC current on any output
Ptot
Tstg
Tamb
Tj
total power dissipation
mW
°C
storage temperature
−65
−40
−
+150
+85
operating ambient temperature
operating junction temperature
°C
+125
°C
23 DC CHARACTERISTICS
VDD = 1.8 to 6 V; VSS = 0 V; Tamb = −25 to +55 °C; see notes 1 and 2; all voltages with respect to VSS unless specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Supply
VDD
supply voltage
operating
2.5
−
−
6.0
6.0
V
V
RAM retention voltage in
Power-down mode
1.0
IDD
supply current operating
supply current Idle mode
Power-down current
VDD = 5 V; fCLK = 12 MHz; note 3
−
−
−
−
−
−
27.0
5.0
mA
mA
mA
mA
µA
VDD = 3 V; fCLK = 3.58 MHz; note 3 −
VDD = 5 V; fCLK = 12 MHz; note 4
VDD = 3 V; fCLK = 3.58 MHz; note 4 −
IDD(idle)
−
10.0
3.0
IDD(pd)
Inputs (note 6)
VDD = 1.8 V; Tamb = 25°C; note 5
−
10
VIL
VIH
ILI
LOW level input voltage
VSS
0.7VDD
−
−
−
−
0.3VDD
VDD
V
HIGH level input voltage
V
input leakage current (Port 0; EA)
VSS < VI < VDD
±10
µA
Outputs
IOL
LOW level output current
(except SDA; SCL)
VDD = 5 V; VOL = 0.4 V
VDD = 2.5 V; VOL = 0.4 V
1.6
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
mA
mA
mA
mA
mA
mA
mA
mA
mA
0.7
LOW level output current SDA; SCL VDD = 5 V; VOL = 0.4 V
3.0
LOW level output current PWM0
VDD = 5 V; VOL = 0.4 V
3.2
VDD = 2.5 V; VOL = 0.4 V
1.6
IOH
HIGH level output current PWM0
VDD = 5 V; VOH = VDD − 0.4 V
VDD = 2.5 V; VOH = VDD − 0.4 V
VDD = 5 V; VOH = VDD − 0.4 V
VDD = 2.5 V; VOH = VDD − 0.4 V
−3.2
−1.6
−1.6
−0.7
IOH
HIGH level output current
(push-pull options only)
1997 Mar 14
65
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
SYMBOL
PARAMETER
input current logic 0
CONDITIONS
VDD = 5 V; VIN = 0.4 V
VDD = 2.5 V; VIN = 0.4 V
MIN.
TYP. MAX. UNIT
IIL
−
−
−
−
−
−
−
−
−
−100
−50
µA
µA
mA
µA
kΩ
IITL
input current logic 0; HIGH-to-LOW VDD = 5 V; VIN = 0.5VDD
transition
−1.0
−500
200
VDD = 2.5 V; VIN = 0.5VDD
RRST
RST pull-down resistor
10
Analog inputs (note 7)
VIN(A)
Vref(p)(A)
Rref
analog input voltage
VSSA
2.7
−
−
−
VDD
VDD
100
mA
mA
kΩ
reference voltage
resistance between
Vref(p)(A) and VSSA
25
CAIN
Ae
analog on-chip input capacitance
absolute error (note 8)
−
−
−
−
−
3
−
−
−
−
−
pF
±1
±1
±1
±1⁄2
LSB
LSB
LSB
LSB
OSe
DLe
Mctc
zero-offset error (note 9)
differential non-linearity (note 10)
channel-to-channel matching
(note 11)
Notes to the DC characteristics
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the LOW level output
voltage of ALE, Port 1 and Port 3 pins when these make a HIGH-to-LOW transition during bus operations. The noise
is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make HIGH-to-LOW
transitions during bus operations. In the most adverse conditions (capacitive loading > 100 pF), the noise pulse on
the ALE line may exceed 0.8 V. In such events it may be required to qualify ALE with a Schmitt trigger, or use an
address latch with a Schmitt trigger strobe input.
2. Capacitive loading on Ports 0 and 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall
below the 0.9VDD specification when the address bits are stabilizing.
3. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns;
VIL = VSS; VIH = VDD; XTAL2 not connected; EA = RST = Port 0 = VDD
4. The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns;
VIL = VSS; VIH = VDD; XTAL2 not connected; EA = Port 0 = VDD
5. The power-down current is measured with all output pins disconnected; XTAL1 not connected; EA = Port 0 = VDD
RST = VSS
.
.
;
.
6. The input threshold voltage of P1.6/SCL and P1.7/SDA meet the I2C-bus specification. Therefore, an input voltage
below 0.3VDD will be recognized as a logic 0 and an input voltage above 0.7VDD will be recognized as a logic 1.
7. VDD = 2.7 to 6 V; VSS = 0 V; VSSA = 0 V; Vref(p)(A) = VDD; Tamb = −40 to +85 °C, unless otherwise specified.
fxtal(min) = 250 kHz.
8. Absolute error: the maximum difference between actual and ideal code transitions. Absolute error accounts for all
deviations of an actual converter from an ideal converter.
9. Zero-offset error: the difference between the actual and ideal input voltage corresponding to the first actual code
transition.
10. Differential non-linearity: the difference between the actual and ideal code widths.
11. Channel-to-channel matching: the difference between corresponding code transitions of actual characteristics taken
from different channels under the same temperature, voltage and frequency conditions. Not tested, but verified on
sampling basis.
1997 Mar 14
66
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
MGC761
MGC762
18
16
f
24
XTAL
(MHz)
I
DD
(mA)
14
12
10
18
12 MHz
8.0 MHz
12
6
8
6
4
2
0
3.58 MHz
250 kHz (1)
0
0
2
4
6
0
2
4
6
(V)
V
V
(V)
DD
2.7 V (1)
DD
Tamb = 25 °C.
Oscillator option = Oscillator 3.
(1) The area above the dotted lines give the ADC operating area.
Fig.37 Typical operating current as a function of
frequency and VDD
Fig.36 Frequency operating range.
.
MGC763
MGC764
8
6
handbook, halfpage
handbook, halfpage
I
DD(idle)
(mA)
I
DD(pd)
(µA)
6
12 MHz
4
8.0 MHz
4
2
3.58 MHz
2
0
0
0
0
2
4
6
2
4
6
V
V
(V)
(V)
DD
DD
Tamb = 25 °C.
Tamb = 25 °C.
Oscillator option = Oscillator 3.
Fig.38 Typical Idle current as a function of
frequency and VDD
Fig.39 Typical Power-down current as a function of
VDD
.
.
1997 Mar 14
67
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
255
254
253
252
251
(4)
(1)
(2)
250
code
out
5
4
3
2
1
0
(3)
7
1 LSB (ideal)
1
2
3
4
5
6
250 251 252 253 254 255
V
(LSB
IN(A)
)
ideal
zero offset
error
MGD625
Vref(p)(A) – VSSA
1LSB = -------------------------------------------
256
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential non-linearity (DLe).
(4) Absolute error.
Fig.40 Analog-to-digital conversion characteristics.
68
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
24 AC CHARACTERISTICS
VDD = 5 V; VSS = 0 V; Tamb = −40 to +85 °C; CL = 50 pF for Port 0, ALE and PSEN; CL = 40 pF for all other outputs
unless specified; tCLK = 1/ fCLK
.
fosc = 12 MHz
MIN. MAX.
fosc = VARIABLE
SYMBOL
PARAMETER
UNIT
MIN.
MAX.
Program Memory (Fig.41)
tLHLL
tAVLL
tLLAX
tLLIV
ALE pulse width
127
43
48
−
−
2tCLK − 40
−
−
−
ns
address valid to ALE LOW
address hold after ALE LOW
ALE LOW to valid instruction in
ALE LOW to PSEN LOW
−
t
CLK − 40
CLK − 35
ns
ns
−
t
233
−
−
4tCLK − 100 ns
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tPXAV
tAVIV
tPLAZ
58
215
−
tCLK − 25
−
−
ns
ns
PSEN pulse width
−
3tCLK − 35
PSEN LOW to valid instruction in
input instruction hold after PSEN
input instruction float after PSEN
PSEN to address valid
125
−
−
0
−
3tCLK − 125 ns
0
−
ns
ns
ns
−
63
−
t
CLK − 20
75
−
tCLK − 8
−
address to valid instruction in
PSEN LOW to address float
302
−
−
5tCLK − 115 ns
12
0
−
ns
External Data Memory (Figs 42 and 43)
tRLRH
tWLWH
tLLAX
RD pulse width
400
400
48
−
−
6tCLK − 100 −
6tCLK − 100 −
ns
ns
ns
WR pulse width
−
address hold after ALE LOW
RD LOW to valid data in
data float after RD
−
tCLK − 35
−
tRLDV
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
150
97
517
585
300
−
−
−
5tCLK − 165 ns
2tCLK − 70 ns
8tCLK − 150 ns
9tCLK − 165 ns
−
ALE LOW to valid data in
address to valid data in
ALE LOW to RD or WR LOW
address valid to RD or WR LOW
RD or WR HIGH to ALE HIGH
data valid to WR transition
data valid time WR HIGH
data hold after WR
−
−
−
200
203
43
23
433
33
−
3tCLK − 50 3tCLK + 50 ns
4
−
ns
ns
ns
ns
ns
ns
123
−
t
CLK − 40
CLK − 60
tCLK + 40
t
−
−
7tCLK − 150 −
−
tCLK −50
−
RD LOW to address float
12
−
12
1997 Mar 14
69
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
t
CY
t
t
LLIV
LHLL
ALE
PSEN
t
LLPL
t
PLPH
t
t
LLAX
PXAV
t
t
t
PXIZ
AVLL
PLIV
PORT 0
PORT 2
A0 to A7
inst. input
A0 to A7
inst. input
t
t
PXIX
PLAZ
t
AVIV
address A8 to A15
address A8 to A15
MGD680
Fig.41 Read from Program Memory.
t
CY
ALE
t
t
t
LHLL
LLDV
WHLH
PSEN
RD
t
t
RLRH
LLWL
t
t
t
RHDZ
AVLL
LLAX
t
t
t
RHDX
AVWL
RLDV
PORT 0
PORT 2
A0 to A7
data input
t
RLAZ
t
AVDV
address A8 to A15 (DPH) or Port 2
MGA177
Fig.42 Read from Data Memory.
70
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
t
CY
t
t
LHLL
WHLH
ALE
PSEN
t
t
WLWH
LLWL
WR
t
AVWL
t
t
t
t
AVLL
LLAX
QVWH
WHQX
t
QVWX
PORT 0
PORT 2
A0 to A7
data output
address A8 to A15 (DPH) or Port 2
MGA178
Fig.43 Write to Data Memory.
1997 Mar 14
71
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
one machine cycle
one machine cycle
h
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
P1 P2
P1 P2
P1 P2 P1 P2 P1 P2
P1 P2 P1 P2 P1 P2
P1 P2 P1 P2 P1 P2
P1 P2
XTAL1
INPUT
dotted lines
are valid when
RD or WR are
active
ALE
PSEN
RD
only active
during a read
from external
data memory
only active
during a write
to external
data memory
WR
BUS
(PORT 0)
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
external
program
memory
fetch
address A8 - A15
address A8 - A15
address A8 - A15
address A8 - A15
PORT 2
BUS
(PORT 0)
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
address
A0 - A7
data output or data input
read or
write of
external data
memory
address A8 - A15
address A8 - A15 or Port 2 output
address A8 - A15
PORT 2
PORT 0, 2, 3
OUTPUT
old data
old data
new data
new data
PORT 1
OUTPUT
PORT 0, 2, 3
INPUT
sampling time of I/O port pins during input
SERIAL PORT
SHIFT CLOCK
(MODE 0)
MGD681
Fig.44 Instruction cycle timing.
72
1997 Mar 14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
0.7 V
0.7 V
DD
DD
handbook, halfpage
0.9 V
DD
test points
0.4 V
DD
MLA586
0.3 V
DD
0.3 V
DD
Fig.45 AC testing input waveform.
I
MGD682
IL(T)
handbook, 4 columns
−500 µA
I
L
I
IL
−100 µA
V
0.5 V
DD
DD
Fig.46 Input current.
1997 Mar 14
73
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
25 PACKAGE OUTLINES
VSO56: plastic very small outline package; 56 leads
SOT190-1
D
E
A
X
c
y
H
v
M
A
E
Z
56
29
Q
p
A
2
A
(A )
3
A
1
pin 1 index
θ
L
L
detail X
1
28
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(2)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
0.3
0.1
3.0
2.8
0.42
0.30
0.22 21.65 11.1
0.14 21.35 11.0
15.8
15.2
1.6
1.4
1.45
1.30
0.90
0.55
3.3
0.25
0.01
0.75
0.03
2.25
0.2
0.1
0.1
7o
0o
0.012 0.12
0.004 0.11
0.017 0.0087 0.85
0.012 0.0055 0.84
0.44
0.43
0.62
0.60
0.063 0.057
0.055 0.051
0.035
0.022
inches
0.008 0.004 0.004
0.089
0.13
Note
1. Plastic or metal protrusions of 0.3 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
96-04-02
SOT190-1
1997 Mar 14
74
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT319-2
y
X
A
51
33
52
32
Z
E
e
Q
A
2
H
A
E
(A )
3
E
A
1
θ
w M
p
pin 1 index
L
p
b
L
20
64
detail X
1
19
w M
Z
D
v
M
A
b
p
e
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.25 2.90
0.05 2.65
0.50 0.25 20.1 14.1
0.35 0.14 19.9 13.9
24.2 18.2
23.6 17.6
1.0
0.6
1.4
1.2
1.2
0.8
1.2
0.8
mm
3.20
0.25
1
1.95
0.2
0.2
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT319-2
1997 Mar 14
75
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
If wave soldering cannot be avoided, the following
conditions must be observed:
26 SOLDERING
26.1 Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
QFP100 (SOT382-1) or QFP160 (SOT322-1).
26.3.2 VSO
26.2 Reflow soldering
Wave soldering techniques can be used for all VSO
packages if the following conditions are observed:
Reflow soldering techniques are suitable for all QFP and
VSO packages.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Manual” (order code 9398 510 63011).
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
26.3.3 METHOD (QFP AND VSO)
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
26.4 Repairing soldered joints
26.3 Wave soldering
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
26.3.1 QFP
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1997 Mar 14
76
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
27 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
28 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
29 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Mar 14
77
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
NOTES
1997 Mar 14
78
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
NOTES
1997 Mar 14
79
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
457047/1200/04/pp80
Date of release: 1997 Mar 14
Document order number: 9397 750 01509
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