P82B96PN,112_技术文档

P82B96

Dual bidirectional bus buffer

Rev. 08 — 10 November 2009

Product data sheet

1. General description

The P82B96 is a bipolar IC that creates a non-latching, bidirectional, logic interface

between the normal I²C-bus and a range of other bus conﬁgurations. It can interface

I²C-bus logic signals to similar buses having different voltage and current levels.

For example, it can interface to the 350 µA SMBus, to 3.3 V logic devices, and to 15 V

levels and/or low-impedance lines to improve noise immunity on longer bus lengths.

It achieves this interface without any restrictions on the normal I²C-bus protocols or clock

speed. The IC adds minimal loading to the I²C-bus node, and loadings of the new bus or

remote I²C-bus nodes are not transmitted or transformed to the local node. Restrictions

on the number of I²C-bus devices in a system, or the physical separation between them,

are virtually eliminated. Transmitting SDA and SCL signals via balanced transmission

lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate

directional Tx and Rx signals are provided. The Tx and Rx signals may be directly

connected, without causing latching, to provide an alternative bidirectional signal line with

I²C-bus properties.

2. Features

I Bidirectional data transfer of I²C-bus signals

I Isolates capacitance allowing 400 pF on Sx/Sy side and 4000 pF on Tx/Ty side

I Tx/Ty outputs have 60 mA sink capability for driving low-impedance or high capacitive

buses

I 400 kHz operation over at least 20 meters of wire (see AN10148)

I Supply voltage range of 2 V to 15 V with I²C-bus logic levels on Sx/Sy side

independent of supply voltage

I Splits I²C-bus signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface

with opto-electrical isolators and similar devices that need unidirectional input and

output signal paths.

I Low power supply current

I ESD protection exceeds 3500 V HBM per JESD22-A114, 250 V DIP package, 400 V

SO package MM per JESD22-A115, and 1000 V CDM per JESD22-C101

I Latch-up free (bipolar process with no latching structures)

I Packages offered: DIP8, SO8 and TSSOP8

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

3. Applications

I Interface between I²C-buses operating at different logic levels (for example, 5 V and

3 V or 15 V)

I Interface between I²C-bus and SMBus (350 µA) standard

I Simple conversion of I²C-bus SDA or SCL signals to multi-drop differential bus

hardware, for example, via compatible PCA82C250

I Interfaces with opto-couplers to provide opto-isolation between I²C-bus nodes up to

400 kHz

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

P82B96DP

TSSOP8 plastic thin shrink small outline package; 8 leads;

body width 3 mm

SOT505-1

P82B96PN

P82B96TD

DIP8

SO8

plastic dual in-line package; 8 leads (300 mil)

SOT97-1

SOT96-1

plastic small outline package; 8 leads;

body width 3.9 mm

P82B96TD/S900

SO8

plastic small outline package; 8 leads;

body width 3.9 mm

SOT96-1

4.1 Ordering options

Table 2.

Ordering options

Topside mark

Type number

P82B96DP

P82B96PN

P82B96TD

P82B96TD/S900

Temperature range

−40 °C to +85 °C

−40 °C to +125 °C

82B96

P82B96PN

P82B96T

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

2 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

5. Block diagram

V

(2 V to 15 V)

CC

8

P82B96

1

7

3

2

5

6

Sx (SDA)

Sy (SCL)

Tx (TxD, SDA)

Rx (RxD, SDA)

Ty (TxD, SCL)

Ry (RxD, SCL)

4

GND

002aab976

Fig 1. Block diagram of P82B96

6. Pinning information

6.1 Pinning

P82B96TD

P82B96TD/S900

1

2

3

4

8

7

6

5

Sx

Rx

V

CC

1

2

3

4

8

7

6

5

Sx

Rx

V

CC

1

2

3

4

8

7

6

5

Sx

Rx

V

CC

Sy

Ry

Ty

Sy

Ry

Ty

Sy

Ry

Ty

P82B96PN

P82B96DP

Tx

GND

002aab979

002aab977

002aab978

Fig 2. Pin conﬁguration for DIP8

Fig 3. Pin conﬁguration for SO8

Fig 4. Pin conﬁguration for

TSSOP8

6.2 Pin description

Table 3.

Symbol

Sx

Pin description

Description

I²C-bus (SDA or SCL)

1

2

3

4

5

6

7

8

Rx

receive signal

Tx

transmit signal

GND

Ty

negative supply

transmit signal

Ry

receive signal

I²C-bus (SDA or SCL)

Sy

V_CC

positive supply voltage

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

3 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

7. Functional description

Refer to Figure 1 “Block diagram of P82B96”.

The P82B96 has two identical buffers allowing buffering of both of the I²C-bus (SDA and

SCL) signals. Each buffer is made up of two logic signal paths, a forward path from the

I²C-bus interface pin which drives the buffered bus, and a reverse signal path from the

buffered bus input to drive the I²C-bus interface. Thus these paths are:

• sense the voltage state of the I²C-bus pin Sx (or Sy) and transmit this state to the pin

Tx (Ty respectively), and

• sense the state of the pin Rx (Ry) and pull the I²C-bus pin LOW whenever Rx (Ry) is

LOW.

The rest of this discussion will address only the ‘x’ side of the buffer; the ‘y’ side is

identical.

The I²C-bus pin (Sx) is designed to interface with a normal I²C-bus.

The logic threshold voltage levels on the I²C-bus are independent of the IC supply V_CC

The maximum I²C-bus supply voltage is 15 V and the guaranteed static sink current is

3 mA.

.

The logic level of Rx is determined from the power supply voltage V_CCof the chip. Logic

LOW is below 42 % of V_CC, and logic HIGH is above 58 % of V_CC(with a typical switching

threshold of half V_CC).

Tx is an open-collector output without ESD protection diodes to V_CC. It may be connected

via a pull-up resistor to a supply voltage in excess of V_CC, as long as the 15 V rating is not

exceeded. It has a larger current sinking capability than a normal I²C-bus device, being

able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down

capability as well.

A logic LOW is only transmitted to Tx when the voltage at the I²C-bus pin (Sx) is below

0.6 V. A logic LOW at Rx will cause the I²C-bus (Sx) to be pulled to a logic LOW level in

accordance with I²C-bus requirements (maximum 1.5 V in 5 V applications) but not low

enough to be looped back to the Tx output and cause the buffer to latch LOW.

The minimum LOW level this chip can achieve on the I²C-bus by a LOW at Rx is typically

0.8 V.

If the supply voltage V_CCfails, then neither the I²C-bus nor the Tx output will be held LOW.

Their open-collector conﬁguration allows them to be pulled up to the rated maximum of

15 V even without V_CCpresent. The input conﬁguration on Sx and Rx also present no

loading of external signals even when V_CCis not present.

The effective input capacitance of any signal pin, measured by its effect on bus rise times,

is less than 7 pF for all bus voltages and supply voltages including V_CC= 0 V.

Remark: Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design

does not support this conﬁguration. Bidirectional I²C-bus signals do not allow any

direction control pin so, instead, slightly different logic low voltage levels are used at Sx/Sy

to avoid latching of this buffer. A ‘regular I²C-bus LOW’ applied at the Rx/Ry of a P82B96

will be propagated to Sx/Sy as a ‘buffered LOW’ with a slightly higher voltage level. If this

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

4 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

special ‘buffered LOW’ is applied to the Sx/Sy of another P82B96 that second P82B96 will

not recognize it as a ‘regular I²C-bus LOW’ and will not propagate it to its Tx/Ty output.

The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special

logic thresholds for their operation, for example PCA9511, PCA9515, or PCA9518. The

Sx/Sy side is only intended for, and compatible with, the normal I²C-bus logic voltage

levels of I²C-bus master and slave chips, or even Tx/Rx signals of a second P82B96 if

required. The Tx/Rx and Ty/Ry I/O pins use the standard I²C-bus logic voltage levels of all

I²C-bus parts. There are no restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O

pins to other P82B96s, for example in a star or multipoint conﬁguration with the Tx/Rx and

Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to the line card slave

devices. For more details see Application Note AN255.

8. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Voltages with respect to pin GND.

Symbol

V_CC

V_Sx

V_Tx

V_Rx

I_n

Parameter

Conditions

Min

−0.3

-

Max

+18

250

300

+125

Unit

V

supply voltage

V_CCto GND

voltage on pin Sx

voltage on pin Tx

voltage on pin Rx

current on any pin

total power dissipation

junction temperature

I²C-bus SDA or SCL

buffered output

receive input

V

[1]

V

mA

mW

°C

P_tot

T_j

-

operating range

P82B96TD/S900

−40

T_stg

storage temperature

ambient temperature

−55

−40

+125

+85

°C

T_amb

operating

[1] See also Section 10.2 “Negative undershoot below absolute minimum value”.

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

5 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

9. Characteristics

Table 5.

Characteristics

T_amb= +25 °C; voltages are speciﬁed with respect to GND with V_CC= 5 V, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

T_amb= +25 °C

T_amb= −40 °C to Unit

+125 °C^[1]

Min

Typ

Max

Min

Max

Power supply

V_CC

I_CC

supply voltage

operating

2.0

-

15

1.8

2.5

2.0

15

3

V

supply current

buses HIGH

-

0.9

1.1

-

mA

V_CC= 15 V;

buses HIGH

4

∆I_CC

additional quiescent

supply current

per Tx or Ty LOW

-

1.7

-

3.5

15

-

3.5

15

mA

V

Bus pull-up (load) voltages and currents

V_Sx, V_Sy

maximum input/output

voltage

open-collector;

I²C-bus and V_Rx, V_Ry

HIGH

=

[2]

I_Sx, I_Sy

static output loading on V_Sx, V_Sy= 1.0 V;

0.2

-

18

-

3

-

0.2

3

mA

µA

V

I²C-bus

V

_Rx, V_Ry= LOW

V_Sx, V_Sy= 2 V;

_Rx, V_Ry= LOW

V_Sx, V_Sy= 5 V;

_Rx, V_Ry= HIGH

V_Sx, V_Sy= 15 V;

_Rx, V_Ry= HIGH

dynamic output sink

capability on I²C-bus

7

-

7

-

V

leakage current on

I²C-bus

1

10

15

30

V

-

1

-

V

V_Tx, V_Ty

I_Tx, I_Ty

maximum output voltage open-collector

level

-

15

30

-

static output loading on V_Tx, V_Ty= 0.4 V;

-

mA

buffered bus

V_Sx, V_Sy= LOW on

I²C-bus = 0.4 V

I_Tx, I_Ty

dynamic output sink

capability, buffered bus

V_Tx, V_Ty> 1 V;

60

-

100

1

-

60

-

mA

V

_Sx, V_Sy= LOW on

I²C-bus = 0.4 V

I_Tx, I_Ty

leakage current on

buffered bus

V_Tx, V_Ty= V_CC= 15 V;

_Sx, V_Sy= HIGH

10

µA

V

Input currents

I_Sx, I_Sy

I_Rx, I_Ry

input current from

bus LOW;

V_Rx, V_Ry= HIGH

-

−1

1

-

−10

10

µA

I²C-bus

input current from

buffered bus

bus LOW;

V_Rx, V_Ry= 0.4 V

leakage current on

buffered bus input

V_Rx, V_Ry= V_CC

Output logic LOW level

[3]

V_Sx, V_Sy

output logic level LOW

on normal I²C-bus

I_Sx, I_Sy= 3 mA

0.8

670

-

0.88

730

1.0

790

-

(see Figure 6)

(see Figure 5)

V

I_Sx, I_Sy= 0.2 mA

mV

mV/K

dV_Sx/dT,

dV_Sy/dT

temperature coefﬁcient I_Sx, I_Sy= 0.2 mA

of output LOW levels

−1.8

-

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

6 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

Table 5.

Characteristics …continued

T_amb= +25 °C; voltages are speciﬁed with respect to GND with V_CC= 5 V, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

T_amb= +25 °C

T_amb= −40 °C to Unit

+125 °C^[1]

Min

Typ

Max

Min

Max

Input logic switching threshold voltages

[4]

V_Sx, V_Sy

input logic voltage LOW on normal I²C-bus

-

640

650

600

-

(see Figure 7)

(see Figure 8)

mV

input logic level HIGH

threshold

on normal I²C-bus

700

dV_Sx/dT,

dV_Sy/dT

temperature coefﬁcient

of input thresholds

-

−2

-

mV/K

V_Rx, V_Ry

input logic HIGH level

input threshold

fraction of applied V_CC

0.58V_CC

-

0.58V_CC

-

V

-

0.5V_CC

-

input logic LOW level

0.42V_CC

Logic level threshold difference

[2]

V_Sx, V_Sy

input/output logic level

difference

V_Sxoutput LOW at

0.2 mA − V_Sxinput

HIGH maximum

50

85

-

50

-

mV

Thermal resistance

R_th(j-pcb)thermal resistance from SOT96-1 (SO8);

junction to printed-circuit average lead

-

127

-

K/W

board

temperature at board

interface

Bus release on V_CCfailure

V_Sx, V_Sy, V_CCvoltage at which all

-

1

-

(see Figure 9)

V

V_Tx, V_Ty

dV/dT

buses are guaranteed to

be released

temperature coefﬁcient

of guaranteed release

voltage

−4

-

mV/K

Buffer response time^[5]

T_{fall delay}

buffer time delay on

R

_Txpull-up = 160 Ω;

no capacitive load;

V_CC= 5 V

-

70

90

-

ns

V_Sxto V_Tx, falling input between

V_Syto V_Ty

V

_Sx= input switching

threshold, and V_Tx

output falling 50 %

T_{rise delay}

buffer time delay on

R_Txpull-up = 160 Ω;

-

V_Sxto V_Tx, rising input between

_Syto V_{Ty Sx}= input switching

no capacitive load;

V_CC= 5 V

V

threshold, and V_Tx

output reaching 50 %

V_CC

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

7 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

Table 5.

Characteristics …continued

T_amb= +25 °C; voltages are speciﬁed with respect to GND with V_CC= 5 V, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

T_amb= +25 °C

T_amb= −40 °C to Unit

+125 °C^[1]

Min

Typ

Max

Min

Max

T_{fall delay}

V_Rxto

buffer time delay on

falling input between

R

_Sxpull-up = 1500 Ω;

no capacitive load;

V_CC= 5 V

-

250

-

ns

V_Sx, V_Ry

V

_Rx= input switching

to V_Sy

threshold, and V_Sx

output falling 50 %

T_{rise delay}

V_Rxto

buffer time delay on

rising input between

R_Sxpull-up = 1500 Ω;

no capacitive load;

V_CC= 5 V

-

270

-

ns

V_Sx, V_Ry

V

_Rx= input switching

to V_Sy

threshold, and V_Sx

output reaching 50 %

V_CC

Input capacitance

C_iinput capacitance

effective input

-

7

pF

capacitance of any

signal pin measured

by incremental bus

rise times

[1] Limit data for +125 °C applies to P82B96TD/S900 version. It is guaranteed by design/characterization, but not by 100 % test.

[2] The minimum value requirement for pull-up current, 200 µA, guarantees that the minimum value for V_Sxoutput LOW will always exceed

the minimum V_Sxinput HIGH level to eliminate any possibility of latching. The speciﬁed difference is guaranteed by design within any IC.

While the tolerances on absolute levels allow a small probability the LOW from one Sx output is recognized by an Sx input of another

P82B96, this has no consequences for normal applications. In any design the Sx pins of different ICs should never be linked because

the resulting system would be very susceptible to induced noise and would not support all I²C-bus operating modes.

[3] The output logic LOW depends on the sink current. For scaling, see Application Note AN255.

[4] The input logic threshold is independent of the supply voltage.

[5] The fall time of V_Txfrom 5 V to 2.5 V in the test is approximately 15 ns.

The fall time of V_Sxfrom 5 V to 2.5 V in the test is approximately 50 ns.

The rise time of V_Txfrom 0 V to 2.5 V in the test is approximately 20 ns.

The rise time of V_Sxfrom 0.9 V to 2.5 V in the test is approximately 70 ns.

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

8 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

002aac069

002aac070

1000

1200

V

(mV)

OL

V

(mV)

OL

1000

800

(1)

800

600

400

(2)

(3)

(1)

(2)

(3)

600

400

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

T (°C)

j

V_OLat Sx typical and limits over temperature

(1) Maximum

(2) Typical

(1) Maximum

(2) Typical

(3) Minimum

Fig 5. V_OLas a function of junction temperature

(I_OL= 0.2 mA)

Fig 6. V_OLas a function of junction temperature

(I_OL= 3 mA)

002aac071

002aac072

1000

V

IL(max)

(mV)

IH(min)

(mV)

800

600

400

200

800

600

400

200

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

T (°C)

j

V_IL(max)at Sx changes over temperature range

V_IH(min)at Sx changes over temperature range

Fig 7. V_IL(max)as a function of junction temperature

Fig 8. V_IH(min)as a function of junction temperature

002aac075

1400

V

CC(max)

(mV)

1200

1000

800

600

400

−50

−25

0

25

50

75

100

125

T (°C)

j

Fig 9. V_CC(max)that guarantees bus release limit over temperature

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

9 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

10. Application information

Refer to AN460 and AN255 for more application detail.

+V

(2 V to 15 V)

CC

+5 V

R1

Tx

(SDA)

2

I C-bus

SDA

'SDA' (new levels)

Rx

(SDA)

1

/ P82B96

2

002aab986

Fig 10. Interfacing an ‘I²C’ type of bus with different logic levels

+V

R4

CC

CC1

R2

R5

2

I C-bus

R3

Rx

(SDA)

SDA

+5 V

R1

Tx

(SDA)

2

I C-bus

SDA

1

/ P82B96

2

002aab987

Fig 11. Galvanic isolation of I²C-bus nodes via opto-couplers

main enclosure

remote control enclosure

3.3 V to 5 V

12 V

long cables

SDA

SCL

SDA

SCL

3.3 V to 5 V

12 V

3.3 V to 5 V

P82B96

002aab988

Fig 12. Long distance I²C-bus communications

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

10 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

Figure 13 shows how a master I²C-bus can be protected against short circuits or failures

in applications that involve plug and socket connections and long cables that may become

damaged. A simple circuit is added to monitor the SDA bus, and if its LOW time exceeds

the design value, then the master bus is disconnected. P82B96 will free all its I/Os if its

supply is removed, so one option is to connect its V_CCto the output of a logic gate from,

say, the 74LVC family. The SDA and SCL lines could be timed and V_CCdisabled via the

gate if one or other lines exceeds a design value of ‘LOW’ period as in Figure 28 of

AN255. If the supply voltage of logic gates restricts the choice of V_CCsupply then the

low-cost discrete circuit in Figure 13 can be used. If the SDA line is held LOW, the 100 nF

capacitor will charge and the Ry input will be pulled towards V_CC. When it exceeds 0.5V_CC

the Ry input will set the Sy input HIGH, which in practice means simply releasing it.

In this example the SCL line is made unidirectional by tying the Rx pin to V_CC. The state of

the buffered SCL line cannot affect the master clock line which is allowed when

clock-stretching is not required. It is simple to add an additional transistor or diode to

control the Rx input in the same way as Ry when necessary. The +V cable drive can be

any voltage up to 15 V and the bus may be run at a lower impedance by selecting pull-up

resistors for a static sink current up to 30 mA. V_CC1and V_CC2may be chosen to suit the

connected devices. Because DDC uses relatively low speeds (< 100 kHz), the cable

length is not restricted to 20 m by the I²C-bus signalling, but it may be limited by the video

signalling.

+V cable drive

V

CC1

V

CC2

100 nF

100

kΩ

V

CC

3 m to 20 m

cables

BC

847B

Rx

Tx

Rx

Tx

Sx

Sy

Sx

Sy

SCL

2

Ry

Ty

I C-bus/DDC

slave

2

I C-bus/DDC

master

4.7 kΩ

Ty

SDA

470 kΩ

P82B96

BC

847B

GND

470 kΩ

monitor/flat TV

GND

R

PC/TV receiver/decoder box

G

B

video signals

002aab989

Fig 13. Extending a DDC bus

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

11 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

Figure 14 shows that P82B96 can achieve high clock rates over long cables. While

calculating with lumped wiring capacitance yields reasonable approximations to actual

timing, even 25 meters of cable is better treated using transmission line theory. Flat ribbon

cables connected as shown, with the bus signals on the outer edge, will have a

characteristic impedance in the range 100 Ω to 200 Ω. For simplicity they cannot be

terminated in their characteristic impedance but a practical compromise is to use the

minimum pull-up allowed for P82B96 and place half this termination at each end of the

cable. When each pull-up is below 330 Ω, the rising edge waveforms have their ﬁrst

voltage ‘step’ level above the logic threshold at Rx and cable timing calculations can be

based on the fast rise/fall times of resistive loading plus simple one-way propagation

delays. When the pull-up is larger, but below 750 Ω, the threshold at Rx will be crossed

after one signal reﬂection. So at the sending end it is crossed after 2 times the one-way

propagation delay and at the receiving end after 3 times that propagation delay. For ﬂat

cables with partial plastic dielectric insulation (by using outer cores) the one-way

propagation delays will be about 5 ns per meter. The 10 % to 90 % rise and fall times on

the cable will be between 20 ns and 50 ns, so their delay contributions are small. There

will be ringing on falling edges that can be damped, if required, by using Schottky diodes

as shown.

When the Master SCL HIGH and LOW periods can be programmed separately, for

example using control registers I2SCLH and I2SCLL of 89LPC932, the timings can allow

for bus delays. The LOW period should be programmed to achieve the minimum 1300 ns

plus the net delay in the slave's response data signal caused by bus and buffer delays.

The longest data delay is the sum of the delay of the falling edge of SCL from master to

slave and the delay of the rising edge of SDA from slave data to master. Because the

buffer will ‘stretch’ the programmed SCL LOW period, the actual SCL frequency will be

lower than calculated from the programmed clock periods. In the example for 25 meters

the clock is stretched 400 ns, the falling edge of SCL is delayed 490 ns and the SDA rising

edge is delayed 570 ns. The required additional LOW period is

(490 ns + 570 ns) = 1060 ns and the I²C-bus speciﬁcations already include an allowance

for a worst case bus rise time 0 % to 70 % of 425 ns. (The bus rise time can be 300 ns

30 % to 70 %, which means it can be 425 ns 0 % to 70 %. The 25 meter cable delay times

as quoted already include all rise and fall times.) Therefore, the microcontroller only needs

to be programmed with an additional (1060 ns − 400 ns − 425 ns) = 235 ns, making a

total programmed LOW period 1535 ns. The programmed LOW will the be stretched by

400 ns to yield an actual bus LOW time of 1935 ns, which, allowing the minimum HIGH

period of 600 ns, yields a cycle period of 2535 ns or 394 kHz.

Note that in both the 100 meter and 250 meter examples, the capacitive loading on the

I²C-buses at each end is within the maximum allowed Standard mode loading of 400 pF,

but exceeds the Fast mode limit. This is an example of a ‘hybrid’ mode because it relies on

the response delays of Fast mode parts but uses (allowable) Standard mode bus loadings

with rise times that contribute signiﬁcantly to the system delays. The cables cause large

propagation delays, so these systems need to operate well below the 400 kHz limit, but

illustrate how they can still exceed the 100 kHz limit provided all parts are capable of

Fast mode operation. The fastest example illustrates how the 400 kHz limit can be

exceeded, provided masters and slaves have the required timings, namely smaller than

the maximum allowed for Fast mode. Many NXP slaves have delays shorter than 600 ns

and all Fm+ devices must be < 450 ns.

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

12 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

+V cable drive

V

CC1

V

CC2

R2

V

CC

R2

Sx

R1 R1

R2

Sx

Rx

Tx

Rx

Tx

SCL

SDA

C2

SCL

SDA

C2

2

I C-BUS

MASTER

I C-BUS

Ry

Ty

Ry

Ty

SLAVE(S)

Sy

C2

Sy

C2

cable

P82B96

propagation

delay ≈ 5 ns/m

GND

BAT54A

002aab990

Fig 14. Driving ribbon or ﬂat telephone cables

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

13 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

10.1 Calculating system delays and bus clock frequency for a Fast mode

system

local master bus

buffered expansion bus

remote slave bus

V

CCM

V

CCS

CCB

Rm

Rb

Rs

SCL

MASTER

SLAVE

Sx

Tx/Rx

Sx

P82B96

2

I C-BUS

Cm

Cb

Cs

master bus

capacitance

buffered bus

wiring capacitance

slave bus

capacitance

GND (0 V)

002aab991

Effective delay of SCL at slave: 255 + 17V_CCM+ (2.5 + 4 × 10⁹C_b)V_CCB+ 10V_CCSns.

C = F; V = volts.

Fig 15. Falling edge of SCL at master is delayed by the buffers and bus fall times

local master bus

buffered expansion bus

V

CCM

V

CCB

Rm

Rb

SCL

MASTER

Sx

Tx/Rx

P82B96

2

I C-BUS

Cm

Cb

master bus

capacitance

buffered bus

wiring capacitance

GND (0 V)

002aab992

Effective delay of SCL at master: 270 + RmCm + 0.7RbCb ns.

C = F; R = Ω.

Fig 16. Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

15 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

local master bus

buffered expansion bus

remote slave bus

V

CCM

V

CCS

CCB

Rm

Rb

Rs

SDA

MASTER

SLAVE

Sx

Tx/Rx

Sx

P82B96

2

I C-BUS

Cm

Cb

Cs

master bus

capacitance

buffered bus

wiring capacitance

slave bus

capacitance

GND (0 V)

002aab993

Effective delay of SDA at master = 270 + 0.2RsCs + 0.7 (RbCb + RmCm) ns.

C = F; R = Ω.

Fig 17. Rising edge of SDA at slave is delayed by the buffers and bus rise times

Figure 15, Figure 16, and Figure 17 show the P82B96 used to drive extended bus wiring,

with relatively large capacitance, linking two Fast mode I²C-bus nodes. It includes

simpliﬁed expressions for making the relevant timing calculations for 3.3 V or 5 V

operation. Because the buffers and the wiring introduce timing delays, it may be

necessary to decrease the nominal SCL frequency below 400 kHz. In most cases the

actual bus frequency will be lower than the nominal Master timing due to bit-wise

stretching of the clock periods.

The delay factors involved in calculation of the allowed bus speed are:

A — The propagation delay of the master signal through the buffers and wiring to the

slave. The important delay is that of the falling edge of SCL because this edge ‘requests’

the data or acknowledge from a slave. See Figure 15.

B — The effective stretching of the nominal LOW period of SCL at the master caused by

the buffer and bus rise times. See Figure 16.

C — The propagation delay of the slave's response signal through the buffers and wiring

back to the master. The important delay is that of a rising edge in the SDA signal. Rising

edges are always slower and are therefore delayed by a longer time than falling edges.

(The rising edges are limited by the passive pull-up while falling edges are actively driven).

See Figure 17.

The timing requirement in any I²C-bus system is that a slave's data response (which is

provided in response to a falling edge of SCL) must be received at the master before the

end of the corresponding LOW period of SCL as appears on the bus wiring at the master.

Since all slaves will, as a minimum, satisfy the worst case timing requirements of a

400 kHz part, they must provide their response within the minimum allowed clock LOW

period of 1300 ns. Therefore in systems that introduce additional delays it is only

necessary to extend that minimum clock LOW period by any ‘effective’ delay of the slave's

response. The effective delay of the slaves response equals the total delays in SCL falling

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

16 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

edge from the master reaching the slave (Figure 15) minus the effective delay (stretch) of

the SCL rising edge (Figure 16) plus total delays in the slave's response data, carried on

SDA, reaching the master (Figure 17).

The master microcontroller should be programmed to produce a nominal SCL LOW

period = (1300 + A − B + C) ns, and should be programmed to produce the nominal

minimum SCL HIGH period of 600 ns. Then a check should be made to ensure the cycle

time is not shorter than the minimum 2500 ns. If found necessary, just increase either

clock period.

Due to clock stretching, the SCL cycle time will always be longer than

(600 + 1300 + A + C) ns.

Example:

The master bus has an RmCm product of 100 ns and V_CCM= 5 V.

The buffered bus has a capacitance of 1 nF and a pull-up resistor of 160 Ω to 5 V giving

an RbCb product of 160 ns. The slave bus also has an RsCs product of 100 ns.

The microcontroller LOW period should be programmed to

≥ (1300 + 372.5 − 482 + 472) ns, that is ≥ 1662.5 ns.

Its HIGH period may be programmed to the minimum 600 ns.

The nominal microcontroller clock period will be ≥ (1662.5 + 600) ns = 2262.5 ns,

equivalent to a frequency of 442 kHz.

The actual bus clock period, including the 482 ns clock stretch effect, will be below

(nominal + stretch) = (2262.5 + 482) ns or ≥ 2745 ns, equivalent to an allowable

frequency of 364 kHz.

12 V

twitsted-pair telephone wires,

USB, or flat ribbon cables;

up to 15 V logic levels,

3.3 V to 5 V

include V

and GND

Tx

Rx

CC

Sx

Sy

SDA

SCL

12 V

Ty

Ry

3.3 V 3.3 V

P82B96 P82B96 P82B96 P82B96

P82B96

Sx

Sy Sx

Sy

Sy SDA

Sx SCL

SCL/SDA

no limit to the number of connected bus devices

002aab994

Fig 18. I²C-bus multipoint application

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

17 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

002aab995

002aab996

14

V

14

10

6

V

Tx

Rx

Sx

10

6

Sx

2

−2

0

400

800

1200

1600

2000

0

400

800

1200

1600

2000

ns

Frequency = 624 kHz

Ch1 frequency = 624 kHz

Fig 19. Propagation Sx to Tx (Sx pull-up to 5 V;

Tx pull-up to V_CC= 10 V)

Fig 20. Propagation Rx to Sx (Sx pull-up to 5 V;

Rx pull-up to V_CC= 10 V)

10.2 Negative undershoot below absolute minimum value

The reason why the IC pin reverse voltage on pins Tx and Rx in Table 4 “Limiting values”

is speciﬁed at such a low value, −0.3 V, is not that applying larger voltages is likely to

cause damage but that it is expected that, in normal applications, there is no reason why

larger DC voltages will be applied. This ‘absolute maximum’ speciﬁcation is intended to be

a DC or continuous ratings and the nominal DC I²C-bus voltage LOW usually does not

even reach 0 V. Inside P82B96 at every pin there is a large protective diode connected to

the GND pin and that diode will start to conduct when the pin voltage is more than about

−0.55 V with respect to GND at 25 °C ambient.

Figure 21 shows the measured characteristic for one of those diodes inside P82B96. The

plot was made using a curve tracer that applies 50 Hz mains voltage via a series resistor,

so the pulse durations are long duration (several milliseconds) and are reaching peaks of

over 2 A when more than −1.5 V is applied. The IC becomes very hot during this testing

but it was not damaged. Whenever there is current ﬂowing in any of these diodes it is

possible that there can be faulty operation of any IC. For that reason we put a speciﬁcation

on the negative voltage that is allowed to be applied. It is selected so that, at the highest

allowed junction temperature, there will be a big safety factor that guarantees the diode

will not conduct and then we do not need to make any 100 % production tests to

guarantee the published speciﬁcation.

For the P82B96, in speciﬁc applications, there will always be transient overshoot and

ringing on the wiring that can cause these diodes to conduct. Therefore we designed the

IC to withstand those transients and as a part of the qualiﬁcation procedure we made

tests, using DC currents to more than twice the normal bus sink currents, to be sure that

the IC was not affected by those currents. For example, the Tx/Ty and Rx/Ry pins were

tested to at least −80 mA which, from Figure 21, would be more than −0.8 V. The correct

functioning of the P82B96 is not affected even by those large currents. The Absolute

Maximum (DC) ratings are not intended to apply to transients but to steady state

conditions. This explains why you will never see any problems in practice even if, during

transients, more than −0.3 V is applied to the bus interface pins of P82B96.

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

18 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

Figure 21 “Diode characteristic curve” also explains how the general Absolute Maximum

DC speciﬁcation was selected. The current at 25 °C is near zero at −0.55 V. The P82B96

is allowed to operate with +125 °C junction and that would cause this diode voltage to

decrease by 100 × 2 mV = 200 mV. So for zero current we need to specify −0.35 V and we

publish −0.3 V just to have some extra margin.

Remark: You should not be concerned about the transients generated on the wiring by a

P82B96 in normal applications and that is input to the Tx/Rx or Ty/Ry pins of another

P82B96. Because not all ICs that may be driven by P82B96 are designed to tolerate

negative transients, in Section 10.2.1 “Example with questions and answers” we show

they can be managed if required.

002aaf063

0

diode current

(mA)

−1

−10

−1

−10

2

−10

3

−10

4

−10

−2.0

−1.5

−1.0

−0.5

voltage (V)

0

Fig 21. Diode characteristic curve

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

19 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

10.2.1 Example with questions and answers

Question: On a falling edge of Tx we measure undershoot at −800 mV at the linked Tx,

Rx pins of the P82B96 that is generating the LOW, but the P82B96 data sheet speciﬁes

minimum −0.3 V. Does this mean that we violate the data sheet absolute value?

Answer: For P82B96 the −0.3 V Absolute Maximum rating is not intended to apply to

transients, it is a DC rating. As shown in Figure 22, there is no theoretical reason for any

undershoot at the IC that is driving the bus LOW and no signiﬁcant undershoot should

be observed when using reasonable care with the ground connection of the ‘scope. It is

more likely that undershoot observed at a driving P82B96 is caused by local stray

inductance and capacitance in the circuit and by the oscilloscope connections. As

shown, undershoot will be generated by PCB traces, wiring, or cables driven by a

P82B96 because the allowed value of the I²C-bus pull-up resistor generally is larger

than that required to correctly terminate the wiring. In this example, with no IC

connected at the end of the wiring, the undershoot is about 2 V.

6

voltage

(V)

4

send

2

receive

0

−2

horizontal scale = 62.5 ns/div

time (ns)

5 V

300 Ω

5 V

300 Ω

Rx

Tx

Sx

send

receive

2 meter

cable

P82B96

GND

002aaf064

Fig 22. Transients generated by the bus wiring

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

20 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

Question: We have 2 meters of cable in a bus that joins the Tx/Rx sides of two P82B96

devices. When one Tx drives LOW the other P82B96 Tx/Rx is driven to −0.8 V for over

50 ns. What is the expected value and the theoretically allowed value of undershoot?

Answer: Because the cable joining the two P82B96s is a ‘transmission line’ that will

have a characteristic impedance around 100 Ω and it will be terminated by pull-up

resistors that are larger than that characteristic impedance there will always be negative

undershoot generated. The duration of the undershoot is a function of the cable length

and the input impedance of the connected IC. As shown in Figure 23, the transient

undershoot will be limited, by the diodes inside P82B96, to around −0.8 V and that will

not cause problems for P82B96. Those transients will not be passed inside the IC to the

Sx/Sy side of the IC.

6

voltage

(V)

4

2

receive

send

0

−2

horizontal scale = 62.5 ns/div

time (ns)

5 V

300 Ω

5 V

300 Ω

5 V

Rx

Tx

Rx

Tx

Sx

send

receive

GND

2 meter

cable

P82B96

002aaf065

Fig 23. Wiring transients limited by the diodes in P82B96

Question: If we input 800 mV undershoot at Tx, Rx pins, what kind of problem is

expected?

Answer: When that undershoot is generated by another P82B96 and is simply the

result of the system wiring, then there will be no problems.

Question: Will we have any functional problem or reliability problem?

Answer: No.

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

21 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

Question: If we add 100 Ω to 200 Ω at signal line, the overshoot becomes slightly

smaller. Is this a good idea?

Answer: No, it is not necessary to add any resistance. When the logic signal generated

by Tx or Ty of P82B96 drives long traces or wiring with ICs other than P82B96 being

driven, then adding a Schottky diode (BAT54A) as shown in Figure 24 will clamp the

wiring undershoot to a value that will not cause conduction of the IC’s internal diodes.

6

voltage

(V)

4

2

send

0

receive

−2

horizontal scale = 62.5 ns/div

time (ns)

5 V

300 Ω

5 V

300 Ω

5 V

Rx

Tx

Rx

Tx

Sx

send

receive

2 meter

cable

1

/

BAT54A

P82B96

2

GND

002aaf066

Fig 24. Wiring transients limited by a Schottky diode

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

22 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

11. Package outline

DIP8: plastic dual in-line package; 8 leads (300 mil)

SOT97-1

D

M

E

A

2

A

1

L

c

w M

Z

b

1

e

(e )

1

M

H

b

2

8

5

pin 1 index

E

1

4

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

A

2

(1)

Z

1

w

UNIT

mm

b

c

D

E

e

L

M

H

1

2

1

E

max.

min.

max.

1.73

1.14

0.53

0.38

1.07

0.89

0.36

0.23

9.8

9.2

6.48

6.20

3.60

3.05

8.25

7.80

10.0

8.3

4.2

0.51

3.2

2.54

0.1

7.62

0.3

0.254

0.01

1.15

0.068 0.021 0.042 0.014

0.045 0.015 0.035 0.009

0.39

0.36

0.26

0.24

0.14

0.12

0.32

0.31

0.39

0.33

inches

0.17

0.02

0.13

0.045

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-13

SOT97-1

050G01

MO-001

SC-504-8

Fig 25. Package outline SOT97-1 (DIP8)

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

23 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

D

E

A

X

c

y

H

v

M

A

E

Z

5

8

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

4

e

w

M

detail X

b

p

0

2.5

5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.20

0.014 0.0075 0.19

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches 0.069

0.01 0.004

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT96-1

076E03

MS-012

Fig 26. Package outline SOT96-1 (SO8)

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

24 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm

SOT505-1

D

E

A

X

c

y

H

v

M

A

E

Z

5

8

A

(A )

2

A

3

A

1

pin 1 index

θ

L

p

L

1

4

detail X

e

w M

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

A

b

c

D

E

e

H

E

L

p

UNIT

v

w

y

Z

θ

1

2

3

p

max.

0.15

0.05

0.95

0.80

0.45

0.25

0.28

0.15

3.1

2.9

3.1

2.9

5.1

4.7

0.7

0.4

0.70

0.35

6°

0°

mm

1.1

0.65

0.25

0.94

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-04-09

03-02-18

SOT505-1

Fig 27. Package outline SOT505-1 (TSSOP8)

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

25 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

12. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

12.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

12.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

12.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

26 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

12.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 28) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 7 and 8

Table 7.

SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

≥ 350

220

< 2.5

235

220

≥ 2.5

220

Table 8.

Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 28.

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

27 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 28. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

13. Soldering of through-hole mount packages

13.1 Introduction to soldering through-hole mount packages

This text gives a very brief insight into wave, dip and manual soldering.

Wave soldering is the preferred method for mounting of through-hole mount IC packages

on a printed-circuit board.

13.2 Soldering by dipping or by solder wave

Driven by legislation and environmental forces the worldwide use of lead-free solder

pastes is increasing. Typical dwell time of the leads in the wave ranges from

3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb

or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic

body must not exceed the speciﬁed maximum storage temperature (T_stg(max)). If the

printed-circuit board has been pre-heated, forced cooling may be necessary immediately

after soldering to keep the temperature within the permissible limit.

13.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the

seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is

less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is

between 300 °C and 400 °C, contact may be up to 5 seconds.

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

28 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

13.4 Package related soldering information

Table 9.

Suitability of through-hole mount IC packages for dipping and wave soldering

Soldering method

Package

Dipping

Wave

CPGA, HCPGA

-

suitable

DBS, DIP, HDIP, RDBS, SDIP, SIL

PMFP^[2]

suitable

-

suitable^[1]

not suitable

[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit

board.

[2] For PMFP packages hot bar soldering or manual soldering is suitable.

14. Abbreviations

Table 10. Abbreviations

Acronym

CDM

DDC

Description

Charged Device Model

Display Data Channel

ElectroStatic Discharge

Human Body Model

Integrated Circuit

ESD

HBM

IC

I²C-bus

Inter IC bus

MM

Machine Model

SMBus

System Management Bus

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

29 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

15. Revision history

Table 11. Revision history

Document ID

P82B96_8

Release date

Data sheet status

Change notice

Supersedes

20091110

Product data sheet

-

P82B96_7

Modiﬁcations:

• Table 4 “Limiting values”: added Table note [1].

• Added Section 10.2 “Negative undershoot below absolute minimum value”.

P82B96_7

P82B96_6

P82B96_5

20090212

20080131

20060127

20040329

Product data sheet

Product data

-

P82B96_6

P82B96_5

P82B96_4

P82B96_3

P82B96_4

(9397 750 12932)

P82B96_3

(9397 750 11351)

20030402

20030220

20010306

Product data

853-2241 29602

of 2003 Feb 28

P82B96_2

P82B96_1

-

P82B96_2

(9397 750 11093)

853-2241 29410

of 2003 Jan 22

P82B96_1

(9397 750 08122)

853-2241 25758

of 2001 Mar 06

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

30 of 32

P82B96

NXP Semiconductors

Dual bidirectional bus buffer

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

16.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

P82B96_8

Product data sheet

Rev. 08 — 10 November 2009

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P82B96

NXP Semiconductors

Dual bidirectional bus buffer

18. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3

4

4.1

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7

Functional description . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6

8

9

10

10.1

Application information. . . . . . . . . . . . . . . . . . 10

Calculating system delays and bus clock

frequency for a Fast mode system . . . . . . . . . 15

Negative undershoot below absolute minimum

value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Example with questions and answers. . . . . . . 20

10.2

10.2.1

11

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23

12

Soldering of SMD packages . . . . . . . . . . . . . . 26

Introduction to soldering . . . . . . . . . . . . . . . . . 26

Wave and reﬂow soldering . . . . . . . . . . . . . . . 26

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 26

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 27

12.1

12.2

12.3

12.4

13

13.1

Soldering of through-hole mount packages . 28

Introduction to soldering through-hole mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Soldering by dipping or by solder wave . . . . . 28

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 28

Package related soldering information . . . . . . 29

13.2

13.3

13.4

14

15

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 30

16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 31

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31

16.1

16.2

16.3

16.4

17

18

Contact information. . . . . . . . . . . . . . . . . . . . . 31

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 10 November 2009

Document identifier: P82B96_8


型号：	P82B96PN,112
厂家：	NXP
描述：	P82B96 - Dual bidirectional bus buffer DIP 8-Pin 驱动光电二极管接口集成电路驱动器
文件：	总32页 (文件大小：193K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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