P82B96 [NXP]
Dual bi-directional bus buffer; 双路双向总线缓冲器
| 型号： | P82B96 |
| 厂家： | 
NXP |
| 描述： | Dual bi-directional bus buffer |
| 文件： | 总16页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
P82B96
Dual bi-directional bus buffer
Product data
2004 Mar 26
Supersedes data of 2003 Apr 02
Philips
Semiconductors
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
PIN CONFIGURATIONS
8-pin dual in-line, SO, TSSOP
Sx
Rx
1
2
3
4
8
7
6
5
V
CC
Sy
Tx
Ry
Ty
FEATURES
GND
2
• Bi-directional data transfer of I C-bus signals
• Isolates capacitance allowing 400 pF on Sx/Sy side and
SU01011
4000 pF on Tx/Ty side
• Tx/Ty outputs have 60 mA sink capability for driving
low impedance or high capacitive buses
PINNING
• 400 kHz operation over at least 20 meters of wire (see AN10148)
SYMBOL
PIN
1
DESCRIPTION
2
• Supply voltage range of 2 V to 15 V with I C logic levels on Sx/Sy
2
Sx
Rx
I C-bus (SDA or SCL)
Receive signal
side independent of supply voltage
2
2
• Splits I C signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals
for interface with opto-electrical isolators and similar devices that
need uni-directional input and output signal paths.
Tx
3
Transmit signal
Negative Supply
Transmit signal
Receive signal
GND
Ty
4
• Low power supply current
• ESD protection exceeds 3500 V HBM per JESD22-A114,
250 V DIP package / 400 V SO package MM per JESD22-A115,
and 1000 V CDM per JESD22-C101
5
Ry
6
2
Sy
7
I C-bus (SDA or SCL)
• Latch-up free (bipolar process with no latching structures)
• Packages offered: DIP, SO, and TSSOP
V
8
Positive supply
CC
SPECIAL NOTE:
Two or more Sx or Sy I/Os must not be interconnected. The P82B96
design does not support this configuration. Bi-directional I C signals
TYPICAL APPLICATIONS
2
2
• Interface between I C buses operating at different logic levels
do not allow any direction control pin so, instead, slightly different
logic low voltage levels are used at Sx/Sy to avoid latching of this
(e.g., 5 V and 3 V or 15 V)
2
2
buffer. A “regular I C low” applied at the Rx/Ry of a P82B96 will be
• Interface between I C and SMB (350 µA) bus standard.
propagated to Sx/Sy as a “buffered low” with a slightly higher
voltage level. If this special “buffered low” is applied to the Sx/Sy of
another P82B96 that second P82B96 will not recognize it as a
2
• Simple conversion of I C SDA or SCL signals to multi-drop
differential bus hardware, e.g., via compatible PCA82C250.
2
• Interfaces with Opto-couplers to provide Opto isolation between
“regular I C-bus low” and will not propagate it to its Tx/Ty output.
2
I C-bus nodes up to 400 kHz.
The Sx/Sy side of P82B96 may not be connected to similar buffers
that rely on special logic thresholds for their operation, for example
PCA9511, PCA9515, or PCA9518. The Sx/Sy side is only intended
DESCRIPTION
The P82B96 is a bipolar IC that creates a non-latching,
bi-directional, logic interface between the normal I C-bus and a
range of other bus configurations. It can interface I C-bus logic
2
2
for, and compatible with, the normal I C logic voltage levels of I C
master and slave chips—or even Tx/Rx signals of a second P82B96
2
2
if required. The Tx/Rx and Ty/Ry I/O pins use the standard I C logic
voltage levels of all I C parts. There are NO restrictions on the
2
2
signals to similar buses having different voltage and current levels.
interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s,
for example in a star or multi-point configuration with the Tx/Rx and
Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to
the line card slave devices. For more details see Application
Note AN255.
For example it can interface to the 350 µA SMB bus, to 3.3 V logic
devices, and to 15 V levels and/or low impedance lines to improve
noise immunity on longer bus lengths.
2
It achieves this interface without any restrictions on the normal I C
protocols or clock speed. The IC adds minimal loading to the I C
node, and loadings of the new bus or remote I C nodes are not
2
2
transmitted or transformed to the local node. Restrictions on the
2
number of I C devices in a system, or the physical separation
between them, are virtually eliminated. Transmitting SDA/SCL
signals via balanced transmission lines (twisted pairs) or with
galvanic isolation (opto-coupling) is simple because separate
directional Tx and Rx signals are provided. The Tx and Rx signals
may be directly connected, without causing latching, to provide an
2
alternative bi-directional signal line with I C properties.
2
2004 Mar 26
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
TOPSIDE MARK
DRAWING NUMBER
8-pin plastic dual In-line package
8-pin plastic small outline package
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
P82B96PN
P82B96TD
P82B96DP
P82B96PN
P82B96T
82B96
SOT97-1
SOT96-1
SOT505-1
8-pin plastic thin shrink small outline package
NOTE:
1. Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
BLOCK DIAGRAM
+V (2–15 V)
CC
8
3
2
1
Sx (SDA)
Tx (TxD, SDA)
Rx (RxD, SDA)
5
6
7
Ty (TxD, SCL)
Ry (RxD, SCL)
Sy (SCL)
P82B96
4
GND
SU01012
FUNCTIONAL DESCRIPTION
The P82B96 has two identical buffers allowing buffering of both of
Tx is an open collector output without ESD protection diodes to V
.
CC
2
the I C (SDA and SCL) signals. Each buffer is made up of two logic
It may be connected via a pull-up resistor to a supply voltage in
excess of V as long as the 15 V rating is not exceeded. It has a
2
signal paths, a forward path from the I C interface pin which drives
CC,
2
the buffered bus, and a reverse signal path from the buffered bus
larger current sinking capability than a normal I C device, being able
to sink a static current of greater than 30 mA, and typical 100 mA
dynamic pull-down capability as well.
2
input to drive the I C-bus interface.
Thus these paths are:
1. Sense the voltage state of the I C pin Sx (or Sy) and transmit
2
2
A logic LOW is only transmitted to Tx when the voltage at the I C
2
this state to the pin Tx (Ty resp.), and
pin (Sx) is below 0.6 V. A logic LOW at Rx will cause the I C-bus
2
(Sx) to be pulled to a logic LOW level in accordance with I C
2
2. Sense the state of the pin Rx (Ry) and pull the I C pin LOW
requirements (max. 1.5 V in 5 V applications) but not low enough to
be looped back to the Tx output and cause the buffer to latch LOW.
whenever Rx (Ry) is LOW.
2
The rest of this discussion will address only the “x” side of the buffer:
the “y” side is identical.
The minimum LOW level this chip can achieve on the I C-bus by a
LOW at Rx is typically 0.8 V.
2
2
2
The I C pin (Sx) is designed to interface with a normal I C-bus.
If the supply voltage V fails, then neither the I C nor the Tx output
CC
will be held LOW. Their open collector configuration allows them to
2
The logic threshold voltage levels on the I C-bus are independent of
be pulled up to the rated maximum of 15 V even without V
CC
2
the IC supply V The maximum I C-bus supply voltage is 15 V and
the guaranteed static sink current is 3 mA.
CC
present. The input configuration on Sx and Rx also present no
loading of external signals even when V is not present.
CC
The logic level of Rx is determined from the power supply voltage
The effective input capacitance of any signal pin, measured by its
effect on bus rise times, is less than 7 pF for all bus voltages and
V
CC
of the chip. Logic LOW is below 42 % of V , and logic HIGH is
CC
above 58 % of V : with a typical switching threshold of half V
CC
CC.
supply voltages including V = 0 V.
CC
3
2004 Mar 26
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages with respect to pin GND (pin 4).
SYMBOL
PARAMETER
MIN.
–0.3
–0.3
–0.3
–0.3
—
MAX.
+18
+18
+18
+18
250
UNIT
V
V
V
V
V
I
to GND
Supply voltage range V
CC
bus
Tx
CC
2
Voltage range on I C Bus, SDA or SCL
Voltage range on buffered output
Voltage range on receive input
DC current (any pin)
V
V
V
Rx
mA
mW
°C
°C
R
Power dissipation
—
300
tot
T
stg
Storage temperature range
Operating ambient temperature range
–55
–40
+125
+85
T
amb
CHARACTERISTICS
At T
= 25 °C; Voltages are specified with respect to GND with V = 5 V unless otherwise stated.
amb
CC
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Power Supply
V
Supply voltage (operating)
Supply current, buses HIGH
2.0
—
—
—
—
15
V
CC
I
I
I
0.9
1.1
1.7
1.8
2.5
3.5
mA
mA
mA
CC
Supply current at V = 15 V, buses HIGH
CC
CC
CC
Additional supply current per Tx or Ty LOW
Bus pull-up (load) voltages and currents
V
, V
Maximum input/output voltage level
Open collector;
—
0.2
7
—
—
18
—
1
15
3
V
Sx
Sy
2
I C-bus and V , V = HIGH
Rx
Ry
2
I
I
I
I
, I
Static output loading on I C-bus (Note 1)
V
Sx
V
Rx
, V = 1.0 V;
, V = LOW
Ry
mA
mA
µA
µA
Sx Sy
Sy
2
, I
Dynamic output sink capability on I C-bus
V
Sx
V
Rx
, V > 2 V;
, V = LOW
Ry
—
1
Sx Sy
Sy
2
, I
Leakage current on I C-bus
V
Sx
V
Rx
, V = 5 V;
, V = HIGH
Ry
—
—
Sx Sy
Sy
2
, I
Leakage current on I C-bus
V
Sx
V
Rx
, V = 15 V;
, V = HIGH
Ry
—
Sx Sy
Sy
V
, V
Maximum output voltage level
Open collector
—
—
—
—
15
30
V
Tx
Ty
I
I
I
, I
Static output loading on buffered bus
V
Tx
V
Sx
, V = 0.4 V;
, V = LOW on I C-bus = 0.4 V
Sy
mA
Tx Ty
Ty
2
, I
Dynamic output sink capability, buffered bus
Leakage current on buffered bus
V
Tx
V
Sx
, V > 1 V
, V = LOW on I C-bus = 0.4 V
Sy
60
—
100
1
—
—
mA
Tx Ty
Ty
2
, I
V
Tx
V
Sx
, V = V = 15 V;
, V = HIGH
Sy
µA
Tx Ty
Ty
CC
Input Currents
2
I
I
I
, I
Input current from I C-bus
bus LOW
, V = HIGH
—
—
—
–1
–1
1
—
—
—
µA
µA
µA
Sx Sy
V
Rx
Ry
, I
Rx Ry
Input current from buffered bus
bus LOW
V
Rx
, V = 0.4 V
Ry
, I
Rx Ry
Leakage current on buffered bus input
V
Rx
, V = V
Ry CC
Output Logic LOW Levels
2
V
, V
Output logic level LOW, on normal I C bus
(Note 2)
I
I
I
, I = 3 mA
0.8
670
—
0.88
730
1.0
790
—
V
Sx
Sy
Sx Sy
2
V
Sx
, V
Sy
Output logic level LOW, on normal I C bus
, I = 0.2 mA
Sx Sy
mV
(Note 2)
dV /dT,
dV /dT
Temperature coefficient of output LOW
levels (Note 2)
, I = 0.2 mA
Sx Sy
–1.8
mV/K
Sx
Sy
4
2004 Mar 26
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input logic switching threshold voltages
2
V
V
, V
, V
Input logic voltage LOW (Note 3)
On normal I C-bus
—
700
—
640
650
–2
600
—
mV
mV
Sx
Sy
2
Input logic level HIGH threshold (Note 3)
Temperature coefficient of input thresholds
On normal I C-bus
Sx
Sy
dV /dT,
—
mV/K
Sx
dV /dT
Sy
V
Rx
V
Rx
V
Rx
, V
Ry
, V
Ry
, V
Ry
Input logic HIGH level
Input threshold
Fraction of applied V
Fraction of applied V
Fraction of applied V
0.58
—
—
0.5
—
—
—
V
V
V
CC
CC
CC
Input logic LOW level
—
0.42
Logic level threshold difference
, V Input/Output logic level difference (Note 1)
V
Sx
V
SX
V
SX
output LOW at 0.2 mA –
input HIGH max
50
85
—
mV
Sy
NOTES:
1. The minimum value requirement for pull-up current, 200 µA, guarantees that the minimum value for V output LOW will always exceed the
SX
minimum V input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC. While
SX
the tolerances on absolute levels allow a small probability the LOW from one S output is recognized by an S input of another P82B96 this
X
X
has no consequences for normal applications. In any design the S pins of different ICs should never be linked because the resulting system
X
2
would be very susceptible to induced noise and would not support all I C operating modes.
2. The output logic LOW depends on the sink current. For scaling, see Application Note AN255.
3. The input logic threshold is independent of the supply voltage.
CHARACTERISTICS
At T
= 25 °C; Voltages are specified with respect to GND with V = 5 V unless otherwise stated.
amb
CC
SYMBOL
Bus Release on V Failure
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CC
V
V
, V
,
V voltage at which all buses are
CC
guaranteed to be released
—
—
—
1
V
Sx
Tx
Sy
, V
Ty
dV/dT
Temperature coefficient of guaranteed release
voltage
–4
—
mV/K
Buffer response time
Buffer time delay on FALLING input between
T
R
pull-up = 160 Ω,
—
—
—
—
70
90
—
—
—
—
ns
ns
ns
ns
fall delay
Tx
V
Sx
V
Sy
to V
to V
V
= input switching threshold,
no capacitive load, V = 5 V
Tx
Ty
Sx
CC
and V output falling 50%.
Tx
T
Buffer time delay on RISING input between
R
Tx
pull-up = 160 Ω,
rise delay
V
Sx
V
Sy
to V
to V
V
= input switching threshold,
no capacitive load, V = 5 V
Tx
Ty
Sx
CC
and V output reaching 50% V
Tx
CC
T
V
V
Buffer time delay on FALLING input between
= input switching threshold,
R
pull-up = 1500 Ω, no
Sx
250
270
fall delay
to V
to V
V
Rx
capacitive load, V = 5 V
Rx
Ry
Sx
Sy
CC
and V output falling 50%.
Sx
T
Buffer time delay on RISING input between
R
pull-up = 1500 Ω,
Sx
rise delay
V
Rx
V
Ry
to V
to V
V
= input switching threshold,
no capacitive load, V = 5 V
Sx
Sy
Rx
CC
and V output reaching 50% V
Sx
CC
Input capacitance
C
Effective input capacitance of any signal pin
measured by incremental bus rise times
—
—
7
pF
in
NOTES ON RESPONSE TIME
The fall-time of V from 5 V to 2.5 V in the test is approximately 15 ns.
TX
The fall-time of V from 5 V to 2.5 V in the test is approximately 50 ns.
SX
The rise-time of V from 0 V to 2.5 V in the test is approximately 20 ns.
TX
The rise-time of V from 0.9 V to 2.5 V in the test is approximately 70 ns.
SX
5
2004 Mar 26
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
TYPICAL APPLICATIONS
See AN460 and AN255 for more application detail.
+V (2–15 V)
CC
+5 V
R1
2
I C
SDA
‘SDA’
(NEW LEVELS)
Tx
(SDA)
Rx
(SDA)
1/2 PB2B96
SU01013
2
Figure 1. Interfacing an ‘I C’ type of bus with different logic levels.
+V
CC1
+V
CC
R4
R2
R5
R3
2
I C
SDA
+5 V
R1
Rx
(SDA)
2
I C
SDA
Tx
(SDA)
1/2 P82B96
SU01014
2
Figure 2. Galvanic isolation of I C nodes via opto-couplers
MAIN ENCLOSURE
12 V
REMOTE CONTROL ENCLOSURE
12 V
3.3–5 V
3.3–5 V
LONG CABLES
SCL
SCL
12 V
3.3–5 V
3.3–5 V
SDA
SDA
P82B96
P82B96
SU01708
2
Figure 3. Long distance I C communications
6
2004 Mar 26
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
V
CC1
+V CABLE DRIVE
+V CABLE DRIVE
V
CC2
V
CC
V
CC
BC
847B
R
X
3 – 20 m CABLES
R
X
T
S
S
X
X
S
S
T
X
X
SCL
SCL
2
2
I C/DDC
SLAVE
R
I C/DDC
MASTER
Y
2
I C/DDC
R
Y
4K7
T
Y
Y
T
Y
Y
SDA
SDA
470 kΩ
BC
847B
P82B96
P82B96
470 kΩ
GND
MONITOR/FLAT TV
GND
PC/TV RECEIVER/DECODER BOX
R
G
B
su01785
VIDEO SIGNALS
Figure 4. Extending a DCC bus
2
Figure 4 shows how a master I C-bus can be protected against
short circuits or failures in applications that involve plug/socket
connections and long cables that may become damaged. A simple
circuit is added to monitor the SDA bus and if its LOW time exceeds
the design value then the master bus is disconnected. P82B96 will
free all its I/Os if its supply is removed, so one option is to connect
is better treated using transmission line theory. Flat ribbon cables
connected as shown, with the bus signals on the outer edge, will
have a characteristic impedance in the range 100 – 200 Ω. For
simplicity they cannot be terminated in their characteristic
impedance but a practical compromise is to use the minimum
pull-up allowed for P82B96 and place half this termination at each
end of the cable. When each pull-up is below 330 Ω, the rising edge
waveforms have their first voltage ‘step’ level above the logic
threshold at Rx and cable timing calculations can be based on the
fast rise/fall times of resistive loading plus simple one-way
propagation delays. When the pull-up is larger, but below 750 Ω, the
threshold at Rx will be crossed after one signal reflection. So at the
sending end it is crossed after 2 times the one-way propagation
delay and at the receiving end after 3 times that propagation delay.
For flat cables with partial plastic dielectric insulation (by using outer
cores) the one-way propagation delays will be about 5 ns/meter.
The 10% to 90% rise and fall times on the cable will be between
20 ns and 50 ns, so their delay contributions are small. There will be
ringing on falling edges that can be damped, if required, using
Schottky diodes as shown.
its V to the output of a logic gate from, say, the 74LVC family. The
SDA and SCL lines could be timed and V disabled via the gate if
one or other lines exceeds a design value of ‘LOW’ period as in
Figure 28 of AN255. If the supply voltage of logic gates restricts the
choice of V supply then the low-cost discrete circuit in Figure 4
can be used. If the SDA line is held LOW, the 100 nF capacitor will
charge and the R input will be pulled towards V . When it
exceeds V /2 the R input will set the S input HIGH, which in
practice means simply releasing it.
CC
CC
CC
y
CC
CC
y
y
In this example the SCL line is made uni-directional by tying the R
pin to V . The state of the buffered SCL line cannot affect the
master clock line which is allowed when clock-stretching is not
required. It is simple to add an additional transistor or diode to
control the R input in the same way as R when necessary. The +V
x
CC
x
y
cable drive can be any voltage up to 15 V and the bus may be run at
a lower impedance by selecting pull-up resistors for a static sink
When the Master SCL HIGH and LOW periods can be programmed
separately, e.g. using control registers I2SCLH and I2SCLL of
89LPC932, the timings can allow for bus delays. The LOW period
should be programmed to achieve the minimum 1300 ns plus the
net delay in the slave’s response data signal caused by bus and
buffer delays. The longest data delay is the sum of the delay of the
falling edge of SCL from master to slave and the delay of the rising
edge of SDA from slave data to master. Because the buffer will
‘stretch’ the programmed SCL LOW period, the actual SCL
current up to 30 mA. V
and V
may be chosen to suit the
CC1
CC2
connected devices. Because DDC uses relatively low speeds
2
(<100 kHz), the cable length is not restricted to 20 m by the I C
signalling, but it may be limited by the video signalling.
Figure 5 shows that P82B96 can achieve high clock rates over long
cables. While calculating with lumped wiring capacitance yields
reasonable approximations to actual timing, even 25 meters of cable
7
2004 Mar 26
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
frequency will be lower than calculated from the programmed clock
periods. In the example for 25 meters the clock is stretched 400 ns,
the falling edge of SCL is delayed 490 ns and the SDA rising edge is
delayed 570 ns. The required additional LOW period is
Note that in both the 100-meter and 250-meter examples the
capacitive loading on the I C-buses at each end is within the
2
maximum allowed Standard mode loading of 400 pF, but exceeds
the Fast mode limit. This is an example of a ‘hybrid’ mode because it
relies on the response delays of Fast mode parts but uses
(allowable) Standard mode bus loadings with rise times that
contribute significantly to the system delays. The cables cause large
propagation delays so these systems need to operate well below the
400 kHz limit but illustrate how they can still exceed the 100 kHz
limit provided all parts are capable of Fast mode operation. The
fastest example illustrates how the 400 kHz limit can be exceeded
provided master and slave parts have delay specifications smaller
than the maximum allowed. Many Philips slaves have delays shorter
than 600 ns, but none have that guaranteed.
2
(490 + 570) = 1060 ns and the I C-bus specifications already
include an allowance for a worst case bus risetime 0 to 70% of
425 ns. (The bus risetime can be 300 ns 30% to 70%, which means
it can be 425 ns 0–70%. The 25-meter cable delay times as quoted
already include all rise/fall times.) Therefore, the micro only needs to
be programmed with an addtional (1060 – 400 – 425) = 235 ns,
making a total programmed LOW period 1535 ns. The programmed
LOW will the be stretched by 400 ns to yield an actual bus LOW
time of 1935 ns, which, allowing the minimum HIGH period of
600 ns, yields a cycle period of 2535 ns or 394 kHz.
+V CABLE DRIVE
V
V
CC1
CC2
R2
R2
V
V
CC
CC
R2
R1
R1
R1
R1
R2
R
T
R
T
X
X
SCL
SDA
C2
S
S
S
SCL
SDA
C2
X
X
X
X
2
2
R
Y
R
Y
I C
I C
MASTER
SLAVE(S)
T
S
T
Y
Y
Y
Y
CABLE
P82B96
P82B96
PROPAGATION
DELAY ' 5 ns/m
C2
C2
GND
GND
BAT54A
BAT54A
su01786
Figure 5. Driving ribbon or flat telephone cables
EXAMPLES OF BUS CAPABILITY (refer to Figure 5)
SET MASTER
NOMINAL SCL
EFFECTIVE
BUS
CLOCK
MAXIMUM
SLAVE
RESPONSE
+V
CABLE
C2
CABLE
CABLE
CABLE
+V
CC1
+V
CC2
R1
R2
(pF) LENGTH CAPACITANCE DELAY
HIGH
LOW
SPEED
DELAY
PERIOD PERIOD
Normal spec.
400 kHz
parts
Not applicable
(delay based)
5 V
12 V
12 V
5 V
750 2.2 k 400
750 2.2 k 220
250 m
100 m
1.25 µs
600 ns
600 ns
4000 ns
2600 ns
120 kHz
185 kHz
Normal spec.
400 kHz
parts
Not applicable
(delay based)
5 V
5 V
500 ns
Normal spec.
400 kHz
parts
3.3 V
3.3 V
5 V
5 V
3.3 V 330
3.3 V 330
1 k
1 k
220
100
25 m
3 m
1 nF
125 ns
15 ns
600 ns
600 ns
1500 ns
1000 ns
390 kHz
500 kHz
120 pF
600 ns
8
2004 Mar 26
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
CALCULATING SYSTEM DELAYS AND BUS CLOCK FREQUENCY FOR A FAST MODE SYSTEM
LOCAL MASTER BUS
BUFFERED EXPANSION BUS
REMOTE SLAVE BUS
V
V
V
CCS
CCM
CCB
Rm
Rb
Rs
SCL
SCL
MASTER
SLAVE
Sx
Tx/Rx
Tx/Rx
Sx
P82B96
P82B96
2
2
I C
I C
Cm = MASTER BUS
CAPACITANCE
Cb = BUFFERED BUS
WIRING CAPACITANCE
Cs = SLAVE BUS
CAPACITANCE
GND/0 V
A) FALLING EDGE OF SCL AT MASTER IS DELAYED BY THE BUFFERS AND BUS FALL TIMES
9
(ns) C = F, V = VOLTS
CCB
EFFECTIVE DELAY OF SCL AT SLAVE = 255 + 17 V
+ (2.5 + 4 × 10 Cb) V
su01787
CCM
Figure 6.
LOCAL MASTER BUS
BUFFERED EXPANSION BUS
V
V
CCB
CCM
Rb
Rm
SCL
MASTER
Sx
Tx/Rx
Tx/Rx
P82B96
2
I C
Cm = MASTER BUS
CAPACITANCE
Cb = BUFFERED BUS
WIRING CAPACITANCE
GND/0 V
B) RISING EDGE OF SCL AT MASTER IS DELAYED (CLOCK STRETCH) BY BUFFER AND BUS RISE TIMES
EFFECTIVE DELAY OF SCL AT MASTER = 270 + RmCm + 0.7RbCb (ns), C = F, R = Ω
su01788
Figure 7.
9
2004 Mar 26
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
LOCAL MASTER BUS
BUFFERED EXPANSION BUS
REMOTE SLAVE BUS
V
V
V
CCS
CCM
CCB
Rm
Rb
Rs
SDA
SDA
MASTER
SLAVE
Sx
Tx/Rx
Tx/Rx
Sx
P82B96
P82B96
2
2
I C
I C
Cm = MASTER BUS
CAPACITANCE
Cb = BUFFERED BUS
WIRING CAPACITANCE
Cs = SLAVE BUS
CAPACITANCE
GND/0 V
C) RISING EDGE OF SDA AT SLAVE IS DELAYED BY THE BUFFERS AND BUS RISE TIMES
EFFECTIVE DELAY OF SDA AT MASTER = 270 + 0.2RsCs + 0.7 (RbCb + RmCm) (ns), C = F, R = Ω
su01789
Figure 8.
Figures 6, 7, and 8 show the P82B96 used to drive extended bus
wiring, with relatively large capacitance, linking two Fast mode
I C-bus nodes. It includes simplified expressions for making the
relevant timing calculations for 3.3/5 V operation. Because the
buffers and the wiring introduce timing delays, it may be necessary
to decrease the nominal SCL frequency below 400 kHz. In most
cases the actual bus frequency will be lower than the nominal
Master timing due to bit-wise stretching of the clock periods.
extend that minimum clock low period by any “effective” delay of the
Slave’s response. The effective delay of the slaves response = total
delays in SCL falling edge from the Master reaching the Slave (A) –
the effective delay (stretch) of the SCL rising edge (B) + total delays
in the Slave’s response data, carried on SDA, reaching the
Master (C).
2
The Master microcontroller should be programmed to produce a
nominal SCL LOW period = (1300 + A – B + C) ns, and should be
programmed to produce the nominal minimum SCL HIGH period of
600 ns. Then a check should be made to ensure the cycle time is
not shorter than the minimum 2500 ns. If found necessary, just
increase either clock period.
The delay factors involved in calculation of the allowed bus speed
are:
A) The propagation delay of the Master signal through the buffers
and wiring to the Slave. The important delay is that of the falling
edge of SCL because this edge ‘requests’ the data or
Acknowledge from a Slave.
Due to clock stretching, the SCL cycle time will always be longer
than (600 + 1300 + A + C) ns.
B) The effective stretching of the nominal LOW period of SCL at the
Master caused by the buffer and bus rise times
Example:
The Master bus has an RmCm product of 100 ns and V
= 5 V.
CCM
C) The propagation delay of the Slave’s response signal through the
buffers and wiring back to the Master. The important delay is
that of a rising edge in the SDA signal. Rising edges are always
slower and are therefore delayed by a longer time than falling
edges. (The rising edges are limited by the passive pull-up while
falling edges are actively driven)
The buffered bus has a capacitance of 1 nF and a pull-up resistor of
160 ohms to 5 V giving an RbCb product of 160 ns. The Slave bus
also has an RsCs product of 100 ns.
The microcontroller LOW period should be programmed to
≥ (1300 + 372.5 – 482 + 472) ns, that is ≥ 1662.5 ns.
2
The timing requirement in any I C system is that a Slave’s data
Its HIGH period may be programmed to the minimum 600 ns.
response (which is provided in response to a falling edge of SCL)
must be received at the Master before the end of the corresponding
low period of SCL as appears on the bus wiring at the Master. Since
all Slaves will, as a minimum, satisfy the worst case timing
The nominal microcontroller clock period will be
≥ (1662.5 + 600) ns = 2262.5 ns, equivalent to a frequency of
442 kHz.
requirements of a 400 kHz part, they must provide their response
within the minimum allowed clock LOW period of 1300 ns. Therefore
in systems that introduce additional delays it is only necessary to
The actual bus clock period, including the 482 ns clock stretch
effect, will be below (nominal + stretch) = (2262.5 + 482) ns or
≥ 2745 ns, equivalent to an allowable frequency of 364 kHz.
10
2004 Mar 26
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
12 V
12 V
TWISTED-PAIR TELEPHONE WIRES,
USB, OR FLAT RIBBON CABLES.
UP TO 15 V LOGIC LEVELS,
3.3–5 V
INCLUDE V AND GND.
CC
T
X
S
X
SCL
R
X
3.3–5 V
12 V
T
Y
S
3.3 V 3.3 V
Y
SDA
R
Y
P82B96
P82B96
P82B96
P82B96
P82B96
S
S
S
S
S
S
Y
X
Y
X
Y
X
S
S
SDA
SCL
Y
X
SCL/SDA
SCL/SDA
SCL/SDA
NO LIMIT TO THE NUMBER OF CONNECTED BUS DEVICES.
su01709
2
Figure 9. I C multi-point applications
ch1: freq = 624 kHz
ch1: freq = 624 kHz
Rx
Tx
Sx
10 V
5 V
Sx
0 V
CH1!2.00V = AVG
CH2!2.00V = BWL MTB 200 ns – 0.98dvch1+
CH1!2.00V = AVG
CH2!2.00V = BWL MTB 200 ns – 0.98dvch1+
SU01069
Horiz: 200 ns/div. VertL 2 V/div.
SU01070
Horiz: 200 ns/div. VertL 2 V/div.
Figure 10. Propagation Sx to Tx — Sx pull-up to 5V,
Tx pull-up to V = 10 V
Figure 11. Propagation Rx to Sx — Sx pull-up to 5V,
Rx pull-up to V = 10 V
CC
CC
11
2004 Mar 26
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
12
2004 Mar 26
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
13
2004 Mar 26
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
14
2004 Mar 26
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
REVISION HISTORY
Rev
Date
Description
_4
20040326
Product data (9397 750 12932). Supersedes data of 2003 Apr 02 (9397 750 11351).
Modifications:
• Page 2:
– Features section re-written.
– Add “TSSOP” to heading for pin configurations
• Page 3, Ordering information table: correct description of TSSOP8 package.
• Page 5, (continued) Characteristics table, Note 1,
– third sentence:
from “... the LOW from on S output ...”
X
to “... the LOW from one S output ...”
X
– fourth sentence:
from “In any design the S pins of different ICs because the resulting ...”
X
to “In any design the S pins of different ICs should never be linked because the resulting ...”
X
• Figure 4: Change 2 transistors to bipolar type. Add dashed line between V
and V , and between V
CC CC2
CC1
and V to indicate optional/allowed links.
CC
• Figure 5: Add dashed line between V
and V , and between V
and V to indicate optional/allowed
CC2 CC
CC1
CC
links.
• Page 8, table “Examples of bus capability”:
– cable capacitance 1 nF:
change LOW period from “1600 ns” to “1500 ns”
change Effective bus clock speed from “380 kHz” to “390 kHz”
– change cable capacitance “120 nF” to “120 pF”
• Add title “Calculating system delays and bus clock frequency for a Fast mode system” on page 9.
• Add V label to Figures 6, 7 and 8.
CCB
• Page 10, “Example:” paragraphs 3, 5 and 6: values corrected in equations.
• Add signal names to Figure 9.
• Add package outline drawing SOT505-1.
_3
_2
_1
20030402
20030226
20010306
Product data (9397 750 11351); ECN 853-2241 29602 dated 28 February 2003.
Supersedes data of 2003 Jan 22 (9397 750 11093)
Product data (9397 750 11093); ECN 853-2241 29410 of 22 January 2003;
supersedes data of 2001 Mar 06 (9397 750 08122)
Product data (9397 750 08122); ECN 853-2241 25758 of 2001 Mar 06.
15
2004 Mar 26
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent
2
to use the components in the I C system provided the system conforms to the
I C specifications defined by Philips. This specification can be ordered using the
2
code 9398 393 40011.
Data sheet status
Product
status
Definitions
[1]
Level
Data sheet status
[2] [3]
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys
nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2004
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 03-04
9397 750 12932
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
相关型号：
P82B96DP-T
Dual bidirectional bus buffer - I2C-bus: 400 kHz; Inputs: 1 ; Operating temperature: -40~85 Cel; Operating voltage: 2.0~15.0 VDC; Outputs: 1
NXP
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