P83C566 [NXP]
Microcontrollers for PAL/SECAM TV with OSD and VST; 为PAL / SECAM电视微控制器,具有OSD和VST型号: | P83C566 |
厂家: | NXP |
描述: | Microcontrollers for PAL/SECAM TV with OSD and VST |
文件: | 总92页 (文件大小:384K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
P8xCx66 family
Microcontrollers for PAL/SECAM
TV with OSD and VST
1999 Mar 10
Product specification
File under Integrated Circuits, IC20
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
CONTENTS
1
FEATURES
2
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
3
4
5
PINNING INFORMATION
MEMORY ORGANIZATION
I/O FACILITY
6
7
8
TIMERS AND EVENT COUNTERS
REDUCED POWER MODE
I2C-BUS SERIAL I/O
9
10
11
12
13
14
15
16
17
18
19
INTERRUPT SYSTEM
OSCILLATOR CIRCUITRY
RESET CIRCUITRY
PIN FUNCTION SELECTION
ANALOG CONTROL
ANALOG-TO-DIGITAL CONVERTERS (ADC)
ON-SCREEN DISPLAY (OSD)
EPROM PROGRAMMER
SPECIAL FUNCTION REGISTERS
ADDRESS MAP
20
21
22
23
24
25
26
27
LIMITING VALUES
CHARACTERISTICS
PINNING CHARACTERIZATION
PACKAGE OUTLINES
SOLDERING
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
1999 Mar 10
2
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
1
FEATURES
1.1
P80C51 CPU core
• 80C51 8-bit CPU
• 64-kbyte Multiple Programming ROM (MTP ROM)
• Two 16-bit timer/event counters
– 110 horizontal starting positions controlled by
• Crystal oscillator for system clock (up to 12 MHz)
software
• 12 source, 12 vector interrupt structure with two priority
levels
– Character size: 4 different character sizes on a
line-by-line basis
• Enhanced architecture with:
– Character matrix: 12 × 18 with no spacing between
– Non-page orientated instructions
– Direct addressing
characters
– Foreground colours: 8 on a character-by-character
basis
– Four 8-byte RAM register banks
– Stack depth up to 128 bytes
– Background/shadowing modes: two primary modes -
TV mode and Frame mode on a frame basis. Each
primary mode has four sub-modes on a line basis:
Sub-mode 1: Superimpose (no background)
Sub-mode 2: North-West shadowing
– Multiply, divide, subtract and compare instructions.
1.2
P8xCx66 family
• ROM/RAM: see Table 1
Sub-mode 3: Box background
Sub-mode 4: Border shadowing
• Pulse Width Modulated (PWM) outputs:
– Background colours: 8 on a word-by-word basis,
available in all four sub-modes
– One 14-bit PWM output for Voltage Synthesized
Tuning (VST)
– Display RAM starting address is programmable; fast
switching between banks of display (RAM)
– Eight 7-bit PWM outputs for analog controls.
• 3 Analog-to-Digital (ADC) inputs with 4-bit DAC and
comparator
characters is possible through software control
– HSYNC driven PLL for OSD clock (4 to 12 MHz)
– Character blinking ratio: 1 : 1
• LED driver port:
– All I/O port lines with 10 mA LED drive capability
(VO <1.0 V)
– Character blinking frequency: programmable using
fVSYNC divisors of 32 and 64, on a character basis
– Up to 5 LEDs can be driven at any one time.
– Flexible display format using the Carriage Return
code and the Space codes
• Serial I/O:
– Multi-master I2C-bus interface
– Maximum I2C-bus frequency 400 kHz.
• Watchdog timer
– Display RAM address post incremented each time
new data is written into RAM
– Vertical jitter cancelling circuit to avoid unstable
VSYNC leading edge mismatch with HSYNC signal
• Improved EMC measures and slope controlled I/Os
• OSD functions:
– OSD meshing.
• Power-on reset
– Programmable VSYNC and HSYNC active levels
– Display RAM: 192 × 12 bits
• Packages: SDIL42 (PLCC68 for piggy-back only)
• Operating voltage: 4.5 to 5.5 V
• Operating temperature: −20 to +70 °C
• System clock frequency: 4 to 12 MHz
• OSD clock frequency: 4 to 12 MHz.
– Display character fonts: 128 (126 customer fonts plus
2 reserved codes)
– 63 vertical starting positions controlled by software
1999 Mar 10
3
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
The Philips 80C51 CPU is object code compatible with the
industry standard 80C51. All devices are manufactured in
an advanced CMOS technology.
2
GENERAL DESCRIPTION
The P8xCx66 family consists of the following devices:
• P83C266
• P83C366
• P83C566
• P83C766
• P87C766.
The P8xCx66 family also function as arithmetic processors
having facilities for both binary and BCD arithmetic plus bit
handling capabilities. The instruction set consists of over
100 instructions: 49 one-byte, 46 two-byte and
16 three-byte. Multiply and divide instructions are
implemented by hardware with a cycle time of 4 µs
(fCLK = 12 MHz).
The P8xCx66 family are 80C51-based microcontrollers
designed for medium-high to high-end TV control
applications. The P8xCx66 devices incorporate many
unique features on-chip, giving them a competitive edge
over similar devices from other manufacturers.
The term P8xCx66 is used throughout this data sheet to
refer to all family members; differences between devices
are highlighted in the text.
Table 1 Memory structure for the different family members
MEMORY
P83C266
24 kbytes
P83C366
32 kbytes
P83C566
48 kbytes
P83C766
64 kbytes
P87C766
ROM
−
RAM
512 bytes
−
512 bytes
−
1 kbyte
−
1 kbyte
−
2 kbytes
EPROM
64 kbytes
256 bytes
1792 bytes
Main memory
Auxiliary RAM
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
768 bytes
256 bytes
768 bytes
3
ORDERING INFORMATION
PACKAGE
DESCRIPTION
plastic shrink dual in-line package; 42 leads (600 mil)
TYPE NUMBER
NAME
VERSION
P83C266BDR
P83C366BDR
P83C366CBP
P83C566BDR
P83C766BDP
P87C766BDR
P87C766CBP
P83C366BDA
P83C566BDA
P83C766BDA
P87C766CBA
SDIP42
SOT270-1
PLCC68
plastic leaded chip carrier; 68 leads
SOT188-2
1999 Mar 10
4
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
e
(3)
(3)
V
V
DDD SSD
T1
T0
FB
B
G
R
VSYNC HSYNC
ROM
32 KBYTES
OR
EPROM
64 KBYTES
TWO 16-BIT
TIMER/
COUNTERS
(T0 AND T1)
8-BIT
WATCHDOG
TIMER
RAM
512 BYTES
OR
V
V
(1)
(2)
DDA
SSA
(1)
(2)
ON SCREEN DISPLAY
(OSD)
XTALIN
(T3)
2 KBYTES
XTALOUT
PLL
P8xCx66
CPU
RESET
8-bit internal bus
V
PP
80C51 CORE
EXCLUDING
ROM/RAM
FUNCTION
2
COMBINED
PARALLEL
I/O PORTS
3 × 4-BIT
ADCS
PARALLEL
I/O PORT
8 × 7-BIT
DACS
I C-BUS
14-BIT DAC
INTERFACE
6
internal
interrupts
MGL302
8
6
8
4
8
(5)
ADC1
(4)
(4)
(5)
(5)
(3)
(3)
external
P1
PWM0 to PWM7
TPWM
ADC0
ADC2
SDA SCL
P0
P3
P5
interrupts
(1) For the P83C366.
(2) For the P87C766.
(3) Alternative functions of Port 1.
(4) Alternative functions of Port 5, except PWM7 which is an alternative function of Port 3.
(5) Alternative functions of Port 3.
Fig.1 P83C366 and P87C766 block diagram.
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
5
PINNING INFORMATION
Pinning
5.1
handbook, halfpage
V
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P5.0/TPWM
DDD
P5.1/PWM0
P5.2/PWM1
P5.3/PWM2
P5.4/PWM3
P5.5/PWM4
P5.6/PWM5
P5.7/PWM6
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/PWM7
P0.0
P1.7
3
P1.6/SDA
P1.5/SCL
P1.4/T1
P1.3/INT0
P1.2/T0
P1.1/INT1
P1.0
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
RESET
XTALOUT
XTALIN
P8xCx66
V
PP
V
P0.1
SSA
V
P0.2
DDA
P0.3
VSYNC
P0.4
HSYNC
P0.5
FB
R
P0.6
P0.7
G
V
B
SSD
MGL301
Fig.2 Pin configuration (SDIP42).
6
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
n.c. 10
P5.6/PWM5 11
P5.7/PWM6 12
P3.0/ADC0 13
PH1SEM 14
S1ESEM 15
P3.1/ADC1 16
P2.0 17
60 n.c.
59 P1.2/T0
58 P1.1/INT1
57 P1.0
56 V
SS
55 EMUPBX
54 RESET
53 IDLPDEM
52 P2.7
P3.2/ADC2 18
P2.1 19
P87C766
51 XTALOUT
50 XTALIN
P3.3/PWM7 20
P2.2 21
49 V
SS
P2.3 22
48 V
PP
P0.0 23
47 P2.6
P0.1 24
46 V
SSA
P0.2 25
45 V
DDA
OSD_EPR_TST 26
44 n.c.
MGL329
Fig.3 Pin configuration (PLCC68).
7
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
5.2
Pin description
Table 2 Pin description for SDIP42 and PLCC68 packages
PIN
SYMBOL
I/O
DESCRIPTION
SDIP42 PLCC68
P5.0/TPWM
P5.1/PWM0
P5.2/PWM1
P5.3/PWM2
P5.4/PWM3
P5.5/PWM4
P5.6/PWM5
P5.7/PWM6
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/PWM7
1
2
3
4
I/O Port 5: 8-bit open-drain, bidirectional port.(P5.0 to P5.7) with 8 alternative
functions.
TWPM: 14-bit PWM output.
PWM0 to PWM6: 7-bit PWM outputs.
3
5
4
6
5
7
6
8
7
11
12
13
16
18
20
8
9
I/O Port 3: 4-bit open-drain, bidirectional port.(P3.0 to P3.3) with 4 alternative
functions.
ADC0 to ADC2: ADC inputs.
PWM7: 7-bit PWM output.
10
11
12
P0.0 to P0.7 13 to 20 23 to 25, I/O Port 0: 8-bit open-drain, bidirectional port (P0.0 to P0.7).
28 to 32
VSSD
B
21
22
23
24
25
26
27
28
29
30
−
O
O
O
O
I
Ground line for digital circuits.
37
38
39
40
41
42
45
46
48
OSD blue colour output.
G
OSD green colour output.
R
OSD red colour output.
FB
OSD fast blanking output.
HSYNC
VSYNC
VDDA
VSSA
VPP
TV horizontal sync Schmitt trigger input (for OSD synchronization).
TV vertical sync Schmitt trigger input (for OSD synchronization).
5 V analog power supply.
I
−
−
I
Ground line for analog circuits.
+12.75 V programming voltage supply (OTP) for EPROM only. 0 V in
normal application. For the ROM version this pin is not connected.
XTALIN
31
32
50
51
I
Crystal input.
XTALOUT
O
Crystal output.
1999 Mar 10
8
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
PIN
SYMBOL
I/O
DESCRIPTION
SDIP42 PLCC68
RESET
P1.0
33
34
35
36
37
38
39
40
41
42
−
54
57
I
Reset input.
I/O Port 1: 8-bit open-drain, bidirectional port (P1.0 to P1.7) with 6 alternative
functions.
P1.1/INT1
P1.2/T0
P1.3/INT0
P1.4/T1
P1.5/SCL
P1.6/SDA
P1.7
58
INT1 and INT0: external interrupts 1 and 0.
T1 and T0: 16-bit timer/counter 1 and 0 inputs
SCL: I2C-bus clock line
59
62
63
SDA: I2C-bus data line
64
65
66
VDDD
33
−
−
−
5 V digital power supply.
Ground lines.
VSS
1, 49, 56
n.c.
−
9, 10, 27,
43, 44,
60, 61
not connected
INTD
PH1SEM
S1ESEM
P2.0
−
−
−
−
−
−
−
−
−
−
−
−
2
I
These 3 signals are used for metalink+ emulation.
14
15
17
19
21
22
35
36
47
52
26
I/O
I/O
I/O Port 2: 8-bit open-drain, bidirectional port (P2.0 to P2.7).
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
OSD_EPR_
TST
I/O OSD EPROM test enable.
IDLPDEM
EMUPBX
VSSD1
−
−
−
−
53
55
67
68
I/O These 2 signals are used for metalink+ emulation.
I/O
−
−
Ground line for digital circuits.
5 V digital power supply.
VDDD1
1999 Mar 10
9
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
6
MEMORY ORGANIZATION
6.3
AUX RAM
The P8xCx66 family provides 24, 32, 48 or 64 kbytes of
program memory (ROM/EPROM) plus 512, 1024 or
2048 bytes of data memory (RAM) on-chip (see Table 1).
The device has separate address spaces for program and
data memory (see Fig.4). These devices have no external
memory access capability as the RD (read), WR (write),
EA (External Access), PSEN (read strobe) and ALE
(Address Latch Enable) signals are not bonded out.
The 1792 byte (P87C766) or 768 byte (P83C766)
AUX RAM, while physically located on-chip, logically
occupies the first 1792/768 bytes of external data memory.
As such, it is indirectly addressed in the same way as
external data memory using MOVX instructions in
combination with any of the registers R0, R1 or DPTR.
6.4
Addressing
The P80C51 CPU has five methods for addressing source
operands
6.1
Data memory
The P8xCx66 family contains 512, 1024 or 2048 bytes of
internal RAM and 56 Special Function Registers (SFRs).
Figure 4 shows the internal data memory space divided
into the lower 128, the upper 128, AUX-RAM and the SFR
space. The lower 128 bytes of internal RAM are organized
as shown in Fig.5. The lowest 32 bytes are grouped into
4 banks of 8 registers. Program instructions refer to these
registers as R0 to R7. Two bits in the Program Status
Word (PSW) select which register bank is in use. The next
16 bytes above the register bank form a block of
bit-addressable memory space. The 128 bits in this area
can be directly addressed by the single-bit manipulation
instructions. The remaining registers (30H to 7FH) are
directly and indirectly byte addressable. The registers that
reside at addresses above 7FH and up to FFH can only be
accessed indirectly. These register addresses overlap the
SFR addresses as described in Section 6.2.
• Register
• Direct
• Register-indirect
• Immediate
• Base-register-plus index-register-indirect.
The first three methods can be used for addressing
destination operands. Most instructions have a
‘destination/source’ field that specifies the data type,
addressing methods and operands involved.
For operations other than MOVs, the destination operand
is also a source operand.
Access to memory addressing is as follows:
• Registers in one of the four register banks through
register direct or indirect
• Internal RAM (128 bytes) through direct or
6.2
Special Function Registers
register-indirect
• Special Function Registers through direct
The upper 128 bytes are the address locations of the
SFRs when accessed directly. SFRs include the port
latches, timers, 7-bit PWMs, 14-bit VST PWM, ADCs and
OSD control registers. These registers can only be
accessed by direct addressing. There are
128 bit-addressable locations in the SFR address space
(SFRs with addresses divisible by eight). Their addresses
are a multiple of 08H, from 80H to F8H. (i.e., 80H, 88H,
90H, 98H etc.). See Chapter 19 for SFR list.
• External data memory through register-indirect
(for AUX RAM)
• Program memory look-up tables through
base-register-plus index-register-indirect.
1999 Mar 10
10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
(1)
64 KBYTES
OVERLAPPED SPACE
AUX RAM
1792 BYTES
255
(2)
SPECIAL
FUNCTION
REGISTERS
OR
768 BYTES
(3)
127
0
INTERNAL
DATA RAM
0
INTERNAL
INTERNAL DATA MEMORY
MGM680
PROGRAM MEMORY
(1) For the P83C766 and the P87C766.
(2) For the P87C766.
(3) For the P83C566 and the P83C766.
Fig.4 Memory map.
handbook, halfpage
7FH
30H
2FH
bit-addressable space
(bit addresses 00H to 7FH)
20H
1FH
R7
R0
R7
18H
17H
R0
R7
10H
0FH
4 banks of 8 registers
(R0 to R7)
R0
R7
08H
07H
R0
0
MGM677
Fig.5 The lower 128 bytes of internal RAM.
11
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
Port 3. Only 4 lines available for alternative functions:
7
I/O FACILITY
I/O ports
•
7-bit PWM output (PWM7)
7.1
• ADC inputs ADC0 to ADC2.
The SDIP42 package has 28 I/O lines treated as
28 individual addressable bits or as 3 parallel 8-bit
addressable ports (Ports 0, 1 and 5) and one 4-bit port
(Port 3).
Port 5.
• Provides the 14-bit PWM output (TPWM)
• 7-bit PWMs outputs (PWM0 to PWM6).
When these 28 I/O lines are used as input ports, the
corresponding bits in SFRs P0, P1, P3 and P5 should be
set to a logic 1 to facilitate the external input signal.
To enable the alternative functions of Ports 1, 3 and 5, the
port bit latch of its associated SFR must contain a logic 1.
Each port consists of a latch (SFRs P0, P1, P3 and P5), an
output driver and an input buffer.
Ports 1, 3 and 5 also perform the following alternative
functions.
Port 1. Used for a number of special functions:
7.2
Port configurations
• Provides the external interrupt inputs (INT0 and INT1)
• Provides the 16-bit timer/counter inputs (T0 and T1)
• Provides the I2C-bus data and clock signals (SDA and
1. Open-drain quasi-bidirectional I/O with n-channel
pull-down (see Fig.6). Use as an output requires the
connection of an external pull-up resistor. Use as an
input requires to write a logic 1 to the port latch before
reading the port line.
SCL)
• P1.0 and P1.7 can be used as external interrupt inputs.
2. Push-pull; gives drive capability of the output in both
polarities, see Fig.7.
I/O pin
strong pull-up
handbook, halfpage
handbook, halfpage
+5 V
Q
from port latch
n
p1
output pin
Q
from port latch
input data
read port pin
n
INPUT
BUFFER
MGM679
MGK547
Fig.6 Open-drain port.
Fig.7 Push-pull port.
1999 Mar 10
12
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
8
TIMERS AND EVENT COUNTERS
The Watchdog timer consists of an 8-bit timer with an
11-bit prescaler as shown in Fig.8. The prescaler input
frequency is 1⁄12fosc. The 8-bit timer is incremented every
‘t’ seconds where ‘t’ is calculated as shown below:
The P8xCx66 contains two 16-bit timers/counters: Timer 0
and Timer 1 and also an 8-bit Watchdog timer.
8.1
16-bit timer/counters (T0 and T1)
1
fosc
t = 12 × 2048 ×
--------
Timer 0 and Timer 1 perform the following functions:
• Measure time intervals and pulse durations
• Count events
The 8-bit timer is an up-counter so a value 00H gives the
maximum timer interval (510 ms at 12 MHz, 1536 ms at
4 MHz), and a value of FFH gives the minimum timer
interval (2 ms at 12 MHz, 6 ms at 4 MHz). When the 8-bit
timer produces an overflow a short internal reset pulse is
generated which will reset the P8xCx66.
• Generate interrupt requests.
Timer 0 and Timer 1 can be independently programmed to
operate in one of four modes.
Mode 0 8-bit timer or counter with divide-by-32 prescaler.
Mode 1 16-bit time-interval or event counter.
The timer has no disable function. Consequently, all
applications must reload the timer within the previously
loaded timer interval otherwise a reset will occur. The timer
is not stopped in the Idle mode. The interrupt routine for
the Idle mode should also service the Watchdog timer.
Mode 2 8-bit time-interval or event counter with automatic
reload upon overflow.
Mode 3 Timer 0 establishes TL0 and TL1 as two
separate counters.
The Watchdog timer is controlled by the WLE bit in the
Power Control Register (see Section 9.6). The WLE bit
must be set by the Watchdog timer service routine before
the timer interval can be loaded into T3. A load of T3
automatically clears the WLE bit.
In the ‘timer’ function, the register is incremented every
machine cycle. Since a machine cycle consists of
12 oscillator periods, the count rate is 1⁄12fosc
.
A system reset clears the Watchdog timer and the
prescaler.
In the ‘counter’ function, the register is incremented in
response to a HIGH-to-LOW transition. Since it takes
2 machine cycles (24 oscillator periods) to recognize a
HIGH-to-LOW transition, the maximum count rate is
1⁄24fosc. To ensure that a given level is sampled, it should
be held for at least one complete machine cycle.
8.2.1
WATCHDOG TIMER REGISTER (WDT)
Table 3 Watchdog timer Register (SFR address FFH)
7
6
5
4
3
2
1
0
8.2
Watchdog timer (T3)
T37 T36 T35 T34 T33 T32 T31 T30
In addition to the standard timers, a Watchdog timer is
implemented on-chip. The Watchdog timer generates a
hardware reset upon overflow. In this way a
microcontroller system can recover from erroneous
processor states caused by electrical noise, RFI or
unexpected ROM code behaviour.
1999 Mar 10
13
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
a
INTERNAL BUS
WDT REGISTER
(8-BIT)
PRESCALER
1/12 f
11-BIT
CLEAR
osc
internal reset
RESET
LOAD
LOADEN
R
RESET
CLEAR
WLE
IDL
LOADEN
PCON.4
PCON.0
write T3
INTERNAL BUS
MGL298
Fig.8 Block diagram of the Watchdog timer.
1999 Mar 10
14
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
9
REDUCED POWER MODE
9.2.3
VIA A WATCHDOG TIMER OVERFLOW
Only one reduced power mode is implemented; this is the
Idle mode.
If the Watchdog timer is allowed to overflow or an
erroneous processor state causes an overflow, a
hardware reset will be generated, thus terminating the Idle
mode.
During Idle mode all blocks are inactive except Timer 0,
Timer 1, INT0, INT1 and the Watchdog timer. These active
functions may generate an interrupt (if their interrupts are
enabled) and this will cause the device to leave the Idle
mode.
9.3
General purpose flags (GF0 and GF1)
Flags GF0 and GF1 may be used to determine whether
the interrupt was received during normal execution or Idle
mode. For example, the instruction that writes to PCON.0
to set the Idle mode can also set or clear one or both flags.
When the Idle mode is terminated by an interrupt, the
service routine can examine the status of the flag bits.
The Idle mode is activated by software using the PCON
register; this register is described in Section 9.6.
9.1
Idle mode
The instruction that sets PCON.0 is the last instruction
executed before entering the Idle mode. Once in the Idle
mode, the internal clock is gated away from the CPU and
from all derivative functions (PWM/TPWM/ADC/I2C-bus),
except Timer 0, Timer 1 and interrupts INT0 and INT1.
The Watchdog timer remains active. The CPU status is
preserved along with the Stack Pointer, Program Counter,
Program Status Word and the Accumulator. The RAM and
all other registers maintain their data during Idle mode and
the port pins retain the logic states held at Idle mode
activation. The OSD clock is gated away from OSD circuit
in Idle mode.
9.4
Output in Idle mode
• Ports will keep the value they had before entering the
Idle mode
• The PWM0 to PWM7 outputs will be LOW
• The TPWM output will be LOW
• The I2C-bus output is HIGH
• The pins R, G, B and FB will be the ‘inverse of Bp’,
(defined by bit 2 of SFR OSCON).
9.5
Pending interrupts in Idle mode
9.2
Recover from Idle mode
If pending interrupts (I2C-bus, VSYNC, P1.0 to P1.4 or
P1.7) are present at the moment the CPU is switched to
Idle mode, then these interrupts will wake-up the CPU.
If this is not wanted then before entering the Idle mode all
interrupts must be disabled, except those interrupts
allowed to wake-up the CPU (INT0, INT1, Timer 0 and
Timer1). New interrupts from I2C-bus, VSYNC,
P1.0 to P1.4 or P1.7 are disabled as soon as Idle mode is
entered.
There are 3 methods used to terminate the Idle mode.
9.2.1
VIA AN INTERRUPT
Activation of INT0, INT1 or an interrupt from Timer 0 or
Timer 1 will cause PCON to be cleared by hardware thus
terminating the Idle mode. The interrupt is serviced and
following the RETI instruction, the next instruction to be
executed will be the one following the instruction that put
the device in the Idle mode. All the other interrupts are
disabled and will not generate an interrupt to wake-up the
CPU.
For example if a high priority interrupt is serviced just
before the instruction which sets PCON.0 and a lower
priority interrupt is generated during the interrupt service
routine of the high priority interrupt, then the lower priority
interrupt is pending. After the high priority interrupt is
serviced (last instruction of routine is RETI) the main
program will execute at least one more instruction to
prevent a deadlock of the main program. In this case, it is
the instruction which sets the PCON.0 bit (enter Idle
mode). The pending lower level interrupt will, if enabled,
immediately wake-up the CPU for an interrupt service,
even though this interrupt is not INT0, INT1 or an interrupt
from Timer 1 or Timer 0.
9.2.2
VIA RESET
The second method of terminating the Idle mode is with an
external hardware reset. Since the oscillator is still
running, the hardware reset is required to be active for only
two machine cycles to complete the reset operation. Reset
redefines all SFRs, but does not effect the on-chip RAM.
1999 Mar 10
15
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
9.6
Power Control Register (PCON)
PCON is byte addressable only.
Table 4 Power Control Register (SFR address 87H)
7
6
5
4
3
2
1
0
−
−
−
WLE
GF1
GF0
0
IDL
Table 5 Description of PCON bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
−
−
These 3 bits are reserved.
−
WLE
Watchdog Load Enable. If WLE = 1, the Watchdog timer can be loaded. If WLE = 0,
the Watchdog timer cannot be loaded.
3
2
1
0
GF1
GF0
−
General purpose flag 1.
General purpose flag 0.
This bit is reserved and must be set to a logic 0.
IDL
Idle mode select. If IDL = 1, the Idle mode is selected. If IDL = 0, the Idle mode is
inhibited, i.e. normal operation.
1999 Mar 10
16
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
10 I2C-BUS SERIAL I/O
10.1 The I2C-bus
10.2 Operation modes
The I2C-bus serial I/O has complete autonomy in byte
handling and operates in four modes
The serial port supports the two line I2C-bus. The I2C-bus
consists of a serial data line (SDA) and a serial clock line
(SCL). These lines can also function as I/O port lines
P1.6 and P1.5 respectively. To utilize this facility pins
P1.5/SCL and P1.6/SDA must be configured as alternative
functions instead of port lines; see Section 10.8.
• Master transmitter
• Master receiver
• Slave transmitter
• Slave receiver.
These functions are controlled by the S1CON register.
S1STA is the status register whose contents may also be
used as a vector to various service routines. S1DAT is the
data shift register and S1ADR the slave address register.
Slave address recognition is performed by hardware.
The system is unique because data transport, clock
generation, address recognition and bus control arbitration
are all controlled by hardware.
Full details of the I2C-bus are given in the document
“The I2C-bus and how to use it”. This document may be
ordered using the code 9398 393 40011.
GC
SLAVE ADDRESS
S1ADR
SHIFT REGISTER
S1DAT
SDA
ARBITRATION LOGIC
SCL
BUS CLOCK GENERATOR
7
6
6
5
5
4
4
3
3
2
2
1
0
S1CON
7
1
0
MBC749 - 1
S1STA
Fig.9 Block diagram of I2C-bus serial I/O.
1999 Mar 10
17
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
10.3 Serial Control Register (S1CON)
Table 6 Serial Control Register (SFR address D8H)
7
6
5
4
3
2
1
0
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
Table 7 Description of S1CON bits
BIT
SYMBOL
DESCRIPTION
6
ENSI
Enable Serial I/O. When ENSI = 0, the SIO is disabled and reset. The SDA and SCL
outputs are in a high-impedance state; P1.5 and P1.6 function as open-drain ports.
When ENSI = 1, the SIO is enabled. The P1.5 and P1.6 port latches must be set to
logic 1.
5
4
STA
STO
START flag. When the STA bit is set in Slave mode, the SIO hardware checks the
status of the I2C-bus and generates a START condition if the bus is free. If STA is set
while the SIO is in Master mode, SIO transmits a repeated START condition.
STOP flag. With this bit set while in Master mode a STOP condition is generated. When
a STOP condition is detected on the bus, the SIO hardware clears the STO flag. In the
Slave mode, the STO flag may also be set to recover from an error condition. In this
case, no STOP condition is transmitted to the I2C-bus interface. However, the SIO
hardware behaves as if a STOP condition has been received and releases SDA and
SCL. The SIO then switches to the ‘not addressed’ slave receiver mode. The STO flag
is automatically cleared by hardware.
3
SI
SIO interrupt flag. When the SI flag is set, an acknowledge is returned after any one of
the following conditions:
• A START condition is generated in Master mode
• Own slave address received during AA = 1
• General call address received while S1ADR.0 = 1 and AA = 1
• Data byte received or transmitted in Master mode (even if arbitration is lost)
• Data byte received or transmitted as selected slave
• STOP or START condition received as selected slave receiver or transmitter.
2
AA
Assert Acknowledge. When the AA flag is set, an acknowledge (LOW level to SDA)
will be returned during the acknowledge clock pulse on the SCL line when:
• Own slave address is received
• General call address is received (S1ADR.0 = 1)
• Data byte received while device is programmed as a Master receiver
• Data byte received while device is a selected Slave receiver.
With AA = 0, no acknowledge will be returned. Consequently, no interrupt is requested
when the ‘own slave address’ or general call address is received.
7
1
0
CR2
CR1
CR0
Clock Rate selection. These three bits determine the serial clock frequency when SIO
is in a Master mode; see Table 8. The maximum I2C-bus frequency is 400 KHz.
1999 Mar 10
18
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
Table 8 Selection of SCL frequency in Master mode
CR2
0
CR1
0
CR0
0
fosc DIVISOR
BIT RATE (kHz) at fosc = 12 MHz
60
1600
40
200
7.5
0
0
1
0
1
0
300
400
50
0
1
1
30
1
0
0
240
3200
160
120
1
0
1
3.75
75
1
1
0
1
1
1
100
10.4 Status Register (S1STA)
S1STA is an 8-bit read-only Special Function Register. The contents of S1STA may be used as a vector to a service
routine. This optimizes response time of the software and consequently that of the I2C-bus. The status codes for all
possible modes of the I2C-bus interface are given in Table 12. The abbreviations used in Table 12 are defined in
Table 11.
Table 9 Status Register (SFR address D9H)
7
6
5
4
3
2
1
0
SC4
SC3
SC2
SC1
SC0
0
0
0
Table 10 Description of S1STA bits
BIT
SYMBOL
SC4 to SC0 5-bit status code; see Table 12.
These 3 bits are held LOW.
DESCRIPTION
7 to 3
2 to 0
−
Table 11 Abbreviations used in Table 12
SYMBOL
DESCRIPTION
SLA
R
7-bit slave address
read bit
write bit
W
ACK
ACK
DATA
MST
SLV
TRX
REC
acknowledgment (Acknowledge bit = 0)
not acknowledge (Acknowledge bit = 1)
8-bit byte to or from the I2C-bus
master
slave
transmitter
receiver
1999 Mar 10
19
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
Table 12 Status codes
S1STA VALUE
DESCRIPTION
MST/TRX mode
08H
10H
18H
20H
28H
30H
38H
a START condition has been transmitted
a repeated START condition has been transmitted
SLA and W have been transmitted, ACK received
SLA and W have been transmitted. ACK received
DATA of S1DAT has been transmitted, ACK received
DATA of S1DAT has been transmitted, ACK received
arbitration lost in SLA, R/W or DATA
MST/REC mode
38H
40H
48H
50H
58H
arbitration lost while returning ACK
SLA and R have been transmitted, ACK received
SLA and R have been transmitted, ACK received
DATA has been received, ACK returned
DATA has been received, ACK returned
SLV/REC mode
60H
68H
own SLA and W have been received, ACK returned
arbitration lost in SLA, R/W as MST; own SLA and W have been received, ACK
returned
70H
78H
80H
88H
90H
98H
A0H
general CALL has been received, ACK returned
arbitration lost in SLA, R/W as MST; general CALL has been received
previously addressed with own SLA; DATA byte received, ACK returned
previously addressed with own SLA; DATA byte received, ACK returned
previously addressed with general CALL; DATA byte has been received, ACK returned
previously addressed with general CALL; DATA byte has been received, ACK returned
a STOP condition or repeated START condition has been received while still addressed
as SLV/REC or SLV/TRX
SLV/TRX mode
A8H
B0H
own SLA and R have been received. ACK returned
arbitration lost in SLA, R/W as MST. Own SLA and R have been received, ACK
returned
B8H
C0H
C8H
DATA byte has been transmitted, ACK received
DATA byte has been transmitted, ACK received
last DATA byte has been transmitted (AA = logic 0) ACK received
Miscellaneous
00H
bus error during MST mode or SLV mode, due to an erroneous START or STOP
condition
1999 Mar 10
20
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
10.5 Data Shift Register (S1DAT)
S1DAT contains the serial data to be transmitted or data that has just been received. Bit 7 is transmitted or received first.
Table 13 Data Shift Register (SFR address DAH)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
10.6 Slave Address Register (S1ADR)
This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as
slave receiver/transmitter. The LSB bit (GC) is used to determine whether the general CALL address is recognized.
Table 14 Slave Address Register (SFR address DBH)
7
6
5
4
3
2
1
0
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
GC
Table 15 Description of S1ADR bits
BIT
SYMBOL
DESCRIPTION
7 to 1
SLA6 to
SLA0
Own slave address.
0
GC
When GC = 0, the general CALL address is not recognized. When GC = 1, the general
CALL address is recognized.
10.7 Internal Status Register (S1IST)
S1IST is an 8-bit read-only Special Function Register and will exist in the design but is not mapped for the user.
Table 16 Internal Status Register (SFR address DCH)
7
6
5
4
3
2
1
0
MST
TRX
BB
FB
ARL
SEL
AD0
SHRA
10.8 I2C-bus Control Register (I2CCON)
Table 17 I2C-bus Control Register (SFR address 86H)
7
6
5
4
3
2
1
0
−
−
−
−
−
I2CE
−
−
Table 18 Description of I2CCON bits
BIT
7 to 3
2
SYMBOL
DESCRIPTION
−
These 5 bits are not used.
I2CE
I2C-bus enable. This bit selects the functions of pins 39 and 40 for the SDIP42 package
(or pins 64 and 65 for the PLCC68 package). When I2CE = 1, the alternative functions
SCL and SDA are selected. When I2CE = 0, these pins act as port lines P1.5 and P1.6.
1 to 0
−
These bits are not used.
1999 Mar 10
21
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
Register. Each flag will be set on interrupt request but it
must be cleared by software, i.e. via the interrupt software.
11 INTERRUPT SYSTEM
External events and the real-time driven on-chip
peripherals require service by the CPU asynchronous to
the execution of any particular section of code. To tie the
asynchronous activities of these functions to normal
program execution a multiple-source, two-priority-level,
nested interrupt system is provided. The P8xCx66
acknowledges interrupt requests from twelve sources as
shown in Table 20.
11.2 Interrupt priority
Each interrupt source can be set to either high or low
priority. If both priorities are requested simultaneously, the
controller will branch to the high priority vector.
A low priority interrupt can only be interrupted by a high
priority interrupt. A high priority interrupt routine cannot be
interrupted
Each interrupt vectors to a separate location in program
memory for its service routine. Each source can be
individually enabled or disabled by using corresponding
bits in the Interrupt Enable Registers (IEN0 and IEN1).
The priority level is selected via the Interrupt Priority
Registers (IP0 and IP1). All enabled sources can be
globally disabled or enabled. The minimum width of the
external interrupt signal is ≥6 XTAL clocks. The maximum
width of the interrupt signal is the total length of all
instructions in the interrupt service routine until the clear
instruction of the IRQ bit. The external interrupts are INT0,
INT1, P1.0, P1.1, P1.2, P1.3, P1.4 and P1.7.
11.3 Related registers
The following registers are used in conjunction with the
interrupt system.
Table 19 Interrupt registers
REGISTER
ADDRESS
E9H
Interrupt Polarity Register (IX1)
Interrupt Request Flag Register (IRQ1)
Interrupt Enable Register 0 (IEN0)
C0H
A8H
11.1 External interrupts INT2 to INT7 and INT9
Interrupt Enable Register 1 (IEN1);
interrupts INT2 to INT9
E8H
Port 1 lines also serve as additional interrupts
INT2 to INT7 (P1.0, P1.1, P1.2, P1.3, P1.4 and P1.7).
INT7 is used by the derivative functional blocks as follows:
Interrupt Priority Register 0 (IP0)
B8H
F8H
Interrupt Priority Register 1 (IP1);
interrupts INT2 to INT9
X7 VSYNC interrupt 0063H
Using the IX1 register, each pin may be initialized to be
either active HIGH or active LOW except INT7 which is
fixed active HIGH because this interrupt is from another
derivative function. IRQ1 is the Interrupt Request Flag
Table 20 Interrupt request (priority within level)
INTERRUPT MNEMONIC
PX0 (highest)
SOURCE
VECTOR ADDRESS
external interrupt 0 (INT0)
I2C-bus
0003H
002BH
000BH
0033H
005BH
0013H
003BH
0063H
001BH
0043H
004BH
0073H
S1
T0
Timer 0 overflow
P1.0 port line
PX2
PX6
PX1
PX3
PX7
T1
P1.4 port line
external interrupt 1 (INT1)
P1.1 port line
VSYNC interrupt
Timer 1 overflow
P1.2 port line
PX4
PX5
PX9 (lowest)
P1.3 port line
P1.7 port line
1999 Mar 10
22
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
INTERRUPT
SOURCES
IEN0/1
REGISTERS
IP0/1
REGISTERS
PRIORITY
HIGH
PX0
S1
LOW
T0
PX2
PX6
PX1
PX3
PX7
T1
PX4
PX5
PX9
GLOBAL
ENABLE
MGL297
Fig.10 Interrupt system.
23
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
IX1
IRQ1
IEN1
X9
X7
X6
X5
X4
X3
X2
P1.7
VSYNC
P1.4
P1.3
P1.2
P1.1
P1.0
MGL296
Fig.11 External and derivative interrupt configuration.
1999 Mar 10
24
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
11.4 Interrupt Enable Register 0 (IEN0)
Table 21 Interrupt Enable Register (SFR address A8H)
7
6
5
4
3
2
1
0
EA
−
ES1
−
ET1
EX1
ET0
EX0
Table 22 Description of IEN0 bits
A logic 0 disables the interrupt; a logic 1 enables the interrupt.
BIT
SYMBOL
DESCRIPTION
7
EA
General enable/disable control. When EA = 0, no interrupt is enabled. When EA = 1,
any individually enabled interrupt will be accepted.
6
5
4
3
2
1
0
−
not used
enable I2C-bus SIO interrupt
ES1
−
not used
ET1
EX1
ET0
EX0
enable Timer 1 interrupt
enable external interrupt 1
enable Timer 0 interrupt
enable external interrupt 0
11.5 Interrupt Enable Register 1 (IEN1)
Table 23 Interrupt Enable Register (SFR address E8H)
7
6
5
4
3
2
1
0
EX9
−
EX7
EX6
EX5
EX4
EX3
EX2
Table 24 Description of IEN1 bits
Where EXx = 0, interrupt disabled. EXx = 1, interrupt enabled
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
EX9
−
enable external interrupt 9 (P1.7 port line)
not used
EX7
EX6
EX5
EX4
EX3
EX2
enable external interrupt 7 (VSYNC interrupt)
enable external interrupt 6 (P1.4 port line)
enable external interrupt 5 (P1.3 port line)
enable external interrupt 4 (P1.2 port line)
enable external interrupt 3 (P1.1 port line)
enable external interrupt 2 (P1.0 port line)
1999 Mar 10
25
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
11.6 Interrupt Priority Register 0 (IP0)
Table 25 Interrupt Priority Register 0 (SFR address B8H)
7
6
5
4
3
2
1
0
−
−
PS1
−
PT1
PX1
PT0
PX0
Table 26 Description of IP0 bits
A logic 0 selects low priority; a logic 1 selects high priority.
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
−
These 2 bits are not used.
−
PS1
−
I2C-bus SIO interrupt priority level
This bit is not used.
PT1
PX1
PT0
PX0
Timer 1 interrupt priority level
external interrupt 1 priority level
Timer 0 interrupt priority level
external interrupt 0 priority level
11.7 Interrupt Priority Register 1 (IP1)
Table 27 Interrupt Priority Register 1 (SFR address F8H)
7
6
5
4
3
2
1
0
PX9
−
PX7
PX6
PX5
PX4
PX3
PX2
Table 28 Description of IP1 bits
Where PXx = 0 selects low priority; PXx = 1 selects high priority.
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
PX9
−
enable external interrupt 9 priority level (P1.7 port line)
not used
PX7
PX6
PX5
PX4
PX3
PX2
enable external interrupt 7 priority level (VSYNC interrupt)
enable external interrupt 6 priority level (P1.4 port line)
enable external interrupt 5 priority level (P1.3 port line)
enable external interrupt 4 priority level (P1.2 port line)
enable external interrupt 3 priority level (P1.1 port line)
enable external interrupt 2 priority level (P1.0 port line)
1999 Mar 10
26
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
11.8 Interrupt Polarity Register (IX1)
Writing a logic 1 to bits IL9, IL6, IL5, IL4, IL3 and IL2 will set the polarity level of the corresponding external interrupt to
be active HIGH. Writing a logic 0 to these bits will set the corresponding external interrupt to be active LOW.
External interrupts INT1 and INT0 however can be programmed to be edge sensitive. Writing a logic 1 to bits IL8 and IL7
will activate the external interrupts INT1 and INT0 on a rising edge (LOW-to-HIGH). Writing a logic 0 to bits IL8 and IL7
will activate the external interrupts INT1 and INT0 on a falling edge (HIGH-to-LOW). This feature is useful for pulse width
measurement; see Section 11.8.1.
Table 29 Interrupt Polarity Register (SFR address E9H)
7
6
5
4
3
2
1
0
IL9
IL8
IL7
IL6
IL5
IL4
IL3
IL2
Table 30 Description of IX1 bits
BIT
SYMBOL
DESCRIPTION
external interrupt 9 polarity level (P1.7 port line)
7
6
5
4
3
2
1
0
IL9
IL8
IL7
IL6
IL5
IL4
IL3
IL2
external interrupt 1 polarity level (INT1) polarity level
external interrupt 0 polarity level (INT0) polarity level
external interrupt 6 polarity level (P1.4 port line)
external interrupt 5 polarity level (P1.3 port line)
external interrupt 4 polarity level (P1.2 port line)
external interrupt 3 polarity level (P1.1 port line)
external interrupt 2 polarity level (P1.0 port line)
11.8.1 PULSE WIDTH MEASUREMENT EXAMPLE
To determine the LOW time of a signal on the external interrupt pin INT0 the following sequence should be followed.
1. External interrupt 0 must be programmed to edge sensitivity (SFR TCON, address 88H).
2. IL7 must be programmed as shown in Fig.12.
3. The value held in Timer 0 or Timer 1 represents the pulse width of the signal on the INT0 pin.
INT0
IL7
INT0(CPU)
Start interrupt service
routine to start counting
system clock periods
with Timer 0 or Timer 1
Start interrupt service
routine to stop counting
of Timer 0 or Timer 1
MGL295
Fig.12 Pulse width measurement timing diagram.
27
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
11.9 Interrupt Request Flag Register (IRQ1)
Bits IQ9 and IQ6 to IQ2 will be set to a logic 1, if one of the two conditions specified below is met:
• If its associated port line is programmed to generate an interrupt when HIGH (selected using the Interrupt Polarity
Register) and the state of that port line is HIGH
• If its associated port line is programmed to generate an interrupt when LOW (selected using the Interrupt Polarity
Register) and the state of that port line is LOW.
IQ7 is set to a logic 1, if the interrupt condition is met within the corresponding derivative function. Therefore, all IRQ1 bits
serve not only as pending interrupt request bits but also as interrupt status bits. This means that even if the external
interrupts are disabled (using the Interrupt Enable Register 1) the IRQ1 bits can still be set to a logic 1 if the interrupt
condition is met within the corresponding derivative function. For example, if the interrupt condition within VSYNC is met
then:
• If IEN0.7 = X, IEN1.5 = 0 then IRQ1.5 = 1, no pending interrupt to CPU
• If IEN0.7 = 0, IEN1.5 = 1 then IRQ1.5 = 1, interrupt to CPU is pending
• If IEN0.7 = 1, IEN1.5 = 1 then IRQ1.5 = 1, interrupt will be serviced when either:
– The CPU finishes current instruction, if not in the interrupt service routine
– The current interrupt service routine is interrupted if the VSYNC has a higher interrupt priority
– This VSYNC interrupt becomes pending, waiting until the current higher priority level interrupt is serviced.
Bits IQ9 and IQ7 to IQ2 can be reset by software.
Table 31 Interrupt Request Flag Register (SFR address C0H)
7
6
5
4
3
2
1
0
IQ9
−
IQ7
IQ6
IQ5
IQ4
IQ3
IQ2
Table 32 Description of IRQ1 bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
IQ9
−
external interrupt 9 request flag (P1.7 port line)
reserved
IQ7
IQ6
IQ5
IQ4
IQ3
IQ2
external interrupt 7 request flag (VSYNC interrupt)
external interrupt 6 request flag (P1.4 port line)
external interrupt 5 request flag (P1.3 port line)
external interrupt 4 request flag (P1.2 port line)
external interrupt 3 request flag (P1.1 port line)
external interrupt 2 request flag (P1.0 port line)
1999 Mar 10
28
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
11.10 VSYNC interrupt and level status bit
The SFR VINT is read-only. Figure 13 shows the timing diagram of VSYNC interrupt.
Table 33 VSYNC Interrupt Register (SFR address C9H)
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
VLVL
Table 34 Description of VINT bits
BIT
SYMBOL
DESCRIPTION
7 to 1
0
−
These 7 bits are not used.
VLVL
VSYNC input pin level. The state of this bit indicates the level of the VSYNC input. As
the input polarity of VSYNC is programmable two situations may be defined.
If VSYNC is programmed active HIGH then:
VLVL = 0, means VSYNC is at a LOW level, i.e. raster scan period
VLVL = 1, means VSYNC is at HIGH level, i.e.vertical fly-back period.
If VSYNC is programmed to active LOW then:
VLVL = 0, means VSYNC is at LOW level, i.e. vertical fly-back period
VLVL = 1, means VSYNC is at HIGH level, i.e. raster scan period
11.10.1 EXTERNAL INTERRUPT REQUEST (IQ7)
A rising or falling edge (see Fig.13) of the active VSYNC signal generates a pending interrupt to the CPU and drives IQ7
HIGH (IQ7 resides in the SFR IRQ1). In the service routine, this bit should be cleared before return to main routine.
As long as this bit is HIGH a pending interrupt is always there. Each time VSYNC is activated by a rising or falling edge,
IQ7 is set HIGH. If the interrupt is not serviced before the next leading VSYNC edge, then IQ7 is written HIGH again and
no error of overrun is indicated.
VSYNC active HIGH (V = 1)
p
VSYNC
The rising edge of VSYNC generates an interrupt
VSYNC active LOW (V = 0)
p
VSYNC
The falling edge of VSYNC generates interrupt
MGL286
Fig.13 Timing diagram of VSYNC interrupt.
29
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
12 OSCILLATOR CIRCUITRY
The on-chip oscillator circuitry of the P8xCx66 is a single-stage inverting amplifier biased by an internal feedback resistor.
For operation as a standard quartz oscillator, no external components are needed. When using external ceramic
resonators different configurations are supported (see Fig.15). The crystal oscillator operating frequency range is
4 to 12 MHz.
P8xCx66
to internal
timing circuits
V
V
DD
DD
R
C1
C2
i
bias
i
XTALIN
XTALOUT
MGM678
Fig.14 Standard oscillator.
STANDARD
QUARTZ
OSCILLATOR
CERAMIC
RESONATOR
XTALIN
XTALOUT
XTALIN
XTALOUT
MGL294
Fig.15 Alternative oscillator configurations.
30
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
The OSD SFRs are only updated when VSYNC and
HSYNC are present. If these signals are not present during
a reset operation then the OSD SFRs will retain their
values held after a Power-on reset.
13 RESET CIRCUITRY
To initialize the P8xCx66 a reset is performed by one of
3 methods:
• Via the RESET pin
In existing television systems HSYNC and VSYNC are
often generated by a dedicated IC, consequently during
start-up these signals may not be present. In this situation,
it is mandatory to initialize all the OSD registers before
entering the application.
• Via a Power-on reset
• Via the Watchdog timer.
A reset leaves the internal registers as shown in Table 35.
The reset input of the P8xCx66 is the RESET pin. A
Schmitt trigger input qualifies the input for noise rejection.
The output of the Schmitt trigger is sampled by the reset
circuitry every machine cycle. A reset is accomplished by
holding the RESET pin HIGH for at least two machine
cycles (24 oscillator periods), while the oscillator is
running. The CPU responds by generating an internal
reset. Port pins adopt their reset state immediately after
RESET goes HIGH.
13.2 Power-on reset
The P8xCx66 contains on-chip circuitry which switches the
port to the customer defined logic level as soon as VDD
exceeds 3.9 V. As soon as the minimum supply voltage is
reached, the oscillator will start-up. However, to ensure
that the oscillator is stable before the controller starts, the
reset is extended internally for 2048 oscillator periods.
A hysteresis of approximately 500 mV at a typical
power-on switching level of 3.9 V will ensure correct
operation.
The external reset is asynchronous to the internal clock.
The RESET pin is sampled during state 5, phase 2 of
every machine cycle. After a HIGH is detected at the
RESET pin, an internal reset is repeated until RESET goes
LOW.
An automatic reset can be obtained at power-on by
connecting the RESET pin to VDD via a 10 µF capacitor.
At power-on, the voltage on the RESET pin is equal to VDD
minus the capacitor voltage, and decreases from VDD as
the capacitor discharges through the internal resistor
The internal RAM is not affected by reset. When VDD is
switched on the RAM contents are indeterminate.
RRESET to ground. The larger the capacitor, the more
13.1 Reset operation for the OSD SFRs
slowly VRESET decreases. VRESET must remain above the
lower threshold of the Schmitt trigger input long enough to
effect a complete reset. The time required is
There are 12 OSD Special Function Registers: OSAT,
OSDT, OSAD, OSCON, OSCON2, OSORGV, OSORGH,
OSDDEF, OSSTART, HDEL, OSFBD and OSPLL.
2048 oscillator cycles plus 2 machine cycles.
V
handbook, halfpage
DD
SCHMITT
TRIGGER
handbook, halfpage
RESET
10 µF
V
DD
P8xCx66
RESET
CIRCUITRY
RESET
MGL293
R
RESET
MGL291
Fig.16 Reset configuration at RESET pin.
Fig.17 Recommended Power-on reset circuity.
1999 Mar 10
31
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
a
t
= 200 ns at 3.9 V
w
5 V
3.9 V
3.9 V
3.9 V
0 V
0 V
V
DDD
t
p
5 V
3.9 V
3.9 V
0 V
0 V
Power-on reset
delay 10 µs
delay 10 µs
MGL292
Fig.18 Power-on reset switching level.
1999 Mar 10
32
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
Table 35 State of internal registers after a reset
REGISTER
ADDRESS
REGISTER
ADDRESS
REGISTER
CONTENTS(1)
REGISTER
CONTENTS(1)
ACC
B
E0H
F0H
82H
83H
A8H
E8H
B8H
F8H
E9H
C0H
D0H
87H
80H
90H
A0H
B0H
98H
9CH
DBH
D8H
DAH
D9H
81H
88H
8CH
8DH
8AH
8BH
89H
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
XX00 0000
0000 0000
0000 0000
0000 0000
0000 0000
XXX0 0000
1111 1111
1111 1111
1111 1111
XXXX 1111
1111 1111
001X 0010
0000 0000
X000 0000
0000 0000
1111 1000
0000 0111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
I2CCON
OSAT
86H
99H
9AH
9BH
C1H
C2H
C3H
C4H
C5H
C6H
C7H
C8H
DCH
C9H
CAH
CFH
D2H
D3H
E4H
E5H
E6H
E7H
ECH
EDH
EEH
EFH
FFH
XXXX X0XX
XXX1 1111
1111 1111
0000 0000
0001 1100
XX11 1111
X111 1111
0000 0000
0000 0000
XXXX 0000
XXXX 0000
0000 0000
0000 0000
XXXX XXXX
XXXX X000
XXX0 0010
0000 0000
0X00 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
DPL
DPH
IEN0
IEN1
IP0
OSDT
OSAD
OSCON
OSORGV
OSORGH
OSPLL
OSSTART
HDEL
IP1
IX1
IRQ1
PSW
PCON
P0
OSFBD
SAD
S1IST
P1
VINT
P2
SAD2
P3
OSCON2
TDACL
TDACH
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
WDT
P5
OSDDEF
S1ADR
S1CON
S1DAT
S1STA
SP
TCON
TH0
TH1
TL0
TL1
Note
1. Where X = undefined state.
TMOD
1999 Mar 10
33
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
Each 7-bit PWM output can be selected by setting the
PWMnE bit in its associated PWMn register, to a logic 1
(see Section 15.1). When the PWMnE bit is a logic 0 the
port line function is selected. The 14-bit PWM output
(TPWM) is selected by setting the TPWME bit in SFR
TDACH to a logic 1 (see Section 15.2).
14 PIN FUNCTION SELECTION
Ports 1, 3 and 5 are dual purpose ports and can be
configured as general I/O port lines or selected as
alternative functions. Selection of the pin function as an
alternative function is achieved by setting the associated
port latch bit to a logic 1 and then enabling the alternative
function using its associated SFR.
P3.3 can also be selected as a bidirectional port line (P3.3)
or as a 7-bit PWM output (PWM7). The 7-bit PWM output
is enabled by setting the PWME7 bit in SFR PWM7 to a
logic 1 (see Section 15.1).
14.1 Port 1 pin function selection
Port 1 is an 8-bit port which can be configured as eight
bidirectional port lines (P1.0 to P1.7) or as two external
interrupts (INT0 and INT1), two timer/counter inputs
(T0 and T1) and the I2C-bus lines (SDA and SCL).
P1.0 and P1.7 have no alternative functions.
14.3 Port 3 pin function selection
Port 3 is a 4-bit port which can be configured as four
bidirectional port lines (P3.0 to P3.3) or as 3 ADC inputs
(ADC0 to ADC2) and one 7-bit PWM output (PWM7).
The selection of the PWM7 output is discussed in
Section 14.2.
To configure these pins as alternative functions the
corresponding bit in the Port 1 Latch (P1) should be
programmed to a logic 1. The I2C-bus lines are enabled by
setting the I2CE bit in the I2C-bus Port Control Register,
see Section 10.8. The remaining alternative functions are
enabled using the associated SFR.
To select the alternative function of these port lines the
corresponding bit in the Port 3 Latch (P3) should be
programmed to a logic 1. The ADC inputs are then
enabled using the SFR SAD2 as described in
Section 14.3.1.
To use Port 1 pins as general I/O lines the alternative
functions must be disabled.
To use Port 3 pins as general I/O lines the alternative
functions must be disabled.
14.2 Port 5 and P3.3 pin function selection
Port 5 pins can be selected as eight bidirectional port lines
(P5.0 to P5.7) or as seven 7-bit PWM outputs
(PWM0 to PWM6) and one 14-bit PWM output (TPWM).
14.3.1 ADC CONTROL REGISTER 2 (SAD2)
Table 36 ADC Control Register 2 (SFR address CAH)
7
6
5
4
3
2
1
0
−
−
−
−
−
ADCE2
ADCE1
ADCE0
Table 37 Description of SAD2 bits
BIT
SYMBOL
DESCRIPTION
7 to 3
2
−
These 5 bits are not used.
ADCE2
ADC2 input select. If ADC2 = 1, the ADC2 input is selected. If ADC2 = 0, the
open-drain bidirectional port line P3.2 is selected.
1
0
ADCE1
ADCE0
ADC1 input select. If ADC1 = 1, the ADC1 input is selected. If ADC2 = 0, the
open-drain bidirectional port line P3.1 is selected.
ADC0 input select. If ADC0 = 1, the ADC0 input is selected. If ADC0 = 0, the
open-drain bidirectional port line P3.0 is selected.
1999 Mar 10
34
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
The clock frequency of each PWM circuit is 1⁄4fosc and
15 ANALOG CONTROL
therefore the repetition frequency of each 7-bit PWM
The P8xCx66 has nine Pulse Width Modulated (PWM)
outputs for analog control purposes e.g., volume, balance,
brightness, voltage synthesized tuning etc. Each PWM
output generates a pulse pattern with a programmable
duty cycle.
output is 1⁄512 osc
.
f
The polarity of each PWM output is fixed active HIGH.
The HIGH period of each PWM output is dependent upon
the contents of the PWM data latch and may be calculated
as shown below:
The nine PWM outputs are specified below:
4 × (PWMn)
• 8 PWM outputs with 7-bit resolution (PWM0 to PWM7)
• 1 PWM output with 14-bit resolution (TPWM).
tHIGH
=
---------------------------------
fosc
where (PWMn) is the decimal value held in the PWMn data
latch
The 7-bit PWM outputs are described in Section 15.1 and
the 14-bit PWM output is described in Section 15.2.
The PWM output analog value is determined by the ratio
of the HIGH period and the repetition period. A DC voltage
proportional to the PWM control setting is obtained by
means of an external integration network (low-pass filter)
connected to the PWM output pin.
15.1 7-bit PWM outputs (PWM0 to PWM7)
The block diagram of a typical 7-bit PWM circuit is shown
in Fig.19.
PWM outputs PWM0 to PWM7 share the same pins as
general I/O port lines P5.1 to P5.7 and P3.3 respectively.
Selection of the pin function as either a PWM output or
general I/O port line is achieved by setting the PWMnE bit
in the associated PWM register (where n = 0 to 7).
The PWM registers are shown in Table 38.
The rising edge of each of the 8 PWM outputs is separated
by one 1⁄4fosc cycle, this is shown in Fig.21. PWM1 will
always start at ‘2’, and PWM5 will start at ‘6’ independent
of other PWMs value.
Figure 20 shows active HIGH PWM output patterns.
Table 38 7-bit PWM data registers
REGISTER ADDRESS
7
6
5
4
3
2
1
0
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
E4H
E5H
E6H
E7H
ECH
EDH
EEH
EFH
PWM0E
PWM1E
PWM2E
PWM3E
PWM4E
PWM5E
PWM6E
PWM7E
data6
data6
data6
data6
data6
data6
data6
data6
data5
data5
data5
data5
data5
data5
data5
data5
data4
data4
data4
data4
data4
data4
data4
data4
data3
data3
data3
data3
data3
data3
data3
data3
data2
data2
data2
data2
data2
data2
data2
data2
data1
data1
data1
data1
data1
data1
data1
data1
data0
data0
data0
data0
data0
data0
data0
data0
1999 Mar 10
35
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
internal data bus
f
Port data I/O
osc
4
7-BIT PWM DATA LATCH
PWMnE
Q
7-BIT DAC PWM
CONTROLLER
Port/PWMn
MGL398
Fig.19 Block diagram of a typical 7-bit PWM circuit.
f
osc
4
128
1
2
3
m
m + 1
m + 2
127
128
1
00
01
m
127
MGL290
decimal value PWM data latch
Fig.20 Example of 7-bit PWM output patterns.
36
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
f
osc
4
128
1
2
3
m
m + 1
m + 2
128
1
2
3
PWM0
PWM1
PWM2
(1)
(1)
(1)
(1)
PWM3
MGL289
(1) PWM outputs displaced by 1⁄4fOSC cycle.
Fig.21 Separation of PWM output rising edges.
1999 Mar 10
37
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
Figure 24 shows the output of the coarse pulse controller
when VSTH = 001 1101; Fig.25 shows the output of the
fine pulse controller when VSTL = 1111010, and Fig.26
shows a typical TPWM output after the ‘OR’ operation has
been carried out by the mixer.
15.2 14-bit PWM output (TPWM)
The on-chip 14-bit DAC has one output with a resolution of
16384 levels for Voltage Synthesized Tuning (VST).
The output is active HIGH, the HIGH period being
determined by the values stored in the SFRs TDACH and
TDACL. The 14-bit DAC output is connected to the TPWM
pin.
15.2.1 REPETITION TIME OF OUT1 AND OUT2:
The repetition period of OUT1 (Tsub) may be calculated as
shown in Equation (1).
TPWM shares the same pin as port line P5.0. Selection of
the pin function as either a PWM output or as a port line is
achieved using the TPWME bit in SFR TDACH, see
Section 15.2.5.
128
Tsub
=
= 128 × t0
(1)
-------------
fTDAC
The block diagram for the 14-bit PWM circuit is shown in
Fig.22 and consists of:
1
Where t0
=
-------------
fTDAC
• Two 7-bit SFRs: TDACH and TDACL
• One 14-bit register TDACREG
The repetition period of OUT2 (Tstd) may be calculated as
shown in Equation (2).
• One coarse control block for the generation of the
coarse adjustment pulse
128
fTDAC
T std
=
× 128 = 16384 × t
(2)
--------------
0
• One fine control block for the generation of the fine
adjustment pulses
15.2.2 COARSE ADJUSTMENT
• One 14-bit counter running at fTDAC
An active HIGH pulse is generated in every subperiod
• One mixer block that combines the coarse adjustment
pulse and fine tuning pulses; the resultant pulse pattern
is fed to the TPWM output.
(except the first one); the pulse duration being determined
by the contents of VSTH. The coarse pulses are generated
at the OUT1 output. The coarse pulse output is LOW at the
start of each subperiod and will remain LOW until the time
[ (128 – VSTH) × t0] has elapsed. The output will then go
HIGH and remain HIGH until the start of the next
subperiod. The coarse pulse duration is (VSTH × t0) .
The trailing edge of each coarse pulse coincides with the
end of each Tsub period. If VSTH = 0000000, then the
coarse output is LOW for the complete period. If the
contents of VSTH = 1111111, then the coarse output is
LOW for the first t0 period but will go HIGH for the
remaining 127 × t0 periods of Tsub.
Data is loaded into the 14-bit data latch (TDACREG) from
the two 7-bit data latches (TDACL and TDACH) at the
beginning of the first Tsub period, after TDACH has been
written to. To ensure that correct data is loaded into
TDACREG, the data held in TDACL must be valid before
the write operation to TDACH is started. In other words,
TDACL must be written first before TDACH can be written
to. Examples of valid and invalid loading sequences are
shown in Fig.23.
Once TDACREG has been loaded it takes one Tsub period
to generate the appropriate pulse patterns. To ensure
correct operation of the DAC, two Tsub periods should be
allowed before any further changes to the data latches are
made.
15.2.3 FINE ADJUSTMENT
Fine adjustment is achieved by generating an additional
pulse in specific subperiods. These additional pulses
appear at the OUT2 output. The pulse is added at the start
of the selected subperiod and has a pulse width of t0.
The value held in VSTL determines the subperiod in which
an additional pulse is generated and also determines the
number of additional pulses that will be added during one
Tstd period. Table 39 shows the relationship between the
value held in VSTL, the subperiod during which an
additional pulse OUT2 is generated and the total number
of additional OUT2 pulses generated.
The upper seven bits of TDACREG, identified as VSTH,
are used for coarse adjustment and the lower seven bits,
identified as VSTL, are used for fine adjustment.
The outputs OUT1 and OUT2 of the coarse and fine pulse
controllers are ‘ORed’ in the mixer to give the TPWM
output.
The 14-bit counter is continuously running and is clocked
by fTDAC which is 1⁄4fosc
.
1999 Mar 10
38
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
For example, if the contents of VSTL = 000 0000, no
additional pulses are generated; if the contents of
VSTL = 111 1111, the number of additional pulses that are
generated is 127. Therefore, up to 127 additional pulses
can be added during a Tstd period. Additional pulses must
be distributed equally in one Tstd period (pulse distribution
procedure).
Two extreme cases are worthy of further analysis:
• VSTH = 000 0000, and VSTL = 000 0000. No coarse
pulses will be generated and OUT1 is LOW for the whole
Tstd period. No fine pulses will be generated and
consequently TPWM is LOW for the whole Tstd period.
• VSTH = 111 1111 and VSTL = 111 1111. This value of
VSTH results in OUT1 being LOW for the first t0 period
but will go HIGH for the remaining 127 × t0 periods in the
Tsub cycle. This value of VSTL will generate
Figure 25 shows some examples of OUT2.
15.2.4 THE TPWM OUTPUT
127 additional fine pulses (in every Tsub cycle except in
T
sub0). These additional fine pulses fill the gaps in the
If the contents of VSTH = 001 1101, and the contents of
VSTL = 000 0010, then the TPWM output is as shown in
Fig.26. The additional OUT2 pulses are generated in
subperiods 32 and 96.
OUT1 output (except in Tsub0). Consequently, the
TPWM output will be LOW for the first t0 period (Tsub0
but will be HIGH for the remainder of the Tstd period.
)
Table 39 Additional pulse distribution
VSTL
CONTENTS
ADDITIONAL PULSE GENERATED
IN SUBPERIOD Tsubn
TOTAL NUMBER OF
BINARY POSITION
ADDITIONAL OUT2 PULSES
000 0000
000 0001
000 0010
−
−
0
1
2
3
64
100 0000
010 0000
32, 96
32, 64, 96
100 0000
010 0000
000 0011
000 0100
000 0101
000 1000
001 0000
16, 48, 80, 112
001 0000
4
5
16, 48, 64, 80, 112
100 0000
001 0000
8, 24, 40, 56, 72, 88, 104, 120
000 1000
8
4, 12, 20, 28, 36, 44, 52, 60, ...116,
124
16
000 0100
010 0000
100 0000
2, 6, 10, 14, 18, 22, 26, 30, ...122, 126
1, 3, 5, 7, 9, 11, 13, 15, ...125, 127
000 0010
000 0001
32
64
1, 2, 3, 4, ...62, 63, 65, 66, ...125, 126,
127
010 0000
001 0000
000 1000
000 0100
000 0010
000 0001
126
111 1110
111 1111
1, 2, 3, 4, 5, 6, 7, ...125, 126, 127
100 0000
010 0000
001 0000
000 1000
000 0100
000 0010
000 0001
127
1999 Mar 10
39
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
15.2.5 SPECIAL FUNCTION REGISTER TDACH
Table 40 SFR TDACH (SFR address D3H)
7
6
5
4
3
2
1
0
TPWME
−
TD13
TD12
TD11
TD10
TD9
TD8
Table 41 Description of TDACH bits
BIT
SYMBOL
DESCRIPTION
7
TPWME
TPWM enable. When TPWME = 1, pin 1 is the TPWM output. When TPWME = 0, pin 1
is general I/O line P5.0.
6
−
This bit is not used.
5 to 0
TD13 to TD8 These 6 bits are loaded into TDACREG and form the 6 MSBs (TDACREG<13-8>).
15.2.6 SPECIAL FUNCTION REGISTER TDACL
Table 42 SFR TDACL (SFR address D2H)
7
6
5
4
3
2
1
0
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TD0
Table 43 Description of TDACL bits
BIT
SYMBOL
DESCRIPTION
This bit is loaded into TDACREG and becomes bit 7 (TDACREG.7).
7
TD7
6 to 0
TD6 to TD0 These 7 bits are loaded into TDACREG and form the 7 LSBs (TDACREG<6-0>).
1999 Mar 10
40
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
internal data bus
SFR address: D3H
SFR address: D2H
"MOV instruction"
7-BIT DATA LATCH
(TDACH)
7-BIT DATA LATCH
(TDACL)
(1)
(2)
7
7
DATA LOAD
TIMING PULSE
14-BIT DATA LATCH
(TDACREG)
LOAD
7
7
COARSE 7-BIT
PWM
FINE PULSE
GENERATOR
OUT1
OUT2
MIXER
Q
TDAC output
TPWM
Q14 to Q8
Q7 to Q1
f
= f
14-BIT COUNTER
TDAC osc
4
MGL399
(1) These are the upper 7 bits of TDACREG and are called VSTH.
(2) These are the lower 7 bits of TDACREG and are called VSTL.
Fig.22 Block diagram of the 14-bit PWM circuit.
41
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
T
T
T
sub
sub
sub
Case 1
correct
write
TDACL TDACH
write
new TDACL and TDACH is loaded
into TDAC
VSTH old
VSTL old
VSTH new
VSTL new
status bus
Case 2
write
TDACL
write
TDACH
new TDACL and TDACH is loaded
into TDAC
correct
status bus
Case 3
VSTH old
VSTL old
VSTH old
VSTL old
VSTH new
VSTL new
write
TDACH
old TDACL and TDACH is loaded
write
TDACL
wrong
into TDAC
VSTH old
VSTL old
VSTH new
VSTL old
VSTH new
VSTL old
MGL288
status bus
Fig.23 Loading VSTL and VSTH into VSTREG.
T
(= 128T
T
)
sub
std
T
sub1
T
subm
sub128
VSTH × t
VSTH × t
VSTH × t
0
0
0
MGL287
0
128 × t
0
(128-VSTH) × t
0
Fig.24 Coarse adjustment output (OUT1).
42
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
T
(= 128T
T
)
sub
std
T
T
T
T
T
T
T
sub0
sub16
sub32
sub48
sub64
sub80
sub96
sub112
subperiod
000 0000
000 0001
000 0010
000 0011
000 0100
111 1110
111 1111
VSTL
MGL281
Fig.25 Fine adjustment output (OUT2).
T
std
T
T
T
T
T
T
sub127
sub0
sub31
sub32
sub95
sub96
OUT1
VSTH × t
VSTH × t VSTH × t
VSTH × t VSTH × t
VSTH × t
0
0
0
0
0
0
OUT2
TDAC OUTPUT
VSTH × t
VSTH × t
VSTH × t
VSTH × t
0
0
0
0
(VSTH + 1) × t
(VSTH + 1) × t
0
0
MGL280
Fig.26 An example of TPWM output (VSTH = 001 1101 and VSTL = 000 0010).
43
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
The conversion time of the ADC is equal to 8 machine
cycles (8 µs at 12 MHz). Some NOP instructions should be
added in between the instruction which changes the
reference voltage or the channel selection and the
instruction which reads the VHI register bit. The ST bit
must be set to a logic 1 at the same time as the reference
voltage or channel selection change, otherwise the VHI
state of the previous comparison will be read out.
The recommended procedure is as follows:
16 ANALOG-TO-DIGITAL CONVERTERS (ADC)
The 3 channel ADC consists of a 4-bit Digital-to-Analog
Converter (DAC), a comparator, an analog channel
selector and control circuitry. The block diagram of the
ADC circuit is shown in Fig.27.
One of these channels can be used to measure the level
of the Automatic Frequency Control signal. This is
achieved by comparing the ADC signal with the output of
a 4 bit DAC using the comparator (accuracy ±1⁄2 LSB).
1. Write SFR SAD (X, CH<1:0>, ST = 1, SAD<3:0>)
2. Wait 8 machine cycles (for example 8 NOPs)
3. Read SFR SAD for VHI value.
The ADC inputs ADC0, ADC1 and ADC2 share the same
pins as general I/O port lines P3.0, P3.1 and P3.2,
respectively. Selection of the pin function as either an ADC
input or a general I/O port line is achieved using bits
ADCE0, ADCE1 and ADCE2 in SFR SAD2 (see
Section 16.2).
ST is reset by hardware when it is set to a logic 1 by a
written instruction. When ST is read, the value is always a
logic 0.
internal bus
DERIVATIVE PORT
SELECTOR
EN0
EN1
EN2
P3.0/ADC0
ADC
CHANNEL
SELECTOR
VHI
P3.1/ADC1
(SFR address: C8H)
COMPARATOR
EN
V
ref
P3.2/ADC2
ENABLE
SELECTOR
Channel selection
CH1
CH0
4-BIT DAC
ADCE2 ADCE1 ADCE0
ADC enable selection (SFR address: CAH)
SAD3
SAD2
SAD1
SAD0
MGL397
AFC value selection (SFR address: C8H)
Fig.27 ADC block diagram.
1999 Mar 10
44
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
16.1 ADC Control Register 1 (SAD)
Table 44 ADC Control Register 1 (SFR address C8H)
7
6
5
4
3
2
1
0
VHI
CH1
CH0
ST
SAD3
SAD2
SAD1
SAD0
Table 45 Description of SAD bits
BIT
SYMBOL
DESCRIPTION
7
VHI
Compare result. If VHI = 0, then the ADC input voltage is lower than the reference
voltage. If VHI = 1, then the ADC input voltage is higher than the reference voltage.
6
5
4
CH1
CH0
ST
ADC input channel selection. These 2 bits select the ADC channel, see Table 46.
Start voltage comparison. If ST = 0, voltage comparison is disabled. If ST = 1, a
voltage comparison is started.
3
2
1
0
SAD3
SAD2
SAD1
SAD0
Reference voltage level selection. These 4 bits are used to select the analog output
voltage (Vref) of the 4-bit DAC. Vref is calculated as shown below.
V
Vref
=
DD × (SAD value + 1)
----------
16
Table 46 ADC input channel selection
CH1
CH0
CHANNEL SELECTED
0
0
1
1
0
1
0
1
Reserved.
Input channel ADC0 selected.
Input channel ADC1 selected.
Input channel ADC2 selected.
16.2 ADC Control Register 2 (SAD2)
Table 47 ADC Control Register 2 (SFR address CAH)
7
6
5
4
3
2
1
0
−
−
−
−
−
ADCE2
ADCE1
ADCE0
Table 48 Description of SAD2 bits
BIT
SYMBOL
DESCRIPTION
7 to 3
2
−
These 5 bits are not used.
ADCE2
ADC2 input select. If ADC2 = 1, then pin 11 is selected as the ADC2 input. If
ADC2 = 0, then pin 11 is selected as the open-drain bidirectional port line P3.2.
1
0
ADCE1
ADCE0
ADC1 input select. If ADC1 = 1, then pin 10 is selected as the ADC1 input. If
ADC2 = 0, then pin 10 is selected as the open-drain bidirectional port line P3.1.
ADC0 input select. If ADC0 = 1, then pin 9 is selected as the ADC0 input. If ADC0 = 0,
then pin 9 is selected as the open-drain bidirectional port line P3.0.
1999 Mar 10
45
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
• Vertical jitter cancelling circuit to avoid unstable VSYNC
leading edge mismatch with HSYNC signal
17 ON-SCREEN DISPLAY (OSD)
17.1 Features
• OSD clock operating frequency: 4 to 12 MHz
• Meshing function.
• Programmable active level polarity of VSYNC, HSYNC
and digital RGB with polarity selection
• Display RAM: 192 × 12 bits
17.2 Flexible display format
• Display character fonts: 128 (126 customer fonts plus
2 reserved codes)
Figures 28 and 29 show typical examples of on-screen
displays generated by the P8xCx66.
• One programmable vertical starting position counter
giving 63 different vertical starting positions
There are 128 different fonts available two of which, the
Carriage Return (CR) code and the Space (SP) code, are
reserved for special functions. The CR code performs the
same function as the return key on a conventional
keyboard, the display will start on the next line. The SP
code enables the background colour of the space itself
and that of the following characters to be changed.
• One programmable horizontal starting position counter
giving 110 different horizontal starting positions
• Character size: 4 character sizes on a line-by-line basis
• Character matrix: 12 × 18 with no spacing between
characters
There are 192 display RAM locations (00H to BFH) and
these are considered as a linear addressed RAM. The first
character fetched is from the display RAM address pointed
to by the contents of the Special Function Register
OSSTART (see Section 17.3.5).
• Foreground colours: 8 on a character-by-character
basis
• Background/shadowing modes: Two primary modes:
TV mode and Frame mode on a frame basis. Each
primary mode has four sub-modes on a character row
basis:
The OSD starting position is programmable, this is
described in detail in Section 17.2.1.
– Sub-mode 1: Superimpose (no background)
– Sub-mode 2: North-West shadowing
– Sub-mode 3: Box background
Two other registers are used to program the OSD:
OSCON and OSCON2. These registers are described in
Sections 17.3.2 and 17.3.6.
– Sub-mode 4: Border shadowing.
• Background colours: 8 on a word-by-word basis.
Available when background is either in North-West
shadowing, Box background, Border shadowing and
Frame shadowing sub-modes.
17.2.1 OSD STARTING POSITION
The horizontal and vertical starting position of the display
is controlled by two counters: SFRs OSORGH and
OSORGV.
• Display RAM starting address is programmable. Fast
switching between banks of display characters is
possible through software control.
OSORGH controls the horizontal starting position. This
counter is incremented every OSD clock cycle after the
falling edge of HSYNCP (after the polarity selection).
HSYNCP is always active HIGH. OSORGH is described in
Section 17.3.4.
• HSYNC driven PLL (frequency determined by SFR
OSPLL)
• Character blinking ratio: 1 : 1
OSORGV controls the vertical starting position. This
counter is incremented every HSYNC cycle and is reset by
the VSYNC signal. OSORGV is described in
Section 17.3.3.
• Character blinking frequency: programmable using
fVSYNC divisors of 32 and 64, on a character basis
• Display format: Flexible display format by using CR
(carriage return) and SP1, SP2 (space) and split space
code
The OSD starting position reference points are shown in
Fig.32.
• Display RAM address post increment each time new
data is written
1999 Mar 10
46
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
OSORGV
(C2H)
OSORGH
(C3H)
SP1
CR
CR
SP1
SP2
CR
SP1
CR
MGL303
Fig.28 An example of flexible display format (Split space off).
ahdnbok,uflapegwidt
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
VPx
(C2H)
HPx
(C3H)
SP1
CR
SP2
CR
SP1
SP2
SP2
CR
SP2
SP1
CR
MGL304
Fig.29 An example of flexible display format (Split space on).
ahdnbok,uflapegwidt
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
17.3 OSD registers
17.3.1 OSD DEFAULT REGISTER (OSDDEF)
This register is used to set the default values for background colour, character size and sub-mode after each VSYNC
pulse. After a system reset OSDDEF holds 22H. These values can be changed by writing new data to OSDDEF or by
starting the screen with a space code (SP1 or SP2) and a CR code.
Table 49 OSD Default Register (SFR address 9CH)
7
6
5
4
3
2
1
0
R
G
B
−
SV
SH
M1
M0
Table 50 Description of OSDEF bits
BIT
7
SYMBOL
DESCRIPTION
R
G
Default background colour. These 3 bits select the default background colour.
6
5
B
4
−
This bit is reserved for future use (intensity output).
3
SV
Default character size. If SV = 0, then the vertical dot size is equal to one horizontal
line. If SV = 1, then the vertical dot size is equal to two horizontal lines.
2
SH
Default horizontal dot size. If SH = 0, then the horizontal dot size is equal to one OSD
clock. If SH = 1, then the horizontal dot size is equal to two OSD clocks.
1
0
M1
M0
Default sub-mode selection. These 2 bits select the default sub-mode; see Table 51.
Table 51 Default sub-mode selection
M1
M0
SUB-MODE
0
0
1
1
0
1
0
1
Superimpose mode selected.
North-West shadowing mode selected.
Box background mode selected.
Border shadowing mode selected.
The default value of OSDDEF gives the following initial settings:
• Character size = 1 horizontal line/1 DOSC (Fig.31)
• Background colour = blue (R = G = 0, B = 1)
• Sub-mode = Box background mode.
1999 Mar 10
49
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
17.3.2 OSD CONTROL REGISTER 1 (OSCON)
Table 52 OSD Control Register 1 (SFR address C1H)
7
6
5
4
3
2
1
0
Split
Mesh
Mode
Hp
Vp
Bp
BF
OSDE
Table 53 Description of OSCON bits
BIT
SYMBOL
DESCRIPTION
7
Split
Split space control. If Split = 0, then split space is disabled. If Spilt = 1, then split
space is enabled on frame-by-frame basis. Split space only effects Space 1 (SP1)
because Space 2 (SP2) is displayed transparent.
6
5
Mesh
Mode
OSD meshing mode. If Mesh = 0, then the OSD meshing mode is disabled.
If Mesh = 1, the OSD meshing mode is enabled.
Background mode selection. If Mode = 0, then TV mode is selected (FB only active
when there are characters displayed). If Mode = 1, then Frame mode is selected (FB is
active in every single active scan line; FB is inactive during horizontal and vertical
retrace period).
4
3
2
1
Hp
Vp
Bp
BF
HSYNC active polarity selection. If Hp = 0, then HSYNC is an active LOW input.
If Hp = 1, then HSYNC is an active HIGH input. See Fig.30.
VSYNC active polarity selection. If Vp = 0, then VSYNC is an active LOW input.
If Vp = 1, then VSYNC is an active HIGH input. See Fig.30.
Active R, G, B and FB output polarity selection. If Bp = 0, then these signals are all
active LOW. If Bp = 1, then these signals are all active HIGH. See Fig.31.
Character blinking frequency control. If BF = 0, the blinking frequency is 1⁄32fVSYNC. If
BF = 1, the blinking frequency is 1⁄64fVSYNC. The duty cycle of the blinking frequency is
fixed at 1 : 1.
0
OSDE
OSD circuit general enable/disable. If OSDE = 0, the OSD is disabled and the R, G, B
and FB signals stay in the inactive status (inverse of the Bp bit in SFR OSCON). If
OSDE = 1, the OSD is enabled.
fly-back period
HSYNC/VSYNC pin
Hp/Vp = 0 (active LOW)
character display interval
HSYNC/VSYNC pin
Hp/Vp = 1 (active HIGH)
MGL284
fly-back period
Fig.30 HSYNC and VSYNC active level selection.
50
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
FB (R, G, B) pin
Bp = 0 (active LOW)
character
display
character
display
intervals
intervals
FB (R, G, B) pin
Bp = 1 (active HIGH)
MGL283
Fig.31 Active R, G, B and FB polarity control.
17.3.3 OSD VERTICAL START REGISTER (OSORGV)
Table 54 OSD Vertical Start Register (SFR address C2H)
7
6
5
4
3
2
1
0
−
−
VP5
VP4
VP3
VP2
VP1
VP0
Table 55 Description of OSORGV bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
−
These 2 bits are not used.
−
VP5
VP4
VP3
VP2
VP1
VP0
Vertical starting position selection. These 6 bits select the vertical starting position of
the OSD. 1 of 63 starting positions may be selected. The reference point of the vertical
starting position is the leading edges of VSYNCP and HSYNCP. The vertical starting
position (VP) is calculated as follows:
VP = 4 × (VP5 → VP0) × horizontal scan lines
Where (VP5 → VP0) is the decimal value of the contents of OSORGV and
(VP5 → VP0) ≥ 1.
1999 Mar 10
51
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
17.3.4 OSD HORIZONTAL START REGISTER (OSORGH)
Table 56 OSD Horizontal Start Register (SFR address C3H)
7
6
5
4
3
2
1
0
−
HP6
HP5
HP4
HP3
HP2
HP1
HP0
Table 57 Description of OSORGH bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
−
This bit is not used.
HP6
HP5
HP4
HP3
HP2
HP1
HP0
Horizontal starting position selection. These 7 bits select the horizontal starting
position of the OSD. 1 from 110 starting positions may be selected.The reference point
of the horizontal starting position is the leading edge of HSYNC. The horizontal starting
position (HP) is calculated as follows:
HP = 2 × (HP6 → HP0) × OSD clock
Where (HP6 → HP0) is the decimal value of the contents of OSORGH and
(HP6 → HP0) ≥ 12H.
Note that the period of the horizontal starting position plus characters display cannot be
more than one HSYNC period (for example 64 µs).
HSYNCP
VSYNCP
VPx
Personal preferrance
Sound
HPx
Picture
Tuning
Leading edge of HSYNCP is the reference point of HPx
Leading edge of VSYNCP is the reference point of VPx
MGL285
Fig.32 OSD starting position reference points.
52
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
17.3.5 OSD START REGISTER (OSSTART)
Table 58 OSD Start Register (SFR address C5H)
7
6
5
4
3
2
1
0
START7
START6
START5
START4
START3
START2
START1
START0
Table 59 Description of OSSTART bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
START7
START6
START5
START4
START3
START2
START1
START0
RAM start address. These 7 bits specify the display RAM address from which the first
character will be fetched. The display RAM address is from 0 to 191 decimal, or
00 to BF hexadecimal.
17.3.6 OSD CONTROL REGISTER 2 (OSCON2)
Table 60 OS Control Register 2 (SFR address CFH)
7
6
5
4
3
2
1
0
−
−
−
TCEN
R
G
B
−
Table 61 Description of OSCON2 bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
−
These 3 bits are reserved.
−
−
TCEN
Test Code Enable. When TCEN = 1, the content of the space from character ROM is
displayed. This is valid for Space 1 and Space 2. The default value of TCEN is a logic 0.
This feature is for testing purposes only.
3
2
1
0
R
G
B
−
Background colour selection. These 3 bits select the background colour of the
TV screen in the Frame mode. The default background colour is blue.
This bit is reserved.
1999 Mar 10
53
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
17.4 OSD clock generator
The clock generator comprises Phase-Locked-Loop circuitry. The frequency of the OSD clock is programmable and is
determined by the decimal value of the contents of the 8-bit OSPLL register. OSD clock frequencies within the range
4 to 12 MHz can be selected in increments of 31.25 kHz. The OSD frequency (fOSD) is calculated as shown below:
fOSD = 2 × fHSYNCP × (129 + OSPLL value)
Where fHSYNCP is the horizontal sync frequency after the polarity selection circuit.
17.4.1 OSD PLL REGISTER (OSPLL)
The reset value of OSPLL is 00H.
Table 62 OSD PLL Register (SFR address C4H)
7
6
5
4
3
2
1
0
PLL7
PLL6
PLL5
PLL4
PLL3
PLL2
PLL1
PLL0
Table 63 Description of OSPLL bits
BIT
SYMBOL
DESCRIPTION
7 to 0
PLL7 to PLL0 These 8 bits are used to select the OSD clock frequency. Examples of OSD clock
selection are shown in Table 64.
Table 64 Selection of OSD clock frequency
OSPLL VALUE
OSD FREQUENCY (MHz)
00H
3FH
7FH
BFH
FFH
4.00
6.00
8.00
10.00
12.00
SYSCLK
handbook, halfpage
DI
RESET
OSPLL
(C4H)
LOAD_SFR
HSYNCP
f
OSD
PLL
DIVIDER
÷2
HSYNC
MGM681
Fig.33 OSD PLL.
54
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
Bit <0> is the end of display control bit and stops the
display function before the last display RAM address
(191 decimal). By combining the ‘end of display’ feature
with the start RAM address (controlled by SFR OSSTART)
the display RAM can be configured into several banks for
fast display data switching. The states of the end of display
control bit are defined in Table 68.
17.5 Display RAM organization
The display character RAM is organized as 192 × 12 bits.
The general format of each RAM location is as follows.
Bits <11-5> hold character data: 1 out of 128 different
character fonts may be specified (126 customized fonts
plus 2 reserved codes). Bits <4-0> hold attribute data of
the character font, for example, colour, character size etc.
Table 65 Selection of vertical size
17.5.1 DISPLAY RAM FORMATS
BIT 4
VERTICAL SIZE
There are four different formats to be considered:
1. Customer character code.
0
One vertical dot is equal to one horizontal
scan-line width.
2. Carriage Return code
1
One vertical dot is equal to two horizontal
scan-line widths.
3. Space code 1 and Space code 2.
These formats are shown in Tables 70 to 72.
17.5.1.1 Customer character code
Table 66 Selection of horizontal size
BIT 3
HORIZONTAL SIZE
If bits <11-5> are in the range 00H to 7CH then this is a
customized character code.
0
One horizontal dot is equal to one OSD clock
width.
Bits <4-2> select the character colour, a choice of
8 colours are available.
1
One horizontal dot is equal to two OSD clock
widths.
Bit <0> determines whether the character blinks or not.
The actual blinking frequency is determined by the BF bit
in SFR OSCON.
Table 67 Selection of sub-modes
BIT 2
BIT 1
SUB-MODE
Superimpose
0
0
1
1
0
1
0
1
17.5.1.2 Carriage Return code
North-West shadowing
Box shadowing
If bits <11-5> hold 7EH then this is the Carriage Return
code. A transparent pattern will be displayed on the
screen, the current display row will be terminated and the
character stored in the display RAM next to this code will
be displayed at the beginning of the next row.
Border shadowing
Table 68 End of display control
Bits <4-3> select the size of the characters to be displayed
in the next row. The character size is independently
controlled in both the vertical and the horizontal direction.
Bit <4> controls the vertical size as shown in Table 65 and
bit <3> controls the horizontal size as shown in Table 66.
Figure 34 shows the four different character sizes
available.
BIT 0
OPERATION
0
1
Continue to display in next row.
Stop the display and wait for the next display
field. As soon as the horizontal and vertical
starting position has been reached, continue
to display.
Bits <2-1> select the display sub-mode of the next row.
Four sub-modes can be selected (see Table 67) in either
the Frame mode or the TV mode. Therefore a total of
8 different modes are available, these are illustrated in
Figs 35 and 36.
1999 Mar 10
55
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
• In North-West shadowing sub-mode the background
17.5.1.3 Space code 1 and Space code 2
colour is the colour of the bit pattern shadow
If bits <11-5> hold 7FH, then this is a space code. One of
two space codes can be selected: Space code 1 and
Space code 2.
• In Box shadowing sub-mode the background colour is
the colour within the character 12 × 18 dot matrix where
no foreground character bits are present
Space code 2 always displays a transparent pattern, equal
to one character width, on the screen regardless of which
primary mode and sub-mode is selected. Space code 1
only differs from Space code 2 when in the Box shadowing
sub-mode. In this mode SP1 displays a 12 × 18 dot matrix
pattern filled with the background colour whilst SP2
displays a transparent pattern. See Figs 37 and 38.
• In the Superimpose sub-mode there is no background
colour
• In the Border shadowing sub-mode the background
colour is the colour of the border bit pattern.
17.5.1.4 Summary of CR, SP1 and SP2 functions
• Carriage Return code:
Selection of a specific space code is determined by the
state of bit 0 as detailed in Table 69.
– Ends the current display row and uses the character
in the display RAM next to this CR code as the first
character of next display row
Table 69 Selection of Space code
– Selects the character size of next display row
– Selects the character sub-mode of next display row
– Indicates the end of display for present screen.
• Space code 1 and Space code 2:
BIT 0
SPACE CODE
Space code 1 is selected.
Space code 2 is selected.
0
1
– Inserts transparent pattern in a row of characters
Bits <4-1> determine the background colour of the
characters that follow the space code dependent upon the
sub-mode selected, see Figs 35 and 36.
– Selects the background colour of the characters
following this space code.
Table 70 Format of Character font code
11
10
9
8
7
6
5
4
3
2
1
0
Character Font code (00H to 7CH)
Foreground colour
Blink
T0
C6
C5
C4
C3
C2
C1
C0
T4
T3
T2
T1
Table 71 Format of Carriage Return code
11
10
9
8
7
6
5
4
3
2
1
0
Carriage Return code (7EH)
Character size
Mode
End
T1
C6
C5
C4
C3
C2
C1
C0
T4
T3
T2
T1
Table 72 Format of Space code
11
10
9
8
7
6
5
4
3
2
1
0
Space code 1 and Space code 2 (7FH)
Background colour
0
SP1
SP2
C6
C5 C4 C3 C2 C1
C0
T4 T3 T2
T1
T0
1999 Mar 10
56
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
1 horizontal
1 horizontal
scan line
scan line
SH = 0
SV = 0
SH = 1
SV = 0
f
2 x f
OSD
OSD
2 horizontal
scan line
2 horizontal
scan line
SH = 1
SV = 1
SH = 0
SV = 1
MLC789
2 x f
f
OSD
OSD
Fig.34 Four different character size combinations.
1999 Mar 10
57
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
Superimpose
sub-mode
North-West
shadowing
sub-mode
Border shadowing
sub-mode
TV screen
TV picture
Box
shadowing
sub-mode
MGL305
foreground colour
background colour
OSCON < 5 > = 0 (TV MODE)
Fig.35 Four different sub-modes in TV mode.
Superimpose
sub-mode
North-West
shadowing
sub-mode
Border shadowing
sub-mode
TV screen
this monitor
background colour
is controlled
by SFR OSCON2
Box
shadowing
sub-mode
MGL306
foreground colour
background colour
OSCON < 5 > = 1 (Frame mode)
Fig.36 Four different sub-modes in Frame mode.
58
1999 Mar 10
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
Box background sub-mode
SP1
SP1
SP2
SP2
SP1
CR
Superimpose sub-mode
SP2
CR
North-west shadowing sub-mode
Border shadowing sub-mode
SP1
SP2
SP2
CR
SP2
SP1
SP2
CR
MGL310
Fig.37 SP1 and SP2 codes in the 4 sub-modes of TV mode.
ahdnbok,uflapegwidt
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
Box background sub-mode
SP1
SP1
SP2
SP2
SP1
CR
Superimpose sub-mode
SP2
CR
North-west shadowing sub-mode
Border shadowing sub-mode
SP1
SP2
SP2
CR
SP2
SP1
SP2
CR
MGL311
Fig.38 SP1 and SP2 codes in the 4 sub-modes of Frame mode.
ahdnbok,uflapegwidt
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
17.6 Loading character data into display RAM
17.7 Writing character data into the display RAM
Three registers are used to address and load data into the
display RAM: OSAD, OSDT and OSAT. These registers
are described in Sections 17.6.1 to 17.6.3.
The procedure for writing character data into the display
RAM is as follows:
1. Initialize the starting address of the display RAM by
writing data into OSAD.
17.6.1 OSD ADDRESS REGISTER (OSAD)
2. Write the character attributes to OSAT. If the attributes
of a series of displayed characters are the same, the
contents of this register need not be changed; only
OSDT need be updated.
This register holds the address of the location in display
RAM, into which character data is to be written.
Table 73 OSD Address Register (address 9BH)
3. Write the character font code to be displayed to OSDT.
When the write to OSDT operation is finished an
automatic transfer occurs that loads the data stored in
OSAT and OSDT into the display RAM location
addressed by OSAD. The address held in OSAD is
then incremented by ‘1’.
7
6
5
4
3
2
1
0
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
17.6.2 OSD DATA REGISTER (OSDT)
4. Post increment operation is executed in OSAD
(OSAD ← OSAD + 1) making it point to the next RAM
location. On overflow OSAD is cleared. Figure 39
shows the post-increment operation.
This register holds the character font data that will be
loaded into bits <11-5> of the location in RAM addressed
by the contents of OSAD.
Table 74 OSD Data Register (address 9AH)
7
6
5
4
3
2
1
0
−
C6
C5
C4
C3
C2
C1
C0
17.6.3 OSD ATTRIBUTE REGISTER (OSAT)
This register is loaded with character attribute data.
handbook, halfpage
00
01
02
03
04
89
OSAD
The data will be loaded into bits <4-0> of the location in
RAM addressed by the contents of OSAD. The actual
attribute is dependent upon whether the Character Font
Code, Carriage Return Code, Space Code 1 or Space
Code 2 has been selected.; this is explained in
191
190
189
numbers are in decimal
91
90
MGL282
Section 17.5.1. Bits 7 to 5 are not used and are reserved.
Fig.39 OSAD post-increment operation.
Table 75 OSD Attribute Register (address 99H)
7
6
5
4
3
2
1
0
−
−
0
T4
T3
T2
−
T0
1999 Mar 10
61
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
17.8 Character ROM
17.10 Combination of two or more font cells
128 character fonts may be stored in ROM: 126 customer
selected character fonts plus two reserved codes (the
Carriage Return code and the Space code).
Two (or more) character font cells may be combined in a
vertical or horizontal direction to create a new higher
resolution pattern.
Each character font is stored in a 12 × 19 dot matrix in
character ROM. However, only elements in rows 1 to 18
can be selected as visible dots on the TV screen. Row 0 is
used only in the North-West shadowing sub-mode and the
Border shadowing sub-mode when two character cells are
to be combined in a vertical direction to formulate a new
pattern. If combination of character fonts is not required
then row 0 should be filled with zeros. An example of a bit
pattern stored in ROM is shown in Fig.40.
The combination of two cells in a horizontal direction is
straight forward and presents no problems to the user.
All 4 background/shadowing sub-modes can be used.
However, the combination of two character font cells in a
vertical direction is more difficult and care must be taken
otherwise the new pattern may be created with gaps in its
shadowing.
• Row 0 in the character ROM is for use in the North-West
shadowing and Border shadowing sub-modes. If either
of these sub-modes is selected when combining two
character cells in a vertical direction then row 0 must
contain the bit pattern of row 18 of the font above it
otherwise a broken dot in the shadow may occur.
A software package that helps the customer design the
character fonts on the screen and that also generates the
bit pattern HEX files automatically, is available on request,
from local Philips sales organisations. The package is run
under the MS-DOS environment for IBM compatible PCs.
17.11 More about North-West shadowing and Border
shadowing sub-modes
17.9 Character ROM organization
ROM is divided into two parts: OSDL and OSDH.
The address of OSDL is from 0000H to 0FFFH and the
address of OSDH is from 1000H to 1FFFH.
Some special care must be taken when designing the
character bit pattern if the character is intended to be used
in the North-West shadowing or Border shadowing
sub-mode.
The organisation of the bit patterns stored in ROM and the
file format to submit to Philips for customized character
sets is shown in Fig.40. Regarding Fig.40 the following
points should be noted.
• North-West shadowing and Border shadowing
sub-modes are limited in the 18 display scan lines box
only in the vertical direction if the character in the next
row is not in North-West shadowing sub-mode
(otherwise as described in Section 17.10) if the shadow
of the last foreground bit pattern line is intended to be
seen as well. To get correct shadowing following the
character font then in:
1. Each character is structured using 38 bytes.
2. Row 0 of each font is reserved for vertical combination
of two fonts. In vertical mergence row 0 holds the
same code as row 18 of the previous font.
3. Binary 1 denotes visual dots.
– North-West shadowing: row 18 must be blank
– Border shadowing: row 1 and 18 must be blank.
4. ROM data files are in Intel HEX format on a byte basis.
Each byte is structured high nibble followed by low
nibble.
• North-West shadowing and Border shadowing
sub-modes are not limited to the 12 horizontal OSD
dots. Shadows of the previous font cell may cross over
the 12 dot boundary and appear in the next font cell.
5. The unused bytes in ROM must be filled with FFH.
1999 Mar 10
62
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
k
Column
ROM
EPROM
OSDH
EPROM
OSDL
11 10 9
8 7 6 5 4 3 2 1 0
0 0 0
3 F C
2 2 0
2 2 0
3 F C
2 2 0
2 2 0
3 F C
2 2 0
2 2 0
3 F F
0 0 1
0 0 1
5 5 3
5 5 2
0 0 6
0 0 C
0 5 8
0 3 0
F 0
F 3
F 2
F 2
F 3
F 2
F 2
F 3
F 2
F 2
F 3
F 0
F 0
F 5
F 5
F 0
F 0
F 0
F 0
0 0
F C
2 0
2 0
F C
2 0
2 0
F C
2 0
2 0
F F
0 1
0 1
5 3
5 2
0 6
0 C
5 8
3 0
0
1
2
3
4
5
6
7
8
Row
9
10
11
12
13
14
15
16
17
18
Intel Hex
Format
Byte#
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10 0000 00
10 0010 00
10 0020 00
10 0030 00
10 0040 00
..................
00 FC 20 20 FC 20 20 FC 20 20 FF 01 01 53 52 06
--- ---
--- ---
0C 58 30
OSDL
Data for font 2 OSDL
Data for font 3 OSDL
Data for font 4
--- ---
.... .... .... .... .... .... .... ....
--- ---
10 0FE0 00
10 0FF0 00
10 1000 00
10 1010 00
10 1020 00
10 1030 00
10 1040 00
.................
10 1FE0 00
10 1FF0 00
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
F0 F3 F2 F2 F3 F2 F2 F3 F2 F2 F3 F0 F0 F5 F5 F0
--- ---
--- ---
F0 F0 F0
Data for font 2 OSDH
Data for font 3 OSDH
Data for font 4
--- ---
.... .... .... .... .... .... .... ....
--- ---
OSDH
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
MGL312
Fig.40 Character bit pattern stored in on-chip ROM.
63
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
0
1
2
3
4
5
6
7
8
9 10 11
0
1
2
3
4
5
6
7
8
9 10 11
0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11
0
0
0
1
0
1
2
1
1
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
10
11
12
13
14
15
16
17
10
11
12
13
14
15
16
17
10
11
12
13
14
15
16
17
10
11
12
13
14
15
16
17
Character designed character ROM
North-West shadowing mode
character displayed on TV screen
0
1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11
0
1
0
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
10
11
12
13
14
15
16
17
Border shadowing mode
character displayed on TV screen
MGM686
The minimum dot size is 1. Take 1 horizontal line × as an example of the character displayed on the TV screen, in
both the North-West and Border shadowing submodes.
Fig.41 Combination of two font cells in a horizontal direction.
1999 Mar 10
64
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
handbook, halfpage
0
1
2
3
4
5
6
7
8
9 10 11
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
0
1
2
3
4
5
6
7
8
9 10 11
MGL411
Fig.42 Combination of two font cells in a vertical direction.
65
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
17.12 Maximum number of characters per row
17.13 Maximum number of rows per frame
The number of characters per row is a function of the OSD
clock frequency and the TV standard used.
The number of rows per frame is a function of the number
of active lines per display field and the number of vertical
dots in the character matrix (which is 18). The number of
rows per frame (N) is calculated as shown below.
The active video signal period of a horizontal line is
53.5 µs. However, in order to reduce jittering at the screen
edge, overscan is normally applied by the TV
manufacturer and this reduces the visible video signal
period to 48.15 µs.
number of active lines per field
N =
---------------------------------------------------------------------------------
18
The two examples shown below illustrate how the
maximum number of rows per frame is obtained for
different TV scanning standards.
The examples given below show how the number of
characters per row and the character width may be
obtained for the NTSC 525LPF/60 Hz TV standard using
different OSD clock frequencies.
17.13.1 NTSC 525LPF/60 HZ
The number of active lines per field for this standard is
between 241.5 and 249 H. If the value of 241 is used then
the maximum number of rows per frame is 13.
17.12.1 NTSC 525LPF/60 Hz; fOSD = 6 MHZ
• As fOSD = 6 MHz; TOSD = 0.1666 µs
• The number of visible dots on one horizontal line is 290
(48.15 µs/0.1666 µs)
17.13.2 PAL 625LPF/50 HZ
• Each character is composed of a 12 x 18 dot matrix;
therefore the maximum number of characters on one
line is 24 (290/12)
The number of active lines per field for this standard is 280.
Therefore, the maximum number of rows per frame is 15.
• If a 19 inch TV screen is used, the width of a horizontal
line is approximately 370 mm and this gives a character
width of 15.4 mm (370/24).
17.12.2 NTSC 525LPF/60 HZ; fOSD = 10 MHZ
• As fOSD = 10 MHz; TOSD = 0.1 µs
• The number of visible dots on one horizontal line is 481
(48.15 µs/0.1 µs)
• Each character is composed of a 12 x 18 dot matrix;
therefore the maximum number of characters on one
line is 40
• If a 19 inch TV screen is used, the width of a horizontal
line is approximately 370 mm and this gives a character
width of 9.25 mm.
1999 Mar 10
66
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
17.14 OSD vertical debouncing circuit
The HSYNC and VSYNC signals entering the OSD circuit are usually extracted from the horizontal and vertical deflection
units of a television set. The shaping and timing of these signals is therefore related to several external conditions that
all have certain tolerances. The trigger levels of the input circuitry also influence the internal timing of HSYNC and
VSYNC. In the odd field the leading edge of both signals is very close, so jitter on one or both of them may result in
occasionally miscounting the number of lines in a field causing a displayed character to bounce up and down on a line.
To avoid this situation the HSYNC signal is delayed by a number of dot clocks. Because the relationship between HSYNC
and VSYNC is not fully known there are 16 user selectable delays available. The period of the horizontal starting position
plus the HDEL delay cannot exceed the HSYNC period.
17.14.1 HORIZONTAL DELAY REGISTER (HDEL)
Table 76 Horizontal Delay Register (SFR address C6H)
7
6
5
4
3
2
1
0
−
−
−
−
HDEL3
HDEL2
HDEL1
HDEL0
Table 77 Description of HDEL bits
BIT
SYMBOL
DESCRIPTION
7 to 4
−
These 4 bits are reserved.
3
2
1
0
HDEL3
HDEL2
HDEL1
HDEL0
HSYNC delay. The state of these 4 bits determines the delay time applied to the
HSYNC signal, see Table 78.
Table 78 Selection of HSYNC delay
NO. OF DOT
CLOCKS
DELAY TIME AT
DELAY TIME AT
10 MHz (µs)
HDEL3
HDEL2
HDEL1
HDEL0
5 MHz (µs)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
32
6.4
3.2
64
12.8
19.2
25.6
32
6.4
96
9.6
128
160
192
224
256
288
320
352
384
416
448
480
12.8
16
38.4
44.8
51.2
57.6
64
19.2
22.4
25.6
28.8
32
70.4
76.8
83.2
89.6
96
35.2
38.4
41.6
44.8
48
1999 Mar 10
67
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
• The OSD character itself or its contrast is not affected by
17.15 OSD meshing
the meshing feature
Meshing results is a contrast reduction of a selected video
area. This reduced contrast enhances the reliability of the
OSD character displayed in that area without the loss of
the video information in that area in case of a normal solid
background. This feature is implemented by replacing the
normal character solid background by a checker-board
pattern background and inverts this pattern every new
frame. The checker-board pattern itself is generated by
switching FB on and off with a pixel frequency in the first
frame and off and on in the next frame only for those OSD
characters that have background switched on.
• The meshing function is frame based
• Normal background is replaced by an alternating
meshing pattern
• For meshing the meshing bit and the background mode
must be set
• Meshing can only be activated in TV mode, e.g mode bit
(bit 5 in SFR OSCON) must be a logic 0.
handbook, full pagewidth
TAXI
MGM684
TV/Video colour
OSD background colour
checker-board pattern
Fig.43 TV/video signal superimposed with checker-board pattern.
handbook, full pagewidth
TAXI
VOLUME IIII
MGM685
OSD character
(not affected by the checker-board pattern
Fig.44 Complete meshing feature.
68
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
17.16 FB to RGB delay compensation
The P8xCx66 is connected to an analog video mixer. In the past analog mixers had different delays between FB and
RGB. To compensate for these differences, FB to RGB delay compensation is implemented on-chip. The delay time is
selected using the OSFBD register.
The delay compensation can be done with a resolution of 1⁄2fOSC. The OSC clock runs at 4 times the OSD clock
frequency for OSD frequencies from 4 up to 6.75 MHz, and at 2 times the OSD clock frequency from OSD frequencies
from 6.75 MHz up to 12 MHz. At 4 MHz the delay unit is 33 ns, at 6.5 MHz the delay unit is 19 ns, at 8 MHz the delay
unit is 33 ns, at 10 MHz the delay unit is 25 ns and at 12 MHz the delay unit is 21 ns.
17.16.1 OSD FB DELAY REGISTER (OSFBD)
Table 79 OSD FB Delay Register (SFR address C7H)
7
6
5
4
3
2
1
0
−
−
−
0
FBD3
FBD2
FBD1
FBD0
Table 80 Description of OSFBD bits
BIT
SYMBOL
DESCRIPTION
7 to 5
4
−
−
These 3 bits are not used.
This bit must be set to a logic 0. If set to a logic 1, the character font will come from
internal logic instead of character ROM.
3 to 0
FBD3 to FB FB to RGB delay select. These 4 bits select the delay unit multiple that will determine
D0 the delay time between FB and RGB; see Table 81.
Table 81 Selection of FB to RGB delay
DECIMAL
VALUE
FBD3
FBD2
FBD1
FBD0
FB to RGB DELAY
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
−7
−6
−5
−4
−3
−2
−1
0
Delay RGB with 7 units in relation to FB.
Delay RGB with 6 units in relation to FB.
Delay RGB with 5 units in relation to FB.
Delay RGB with 4 units in relation to FB.
Delay RGB with 3 units in relation to FB.
Delay RGB with 2 units in relation to FB.
Delay RGB with 1 units in relation to FB.
Delay RGB with 0 unit in relation to FB.
Delay FB with 0 unit in relation to RGB.
Delay FB with 1 unit in relation to RGB.
Delay FB with 2 units in relation to RGB.
Delay FB with 3 units in relation to RGB.
Delay FB with 4 units in relation to RGB.
Delay FB with 5 units in relation to RGB.
Delay FB with 6 units in relation to RGB.
Delay FB with 7 units in relation to RGB.
+0
+1
+2
+3
+4
+5
+6
+7
1999 Mar 10
69
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
• Data I/O: D0 to D7 are used for all EPROM modules
• Write Enable (WE): active LOW programming pulse
18 EPROM PROGRAMMER
18.1 Interface to the on-chip EPROMs
• Output Enable (OE): active LOW data output enable,
when in EPROM verify mode, OE must be LOW
The P87C766 contains two EPROMs: the program
EPROM and the OSD EPROM. The EPROM memory map
is shown in Fig.46.
• Programming voltage: the programming and verification
voltage (VPP) is typically 12.75 V; when programming
and verify operations have been completed VPP should
be reduced to 0 V.
The 64K × 8-bit program EPROM is subdivided into four
EPROM modules: Modules 1 to 4, each of 16 kbytes.
The 8K × 8-bit OSD EPROM is subdivided into two
modules: OSDL and OSDH, each of 4 kbytes. The OSDL
module provides the 8 LSBs of the 12-bit character word
and the OSDH module provides the 4 MSBs of the 12-bit
character word. The 4 MSBs of OSDH are not used and
should be programmed to logic 1s.
All other signals to be connected to the EPROM module in
the programming/verification mode are generated
internally. Table 84 gives an overview of the functions
mapped to the pins.
Programming and verification waveform characteristics
are specified in Chapter 21.
To ensure greater reliability and to reduce power
consumption, all unused EPROM cells should be
programmed to logic 1s.
Table 82 Selection of Program EPROM modules
A15 A14
PROGRAM EPROM MODULE
Module 1
To program the EPROM modules, several functions of the
EPROMs must be mapped to the pins of the package.
0
0
1
1
0
1
0
1
Module 2
• The program EPROM uses 16 address lines: A0 to A15
Module 3
– A0 to A13 are used for the EPROM address
Module 4
– A14 and A15 are used to select one of the 4 program
EPROM modules; see Table 82.
Table 83 Selection of OSD EPROM modules
• The OSD EPROM uses 13 address lines A0 to A12
A12
OSD EPROM MODULE
– A0 to A11 are used for the EPROM address
0
1
OSDL module
OSDH module
– A12 is used to select one of the 2 OSD EPROM
modules; see Table 83.
Table 84 Truth table for EPROM modules
OPERATION MODE
WE
OE
VPP
I/O
ADDRESS LINES
Programming Program EPROM
Verification Program EPROM
Programming OSD EPROM
Verification OSD EPROM
0
1
0
1
1
0
1
0
12.75
12.75
12.75
12.75
data in
A0 to A15
A0 to A15
A0 to A12
A0 to A12
data out
data in
data out
1999 Mar 10
70
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
18.2 EPROM Programming mode
Table 86 Test mode selection.
In the EPROM programming mode the selected EPROM is
under the direct control of the external pins. For entering
the programming mode the RESET pin serves as the data
input and the XTALIN pin serves as the clock input. There
is no need to synchronise the addresses, data, read and
write signals with the CPU.
MODE BITS
TEST MODE
1
5
4
3
2
0
0
0
0
1
1
0
1
0
0
Program EPROM
OSD EPROM
18.2.2 ENTERING THE PROGRAMMING MODE
To enter the programming mode, the microcontroller must
first be reset in accordance to the normal reset procedure
to avoid the Idle mode. The programming code is then
shifted in serially via the RESET pin and stored in a
register. After decoding, the required control signals are
generated.
The procedure for entering the Programming mode is
detailed below and illustrated in Fig.47
1. The normal reset should be active for at least
24 XTALIN clocks:
a) The first 10 XTALIN clocks cancel any special
modes
18.2.1 SERIAL PROGRAMMING CODES
b) The 24 XTALIN clocks (2 machine cycles) ensure
that the CPU core is reset.
Once the device has been reset the programming code
can be shifted in via the RESET pin. The 10-bit
programming code is shown in Fig.45 and defined in
Table 85.
2. Shift in the programming code via the RESET pin
3. Wait at least 2 XTALIN clocks until the control signals
are ready, then the EPROM address, data and control
signals can be applied. The RESET pin should be
released within 10 XTALIN clocks to prevent the circuit
escaping from EPROM programming mode.
18.2.3 LEAVING THE PROGRAMMING MODE
bit 0
handbook, halfpage
bit 9
0
X
X
X
X
X
0
1
0
1
The device will exit the Programming mode when the
RESET pin is driven HIGH for at least 10 XTALIN clock
cycles.
Stop bits
Mode bits
Start bit
18.3 Programming and verification
MGM683
It is not recommended to carry out programming/verify
operations on a byte basis. It is far better to program all
program EPROM (or OSD EPROM) and then verify the
contents.
Fig.45 Serial programming code.
18.4 OSD EPROM bit map and the sequence of
programming OSDL and OSDH
Table 85 Programming code format
BIT
FUNCTION
Each character bit pattern is stored in the on-chip
ROM/EPROM. The character displayed on the screen is in
a 12 × 18 dot matrix format, however it is stored in the
on-chip character ROM in a 12 × 19 format. For the OSD
EPROM character the dot matrix is 16 × 19, but only
12 × 19 is used, therefore the high nibble of OSDH must
be filled with FH.
9 to 6
Stop bits. These are the last 4 bits to be
shifted in and always take the value ‘0101’,
indicating the end of the test mode code.
5 to 1
0
Mode bits. These 5 bits follow the start bit
and select the test mode; see Table 86.
Start bit. This is the first bit to be shifted in
and is always a logic 0, indicating that the
following 5 bits are test mode code.
1999 Mar 10
71
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
16383
32767
49151
65535
MODULE 1
16 kbytes
MODULE 2
16 kbytes
MODULE 3
16 kbytes
MODULE 4
16 kbytes
program
EPROM
0
16384
4095
32768
49152
MGM682
8191
OSDH
OSDL
OSD
EPROM
4 kbytes
4 kbytes
4096
0
Fig.46 On-chip EPROM structure for the P87C766.
shift in special 10-bit code of
EPROM mode
XTALIN
start EPROM programming
normal reset
1
2
3
4
5
6
7
8
9
0
RESET
MGM675
T
rst
EPROM address,
data and control signals
can be started
Fig.47 Sequence to enter EPROM programming mode.
72
1999 Mar 10
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
18.5 Summary of the Programming mode configuration
Table 87 Pin connections in Programming mode.
EPROM CONNECTION
SYMBOL
P3.3/PWM7
PIN
PROGRAM
OSD
12
8
A15
−
P5.7/PWM6
P5.6/PWM5
P5.5/PWM4
P5.4/PWM3
P5.3/PWM2
P5.2/PWM1
P5.1/PWM0
P1.4/T1
P1.3/INT0
P1.2/T0
P1.1/INT1
VSYNC
HSYNC
FB
A14
−
7
A13
−
6
A12
A12
5
A11
A11
4
A10
A10
3
A9
A9
2
A8
A8
38
37
36
35
27
26
25
24
23
22
20
19
18
17
16
15
14
13
30
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
R
A0
A0
G
OE
OE
B
WE
WE
P0.7
data I/O, bit 7
data I/O, bit 6
data I/O, bit 5
data I/O, bit 4
data I/O, bit 3
data I/O, bit 2
data I/O, bit 1
data I/O, bit 0
VPP
data I/O, bit 7
data I/O, bit 6
data I/O, bit 5
data I/O, bit 4
data I/O, bit 3
data I/O, bit 2
data I/O, bit 1
data I/O, bit 0
VPP
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
VPP
1999 Mar 10
73
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
Table 88 EPROM module selection.
MEMORY SIZE
ADDRESS LINES
DATA LINES
Program EPROM: Module 1
16K × 8
14-bit address: A0 to A13;
Module 1 select: A14 = 0, A15 = 0
8-bit data byte: D0 to D7
Program EPROM: Module 2
16K × 8 14-bit address: A0 to A13;
Module 2 select: A14 = 1, A15 = 0
Program EPROM: Module 3
16K × 8 14-bit address: A0 to A13;
Module 3 select: A14 = 0, A15 = 1
Program EPROM: Module 4
16K × 8 14-bit address: A0 to A13;
Module 4 select: A14 = 1, A15 = 1
OSD EPROM (OSDL) − LSBs
8-bit data byte: D0 to D7
8-bit data byte: D0 to D7
8-bit data byte: D0 to D7
128 × 19 × 8
12-bit address: A0 to A11; OSDL select: A12 = 0
8-bit data byte: D0 to D7
8-bit data byte: D0 to D7
OSD EPROM (OSDH) − MSBs
128 × 19 × 8
12-bit address: A0 to A11; OSDH select: A12 = 1
1999 Mar 10
74
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
19 SPECIAL FUNCTION REGISTERS ADDRESS MAP
The SFRs are presented in ascending address order in Table 89 to aid designer/programmers quick reference.
Table 89 SFRs address map
ADDRESS
NAME
7
6
5
4
3
2
1
0
80H(1)
81H(1)
82H(1)
83H(1)
86H
87H(1)
88H(1)
89H(1)
8AH(1)
8BH(1)
8CH(1)
8DH(1)
90H(1)
98H
P0 latch
P07
P06
P05
P04
P03
P02
P01
P00
Stack Pointer (SP)
SP7
DPL7
DPH7
−
SP6
DPL6
DPH6
−
SP5
DPL5
DPH5
−
SP4
DPL4
DPH4
−
SP3
DPL3
DPH3
−
SP2
DPL2
DPH2
I2CE
GF0
IT1
SP1
DPL1
DPH1
−
SP0
DPL0
DPH0
−
Data Pointer Low (DPL)
Data Pointer High (DPH)
I2C-bus Port Control Register (I2CCON)
Power Control Register (PCON)
Timer/Counter Control Register (TCON)
Timer/Counter Mode Control Register (TMOD)
Timer 0 Low byte (TL0)
−
−
−
WLE
TR0
M0
GF1
IE1
0
IDL
TF1
Gate
TL07
TL17
TH07
TH17
P17
P57
−
TR1
C/T
TL06
TL16
TH06
TH16
P16
P56
−
TF0
M1
IE0
IT0
Gate
TL03
TL13
TH03
TH13
P13
P53
T3
C/T
M1
M0
TL05
TL15
TH05
TH15
P15
P55
−
TL04
TL14
TH04
TH14
P14
P54
T4
TL02
TL12
TH02
TH12
P12
P52
T2
TL01
TL11
TH01
TH11
P11
P51
−
TL00
TL10
TH00
TH10
P10
P50
T0
Timer 1 Low byte (TL1)
Timer 0 High byte (TH0)
Timer 1 High byte (TH1)
P1 latch
P5 latch
99H
OSD Attribute Register (OSAT)
OSD Character Data Register (OSDT)
OSD Address Register (OSAD)
OSD Default Register (OSDDEF)
P2 latch
9AH
C7
C6
C5
C4
C3
C2
C1
C0
9BH
AD7
R
AD6
G
AD5
B
AD4
−
AD3
SV
AD2
SH
AD1
M1
AD0
M0
9CH
A0H(1)
A8H(1)
B0H(1)
B8H(1)
C0H
P27
EA
P26
−
P25
ES1
−
P24
−
P23
ET1
P33
PT1
IQ5
P22
EX1
P32
PX1
IQ4
P21
ET0
P31
PT0
IQ3
BF
P20
EX0
P30
PX0
IQ2
Interrupt Enable Register 0 (IEN0)
P3 latch
−
−
−
Interrupt Priority Register 0 (IP0)
Interrupt Request Register 1 (IRQ1)
OSD Control Register 1 (OSCON)
OSD Vertical Start Register (OSORGV)
OSD Horizontal Start Register (OSORGH)
OSD PLL Register (OSPLL)
OSD Start Register (OSSTART)
−
−
PS1
IQ7
Mode
VP5
HP5
PLL5
−
IQ9
Split
−
−
IQ6
Hp
C1H
Mesh
−
Vp
Bp
OSDE
VP0
HP0
PLL0
C2H
VP4
HP4
PLL4
VP3
HP3
PLL3
VP2
HP2
PLL2
VP1
HP1
PLL1
C3H
−
HP6
PLL6
C4H
PLL7
C5H
START7 START6 START5 START4 START3 START2 START1 START0
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
ADDRESS
NAME
7
6
5
4
3
2
1
0
C6H
Horizontal Delay Register (HDEL)
OSD FB Delay Register (OSFBD)
ADC Control Register (SAD)
VSYNC Interrupt Register (VINT)
ADC Control Register 2 (SAD2)
OSD Control Register 2 (OSCON2)
Program Status Word (PSW)
TDACL
−
−
−
−
−
HDEL3 HDEL2 HDEL1 HDEL0
C7H
0
FBD3
SAD3
−
FBD2
SAD2
−
FBD1
SAD1
−
FBD0
SAD0
VLVL
C8H
#VHI
−
CH1
−
CH0
−
ST
−
C9H(1)
CAH
CFH
−
−
−
−
−
ADCE2 ADCE1 ADCE0
−
−
−
0
R
G
B
−
D0H(1)
#CY
TD7
#AC
TD6
#F0
RS1
TD4
RS0
TD3
TD11
SI
#OV
TD2
TD10
AA
−
#P
D2H
TD5
TD13
STA
SC2
D5
TD1
TD9
CR1
0
TD0
TD8
CR0
0
D3H
TDACH
TPWME −
TD12
STO
SC1
D4
D8H
Serial Control Register (S1CON)
Status Register (S1STA)
Data Shift Register (S1DAT)
Slave Address Register (S1ADR)
Internal Status Register (S1IST)
Accumulator (ACC)
CR2
SC4
ENS1
D9H(2)
DAH
DBH
DCH(2)
E0H(1)
E4H
SC3
D6
SC0
D3
0
D7
D2
D1
D0
SLA6
MST4
ACC7
SLA5
TX
SLA4
BB
SLA3
FB
SLA2
ARL
ACC3
data3
data3
data3
data3
EX5
IL5
SLA1
SEL
ACC2
data2
data2
data2
data2
EX4
IL4
SLA0
AD0
ACC1
data1
data1
data1
data1
EX3
IL3
GC
SHRA
ACC0
data0
data0
data0
data0
EX2
IL2
ACC6
ACC5
data5
data5
data5
data5
EX7
IL7
ACC4
data4
data4
data4
data4
EX6
PWM0 (7-bit PWM)
PWM0E data6
PWM1E data6
PWM2E data6
PWM3E data6
E5H
PWM1 (7-bit PWM)
E6H
PWM2 (7-bit PWM)
E7H
PWM3 (7-bit PWM)
E8H(1)
E9H(1)
ECH
EDH
EEH
Interrupt Enable Register 1 (IEN1)
Interrupt Polarity Register (IX1)
PWM4 (7-bit PWM)
EX9
IL9
−
IL8
IL6
PWM4E data6
PWM5E data6
PWM6E data6
PWM7E data6
data5
data5
data5
data5
B5
data4
data4
data4
data4
B4
data3
data3
data3
data3
B3
data2
data2
data2
data2
B2
data1
data1
data1
data1
B1
data0
data0
data0
data0
B0
PWM5 (7-bit PWM)
PWM6 (7-bit PWM)
EFH
F0H(1)
PWM7 (7-bit PWM)
B Register (B)
B7
B6
−
F8H
Interrupt Priority Register 1 (IP1)
Watchdog timer Register (WDT)
PX9
T37
PX7
T35
PX6
PX5
T33
PX4
T32
PX3
T31
PX2
T30
FFH
T36
T34
Notes
1. Standard 80C51 register.
2. Read only register.
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
20 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
PARAMETER
MIN.
4.5
TYP.
MAX.
5.5
VDD + 0.5 V
UNIT
VDDX
VI
any supply voltage
−
−
−
−
−
V
input voltage (all inputs)
total power dissipation
storage temperature
−0.5
−
Ptot
170
+125
70
mW
°C
°C
Tstg
Tamb
−55
−20
operating ambient temperature
21 CHARACTERISTICS
DD = 4.5 to 5.5 V; VSS = 0 V; Tamb = −20 to 70 °C; all voltages with respect to VSS unless otherwise specified.
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDD
VDDA
IDDD
IDDA
VPP
digital supply voltage
analog supply voltage
digital supply current
analog supply current
programming voltage
programming current
4.5
5.0
5.5
V
V
4.5
−
5.0
5.5
32
fCLK = 12 MHz
fCLK = 12 MHz
−
mA
mA
V
−
−
5.0
13
12.5
−
12.75
IPP
−
10
mA
CMOS inputs
VIL
VIH
ILI
LOW-level input voltage
−
−
−
−
0.3VDD
−
V
HIGH-level input voltage
input leakage current
0.7VDD
−10
V
VSS <VI <VDD
+10
µA
CMOS inputs (Schmitt trigger)
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
0.2VDD
−
−
−
V
V
−
0.8VDD
TTL inputs
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
−
−
−
0.8
V
V
2.0
−
TTL inputs (Schmitt trigger)
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
0.6
−
−
−
V
V
−
2.4
1999 Mar 10
77
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
SYMBOL
Analog inputs: ADC0 to ADC2
VI input voltage
Push-pull outputs: R, G, B and FB
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VSS
−
VDD
V
IOL
IOH
LOW-level output current
HIGH-level output current
−
−
−
−
1.6
mA
mA
−1.6
Open-drain outputs
tt(L-H)
transition time LOW to HIGH determined by external RC
network
25
25
−
−
100
100
ns
ns
tt(H-L)
transition time HIGH to LOW load independent slope
control for a capacitance
load up to 50 pF
IO(sink)
output sink current logic 0
VOL = 0.4
OL = 1.0
−
−
−
−
1.6
10
mA
mA
V
System clock
fCLK
system clock frequency
4
4
−
−
12
12
MHz
MHz
OSD clock
fOSD
OSD clock frequency
21.1 DC parameters of EPROM
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Toper
IPP
operating temperature (programming/verification)
programming current
−
−
25
−
°C
mA
V
−
10.0
13.0
VPP
programming voltage
12.50
12.75
21.2 Programming specification for programmer
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Toper
VDD
operating temperature (programming/verification)
supply voltage (reading)
−
25
−
°C
V
4.5
−
5.0
5.0
5.8
100
5
5.5
−
VDDP
VDDP
tW(P)
supply voltage (programming)
supply voltage (verify)
V
−
−
V
programming pulse width per time
number of pulses for programming
accumulated programming time per byte
programming voltage
90
−
110
−
µs
−
Nprog
tacc(byte)
VPP
450
12.50
500
12.75
550
13.00
µs
V
1999 Mar 10
78
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
21.3 AC characteristics of Programming mode
Table 90 Timing for programming Program EPROM and OSD EPROM; see Fig.48
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
tsu(A)
th(A)
tsu(D)
th(D)
tsu(PV)
tW(P)
address set-up time
address hold time
data set-up time
data hold time
2
−
−
−
−
−
−
−
−
−
−
µs
ns
ns
ns
µs
µs
ns
µs
ns
µs
ns
ns
20
2
20
2
programming voltage set-up time
programming pulse width
write enable hold time
90
100
−
110
−
th(WE)
tsu(OE)
tACC(OE)
tsu(CE)
tOZ
110
2
output enable set-up time
output enable access verify
chip enable set-up time
−
−
−
−
20
−
2
−
output to high impedance verify
output enable pulse width
14
300
−
−
tW(OE)
−
−
1999 Mar 10
79
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
g
programming
verify
t
W(P)
V
IH
WE
V
IL
t
t
t
h(WE)
su(A)
h(A)
V
address
IH
address valid
A0 to Axx
V
IL
V
IH
D0 to D7
data out
data invalid
V
IL
t
t
su(D)
h(D)
High Z
V
IH
data out
V
IL
t
t
t
su(PV)
su(OE)
OZ
V
PP
(program voltage)
t
ACC(OE)
V
DDP
(power supply)
t
W(OE)
V
IH
OE
V
MGM676
IL
VIH and VIL are CMOS levels and are typically 5 V and 0 V respectively.
When OE is HIGH, P0.0 to P0.7 are used as inputs, when OE is LOW, P0.0 to P0.7 are used as outputs.
During programming the power supply must remain at 5 V. During verification the power supply must remain at 5.8 V.
Fig.48 Programming waveforms.
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
22 PINNING CHARACTERIZATION
This chapter describes every pin used in both the SDIP42 and PLCC68 packages.
22.1 Type of packages
SDIP42: for P8XCX66
PLCC68: for Metalink+ applications
Table 91 Explanation of symbols/terms used in Table 92
SYMBOL/TERM
MEANING
STr
Schmitt trigger
pull-up resistor
pull-down resistor
high-impedance
Rpu
Rpd
Z
original state
the outputs keep the state they had before entering the Idle mode
Table 92 Pin characteristics
PIN
SLOPE
OUTPUT IN
OUTPUT
ACTIVE STATE
SYMBOL
TYPE INPUT LEVEL
OUTPUT TYPE
CONTROL IDLE MODE AFTER RESET SW CONTROL
SDIP42 PLCC68
−
1
2
3
3
4
4
5
5
6
6
7
7
8
8
9
VSS
−
−
−
−
−
−
−
−
−
−
1
1
2
2
3
3
4
4
5
5
6
6
−
INTD
P5.0
I
CMOS + Rpu(1)
−
I/O
O
CMOS
open-drain
push-pull
open-drain
open-drain
open-drain
open-drain
open-drain
open-drain
open-drain
open-drain
open-drain
open-drain
−
Yes
No
original state Z(2)
LOW
original state Z(2)
LOW
original state Z(2)
LOW
original state Z(2)
LOW
original state Z(2)
LOW
original state Z(2)
TPWM
P5.1
−
−
I/O
O
CMOS
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
−
PWM0
P5.2
−
−
I/O
O
CMOS
PWM1
P5.3
−
−
I/O
O
CMOS
PWM2
P5.4
−
−
I/O
O
CMOS
PWM3
P5.5
−
−
I/O
O
CMOS
PWM4
n.c.
−
−
LOW
−
−
−
−
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
PIN
SLOPE
OUTPUT IN
OUTPUT
ACTIVE STATE
SYMBOL
n.c.
TYPE INPUT LEVEL
OUTPUT TYPE
CONTROL IDLE MODE AFTER RESET SW CONTROL
SDIP42 PLCC68
−
10
11
11
12
12
13
13
14
15
16
16
17
18
18
19
20
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
−
−
−
−
−
−
7
P5.6
I/O
O
CMOS
open-drain
open-drain
open-drain
open-drain
Yes
Yes
Yes
Yes
Yes
−
original state Z(2)
LOW
original state Z(2)
LOW
original state Z(2)
7
PWM5
P5.7
−
−
8
I/O
O
CMOS
8
PWM6
P3.0
−
−
9
I/O
I
CMOS + Rpu(3) open-drain
9
ADC0
PH1SEM
S1ESEM
P3.1
analog
−
−
−
−
−
−
−
−
O
−
open-drain, 2 mA
open-drain, 2 mA
note 4
note 4
Yes
−
−
O
−
10
10
−
I/O
I
CMOS + Rpu(3) open-drain
original state Z(2)
ADC1
P2.0
analog
−
−
−
I/O
I/O
I
CMOS
open-drain + Rpu(5) Yes
−
−
11
11
−
P3.2
CMOS + Rpu(3) open-drain
Yes
original state Z(2)
ADC2
P2.1
analog
CMOS
CMOS
−
−
−
−
−
I/O
I/O
O
open-drain + Rpu(5) Yes
−
−
12
12
−
P3.3
open-drain
Yes
original state Z(2)
PWM7
P2.2
open-drain
Yes
LOW
−
−
−
I/O
I/O
I/O
I/O
I/O
CMOS
CMOS
CMOS
CMOS
CMOS
−
open-drain + Rpu(5) Yes
open-drain + Rpu(5) Yes
−
−
P2.3
−
13
14
15
−
P0.0
open-drain
open-drain
open-drain
−
Yes
Yes
Yes
−
original state Z(2)
original state Z(2)
original state Z(2)
P0.1
P0.2
OSD_EPR_TST −
−
−
−
n.c.
−
−
−
−
−
−
16
17
18
19
20
−
P0.3
P0.4
P0.5
P0.6
P0.7
VDDD
VSSD
I/O
I/O
I/O
I/O
I/O
−
CMOS
CMOS
CMOS
CMOS
CMOS
−
open-drain
open-drain
open-drain
open-drain
open-drain
−
Yes
Yes
Yes
Yes
Yes
−
original state Z(2)
original state Z(2)
original state Z(2)
original state Z(2)
original state Z(2)
−
−
−
−
21
−
−
−
−
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
PIN
SLOPE
OUTPUT IN
OUTPUT
ACTIVE STATE
SYMBOL
P2.4
TYPE INPUT LEVEL
OUTPUT TYPE
CONTROL IDLE MODE AFTER RESET SW CONTROL
SDIP42 PLCC68
−
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
I/O
I/O
O
O
O
O
I
CMOS
open-drain + Rpu(5) Yes
open-drain + Rpu(5) Yes
−
−
−
P2.5
B
CMOS
−
−
22
23
24
25
26
27
−
−
push-pull, 1.6 mA
No
No
No
No
−
note 6
LOW(7)
LOW(7)
LOW(7)
LOW(7)
SW con
SW con
SW con
SW con
SW con
SW con
G
−
push-pull, 1.6 mA
note 6
R
−
push-pull, 1.6 mA
note 6
FB
−
push-pull, 1.6 mA
note 6
HSYNC
VSYNC
n.c.
TTL STr
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
I
TTL STr
−
−
−
−
−
n.c.
−
−
−
28
29
−
VDDA
VSS
−
−
−
−
−
−
P2.6
VPP
I/O
I
CMOS
12.75 V
−
open-drain + Rpu(5) Yes
30
−
−
−
−
−
−
−
−
−
VSS
−
31
32
−
XTALIN
XTALOUT
P2.7
IDLPDEM
RESET
I
CPU XTAL
CPU XTAL
CMOS
−
O
I/O
O
I
open-drain + Rpu(5) Yes
−
push-pull, 2 mA
note 4
33
CMOS
STr + Rpd(8)
−
−
−
55
56
−
EMUPBX
VSS
O
−
−
push-pull, 2 mA
note 4
−
−
−
−
−
−
−
−
−
−
34
34
34
35
35
36
36
−
VSS
−
note 9
TTL STr
notes 9 and 10
TTL STr
TTL STr
TTL STr
TTL STr
−
−
−
57
57
58
58
59
59
60
P1.0
VDD
I/O
−
open-drain + Rpu(5) Yes
original state Z(2)
−
−
−
−
P1.1
INT1
P1.2
T0
I/O
I
open-drain
Yes
−
original state Z(2)
−
−
−
I/O
I
open-drain
Yes
−
original state Z(2)
−
−
−
−
−
−
n.c.
−
−
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
PIN
SLOPE
OUTPUT IN
OUTPUT
ACTIVE STATE
SYMBOL
n.c.
TYPE INPUT LEVEL
OUTPUT TYPE
CONTROL IDLE MODE AFTER RESET SW CONTROL
SDIP42 PLCC68
−
61
62
62
63
63
64
64
65
65
66
−
−
−
−
−
−
−
37
37
38
38
39
39
40
40
41
41
−
P1.3
INT0
P1.4
T1
I/O
I
TTL STr
TTL STr
TTL STr
TTL STr
TTL STr
TTL STr
TTL STr
TTL STr
TTL STr
note 9
−
open-drain
−
Yes
−
original state Z(2)
−
−
I/O
I
open-drain
−
Yes
−
original state Z(2)
−
−
P1.5
SCL
P1.6
SDA
P1.7
VSS
I/O
I/O
I/O
I/O
I/O
−
open-drain
open-drain
open-drain
open-drain
Yes
Yes
Yes
Yes
original state Z(2)
HIGH(11)
original state Z(2)
HIGH(11)
original state Z(2)
−
−
open-drain + Rpu(5) Yes
−
−
−
−
−
−
−
−
−
−
−
−
67
68
VSS
−
42
VDD
−
−
Notes
1. A pull-up resistor must be present to prevent a floating input during normal/alternative mode when no external signal is applied to the pad.
Pull-up = present internally.
2. All ports are in input mode after reset; that means the value at the pin is determined by the external circuitry: pull-up registers Rext (and/or external
applied input).
3. A pull-up resistor must be present to prevent floating (digital) inputs if the pad is used for the analog inputs ADCO, ADCI and ADC2. This pull-up is
also present if these pins are used as port function. Pull-up is internally.
4. These pins are standard I/O cells SPF20PGD (2 mA PP slew-rate controlled).
5. A pull-up resistor must be present to prevent a floating input during nominal/alternative mode when no external signal is applied to the pad.
Pull-up = present internally.
6. Inverse of the Bp bit (located in OSCON).
7. After reset the Bp bit (located in OSCON) = 1, therefore output becomes LOW.
8. Its pull-down resistor is present internally (see Section 13.2).
9. For the SDIP42 package, pin P1.0 can be exchanged for a VSS or VDD, pin P1.7 for a VSS
10. For the PLCC68 package, pin P1.0 can be exchanged for a VDD line.
11. Output is HIGH via external resistor.
.
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
23 PACKAGE OUTLINES
PLCC68: plastic leaded chip carrier; 68 leads
SOT188-2
e
e
E
D
y
X
A
60
44
Z
E
43
61
b
p
b
1
w
M
68
1
H
E
E
pin 1 index
A
e
A
1
A
4
(A )
3
k
L
1
p
9
k
27
β
detail X
10
26
v
M
A
e
Z
D
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
(1)
(1)
A
min.
A
max.
k
1
max.
Z
Z
E
(1)
(1)
1
4
D
UNIT
mm
A
A
b
D
E
e
e
e
H
H
k
L
p
v
w
y
β
b
D
E
D
E
3
p
1
max. max.
4.57
4.19
0.81 24.33 24.33
0.66 24.13 24.13
23.62 23.62 25.27 25.27 1.22
22.61 22.61 25.02 25.02 1.07
1.44
1.02
0.53
0.33
0.51
0.51 0.25 3.30
0.020 0.01 0.13
1.27
0.05
0.18 0.18 0.10 2.16 2.16
o
45
0.180
0.165
0.032 0.958 0.958
0.026 0.950 0.950
0.930 0.930 0.995 0.995 0.048
0.890 0.890 0.985 0.985 0.042
0.057
0.040
0.021
0.013
inches
0.020
0.007 0.007 0.004 0.085 0.085
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-03-11
SOT188-2
112E10
MO-047AC
1999 Mar 10
85
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)
SOT270-1
D
M
E
A
2
A
L
A
1
c
e
(e )
1
w M
Z
b
1
M
H
b
42
22
pin 1 index
E
1
21
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
2
max.
(1)
(1)
Z
1
w
UNIT
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.
max.
1.3
0.8
0.53
0.40
0.32
0.23
38.9
38.4
14.0
13.7
3.2
2.9
15.80
15.24
17.15
15.90
mm
5.08
0.51
4.0
1.778
15.24
0.18
1.73
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
90-02-13
95-02-04
SOT270-1
1999 Mar 10
86
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
Typical reflow peak temperatures range from
24 SOLDERING
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
24.1 Introduction
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
24.3.2 WAVE SOLDERING
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mount components are mixed on
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
24.2 Through-hole mount packages
24.2.1 SOLDERING BY DIPPING OR BY SOLDER WAVE
• For packages with leads on two sides and a pitch (e):
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
24.2.2 MANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
300 and 400 °C, contact may be up to 5 seconds.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
24.3 Surface mount packages
24.3.1 REFLOW SOLDERING
24.3.3 MANUAL SOLDERING
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Mar 10
87
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
24.4 Suitability of IC packages for wave, reflow and dipping soldering methods
SOLDERING METHOD
WAVE
REFLOW(1) DIPPING
suitable(2)
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(3)
MOUNTING
PACKAGE
Through-hole mount DBS, DIP, HDIP, SDIP, SIL
−
suitable
Surface mount
BGA, SQFP
suitable
suitable
suitable
suitable
suitable
−
−
−
−
−
PLCC(4), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(4)(5)
not recommended(6)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Mar 10
88
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
25 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
26 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
27 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 Mar 10
89
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
NOTES
1999 Mar 10
90
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
NOTES
1999 Mar 10
91
Philips Semiconductors – a worldwide company
Argentina: see South America
Middle East: see Italy
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
Norway: Box 1, Manglerud 0612, OSLO,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belgium: see The Netherlands
Brazil: see South America
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Portugal: see Spain
Romania: see Italy
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Colombia: see South America
Czech Republic: see Austria
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
Slovakia: see Austria
Slovenia: see Italy
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Spain: Balmes 22, 08007 BARCELONA,
Tel. +30 1 489 4339/4239, Fax. +30 1 481 4240
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1999
SCA62
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
275002/750/01/pp92
Date of release: 1999 Mar 10
Document order number: 9397 750 03304
相关型号:
P83C575EBAA
80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
NXP
P83C575EBBB
80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
NXP
P83C575EBPN
80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
NXP
©2020 ICPDF网 联系我们和版权申明