P83C576EHPN_技术文档

INTEGRATED CIRCUITS

83C576/87C576

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D,

4 comparators, failure detect circuitry, watchdog timer

Product specification

1998 Jun 04

Supersedes data of 1998 Jan 06

IC20 Data Handbook

Philips

Semiconductors

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

FEATURES

• OTP available

• That can be programmed in circuit

• Software Reset

• 15 source, 2 level interrupt structure

• Lower EMI noise

• Programmable I/O pins

• 80C51 based architecture

– 8k × 8 ROM (83C576)

– 8k × 8 EPROM (87C576)

– 256 × 8 RAM

– 10-bit, 6 channel A/D

– Three 16-bit counter/timers

– 2 PWM outputs

• Serial on-board programming

• Schmitt trigger inputs on Port 1

– Programmable Counter Array

– Universal Peripheral Interface

– Enhanced UART

DESCRIPTION

– Oscillator fail detect

– Low active reset

The Philips 83C576/87C576 is a high-performance microcontroller

fabricated with Philips high-density CMOS technology. The Philips

CMOS technology combines the high speed and density

characteristics of HMOS with the low power attributes of CMOS.

Philips epitaxial substrate minimizes latch-up sensitivity.

– 4 analog comparators

– Watchdog timer

– Low V detect

CC

The 8XC576 contains an 8k × 8 ROM (83C576) EPROM (87C576),

a 256 × 8 RAM, 32 I/O lines, three 16-bit counter/timers, a

Programmable Counter Array (PCA), a 10-bit, 6 channel A/D,

2 PWM outputs, an 8-bit UPI interface, a fifteen-source, two-priority

level nested interrupt structure, an enhanced UART, four analog

comparators, power-fail detect and oscillator fail detect circuits, and

on-chip oscillator and clock circuits.

– Power-on detect

• Memory addressing capability

– 64k ROM and 64k RAM

• Power control modes:

– Idle mode

– Power-down mode

• CMOS and TTL compatible

• 6 to 16MHz

In addition, the 8XC576 has a low active reset, and a software reset.

There is also a fully configurable watchdog timer, and internal power

on clear circuit. The part includes idle mode and power-down mode

states for reduced power consumption.

• Extended temperature ranges

ORDERING INFORMATION

FREQ

(MHz)

DRAWING

NUMBER

1

ROM

EPROM

TEMPERATURE RANGE °C AND PACKAGE

P83C576EBPN

P83C576EBAA

P83C576EBBB

P83C576EFPN

P83C576EFA A

P83C576EFBB

P83C576EHPN

P83C576EHAA

P87C576EBPN

P87C576EBAA

P87C576EBBB

P87C576EBPN

P87C576EFA A

P87C576EFBB

P87C576EHPN

P87C576EHAA

P87C576EHBB

OTP

0 to +70, 40-Pin Plastic Dual In-line Package

0 to +70, 44-Pin Plastic Leaded Chip Carrier

0 to +70, 44-Pin Plastic Quad Flat Pack

16

SOT129-1

SOT187-2

SOT307-2

SOT129-1

SOT187-2

SOT307-2

SOT129-1

SOT187-2

SOT307-2

–40 to +85, 40-Pin Plastic Dual In-line Package

–40 to +85, 44-Pin Plastic Leaded Chip Carrier

–40 to +85, 44-Pin Plastic Quad Flat Pack

–40 to +125, 40-Pin Plastic Dual In-line Package

–40 to +125, 44-Pin Plastic Leaded Chip Carrier

–40 to +125, 44-Pin Plastic Quad Flat Pack

P83C576EHBB

NOTE:

1. OTP - One Time Programmable EPROM.

2

1998 Jun 04

853-2067 19495

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

BLOCK DIAGRAM

P0.0-P0.7

P2.0-P2.7

UPI

CONTROL

PORT 0

DRIVERS

PORT 2

DRIVERS

LOW

VOLTAGE

DETECT

POWER

ON

DETECT

V

CC

V

SS

A

B

ROM/

EPROM

RAM ADDR

REGISTER

PORT 0

LATCH

PORT 2

LATCH

RAM

PROGRAM

ADDRESS

REGISTER

B

STACK

POINTER

ACC

REGISTER

TMP1

BUFFER

TMP2

PC

INCRE-

MENTER

ALU

WATCHDOG

TIMER

SFRs

TIMERS

PCA

B

A

PSW

PROGRAM

COUNTER

PSEN

ALE

EA

TIMING

AND

CONTROL

DPTR

RST

CLK AND OSC

FAILURE

DETECT

PORT 1

LATCH

PORT 3

LATCH

PD

PWM

10-BIT

ANALOG TO DIGITAL

CONVERTER

OSCILLATOR

COMPARATOR

BLOCK

PORT 1

DRIVERS

PORT 3

DRIVERS

XTAL1

XTAL2

+AV

CC

P3.0-P3.7

P1.0-P1.5

–AV

SS

SU00255B

3

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

LOGIC SYMBOL

V

SS

CC

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

XTAL1

ADDRESS AND

DATA BUS

XTAL2

RST

ADIN0

ADIN1

ADIN2

ADIN3

ADIN4

ADIN5

PWM1/ECI

CEX4/PWM0

T2/CS#

EA/V

PSEN

PP

ALE/PROG

RxD

TxD

INT0

CMP3+

CMP2+

CMP1+

CMPR–

CMP0+

CMP0–

T2EX/A0

INT1

T0

T1

WR

RD

ADDRESS BUS

CEX3/CMP3

CEX2/CMP2

CEX1/CMP1

CEX0/CMP0

SU00254A

PIN CONFIGURATIONS

44-pin Plastic Quad Flat Pack

Plastic Leaded Chip Carrier

6

1

40

44

34

7

39

29

1

33

23

LCC

PQFP

17

11

18

28

12

22

Pin Function

31 P2.7/A15/PWM1/ECI

32 PSEN

1

2

3

4

5

6

7

8

9

NC*

16 T0/P3.4/CMP1+

17 T1/P3.5/CMPR–

18 WR/P3.6/CMP0+

19 RD/P3.7/CMP0–

20 XTAL2

Pin Function

16

17 NC*

Pin Function

+V

REF

–V

REF

/AV

CC

1

2

3

4

5

6

7

8

9

ADIN3/P1.3

ADIN4/P1.4

ADIN5/P1.5

RST

V

31 P0.6/AD6/DB6

32 P0.5/AD5/DB5

33 P0.4/AD4/DB4

34 P0.3/AD3/DB3

35 P0.2/AD2/DB2

36 P0.1/AD1/DB1

37 P0.0/AD0/DB0

SS

33 ALE/PROG

34 NC*

SS

ADIN0/P1.0

ADIN1/P1.1

ADIN2/P1.2

ADIN3/P1.3

ADIN4/P1.4

ADIN5/P1.5

18 P2.0/A8/CEX0/CMP0

19 P2.1/A9/CEX1/CMP1

20 P2.2/A10/CEX2/CMP2

21 P2.3/A11/CEX3/CMP3

22 P2.4/A12/T2EX/A0

23 P2.5/A13/T2/CS

24 P2.6/A14/CEX4/PWM0

25 P2.7/A15/PWM1/ECI

26 PSEN

35 EA/V

PP

21 XTAL1

36 P0.7/AD7/DB7

37 P0.6/AD6/DB6

38 P0.5/AD5/DB5

39 P0.4/AD4/DB4

40 P0.3/AD3/DB3

41 P0.2/AD2/DB2

42 P0.1/AD1/DB1

43 P0.0/AD0/DB0

RxD/P3.0

22

V

SS

NC*

23 NC*

TXD/P3.1

24 P2.0/A8/CEX0/CMP0

25 P2.1/A9/CEX1/CMP1

26 P2.2/A10/CEX2/CMP2

27 P2.3/A11/CEX3/CMP3

28 P2.4/A12/T2EX/A0

INT0/P3.2/CMP3+

INT1/P3.3/CMP2+

38

V

CC

10 RST

39 NC*

11 RxD/P3.0

12 NC*

10 T0/P3.4/CMP1+

11 T1/P3.5/CMPR–

12 WR/P3.6/CMP0+

13 RD/P3.7CMP0–

14 XTAL2

40 +V

41 –V

/AV

REF

CC

REF

SS

13 TxD/P3.1

27 ALE/PROG

42 ADIN0/P1.0

43 ADIN1/P1.1

44 ADIN2/P1.2

14 INT0/P3.2/CMP3+ 29 P2.5/A13/T2/CS

44

V

CC

28 NC*

15 INT1/P3.3/CMP2+ 30 P2.6/A14/CEX4/PWM0

29 EA/V

PP

15 XTAL1

30 P0.7/AD7/DB7

* NO INTERNAL CONNECTION

SU00252A

* NO INTERNAL CONNECTION

SU00253B

4

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC

DIP

20

LCC

22

QFP TYPE NAME AND FUNCTION

V

SS

16

38

I

Ground: 0V reference.

V

CC

40

44

Power Supply: This is the power supply voltage for normal, idle, and power-down operation.

P0.0-0.7

39-32 43-36 37-30

I/O

Port 0: Port 0 is a bidirectional I/O port. Port 0 is also the multiplexed low-order address and

data bus during accesses to external program and data memory (see Note 5). In this

application, it uses strong internal pull-ups when emitting 1s. Port 0 also receives code bytes

during parallel EPROM programming and outputs code bytes during verification. External

pull-ups are required during program verification. During reset, the port register is loaded

with 1’s. Port 0 has 4 output modes selected on a per bit basis by writing to the P0M1 and

P0M2 Special Function Registers as follows:

P0M1.x

P0M2.x

Mode Description

0

1

0

1

0

1

Open drain (default). See Note 1.

Weak pullup. See Note 2.

High impedance. See Note 3.

Push-pull. See Note 4.

Port 0 is also the data I/O port for the Universal Peripheral Interface (UPI). When the UPI is

enabled, port 0 must be configured as High-Z by the user. Input/Output through P0 is

controlled by pin CS, WR, RD, and A0. Output is push-pull when enabled.

P1.0-P1.5

3-8

5-9

42-44

1-3

I/O

Port 1: Port 1 is a 6-bit bidirectional I/O port with Schmitt trigger inputs. Port 1 receives the control

signals during program memory verification and parallel EPROM programming. During reset, port

1 is configured as a high impedance analog input port. Digital push-pull outputs are enabled by

writing 1’s to the P1M1 register. The programmer must take care to prevent digital outputs from

switching while an A/D conversion is in progress. Port 1 has 3 output modes selected on a per bit

basis by writing to the P1M1 and P1M2 special function registers as follows:

P1M1.X

P1M2.X

Mode Description

0

1

0

1

X

A/D only. (High impedance)

Digital input only. High impedance (default).

Push-pull.

Port 1 pins also serve alternate functions as follows:

3

4

5

6

7

8

4

5

6

7

8

9

42

43

44

1

2

3

I/O

P1.0/ADIN0

P1.1/ADIN1

P1.2/ADIN2

P1.3/ADIN3

P1.4/ADIN4

P1.5/ADIN5

P2.0-P2.7

21-28 24-31 18-25

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port. Port 2 emits the high-order address byte

during accesses to external program and data memory that use 16-bit addresses (MOVX

@DPTR) (see Note 5). In this application, it uses strong internal pull-ups when emitting 1s.

Port 2 receives the high-order address byte during program verification and parallel EPROM

programming. During reset, the port 2 pullups are turned on synchronously, and the port

register is loaded with 1’s. Port 2 has the following output modes which can be selected on a

per bit basis by writing to P2M1 and P2M0:

P2M1.X

P2M2.X

Mode Description

0

1

0

1

0

1

Open drain. See Note 1.

Weak pullup (default). See Note 2.

High impedance. See Note 3.

Push-pull. See Note 4.

Port 2 pins serve alternate functions as follows:

21

22

23

24

25

26

27

28

24

25

26

27

28

29

30

31

18

19

20

21

22

23

24

25

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

CEX0

CMP0

CEX1

CMP1

CEX2

CMP2

CEX3

CMP3

T2EX

A0

T2

CS

CEX4

PCA module 0 external I/O

comparator 0 output

PCA module 1 external I/O

comparator 1 output

PCA module 2 external I/O

comparator 2 output

PCA module 3 external I/O

comparator 3 output

timer 2 capture input

UPI address input

timer 2 external I/O — clock-out (programmable)

UPI chip select input

PCA module 4 external I/O

PWM0 Pulse width modulator 0 output

ECI PCA count input

PWM1 Pulse width modulator 1 output

5

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

PIN DESCRIPTIONS (Continued)

PIN NUMBER

MNEMONIC

DIP

1

LCC

QFP TYPE NAME AND FUNCTION

+V

REF

–V

REF

/AV

2

3

40

41

I

A/D positive power supply

A/D 0V reference

CC

SS

2

P3.0-P3.7

10-17

11,

5,

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port. Port 3 pins that have 1s written to them can

be used as inputs but will source current when externally pulled low (see DC Electrical

13-19 7-13

Characteristics: I ). During reset all pins will be synchronously driven high and will remain

IL

high until written to by software. Port 3 has the following output modes which can be

selected on a per bit basis by writing to P3M1 and P3M2:

P3M1.X

P3M2.X

Mode Description

0

1

0

1

0

1

Open drain. See Note 1.

Weak pullup (default). See Note 2.

High impedance. See Note 3.

Push-pull. See Note 4.

Port 3 pins serve alternate functions as follows:

10

11

12

11

13

14

5

7

8

I

O

I

P3.0

P3.1

P3.2

RxD

TxD

INT0

Serial receive port

Serial transmit port (enabled only when transmitting serial data)

External interrupt 0

CMP3+ Comparator 3 positive input

INT1 External interrupt 1

CMP2+ Comparator 2 positive input

T0 Timer/counter 0 input

CMP1+ Comparator 1 positive input

T1 Timer/counter 1 input

CMPR– Common reference to comparators 1, 2, 3

WR External data memory write strobe

CMP0+ Comparator 0 positive input

RD External data memory read strobe

CMP0– Comparator 0 negative input

13

14

15

16

17

9

15

16

17

18

19

10

9

I

P3.3

P3.4

P3.5

P3.6

P3.7

10

11

12

13

4

I

O

I

RST

Reset: A low on this pin synchronously resets all port pins to a high state. The pin must be

held low with the oscillator running for 24 oscillator cycles to initialize the internal registers.

An internal diffused resistor to V permits a power on reset using only an external

CC

capacitor to V . RST has a Schmitt trigger input stage to provide additional noise immunity

SS

with a slow rising input voltage.

ALE/PROG

30

33

27

I/O

Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address

during an access to external memory. In normal operation, ALE is emitted at a constant rate

of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that

one ALE pulse is skipped during each access to external data memory. ALE is switched off

if the bit 0 in the AUXR register (8EH) is set. This pin is also the program pulse input

(PROG) during parallel EPROM programming. (See also Internal Reset on page 24.)

PSEN

29

31

32

35

26

29

O

I

Program Store Enable: The read strobe to external program memory. When the device is

executing code from the external program memory, PSEN is activated twice each machine

cycle, except that two PSEN activations are skipped during each access to external data

memory. PSEN is not activated during fetches from internal program memory.

External Access Enable/Programming Supply Voltage: EA must be externally held low

to enable the device to fetch code from external program memory locations 0000H to

1FFFH. If EA is held high, the device executes from internal program memory unless the

program counter contains an address greater than 1FFFH. This pin also receives the

EA/V

PP

12.75V programming supply voltage (V ) during EPROM programming. If this pin is at V

PP

voltage during reset the device enters the in-circuit programming mode.

XTAL1

19

18

21

20

15

14

I

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator

circuits.

Crystal 2: Output from the inverting oscillator amplifier.

XTAL2

O

NOTES:

1. When Open Drain mode is selected, ports 0 and 2 have weak pulldowns to guarantee positive leakage current (see DC electrical

characteristic I ).

IH

2. When Weak Pullup mode is selected, ports bits that have 1’s written to them can be used as inputs but will source current when externally

pulled low (see DC electrical characteristic I ).

IL

3. When High Impedance mode is selected, all pullups and pulldowns are turned off. The only current sourced or sunk by the pin is the

parasitic leakage current (see DC electrical characteristic I or I , as applicable.

L2

LC

4. When Push-Pull mode is selected, strong pullups are on continuously when emitting 1’s (see DC electrical characteristic V ).

OH

5. When Open-Drain, Weak Pull-up, or Push-pull mode is selected.

6

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

Table 1.

SYMBOL

ACC*

87C576 Special Function Registers

DIRECT

DESCRIPTION

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

ADDRESS MSB

RESET

VALUE

LSB

Accumulator

E0H

E7

E6

E5

E4

E3

E2

E1

E0

00H

ADC0H#

ADC1H#

ADC2H#

ADC3H#

ADC4H#

ADC5H#

ADC0L#

ADC1L#

ADC2L#

ADC3L#

ADC4L#

ADC5L#

A/D Channel 0 MSB

A/D Channel 1 MSB

A/D Channel 2 MSB

A/D Channel 3 MSB

A/D Channel 4 MSB

A/D Channel 5 MSB

A/D Channel 0 2-LSBits

A/D Channel 1 2-LSBits

A/D Channel 2 2-LSBits

A/D Channel 3 2-LSBits

A/D Channel 4 2-LSBits

A/D Channel 5 2-LSBits

AAH

ABH

ACH

ADH

AEH

AFH

9AH

9BH

9CH

9DH

9EH

9FH

00H

AMOD1

ASCA2 ASCA1

ADCON#

ADCS#

A/D Control

B1H

B2H

ADF

ADCE

AD8M

AMOD0

ASCA0 00H

00H

A/D Channel Select

AUXR#

B*

Auxiliary

8EH

F0H

–

SRST

F3

TXI

F2

LO

F1

AO

F0

xxxx0000B

B register

F7

F6

F5

F4

00H

CCAP0H# Module 0 Capture High

CCAP1H# Module 1 Capture High

CCAP2H# Module 2 Capture High

CCAP3H# Module 3 Capture High

CCAP4H# Module 4 Capture High

CCAP0L# Module 0 Capture Low

CCAP1L# Module 1 Capture Low

CCAP2L# Module 2 Capture Low

CCAP3L# Module 3 Capture Low

CCAP4L# Module 4 Capture Low

FAH

FBH

FCH

FDH

FEH

EAH

EBH

ECH

EDH

EEH

xxxxxxxxB

CCAPM0# Module 0 Mode

CCAPM1# Module 1 Mode

CCAPM2# Module 2 Mode

CCAPM3# Module 3 Mode

CCAPM4# Module 4 Mode

DAH

DBH

DCH

DDH

DEH

–

ECOM

CAPP

CAPN

MAT

TOG

PWM

ECCF

x0000000B

DF

CF

DE

CR

DD

–

DC

DB

DA

D9

D8

CCON*#

CH#

CL#

PCA Counter Control

PCA Counter High

PCA Counter Low

D8H

F9H

E9H

CCF4

CCF3

CCF2 CCF1

CCF0

00x00000B

00H

CMOD#

PCA Counter Mode

D9H

CIDL

C7

WDTE

C6

–

CPS1 CPS0

ECF

00xxx000B

C5

C4

C3

C2

C1

C0

CMP*#

CMPE#

Comparator

C0H

92H

EC3DP EC2DP EC1DP EC0DP C3RO

C2RO C1RO

EC2O EC1O

C0RO

EC0O

00H

Comparator Enable

EC3TDC EC2TDC EC1TDC EC0TDC

EC3O

DPTR:

DPH

DPL

Data Pointer (2 bytes)

Data Pointer High

Data Pointer Low

83H

82H

00H

AF

EA

AE

EC

EIB

AD

ET2

EAD

AC

ES

AB

AA

A9

A8

IE0*#

IE1*#

Interrupt Enable 0

Interrupt Enable 1

A8H

E8H

ET1

EC3

EX1

EC2

ET0

EC1

EX0

EC0

00H

EOB

EC4

*

#

SFRs are bit addressable.

SFRs are modified from or added to the 80C51 SFRs.

7

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

Table 1.

87C576 Special Function Registers (Continued)

DIRECT

DESCRIPTION

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

RESET

VALUE

SYMBOL

ADDRESS MSB

LSB

BF

–

BE

PPC

PIB

86

BD

PT2

PAD

85

BC

PS

BB

PT1

PC3

83

BA

PX1

PC2

82

B9

PT0

PC1

81

B8

IP0*

Interrupt Priority 0

Interrupt Priority 1

B8H

F8H

PX0

PC0

80

x0000000B

00H

IP1*#

POB

87

PC4

84

P0*

P1*

P2*

P3*

Port 0

Port 1

Port 2

Port 3

80H

90H

A0H

B0H

AD7

97

AD6

96

AD5

95

AD4

94

AD3

93

AD2

92

AD1

91

AD0

90

FFH

–

ADIN5 ADIN4

ADIN3

A3

ADIN2 ADIN1 ADIN0 FFH

A7

ECI

B7

RD

A6

A5

T2

B5

T1

A4

T2EX

B4

A2

CEX2

B2

A1

CEX1

B1

A0

CEX0

B0

CEX4

B6

CEX3

B3

FFH

WR

T0

INT1

INT0

TxD

RxD

P0M1#

P0M2#

P1M1#

P1M2#

P2M1#

P2M2#

P3M1#

P3M2#

Port 0 Output Mode 1

Port 0 Output Mode 2

Port 1 Output Mode 1

Port 1 Output Mode 2

Port 2 Output Mode 1

Port 2 Output Mode 2

Port 3 Output Mode 1

Port 3 Output Mode 2

84H

85H

94H

95H

A4H

A5H

B4H

B5H

00H

3FH

00H

FFH

00H

FFH

1

WDT0F

SMOD1

D7

SMOD0

D6

PCON

Power Control

87H

OSF

D5

F0

–

POF

LVF

PD

D1

IDL

D0

00xxxx00B

D4

RS1

–

D3

D2

OV

PSW*

Program Status Word

PWM Control

D0H

BCH

CY

AC

RS0

–

P

00H

EN/CLR

PWCON#

–

PWMF

PWE1

PWE0

PWMP#

PWM0#

PWM1#

PWM Prescaler

PWM Register 0

PWM Register 1

BDH

BEH

BFH

00H

RACAP2H#

RACAP2L#

Timer 2 Capture High

Timer 2 Capture Low

CBH

CAH

00H

SADDR#

SADEN#

Slave Address

Slave Address Mask

A9H

B9H

00H

SBUF

Serial Data Buffer

99H

xxxxxxxxB

9F

9E

9D

9C

9B

9A

99

TI

98

RI

SM0/FE

SCON*

SP

Serial Control

Stack Pointer

98H

81H

SM1

SM2

REN

TB8

RB8

00H

07H

8F

TF1

CF

TF2

–

8E

TR1

CE

8D

TF0

CD

8C

TR0

CC

8B

IE1

8A

IT1

CA

TR2

–

89

IE0

C9

88

IT0

C8

TCON*

Timer Control

88H

00H

CB

T2CON*

T2MOD#

Timer 2 Control

C8H

C9H

EXF2

–

RCLK

–

TCLK

–

EXEN2

–

C/T2

CP/RL2 00H

DCEN xxxxxxx0B

2

Timer 2 Mode Control

T2OE

*

#

SFRs are bit addressable.

SFRs are modified from or added to the 80C51 SFRs.

1. Reset value depends on reset source.

2. Programmable clock-out

8

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

Table 1.

87C576 Special Function Registers (Continued)

DIRECT

DESCRIPTION

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

RESET

VALUE

SYMBOL

ADDRESS MSB

LSB

TH0

TH1

TH2#

TL0

TL1

TL2#

Timer High 0

Timer High 1

Timer High 2

Timer Low 0

Timer Low 1

Timer Low 2

8CH

8DH

CDH

8AH

8BH

CCH

00H

TMOD

UCS#

Timer Mode

89H

86H

GATE

ST7

C/T

M1

M0

GATE

UE

C/T

AF

M1

M0

00H

OBE/OBF

UPI Control/Status

ST6

ST5

ST4

IBF

WDRUN

WDCON

#

Watchdog Timer Control

Watchdog Timer Reload

C4H

PRE2

PRE1

PRE0

LVRE

OFRE

DPD

WDMOD 11111111B

WDL#

C1H

C2H

C3H

00H

xxH

WFEED1# Watchdog Feed 1

WFEED2# Watchdog Feed 2

*

#

SFRs are bit addressable.

SFRs are modified from or added to the 80C51 SFRs.

1. Reset value depends on reset source.

The 8XC576 has a number of failure detect circuits to prevent

abnormal operating conditions. these failure detect circuits generate

resets as shown in Figure 1.

LOW ACTIVE RESET

One of the most notable features on this part is the low active reset.

The low active reset operates exactly the same as high active reset

with the exception that the part is put into the reset mode by

applying a low level to the reset pin. For power-on reset it is also

necessary to invert the power-on reset circuit; connecting the 8.2K

POWER ON CLEAR / POWER ON FLAG

An on-chip Power On Detect Circuit resets the 8XC576 and sets the

resistor from the reset pin to V and the 10µf capacitor from the

reset pin to ground. Figure 1 shows the reset related circuitry.

CC

Power Off Flag (PCON.4) on power up or if V drops to zero

CC

momentarily. The POF can only be cleared by software. The RST

pin is not driven by the power on detect circuit. The POF can be

read by software to determine that a power failure has occurred and

can also be set by software.

When reset the port pins on the 8XC576 are driven high

synchronously.

The 8XC576 also has Low voltage detection circuitry that will, if

enabled, force the part to reset when V (on the part) fails below a

CC

set level. Low Voltage Reset is enabled by a normal reset. Low

Voltage Reset can be disabled by clearing LVRE (bit 4 in the

WDCON SFR) then executing a watchdog feed sequence (A5H to

WFEED1 followed immediately by 5AH to WFEED2). In addition

there is a flag (LVF) that is set if a low voltage condition is detected.

The LVF flag is set even if the Low Voltage detection circuitry is

disabled. Notice that the Low voltage detection circuitry does not

drive the RST# pin so the LVF flag is the only way that the

microcontroller can determine if it has been reset due to a low

voltage condition.

LOW VOLTAGE DETECT

An on-chip Low Voltage Detect circuit sets the Low Voltage Flag

(PCON.3) if V drops below V

(see DC Electrical

CC

LOW

Characteristics) and resets the 8XC576 if the Low Voltage Reset

Enable bit (WDCON.4) is set. If the LVRE is cleared, the reset is

disabled but LVF will still be set if V is low. The RST pin is not

CC

driven by the low voltage detect circuit. The LVF can be read by

software to determine that V was low. The LVF can be set or

CC

cleared by software.

OSCILLATOR FAIL DETECT

The 8XC576 has an on-chip power-on detection circuit that sets the

POF (PCON.4) flag on power up or if the V level momentarily

An on-chip Oscillator Fail Detect circuit sets the Oscillator Fail Flag

(PCON.5) if the oscillator frequency drops below OSCF for one or

more cycles (see AC Electrical Characteristics: OSCF) and resets

the 8XC576 if the Oscillator Fail Reset Enable bit (WDCON.3) is set.

If OFRE is cleared, the reset is disabled but OSF will still be set if

the oscillator fails. The RST pin is not driven by the oscillator fail

detect circuit. The OSF can be read by software to determine that

an oscillator failure has occurred. The OSF can be set or cleared by

software.

CC

drops to 0V. This flag can be used to determine if the part is being

started from a power-on (cold start) or if a reset has occurred due to

another condition (warm start).

The 8XC576 can be reset in software by setting the RST bit of the

AUXR register (AUXR.3). See Figure 1 for reset diagram.

9

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

AUXR

(8EH)

–

SRST

LVF

TXI

LO

PD

AO

IDL

PCON

(87H)

V

CC

SMOD1

SMOD0

OSF

POF

WDTOF

POWER-ON DETECT

8xC576

INTERNAL

RESET

+

–

VLOW

(LOW V

CC

REFERENCE)

OSC FREQ BELOW OSCF

(MIN FREQUENCY)

RST

WDTE

PCA WATCHDOG

SHADOW REGISTER

FOR WDCON

WATCHDOG TIMER

SHADOW REGISTER

WATCHDOG FEED

PRE2

WDCON

PRE1

PRE0

–

LVRE

–

OFRE

–

DPD

WDRUN WDMOD

(C4H)

CMOD

(D9H)

CIDL

WDTE

CPS1

CPS0

ECF

SU00515B

Figure 1. Reset Circuitry

The PCA timer is a common time base for all five modules and can

be programmed to run at: 1/12 the oscillator frequency, 1/4 the

oscillator frequency, the Timer 0 overflow, or the input on the ECI pin

(P2.7). The timer count source is determined from the CPS1 and

CPS0 bits in the CMOD SFR as follows (see Figure 3):

TIMERS

The 8XC576 has four on-chip timers.

Timers 0 and 1 are identical in every way to Timers 0 and 1 on the

80C51.

Timer 2 on the 8XC576 is identical to the 80C52 Timer 2 (described

in detail in the 80C52 overview) with the exception that it is an up or

down counter. To configure the Timer to count down the DCEN bit in

the T2MOD special function register must be set and a low level

must be present on the T2EX pin (P1.1).

CPS1 CPS0 PCA Timer Count Source

0

1

0

1

0

1

1/12 oscillator frequency

1/4 oscillator frequency

Timer 0 overflow

External Input at ECI pin (P2.7)

The Pulse Width Modulator (PWM) system can be used as a timer

by disabling its outputs and monitoring its counter overflow flag, the

PWMF bit in the PWCON register (see the PWM section for details).

In the CMOD SFR are three additional bits associated with the PCA.

They are CIDL which allows the PCA to stop during idle mode,

WDTE which enables or disables the watchdog function on

module 4, and ECF which when set causes an interrupt and the

PCA overflow flag CF (in the CCON SFR) to be set when the PCA

timer overflows. These functions are shown in Figure 3.

The Watchdog timer operation and implementation is similar to the

8XC550 (for additional information see the 8XC550 datasheet) with

the exception that the reset values of the WDCON and WDL special

function registers have been changed. The changes in these

registers cause the watchdog timer to be enabled with a timeout of

The watchdog timer function is implemented in module 4 as

implemented in other parts that have a PCA that are available on the

market. However, if a watchdog timer is required in the target

application, it is recommended to use the hardware watchdog timer

that is implemented on the 87C576 separately from the PCA (see

Figure 15).

16384 × T

when the part is reset. The watchdog can be disabled

OSC

by executing a valid feed sequence and then clearing WDRUN (bit 2

in the WDCON SFR). In timer mode, the timer is controlled by

toggling the WDRUN bit. The timeout flag, WDTOF, is set when the

timer overflows and must be cleared in software.

The CCON SFR contains the run control bit for the PCA and the

flags for the PCA timer (CF) and each module (refer to Figure 6). To

run the PCA the CR bit (CCON.6) must be set by software. The

PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when

the PCA counter overflows and an interrupt will be generated if the

ECF bit in the CMOD register is set, The CF bit can only be cleared

by software. Bits 0 through 4 of the CCON register are the flags for

the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set

by hardware when either a match or a capture occurs. These flags

PROGRAMMABLE COUNTER ARRAY (PCA)

The Programmable Counter Array is a special Timer that has five

16-bit capture/compare modules associated with it. Each of the

modules can be programmed to operate in one of four modes: rising

and/or falling edge capture, software timer, high-speed output, or

pulse width modulator. Each module has a pin associated with it in

port 2. Module 0 is connected to P2.0(CEX0), module 1 to

P2.1(CEX1), etc. The basic PCA configuration is shown in Figure 2.

10

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

also can only be cleared by software. The PCA interrupt system

shown in Figure 4.

16-bit Software Timer Mode

The PCA modules can be used as software timers by setting both

the ECOM and MAT bits in the modules CCAPMn register. The PCA

timer will be compared to the module’s capture registers and when a

match occurs an interrupt will occur if the CCFn (CCON SFR) and

the ECCFn (CCAPMn SFR) bits for the module are both set (see

Figure 10).

Each module in the PCA has a special function register associated

with it. These registers are: CCAPM0 for module 0, CCAPM1 for

module 1, etc. (see Figure 7). The registers contain the bits that

control the mode that each module will operate in. The ECCF bit

(CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module)

enables the CCF flag in the CCON SFR to generate an interrupt

when a match or compare occurs in the associated module. PWM

(CCAPMn.1) enables the pulse width modulation mode. The TOG

bit (CCAPMn.2) when set causes the CEX output associated with

the module to toggle when there is a match between the PCA

counter and the module’s capture/compare register. The match bit

MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON

register to be set when there is a match between the PCA counter

and the module’s capture/compare register.

High Speed Output Mode

In this mode the CEX output (on port 2) associated with the PCA

module will toggle each time a match occurs between the PCA

counter and the module’s capture registers. To activate this mode

the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must

be set (see Figure 11).

Pulse Width Modulator Mode

All of the PCA modules can be used as PWM outputs. Figure 12

shows the PWM function. The frequency of the output depends on

the source for the PCA timer. All of the modules will have the same

frequency of output because they all share the PCA timer. The duty

cycle of each module is independently variable using the module’s

capture register CCAPLn. When the value of the PCA CL SFR is

less than the value in the module’s CCAPLn SFR the output will be

low, when it is equal to or greater than the output will be high. When

CL overflows from FF to 00, CCAPLn is reloaded with the value in

CCAPHn. the allows updating the PWM without glitches. The PWM

and ECOM bits in the module’s CCAPMn register must be set to

enable the PWM mode.

The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5)

determine the edge that a capture input will be active on. The CAPN

bit enables the negative edge, and the CAPP bit enables the

positive edge. If both bits are set both edges will be enabled and a

capture will occur for either transition. The last bit in the register

ECOM (CCAPMn.6) when set enables the comparator function.

Figure 8 shows the CCAPMn settings for the various PCA functions.

There are two additional registers associated with each of the PCA

modules. They are CCAPnH and CCAPnL and these are the

registers that store the 16-bit count when a capture occurs or a

compare should occur. When a module is used in the PWM mode

these registers are used to control the duty cycle of the output.

PCA Interrupt System

The PCA on most 80C51 family devices provides a single interrupt

source, EC (IE.6). The 8xC576 expands the flexibility of the PCA by

providing additional interrupt sources for each of the five PCA

modules, EC0 (IE1.0) through EC4 (IE1.4), in addition to the original

interrupt source EC (IE.6). Any of these sources can be enabled at

any time. It is possible for both a module source (EC0 through EC4)

to be enabled at the same time that the single source, EC, is

enabled. In this case, a module event will generate an interrupt for

both the module source and the single source, EC.

PCA Capture Mode

To use one of the PCA modules in the capture mode either one or

both of the CCAPM bits CAPN and CAPP for that module must be

set. The external CEX input for the module (on port 2) is sampled for

a transition. When a valid transition occurs the PCA hardware loads

the value of the PCA counter registers (CH and CL) into the

module’s capture registers (CCAPnL and CCAPnH). If the CCFn bit

for the module in the CCON SFR and the ECCFn bit in the CCAPMn

SFR are set then an interrupt will be generated. Refer to Figure 9.

16 BITS

P2.0/CEX0

P2.1/CEX1

P2.2/CEX2

P2.3/CEX3

MODULE 0

MODULE 1

16 BITS

PCA TIMER/COUNTER

MODULE 2

MODULE 3

MODULE 4

TIME BASE FOR PCA MODULES

MODULE FUNCTIONS:

16-BIT CAPTURE

16-BIT TIMER

P2.6/CEX4

SU00578

16-BIT HIGH SPEED OUTPUT

8-BIT PWM

WATCHDOG TIMER (MODULE 4 ONLY)

Figure 2. Programmable Counter Array (PCA)

11

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

TO PCA

MODULES

OSC/12

OSC/4

OVERFLOW

INTERRUPT

CH

CL

16–BIT UP COUNTER

TIMER 0

OVERFLOW

EXTERNAL INPUT

(P2.7/ECI)

00

01

10

11

DECODE

IDLE

CMOD

(D9H)

CIDL

CF

WDTE

––

CPS1

CCF2

CPS0

ECF

CCON

(D8H)

CR

CCF4

CCF3

CCF1

CCF0

SU00516

Figure 3. PCA Timer/Counter

CCON

(D8H)

CF

CR

––

CCF4

CCF3

CCF2

CCF1

CCF0

PCA TIMER/COUNTER

MODULE 0

IE0.7

EA

IE1.0

EC0

TO

INTERRUPT

PRIORITY

DECODER

MODULE 1

MODULE 2

IE0.7

EA

IE1.1

EC1

TO

INTERRUPT

PRIORITY

DECODER

MODULE 3

MODULE 4

IE0.7

EA

IE0.6

EC

TO

INTERRUPT

PRIORITY

DECODER

IE0.7

EA

IE1.2

EC2

CCAPMn.0

ECCFn

CMOD.0

ECF

TO

INTERRUPT

PRIORITY

DECODER

IE0.7

EA

IE1.3

EC3

TO

INTERRUPT

PRIORITY

DECODER

IE0.7

EA

IE1.4

EC4

TO

INTERRUPT

PRIORITY

DECODER

SU00579

Figure 4. PCA Interrupt System

12

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

CMOD Address = OD9H

Reset Value = 00XX X000B

CIDL

WDTE

–

CPS1

CPS0

ECF

Bit:

Function

7

6

5

4

3

2

1

0

Symbol

CIDL

Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode.

CIDL = 1 programs it to be gated off during idle.

WDTE

–

Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.

Not implemented, reserved for future use.*

CPS1

CPS0

PCA Count Pulse Select bit 1.

PCA Count Pulse Select bit 0.

CPS1

CPS0

Selected PCA Input**

0

1

0

1

0

1

0

1

2

3

Internal clock, f

÷ 12

÷ 4

OSC

Internal clock, f

OSC

Timer 0 overflow

External clock at ECI/P2.7 pin (max. rate = f

÷ 8)

OSC

ECF

PCA Enable Counter Overflow interrupt:

ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF.

NOTE:

*

User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the

new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

** –f

= oscillator frequency

OSC

SU00686A

Figure 5. CMOD: PCA Counter Mode Register

CCON Address = OD8H

Reset Value = 00X0 0000B

Bit Addressable

CF

CR

–

CCF4

CCF3

CCF2

CCF1

CCF0

Bit:

7

6

5

4

3

2

1

0

Symbol

CF

Function

PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is

set. CF may be set by either hardware or software but can only be cleared by software.

CR

PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA

counter off.

–

Not implemented, reserved for future use*.

CCF4

CCF3

CCF2

CCF1

CCF0

PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

NOTE:

*

User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the

new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

SU00036

Figure 6. CCON: PCA Counter Control Register

13

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

CCAPMn Address

CCAPM0

CCAPM1

CCAPM2

CCAPM3

CCAPM4

0DAH

0DBH

0DCH

0DDH

0DEH

Reset Value = X000 0000B

Not Bit Addressable

–

ECOMn CAPPn

CAPNn

MATn

TOGn

PWMn

ECCFn

Bit:

7

6

5

4

3

2

1

0

Symbol

Function

–

Not implemented, reserved for future use*.

ECOMn

CAPPn

CAPNn

MATn

Enable Comparator. ECOMn = 1 enables the comparator function.

Capture Positive, CAPPn = 1 enables positive edge capture.

Capture Negative, CAPNn = 1 enables negative edge capture.

Match. When MATn = 1, a match of the PCA counter with this module’s compare/capture register causes the CCFn bit

in CCON to be set, flagging an interrupt.

TOGn

Toggle. When TOGn = 1, a match of the PCA counter with this module’s compare/capture register causes the CEXn

pin to toggle.

PWMn

ECCFn

Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output.

Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt.

NOTE:

*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new

bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

SU00037

Figure 7. CCAPMn: PCA Modules Compare/Capture Registers

–

X

ECOMn CAPPn CAPNn

MATn

TOGn

PWMn

ECCFn

MODULE FUNCTION

0

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

1

0

X

0

No operation

16-bit capture by a positive-edge trigger on CEXn

16-bit capture by a negative trigger on CEXn

16-bit capture by a transition on CEXn

16-bit Software Timer

16-bit High Speed Output

8-bit PWM

X

Watchdog Timer

Figure 8. PCA Module Modes (CCAPMn Register)

14

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

CCON

(D8H)

CF

CR

––

CCF4

CCF3

CCF2

CCF1

CCF0

PCA INTERRUPT

(TO CCFn)

PCA TIMER/COUNTER

CH

CL

CAPTURE

CEXn

CCAPnH

CCAPnL

CCAPMn, n= 0 to 4

(DAH – DEH)

––

ECOMn

0

CAPPn

CAPNn

MATn

0

TOGn

0

PWMn

ECCFn

0

SU00749

Figure 9. PCA Capture Mode

CCON

(D8H)

CF

CR

––

CCF4

CCF3

CCF2

CCF1

CCF0

WRITE TO

CCAPnH

RESET

PCA INTERRUPT

CCAPnH

CCAPnL

WRITE TO

CCAPnL

(TO CCFn)

0

1

ENABLE

MATCH

16–BIT COMPARATOR

CH

CL

PCA TIMER/COUNTER

CCAPMn, n= 0 to 4

(DAH – DEH)

––

ECOMn

CAPPn

0

CAPNn

0

MATn

TOGn

0

PWMn

0

ECCFn

SU00750

Figure 10. PCA Compare Mode

15

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

CCON

(D8H)

CF

CR

––

CCF4

CCF3

CCF2

CCF1

CCF0

WRITE TO

CCAPnH

RESET

PCA INTERRUPT

CCAPnH

CCAPnL

WRITE TO

CCAPnL

(TO CCFn)

0

1

MATCH

ENABLE

16–BIT COMPARATOR

TOGGLE

CEXn

CH

CL

PCA TIMER/COUNTER

CCAPMn, n: 0..4

(DAH – DEH)

––

ECOMn

CAPPn

0

CAPNn

0

MATn

TOGn

PWMn

0

ECCFn

1

SU00751

Figure 11. PCA High Speed Output Mode

CCAPnH

CCAPnL

0

CL < CCAPnL

ENABLE

8–BIT

CEXn

COMPARATOR

CL >= CCAPnL

1

CL

OVERFLOW

PCA TIMER/COUNTER

CCAPMn, n: 0..4

(DAH – DEH)

––

ECOMn

CAPPn

0

CAPNn

MATn

0

TOGn

0

PWMn

ECCFn

0

SU00752

Figure 12. PCA PWM Mode

16

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

WATCHDOG TIMER

• Watchdog mode bit set to watchdog mode.

• Watchdog is running.

• Autoload register set to 00 (min. count).

• Watchdog time-out flag is unchanged.

• Prescaler is cleared.

• Prescaler tap set to the highest divide.

• Autoload takes place.

The watchdog timer is not directly loadable by the user. Instead, the

value to be loaded into the main timer is held in an autoload register

or is part of the mask ROM programming. In order to cause the main

timer to be loaded with the appropriate value, a special sequence of

software action must take place. This operation is referred to as

feeding the watchdog timer.

To feed the watchdog, two instructions must be sequentially

executed successfully. No intervening instruction fetches are

allowed, so interrupts should be disabled before feeding the

watchdog. The instructions should move A5H to the WFEED1

register and then 5AH to the WFEED2 register. If WFEED1 is

correctly loaded and WFEED2 is not correctly loaded, then an

immediate underflow will occur.

The watchdog can be fed even though it is in the timer mode.

Note that the operational concept is for the watchdog mode of

operation, when coming out of a hardware reset, the software

should load the autoload registers, set the mode to watchdog, clear

the watchdog timeout flag, and then feed the watchdog (cause an

autoload). The watchdog will now be starting at a known point.

The watchdog timer subsystem has two modes of operation. Its

principal function is a watchdog timer. In this mode it protects the

system from incorrect code execution by causing a system reset

when the watchdog timer underflows as a result of a failure of

software to feed the timer prior to the timer reaching its terminal

count. If the user does not employ the watchdog function, the

watchdog subsystem can be used as a timer. In this mode, reaching

the terminal count sets a flag. In most other respects, the timer

mode possesses the characteristics of the watchdog mode. This is

done to protect the integrity of the watchdog function.

If the watchdog is in the watchdog mode and running and happens

to underflow at the time the external RESET is applied, the

watchdog time-out flag will be set.

When the watchdog is in the watchdog mode and the watchdog

underflows, the following action takes place (see Figure 17):

• Autoload takes place.

• Watchdog time-out flag is set

• Mode bit unchanged.

• Watchdog run bit unchanged.

• Autoload register unchanged.

• Prescaler tap unchanged.

The watchdog timer subsystem consists of a prescaler and a main

counter. The prescaler has 8 selectable taps off the final stages and

the output of a selected tap provides the clock to the main counter.

The main counter is the section that is loaded as a result of the

software feeding the watchdog and it is the section that causes the

system reset (watchdog mode) or time-out flag to be set (timer

mode) if allowed to reach its terminal count.

• All other device action same as external reset.

Note that if the watchdog underflows, the program counter will start

from 00H as in the case of an external reset. The watchdog time-out

flag can be examined to determine if the watchdog has caused the

reset condition. The watchdog time-out flag bit must be cleared by

software.

Programming the Watchdog Timer

Both the EPROM and ROM devices have a set of SFRs for holding

the watchdog autoload values and the control bits. The watchdog

time-out flag is present in the PCON register and operates the same

in all versions. In the EPROM device, the watchdog parameters

(autoload value and control) are always taken from the SFRs. In the

ROM device, the watchdog parameters can be mask programmed

or taken from the SFRs. The selection to take the watchdog

parameters from the SFRs or from the mask programmed values is

controlled by EA (external access). When EA is high (internal ROM

access), the watchdog parameters are taken from the mask

programmed values. If the watchdog is mask programmed to the

timer mode, then the autoload values and the pre-scaler taps are

taken from the SFRs. When EA is low (external access), the

watchdog parameters are taken from the SFRs. The user should be

able to leave code in his program which initializes the watchdog

SFRs even though he has migrated to the mask ROM part. This

allows no code changes from EPROM prototyping to ROM coded

production parts. The run control bit only functions in timer mode

and does not require a feed sequence to modify.

When the watchdog is in the timer mode and the timer software

underflows, the following action takes place:

• Autoload takes place.

• Watchdog time-out flag is set

• Mode bit unchanged.

• Watchdog run bit unchanged.

• Autoload register unchanged.

• Prescaler tap unchanged.

Mask ROM Device (EA = 1)

In the mask ROM device, the watchdog mode bit (WDMOD) is mask

programmed and the bit in the watchdog command register is read

only and reflects the mask programmed selection. If the mask

programmed mode bit selects the timer mode, then the watchdog

run bit (WDRUN) operates as described under EPROM Device. If the

mask programmed bit selects the watchdog mode, then the watchdog

run bit has no effect on the timer operation (see Figure 16).

Watchdog Detailed Operation

EPROM Device (and ROMless Operation: EA = 0)

In the ROMless operation (ROM part, EA = 0) and in the EPROM

device, the watchdog operates in the following manner (see

Figure 15).

Watchdog Function

The watchdog consists of a programmable prescaler and the main

timer. The prescaler derives its clock from the on-chip oscillator. The

prescaler consists of a divide by 2 followed by a 13 stage upcounter

with taps from stage 6 through stage 13. This is shown in Figure 18.

Whether the watchdog is in the watchdog or timer mode, when

external RESET is applied, the following takes place:

17

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

The tap selection is programmable. The watchdog main counter is a

down counter clocked (decremented) each time the programmable

prescaler overflows. The watchdog generates an underflow signal

(and is autoloaded) when the watchdog is at count 0 and the prescaler

clock decrements the watchdog. The watchdog is 8 bits long and the

autoload value can range from 0 to FFH. (The autoload value of 0 is

permissible since the prescaler is cleared upon autoload).

Additional bits in WDCON are used to disable reset generation by

the oscillator fail and low voltage detect circuits. WDCON can be

written by software only by executing a valid watchdog feed

sequence.

WDCON Register Bit Definitions

WDCON.7 PRE2

WDCON.6 PRE1

WDCON.5 PRE0

WDCON.4 LVRE

Prescaler Select 2, reset to 1

Prescaler Select 1, reset to 1

Prescaler Select 0, reset to 1

Low Voltage Reset Enable, reset to 1

(enabled)

This leads to the following user design equations. Definitions :t

OSC

is the oscillator period, N is the selected prescaler tap value, W is

the main counter autoload value, t is the minimum watchdog

MIN

time-out value (when the autoload value is 0), t

is the maximum

MAX

WDCON.3 OFRE

WDCON.2 DPD

Oscillator Fail Reset Enable, reset to 1

(enabled)

Disable Power Down

time-out value (when the autoload value is FFH), t is the design

D

time-out value.

WDCON.1 WDRUN Watchdog Run, reset to 1 (enabled)

WDCON.0 WDMOD Watchdog Mode, reset to 1 (watchdog

mode)

t

= t

× 2 × 64

OSC

MIN

= t

× 128 × 256

MIN

MAX

PRESCALER

= t

× 2

MIN

× (W + 1)

D

Enhanced UART

(where prescaler = 0, 1, 2, 3, 4, 5, 6, or 7)

The UART operates in all of the usual modes that are described in

the first section of this book for the 80C51. In addition the UART can

perform framing error detect by looking for missing stop bits, and

automatic address recognition. The 8XC576 UART also fully

supports multiprocessor communication as does the standard

80C51 UART.

Note that the design procedure is anticipated to be as follows. A

t

will be chosen either from equipment or operation

MAX

considerations and will most likely be the next convenient value

higher than t . (If the watchdog were inadvertently to start from 00H,

D

an underflow would be guaranteed, barring other anomalies, to

occur within t

).

MAX

When used for framing error detect the UART looks for missing stop

bits in the communication. A missing bit will set the FE bit in the

SCON register. The FE bit shares the SCON.7 bit with SM0 and the

function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure

20). If SMOD0 is set then SCON.7 functions as FE. SCON.7

functions as SM0 when SMOD0 is cleared. When used as FE

SCON.7 can only be cleared by software. Refer to Figure 19.

The software must be written so that a feed operation takes place

every t seconds from the last feed operation. Some tradeoffs may

D

need to be made. It is not advisable to include feed operations in

minor loops or in subroutines unless the feed operation is a specific

subroutine.

Watchdog Control Register (WDCON)

Address C4H

The serial port transmitter data can be inverted by setting the TXI

(AUXR.2) bit. For normal operation, the TXI bit should be cleared.

The following bits of this register are read only in the ROM part

when EA is high: WDMOD, DPD, OFRE, LVRE, PRE0, PRE1, and

PRE2. That is, the register will reflect the mask programmed values.

In the ROM part with EA high, these bits are taken from mask coded

bits and are not readable by the program. WDRUN is read only in

the ROM part when EA is high and WDMOD is in the watchdog

mode. When WDMOD is in the timer mode, WDRUN functions

normally.

Automatic Address Recognition

Automatic Address Recognition is a feature which allows the UART

to recognize certain addresses in the serial bit stream by using

hardware to make the comparisons. This feature saves a great deal

of software overhead by eliminating the need for the software to

examine every serial address which passes by the serial port. This

feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART

modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be

automatically set when the received byte contains either the “Given”

address or the “Broadcast” address. The 9 bit mode requires that

the 9th information bit is a 1 to indicate that the received information

is an address and not data. Automatic address recognition is shown

in Figure 21.

The parameters written into WDMOD, DPD, OFRE, LVRE, PRE0,

PRE1, and PRE2 by the program are not applied directly to the

watchdog timer subsystem. The watchdog timer subsystem is

directly controlled by a second register which stores these bits. The

transfer of these bits from the user register to the second control

register takes place when the watchdog is fed. This prevents

random code execution from directly foiling the watchdog function.

This does not affect the operation where these bits are taken from

mask coded values.

The 8 bit mode is called Mode 1. In this mode the RI flag will be set

if SM2 is enabled and the information received has a valid stop bit

following the 8 address bits and the information is either a Given or

Broadcast address.

The reset values of the WDCON and WDL registers will be such that

the timer resets to the watchdog mode with a timeout period of 2 ×

Mode 0 is the Shift Register mode and SM2 is ignored.

64 × 128 × t

. The watchdog timer does not generate an interrupt.

OSC

18

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

TXD

P3.1

TXI

INT. BUS

D

Q

P3.1

LATCH

WRITE TO LATCH

PROGRAMMABLE OUTPUT BUFFER

SU00711

Figure 13. TXI (AUXR.2) Bit Inverts the TxD Pin (P3.1) When Set

CMOD

ECF

CIDL

WDTE

––

CPS1

CPS0

(D9H)

WRITE TO

CCAP4H

RESET

CCAP4H

CCAP4L

WRITE TO

CCAP4L

0

1

ENABLE

MATCH

16–BIT COMPARATOR

RESET

CH

CL

PCA TIMER/COUNTER

CCAPM4

ECCFn

––

ECOMn

CAPPn

0

CAPNn

0

MATn

1

TOGn

X

PWMn

0

(DEH)

X

SU00042

Figure 14. PCA Watchdog Timer

WDL

(C1H)

WATCHDOG FEED SEQUENCE

MOV WFEED1,#0A5H

MOV WFEED2,#5AH

WDTOF (PCON.2)

8–BIT DOWN

COUNTER

PRESCALER

OSC/2

RESET

SHADOW REGISTER

FOR WDCON

WDCON

(C4H)

PRE2

PRE1

PRE0

LVRE

OFRE

DPD

WDRUN

WDMOD

SU00657C

Figure 15. Watchdog Timer in 87C576 and 80C576 / 83C576 (EA = 0)

19

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

ROM–CODE

CONTENT

WDL

WDCON

ADDRESS

2031H

2030H

WATCHDOG FEED SEQUENCE

MOV WFEED1,#0A5H

MOV WFEED2,#5AH

8–BIT DOWN

COUNTER

RESET

WDTOF (PCON.2)

OSC/2

PRESCALER

1

WDCON

(C4H)

PRE2

PRE1

PRE0

LVRE

OFRE

DPD

WDRUN

WDMOD

SU00658C

Figure 16. Watchdog Timer of 83C576 in Watchdog Mode (EA = 1, WDMOD = 1)

ROM–CODE

WDL

(C1H)

CONTENT

WDCON

ADDRESS

2030H

WATCHDOG FEED SEQUENCE

MOV WFEED1,#0A5H

MOV WFEED2,#5AH

8–BIT DOWN

COUNTER

OSC/2

PRESCALER

WDTOF (PCON.2)

0

WDCON

(C4H)

PRE2

PRE1

PRE0

LVRE

OFRE

DPD

WDRUN

WDMOD

SU00659C

Figure 17. Watchdog Timer of 83C576 in Timer Mode (EA = 1, WDMOD = 0)

20

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

OSC/2

÷64

÷2

÷2048

÷2

÷64

÷128

÷256

÷512

÷1024

÷4096

÷8192

TO WATCHDOG

DOWN COUNTER

000

001

010

011

PRE2

PRE1

DECODE 100

101

110

111

PRE0

SU00660

Figure 18. Watchdog Prescaler

SCON Address = 98H

Bit Addressable

SM0/FE

Reset Value = 0000 0000B

SM1

SM2

REN

TB8

RB8

Tl

Rl

Bit:

7

6

5

4

3

2

1

0

(SMOD0/1)*

Symbol

FE

Function

Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid

frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.

SM0

SM1

Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)

Serial Port Mode Bit 1

SM0

SM1

Mode

Description

Baud Rate**

f /12

OSC

0

1

0

1

0

1

0

1

2

3

shift register

8-bit UART

9-bit UART

variable

/64 or f

f

/32

OSC

variable

SM2

Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the

received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.

In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a

Given or Broadcast Address. In Mode 0, SM2 should be 0.

REN

TB8

RB8

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.

In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.

In Mode 0, RB8 is not used.

Tl

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the

other modes, in any serial transmission. Must be cleared by software.

Rl

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in

the other modes, in any serial reception (except see SM2). Must be cleared by software.

NOTE:

*SMOD0/1 is located at PCON.6, PCON.7

**f = oscillator frequency

OSC

SU00766

Figure 19. SCON: Serial Port Control Register

21

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

D0

D1

D2

D3

D4

D5

D6

D7

D8

START

BIT

DATA BYTE

ONLY IN

MODE 2, 3

STOP

BIT

SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)

SM0 TO UART MODE CONTROL

SCON

(98H)

SM0 / FE

SMOD1

SM1

SM2

REN

POF

TB8

LVF

RB8

GF0

TI

RI

PCON

(87H)

SMOD0

–

GF1

IDL

0 : SCON.7 = SM0

1 : SCON.7 = FE

SU00044

Figure 20. UART Framing Error Detection

Using the Automatic Address Recognition feature allows a master to

selectively communicate with one or more slaves by invoking the

Given slave address or addresses. All of the slaves may be

contacted by using the Broadcast address. Two special Function

Registers are used to define the slave’s address, SADDR, and the

address mask, SADEN. SADEN is used to define which bits in the

SADDR are to be used and which bits are “don’t care”. The SADEN

mask can be logically ANDed with the SADDR to create the “Given”

address which the master will use for addressing each of the slaves.

Use of the Given address allows multiple slaves to be recognized

while excluding others. The following examples will help to show the

versatility of this scheme:

Slave 1

SADDR

SADEN

Given

=

1110 0000

1111 1010

1110 0X0X

Slave 2

SADDR

SADEN

Given

=

1110 0000

1111 1100

1110 00XX

In the above example the differentiation among the 3 slaves is in the

lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be

uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and

it can be uniquely addressed by 1110 and 0101. Slave 2 requires

that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0

and 1 and exclude Slave 2 use address 1110 0100, since it is

necessary t make bit 2 = 1 to exclude slave 2.

Slave 0

SADDR

SADEN

Given

=

1100 0000

1111 1101

1100 00X0

The Broadcast Address for each slave is created by taking the

logical OR of SADDR and SADEN. Zeros in this result are treated

as don’t-cares. In most cases, interpreting the don’t-cares as ones,

the broadcast address will be FF hexadecimal.

Slave 1

SADDR

SADEN

Given

=

1100 0000

1111 1110

1100 000X

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR

address 0B9H) are loaded with 0s. This produces a given address

of all “don’t cares” as well as a Broadcast address of all “don’t

cares”. this effectively disables the Automatic Addressing mode and

allows the microcontroller to use standard 80C51 type UART drivers

which do not make use of this feature.

In the above example SADDR is the same and the SADEN data is

used to differentiate between the two slaves. Slave 0 requires a 0 in

bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is

ignored. A unique address for Slave 0 would be 1100 0010 since

slave 1 requires a 0 in bit 1. A unique address for slave 1 would be

1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be

selected at the same time by an address which has bit 0 = 0 (for

slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed

with 1100 0000.

Analog Comparators

Four analog comparators are provided on chip. Three comparators

have a common negative reference CMPR- and independent

positive inputs CMP1+, CMP2+, CMP3+ on port 3. The fourth

comparator has independent positive and negative inputs CMP0+

and CMP0- on port 2. The CMP register contains an output and

enable bit for each comparator. Figure 22 shows the connection of

the comparators.

In a more complex system the following could be used to select

slaves 1 and 2 while excluding slave 0:

Slave 0

SADDR

SADEN

Given

=

1100 0000

1111 1001

1100 0XX0

When the comparator is enabled, the port should be configured by

the user as high impedance.

22

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

D0

D1

D2

D3

D4

D5

D6

D7

D8

SCON

(98H)

SM0

SM1

SM2

REN

1

TB8

X

RB8

TI

RI

1

0

1

RECEIVED ADDRESS D0 TO D7

PROGRAMMED ADDRESS

COMPARATOR

IN UART MODE 2 OR MODE 3 AND SM2 = 1:

INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”

– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES

– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.

SU00045

Figure 21. UART Multiprocessor Communication, Automatic Address Recognition

CMP Register Bit Definitions

CMP.7 enable comparator 3

CMP.6 enable comparator 2

CMP.5 enable comparator 1,

and a bit that can be read by software to determine the state of each

comparator’s output, and CMPE which controls whether the output

from each comparator drives the associated output pin or a capture

input associated with one of the PCA modules.

CMP.4 enable comparator 0

The CMP registers bits 0–3 can be read by software to determine

the state of the output of each comparator. To do this the associated

comparator must be enabled but the output in port 2 can be

disabled. This allows easy polling of the comparator output value

without the need to use up a port pin.

CMP.3 comparator 3 output (read only)

CMP.2 comparator 2 output (read only)

CMP.1 comparator 1 output (read only)

CMP.0 comparator 0 output (read only)

All comparators are disabled automatically in power down mode. In

idle mode unused comparators should be disabled by software to

save power. A comparator can generate an interrupt that will

terminate idle mode when used to drive a PCA capture input.

The CMPE register allows the comparator to drive the associated

PCA module capture input, so that on compare a capture can be

generated in the PCA. Bits 0–3 of this register enable the

comparator output to drive the associated port 2 output circuitry.

Used as a comparator output, the output mode for this port must be

configured for output by the user and the port output SFR bit latch

must be set. If the comparator is not enabled to drive the port 2

circuitry, the associated port 2 pin can be used for other I/O. This

includes when a comparator is enabled to drive the capture input to

a PCA module.

The CMPE register contains bits to enable each comparator to drive

external output pins or internal PCA capture inputs. When the

comparator is configured for external output, the user must also

configure the output port in one of its output modes. The comparator

output is wire-ORed with the corresponding port SFR bit, so the

SFR bit must also be set by software to enable the output.

CMPE Register Bit Definitions

Reduced EMI Mode

CMPE.7 enables comparator 3 to drive CEX3

CMPE.6 enables comparator 2 to drive CEX2

CMPE.5 enables comparator 1 to drive CEX1

CMPE.4 enables comparator 0 to drive CEX0

CMPE.3 enables comparator 3 output on P2.3

CMPE.2 enables comparator 2 output on P2.2

CMPE.1 enables comparator 1 output on P2.1

CMPE.0 enables comparator 0 output on P2.0

There are two bits in the AUXR register that can be set to reduce

the internal clock drive and disable the ALE output. AO (AUXR.0)

when set turns off the ALE output. LO (AUXR.1) when set reduces

the drive of the internal clock circuitry. Both bits are cleared on

Reset. With LO set the 8XC576 will still operate at 12MHz, and will

have reduced EMI in the range above 100MHz.

8XC576 Reduced EMI Mode

AUXR (0X8E)

When 1s are written to CMPE bits 7-4, the comparator outputs will

drive the corresponding capture input. When 1s are written to CMPE

bits 3-0 the comparator output will also drive the corresponding

port 2 pin. If the comparator’s enabled to drive the capture input but

not the port pin, then the port pin can be used for general purpose

I/O. When a comparator output is enabled, the user will need to

configure the port for one of its output modes.

––

RST

TXI

LO

AO

AO: Turns off ALE output.

LO: Reduces drive of internal clock circuitry. 8XC576 spec’d to

12MHz when LO set.

TXI: Inverts TxD when set.

RST: Software reset.

There are two special function registers associated with the

comparators. They are CMP which contains the comparator enables

23

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

CMPE

(92H)

EC3TDC

EC2TDC

EC1TDC

EC0TDC

EC3OD *

EC2OD *

EC1OD *

EC0OD *

P3.6 / CMP0+

P3.7 / CMP0–

+

P2.0 / CMP0

P2.1 / CMP1

P2.2 / CMP2

P2.3 / CMP3

–

TO CEX0 INPUT OF

PCA MODULE 0

ENABLE

+

P3.4 / CMP1+

P3.3 / CMP2+

–

TO CEX1 INPUT OF

PCA MODULE 1

ENABLE

+

–

TO CEX2 INPUT OF

PCA MODULE 2

ENABLE

+

P3.2 / CMP3+

P3.5 / CMPR–

–

TO CEX3 INPUT OF

PCA MODULE 3

ENABLE

* : WILL DISABLE PULLUPS

ON RELEVANT PINS

CMP

(C0H)

EC3DP *

EC2DP *

EC1DP *

EC0DP *

C3RO

C2RO

C1RO

C0RO

SU00517C

Figure 22. Analog Comparators

AMOD1 ADCON.4 – A/D mode select bit 1

AMOD0 ADCON.3 – A/D mode select bit 0

ASCA2 ADCON.2 – A/D channel address bit 2

ASCA1 ADCON.1 – A/D channel address bit 1

ASCA0 ADCON.0 – A/D channel address bit 0

INTERNAL RESET

Internal resets (see Figure 1) generated by the power on, low

voltage, software (SRST), watchdog and oscillator fail detect circuits

are self timed to guarantee proper initialization of the 8XC576. Reset

will be held approximately 24 oscillator periods after normal

conditions are detected by all enabled detect circuits. Internal resets

do not drive RST but will cause missing pulses on ALE.

AMOD1 AMOD0

0

Single Conversion Mode – channel selected by bits

ASCA2..0 in ADCON is converted, the result placed

in the associated result registers; ADF is set on

completion.

Analog to Digital Converter

The 8XC576 has a 6 channel10 bit successive approximation A/D

converter with separate result registers for each channel. Operating

modes are provided for single or multiple channel conversions and

multiple conversions of a single channel without software

intervention. The ADC can also be operated in 8 bit mode with faster

conversion times. Registers ADC0H–ADC5H contain the MSBs and

ADC0L–ADC5L bits 6 and 7 contain the 2 LSBs of the conversion

result for each channel. The ADCS register determines which

channels are converted in multiple channel modes. If the ADCS bit

corresponding to a channel is set, that channel is converted, else if

the bit is clear the channel is skipped.

0

1

Mulitple Channel Scan Mode – all channels selected

in the ADCS register are converted starting with the

channel addressed by bits ASCA2..0 in ADON,

conversion results are placed in the corresponding

result registers for each channel. ADF is set when

the last conversion is completed.

1

0

1

Single Channel Multiple Conversion – channel

selected by bits ASCA2..0 in ADCON is converted 6

times and all 6 results are saved in ADC0H–ADC5H

and ADC0L–ADC5L, ADF is set when all

conversions are complete.

A/D Channel Select (ADCS) Register (Reset Value = 00H)

ADCS5 ADCS.5 – A/D channel 5 select bit

ADCS4 ADCS.4 – A/D channel 4 select bit

ADCS3 ADCS.3 – A/D channel 3 select bit

ADCS2 ADCS.2 – A/D channel 2 select bit

ADCS1 ADCS.1 – A/D channel 1 select bit

ADCS0 ADCS.0 – A/D channel 0 select bit

Multiple Channel Continuous – same as Multiple

Channel Scan mode but repeats as long as

ADCE=1, ADF is set when all channels have been

converted once. Hardware will prevent the ADC

from wiriting to the result registers while they are

being read.

A/D Control (ADCON) Register (Reset Value = 00H)

ADF

ADCON.7 – A/D conversion complete flag

Flag ADF is set upon completion of a conversion, if the ADC

interrupt enable bit EAD is set, the program will vector to the ADC

interrupt location when ADF is set.

ADCE ADCON.6 – A/D conversion enable

AD8M ADCON.5 – A/D 8-bit mode

24

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

Pulse Width Modulator Control Register Bit Definitions

(PWCON = BCH)

PWMs

The pulse width modulator system of the 8XC576 contains two

PWM output channels. These channels generate pulses of

programmable length and interval. The prescaler and counter are

common to both PWM channels.

PWMF

PWCON.3

Counter overflow flag,

must be cleared by software

Counter enable and counter/prescaler

reset when Low

EN/CLR

PWCON.2

The prescaler is loaded with the complement of the PWMP register

during counter overflow, internal reset, and when EN/CLR# = 0. The

repetition frequency is defined by the 8-bit prescaler which clocks

the counter. The prescaler division factor = PWMP+1. Reading the

PWMP gives the current reload value. The actual count of the

prescaler cannot be read.

PWE1

PWE0

PWCON.1

PWCON.0

PWM1 output to P2.7 pin enable

PWM0 output to P2.6 pin enable

Auxiliary Register Bit Definitions (AUXR =8EH)

RST AUXR.3 Software reset bit

TXI AUXR.2 SIO TxD invert

LO AUXR.1 Low Speed, reduces internal clock drive

AO AUXR.0 ALE Off, when set turns off ALE

The 8-bit counter counts from 0–254 inclusive. The value of the

counter is compared to the contents of the compare registers PWM0

and PWM1. When the counter compares to the compare register,

that register’s output goes LOW. When the counter reaches zero the

output is set HIGH unless PWMn = 00H. The duty cycle of each

channel is defined by the contents of its compare register and is in

the range of 0 to 1, programmed in increments of 1/255.

Interrupt Enable 0 (IE0) Register

EA

EC

ET2 IE0.5

ES IE0.4

ET1 IE0.3

EX1 IE0.2

ET0 IE0.1

EX0 IE0.0

IE0.7

IE0.6

Enable all interrupts

Enable PCA interrupt

Enable Timer 2 interrupt

Enable Serial I/O interrupt

Enable Timer 1 interrupt

Enable External interrupt 1

Enable Timer 0 interrupt

Enable External interrupt 0

The outputs can be set continuously low by loading PWMn with 00H

and continuously high by loading with FFH.

The PWM counter is enabled with bit EN/CLR# of the PWCON

register. Output to the port pin is separately enabled by setting the

PWEn bits in the PWCON register. The counter remains active if

EN/CLR# is set even if both PWEn bits are reset. The PWM function

is reset by a chip reset. In idle mode, the PWM will function as

configured by PWCON. In power-down the state of the PWM will

freeze when the internal clock stops. If the chip is awakened with an

external interrupt, the PWM will continue to function from its state

when power-down was entered. The EN/CLR# bit of PWCON will

clear the counter and load the contents of the PWMP into the

prescaler when set LOW. If PWEn is set at this time the output will

go HIGH unless PWMn is 00H.

Interrupt Enable 1 (IE1) Register

EOB IE1.7

EIB IE1.6

Enable OBE interrupt

Enable IBF interrupt

EAD IE1.5

EC4 IE1.4

EC3 IE1.3

EC2 IE1.2

EC1 IE1.1

EC0 IE1.0

Enable ADC interrupt

Enable PCA module 4 interrupt

Enable PCA module 3 interrupt

Enable PCA module 2 interrupt

Enable PCA module 1 interrupt

Enable PCA module 0 interrupt

Interrupt Priority 0 (IP0) Register

IP0.7

PPC IP0.6

PT2 IP0.5

(reserved)

PCA interrupt priority

Timer 2 interrupt priority

Serial I/O interrupt priority

Timer 1 interrupt priority

External interrupt 1 priority

Timer 0 interrupt priority

External interrupt 0 priority

The repetition frequency is given by:

f_OSC

PS

IP0.4

PT1 IP0.3

PX1 IP0.2

PT0 IP0.1

PX0 IP0.0

f_PWM

+

(510 (1 ) PWMP))

An oscillator frequency of 12MHz results in a repetition range of

92Hz to 23.5KHz.

Interrupt Priority 1 (IP1) Register

The high/low ratio of PWMn is PWMn/(255–PWMn) for PWMn

values except 255. A PWMn value of 255 results in a high PWMn

output.

POB IP1.7

PIB IP1.6

OBE interrupt priority

IBF interrupt priority

PAD IP1.5

PC4 IP1.4

PC3 IP1.3

PC2 IP1.2

PC1 IP1.1

PC0 IP1.0

ADC interrupt priority

In order for the PWMn output to be used as a standard I/O pin,

PWMn must be reset. The PWM counter can still be used as an

internal timer by setting EN/CLR#.

PCA module 4 interrupt priority

PCA module 3 interrupt priority

PCA module 2 interrupt priority

PCA module 1 interrupt priority

PCA module 0 interrupt priority

25

1998 Jun 04

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

83C576/87C576

1/2

f

OSC

INTERNAL

BUS

8-BIT

UP

COUNTER

PWMP

REG

8-BIT

PRESCALER

8-BIT

DETECT

OUTPUT

BUFFER

P2.6

PWM0

PWM1

8-BIT

DETECT

OUTPUT

BUFFER

P2.7

SU00256A

Figure 23. Block Diagram of PWMs

PCA Interrupt System

from the host CPU bus, which qualifies RD and WR (these pins

have no effect when CS=1). The A0 pin is an address input from the

host CPU which selects either the port 0 output buffer or the UCS

register to be output during a read operation. During a write

operation, the value of the A0 pin is latched in the AF flag in the

UCS register. The following is a summary of the UPI data control

inputs: