P83C654IFA/XXX [NXP]
IC 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQCC44, PLASTIC, LCC-44, Microcontroller;
| 型号： | P83C654IFA/XXX |
| 厂家： | 
NXP |
| 描述： | IC 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQCC44, PLASTIC, LCC-44, Microcontroller 微控制器 |
| 文件： | 总24页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
83C654
CMOS single-chip 8-bit microcontroller
Product specification
1998 Jan 06
Supersedes data of 1996 Aug 15
IC20 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
8XC654 can be expanded using standard
TTL compatible memories and logic.
DESCRIPTION
FEATURES
• 80C51 central processing unit
The P83C654 Single-Chip 8-Bit
Microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
83C654 has the same instruction set as the
80C51. Two versions of the derivative exist:
The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte and 17
three-byte. With a 16(24)MHz crystal, 58% of
the instructions are executed in 0.75(0.5)µs
and 40% in 1.5(1)µs. Multiply and divide
instructions require 3(2)µs.
• 16k × 8 ROM expandable externally to
64k bytes
• 256 × 8 RAM, expandable externally to
64k bytes
83C654 — 16k bytes mask programmable
ROM
• Two standard 16-bit timer/counters
• Four 8-bit I/O ports
87C654 — EPROM version (described in a
separate data sheet)
2
• I C-bus serial I/O port with byte oriented
master and slave functions
This device provides architectural
• Full-duplex UART facilities
• Power control modes
– Idle mode
enhancements that make it applicable in a
variety of applications for general control
systems. The 83C654 contains a non-volatile
16k × 8 read-only program memory, a volatile
256 × 8 read/write data memory, four 8-bit I/O
ports, two 16-bit timer/event counters
(identical to the timers of the 80C51), a
multi-source, two-priority-level, nested
– Power-down mode
• ROM code protection
• Extended frequency range: 3.5 to 24 MHz
• Three operating ambient temperature
ranges:
2
interrupt structure, an I C interface, UART
and on-chip oscillator and timing circuits. For
systems that require extra capability, the
0 to +70°C
–40 to +85°C
–40 to +125°C
BLOCK DIAGRAM
FREQUENCY
REFERENCE
COUNTERS
XTAL2
XTAL1
T0
T1
OSCILLATOR
AND
TIMING
PROGRAM
MEMORY
(16K x 8 ROM)
DATA
TWO 16-BIT
TIMER/EVENT
COUNTERS
MEMORY
(256 x 8 RAM)
SDA
SHARED
2
I C SERIAL I/O
CPU
WITH
PORT 1
SCL
INTERNAL
INTERRUPTS
64K BYTE BUS
EXPANSION
CONTRTOL
PROG SERIAL PORT
FULL DUPLEX UART
SYNCHRONOUS SHIFT
PROGRAMMABLE I/O
INT0
INT1
SERIAL IN
SERIAL OUT
CONTROL
PARALLEL PORTS,
ADDRESS/DATA BUS
AND I/O PINS
SHARED WITH
PORT 3
EXTERNAL
INTERRUPTS
2
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
LOGIC SYMBOL
V
V
DD SS
RST
XTAL1
XTAL2
EA
PSEN
ALE
SCL
SDA
RxD
TxD
INT0
INT1
T0
T1
WR
RD
PIN CONFIGURATIONS
Plastic dual in-line package
Plastic shrink dual in-line package
42
41
V
DD
1
2
3
P1.0
P1.1
40
V
DD
P1.0
P1.1
P1.2
1
2
3
P0.0/AD0
39 P0.0/AD0
38 P0.1/AD1
P1.2
40 P0.1/AD1
39
P1.3
P1.4
4
5
P0.2/AD2
38 P0.3/AD3
37
P0.4/AD4
37
P1.3
P1.4
4
5
P0.2/AD2
36 P0.3/AD3
35
P0.4/AD4
P1.5
SCL/P1.6
SDA/P1.7
RST
6
7
8
9
P1.5
SCL/P1.6
SDA/P1.7
RST
6
7
8
9
36 P0.5/AD5
35 P0.6/AD6
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
31 EA
34
33
P0.7/AD7
EA
SHRINK
DUAL
IN-LINE
PLASTIC
DUAL
IN-LINE
RxD/P3.0 10
RxD/P3.0 10
TxD/P3.1 11
INT0/P3.2 12
32
31
30
29
28
11
12
13
NC*
TxD/P3.1
INT0/P3.2
NC*
ALE
30 ALE
PACKAGE
PACKAGE
29 PSEN
PSEN
13
28
INT1/P3.3
P2.7/A15
INT1/P3.3 14
T0/P3.4 15
P2.7/A15
P2.6/A14
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
XTAL1 19
T1/P3.5
WR/P3.6
RD/P3.7
16
17
18
27 P2.5/A13
26
P2.4/A12
24
P2.3/A11
23 P2.2/A10
22
25
P2.3/A11
24
P2.1/A9
21 P2.0/A8
XTAL2 19
P2.2/A10
23 P2.1/A9
V
20
XTAL1
20
21
SS
22
V
P2.0/A8
SS
SU00933
SU00934
*
Do not connect.
3
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
Plastic leaded chip carrier
6
5
4
3
2
1
44 43 42 41 40
P1.5
7
8
39 P0.4/AD4
38 P0.5/AD5
P1.6/SCL
P1.7/SDA
9
37 P0.6/AD6
36 P0.7/AD7
35 EA
RST 10
P3.0/RxD 11
NC* 12
PLASTIC LEADED CHIP CARRIER
34 NC*
P3.1/TxD 13
33 ALE
P3.2/INT0 14
P3.3/INT1 15
32 PSEN
31 P2.7/A15
P3.4/T0 16
P3.5/T1 17
30 P2.6/A14
29 P2.5/A13
18 19 20 21 22 23 24 25 26 27 28
SU00929
* Do not connect.
Plastic quad flat pack
44 43 42 41 40 39 38 37 36 35 34
P1.5
1
2
33 P0.4/AD4
32 P0.5/AD5
P1.6/SCL
P1.7/SDA
RST
3
4
5
6
7
31 P0.6/AD6
30 P0.7/AD7
P3.0/RxD
29 EA/V
PP
QUAD FLAT PACK
V
28
V
SS2
SS4
P3.1/TxD
27 ALE
P3.2/INT0
P3.3/INT1
8
9
26 PSEN
25 P2.7/A15
P3.4/T0 10
P3.5/T1 11
24 P2.6/A14
23 P2.5/A13
12 13 14 15 16 17 18 19 20 21 22
SU00935
* Do not connect.
(QFP only): Due to EMC improvements, all V pins (6, 16, 28, 39) must be connected to V on the 80C652/83C654.
SS
SS
4
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
ORDERING INFORMATION
PHILIPS PART ORDER NUMBER
PART MARKING
PHILIPS NORTH AMERICA
PART ORDER NUMBER
DRAWING
NUMBER
TEMPERATURE RANGE (°C)
FREQ
MHz
2,3
AND PACKAGE
1
1
3
ROMless
ROM
ROMless
ROM
EPROM
P80C652EBP P83C654EBP/xxx P80C652EBPN P83C654EBPN S87C654-4N40 SOT129-1
P80C652EBA P83C654EBA/xxx P80C652EBAA P83C654EBAA S87C654-4A44 SOT187-2
P80C652EBB P83C654EBB/xxx P80C652EBBB P83C654EBBB S87C654-4B44 SOT307-2
0 to +70,
Plastic Dual In-line Package
16
16
16
16
16
16
16
16
16
16
20
20
20
20
24
24
24
24
24
24
0 to +70,
Plastic Leaded Chip Carrier
0 to +70,
Plastic Quad Flat Pack
P83C654EBR/xxx
SOT270-1
0 to +70,
Plastic Shrink Dual In-Line Package
P80C652EFP P83C654EFP/xxx P80C652EFPN P83C654EFPN S87C654-5N40 SOT129-1
P80C652EFA P83C654EFA/xxx P80C652EFAA P83C654EFAA S87C654-5A44 SOT187-2
P80C652EFB P83C654EFB/xxx P80C652EFBB P83C654EFBB S87C654-5B44 SOT307-2
–40 to +85,
Plastic Dual In-line Package
–40 to +85,
Plastic Leaded Chip Carrier
–40 to +85,
Plastic Quad Flat Pack
P80C652EHP P83C654EHP/xxx P80C652EHPN P83C654EHPN
P80C652EHA P83C654EHA/xxx P80C652EHAA P83C654EHAA
P80C652EHB P83C654EHB/xxx P80C652EHBB P83C654EHBB
SOT129-1
SOT187-2
–40 to +125,
Plastic Dual In-line Package
–40 to +125,
Plastic Leaded Chip Carrier
SOT307-2
–40 to +125,
Plastic Quad Flat Pack
S87C654-7N40 SOT129-1
S87C654-7A44 SOT187-2
S87C654-8N40 SOT129-1
S87C654-8A44 SOT187-2
SOT129-1
0 to +70,
Plastic Dual In-line Package
0 to +70,
Plastic Leaded Chip Carrier
–40 to +85,
Plastic Dual In-line Package
–40 to +85,
Plastic Leaded Chip Carrier
P80C652IBP
P80C652IBA
P80C652IBB
P80C652IFP
P83C654IBP/xxx
P83C654IBA/xxx
P83C654IBB/xxx
P83C654IFP/xxx
P83C654IFA/xxx
P83C654IFB/xxx
P80C652IBPN
P80C652IBAA
P80C652IBBB
P80C652IFPN
P80C652IFAA
P80C652IFBB
P83C654IBPN
P83C654IBAA
P83C654IBBB
P83C654IFPN
P83C654IFAA
P83C654IFBB
0 to +70,
Plastic Dual In-line Package
SOT187-2
0 to +70,
Plastic Leaded Chip Carrier
SOT307-2
0 to +70,
Plastic Quad Flat Pack
SOT129-1
–40 to +85,
Plastic Dual In-line Package
P80C652IFA
P80C652IFB
NOTES:
SOT187-2
–40 to +85,
Plastic Leaded Chip Carrier
SOT307-2
–40 to +85,
Plastic Quad Flat Pack
1. For full specification, see the 80C652/83C652 data sheet.
2. 83C654 frequency range is 3.5MHz–16MHz or 3.5MHz–24MHz.
3. For specification of the EPROM version, see the 87C654 data sheet.
4. xxx denotes the ROM code number.
5
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC DIP
PLCC
QFP
TYPE NAME AND FUNCTION
V
SS
20
22
6, 16,
28, 39
I
Ground: 0V reference. With the QFP package all V pins (V
connected.
to V
) must be
SS4
SS
SS1
V
DD
40
44
38
I
Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
P0.0–0.7
39–32 43–36 37–30
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and data memory. In this
application, it uses strong internal pull-ups when emitting 1s.
P1.0–P1.7
1–8
2–9
40–44,
1–3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7
which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups. (See DC Electrical Characteristics: I ).
IL
Alternate functions include:
2
P1.6
P1.7
7
8
8
9
2
3
I/O
I/O
SCL: I C-bus serial port clock line.
2
SDA: I C-bus serial port data line.
P2.0–P2.7
21–28 24–31 18–25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I ). Port 2 emits the high-order address byte
IL
during fetches from external program memory and during accesses to external data memory
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit
addresses (MOV @Ri), port 2 emits the contents of the P2 special function register.
P3.0–P3.7
10–17
11,
5,
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low will source current because of the pull-ups.
13–19 7–13
(See DC Electrical Characteristics: I ). Port 3 also serves the special features of the 80C51
IL
family, as listed below:
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
I
O
I
I
I
I
O
O
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
9
10
11
12
13
RST
ALE
9
10
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V permits a power-on reset using only an external
SS
capacitor to V
.
DD
30
33
27
I/O
Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency. Note that one ALE pulse is skipped during each access to external data
memory.
PSEN
29
31
32
35
26
29
O
Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It is
activated twice each machine cycle during fetches from the external program memory. When
executing out of external program memory two activations of PSEN are skipped during each
access to external data memory. PSEN is not activated (remains HIGH) during no fetches
from external program memory. PSEN can sink/source 8 LSTTL inputs and can drive CMOS
inputs without external pull–ups.
EA
I
External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out
of the internal program memory ROM provided the Program Counter is less than 16384. If
during a RESET, EA is held a TTL LOW level, the CPU executes out of external program
memory. EA is not allowed to float.
XTAL1
19
18
21
20
15
14
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2
O
Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V + 0.5V or V – 0.5V, respectively.
DD
SS
6
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
Table 1.
8XC652/654 Special Function Registers
DIRECT
ADDRESS MSB
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
RESET
VALUE
SYMBOL
DESCRIPTION
LSB
E0
ACC*
B*
Accumulator
B register
E0H
F0H
E7
F7
E6
F6
E5
F5
E4
F4
E3
F3
E2
F2
E1
F1
00H
F0
00H
DPTR:
Data pointer
(2 bytes)
DPH
DPL
Data pointer high
Data pointer low
83H
82H
00H
00H
AF
EA
AE
BE
AD
ES1
BD
AC
ES0
BC
AB
ET1
BB
AA
EX1
BA
A9
ET0
B9
A8
EX0
B8
IE*#
IP*#
P0*
Interrupt enable
Interrupt priority
Port 0
A8H
B8H
80H
90H
A0H
0x000000B
xx000000B
FFH
BF
–
PS1
85
PS0
84
PT1
83
PX1
82
PT0
81
PX0
80
87
86
AD6
96
AD7
97
AD5
95
AD4
94
AD3
93
AD2
92
AD1
91
AD0
90
P1*#
P2*
Port 1
SDA
A7
SCL
A6
FFH
A5
A13
B5
A4
A12
B4
A3
A11
B3
A2
A10
B2
A1
A9
A0
A8
Port 2
A15
B7
A14
B6
FFH
B1
B0
P3*
Port 3
B0H
87H
RD
SMOD
9F
WR
–
T1
T0
INT1
GF1
9B
INT0
GF0
9A
TXD
PD
99
RXD
IDL
98
FFH
PCON#
Power control
–
–
0xxx0000B
9E
9D
SM2
9C
REN
S0CON*# Serial 0 port control
98H
99H
SM0
SM1
TB8
RB8
TI
RI
00H
S0BUF#
Serial 0 data buffer
xxxxxxxxB
D7
CY
D6
AC
D5
F0
D4
D3
D2
D1
F1
D0
P
PSW*
S1DAT#
SP
Program status word
Serial 1 data
D0H
DAH
81H
RS1
RS0
OV
00H
00H
07H
00H
Stack pointer
S1ADR#
Serial 1 address
DBH
GC
SLAVE ADDRESS
S1STA#
Serial 1 status
D9H
D8H
SC4
DF
SC3
DE
SC2
DD
SC1
DC
SC0
0
0
0
F8H
DB
SI
DA
AA
8A
IT1
D9
D8
S1CON*# Serial 1 control
CR2
8F
ENS1
8E
STA
8D
STO
8C
CR1
89
CR0
88
00000000B
8B
IE1
TCON*
TH1
Timer control
Timer high 1
Timer high 0
Timer low 1
Timer low 0
Timer mode
88H
8DH
8CH
8BH
8AH
89H
TF1
TR1
TF0
TR0
IE0
IT0
00H
00H
00H
00H
00H
00H
TH0
TL1
TL0
TMOD
GATE
C/T
M1
M0
GATE
C/T
M1
M0
*
#
SFRs are bit addressable.
SFRs are modified from or added to the 80C51 SFRs.
7
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.
ROM CODE PROTECTION
(83C654)
The 83C654 has an additional security
feature. ROM code protection may be
selected by setting a mask–programmable
security bit (i.e., user dependent). This
feature may be requested during ROM code
submission. When selected, the ROM code
is protected and cannot be read out at any
time by any test mode or by any instruction in
the external program memory space.
Power-Down Mode
In the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. A hardware reset is the only way
to terminate the power-down mode. The
control bits for the reduced power modes are
in the special function register PCON. Table 2
shows the state of the I/O ports during low
current operating modes.
Reset
A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To insure a good power-on reset, the
RST pin must be high long enough to allow
the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At
The MOVC instructions are the only
instructions that have access to program
code in the internal or external program
memory. The EA input is latched during
RESET and is “don’t care” after RESET
(also if the security bit is not set). This
implementation prevents reading internal
program code by switching from external
program memory to internal program memory
during a MOVC instruction or any other
instruction that uses immediate data.
power-on, the voltage on V and RST must
DD
2
I C SERIAL COMMUNICATION —
come up at the same time for a proper
start-up.
SIO1
2
2
The I C serial port is identical to the I C
serial port on the 8XC552. The operation of
this subsystem is described in detail in the
8XC552 section of this manual.
Idle Mode
In the idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
OSCILLATOR
CHARACTERISTICS
XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol,
page 3.
Note that in both the 8XC652/4 and the
2
8XC552 the I C pins are alternate functions
to port pins P1.6 and P1.7. Because of this,
P1.6 and P1.7 on these parts do not have a
pull-up structure as found on the 80C51.
Therefore P1.6 and P1.7 have open drain
outputs on the 8XC652/4.
Table 2.
External Pin Status During Idle and Power-Down Mode
PROGRAM
MEMORY
MODE
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
Idle
Internal
1
1
0
0
1
1
0
0
Data
Float
Data
Float
Data
Data
Data
Data
Data
Address
Data
Data
Data
Data
Data
Idle
External
Internal
Power-down
Power-down
External
Data
Serial Control Register (S1CON) – See Table 3
CR2 ENS1 STA STO
SI
AA
CR1 CR0
S1CON (D8H)
Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.
Table 3.
Serial Clock Rates
BIT FREQUENCY (kHz) AT fOSC
6MHz
12MHz
16MHz
24MHz
f
DIVIDED BY
CR2
CR1
CR0
OSC
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
23
27
31.25
37
6.25
50
100
47
54
62.5
75
12.5
100
200
62.5
71
83.3
100
17
94
107
125
150
25
200
400
256
224
192
160
960
120
60
1
1
1
1
1
133
1
1
1
267
0.24 < 62.5
0 to 255
0.49 < 62.5
0 to 254
0.65 < 55.6
0 to 253
0.98 < 50.0
0 to 251
96 × (256 – (reload value Timer 1))
reload value range Timer 1 (in mode 2)
NOTES:
2
2
1. These frequencies exceed the upper limit of 100kHz of the I C-bus specification and cannot be used in an I C-bus application.
8
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
–65 to +150
–0.5 to + 6.0
±5
UNIT
°C
Storage temperature range
Voltage on any other pin to V
V
SS
Input, output current on any single pin
mA
W
Power dissipation
1
(based on package heat transfer limitations, not device power consumption)
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise
SS
noted.
DEVICE SPECIFICATIONS
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
TYPE
TEMPERATURE RANGE (°C)
MIN.
4.5
4.5
4.5
4.5
4.5
MAX.
5.5
MIN.
3.5
3.5
3.5
3.5
3.5
MAX.
P83C654EBx
P83C654EFx
P83C654FHx
P83C654IBx
P83C654IFx
16
16
16
24
24
0 to +70
–40 to +85
–40 to +125
0 to +70
5.5
5.5
5.5
5.5
–40 to +85
9
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
DC ELECTRICAL CHARACTERISTICS
V
SS
= 0V, V = 5V ± 10%
DD
TEST
LIMITS
SYMBOL
PARAMETER
Input low voltage,
except EA, P1.6/SCL, P1.7/SDA
PART TYPE
CONDITIONS
MIN.
MAX.
0.2V –0.1
UNIT
0 to +70°C
–40 to +85°C
–40 to +125°C
–0.5
–0.5
–0.5
V
V
V
V
IL
DD
0.2V –0.15
DD
0.2V –0.25
DD
0 to +70°C
–40 to +85°C
–40 to +125°C
–0.5
–0.5
–0.5
0.2V –0.3
V
V
V
V
IL1
Input low voltage to EA
DD
0.2V –0.35
DD
0.2V –0.45
DD
6
V
V
Input low voltage to P1.6/SCL, P1.7/SDA
–0.5
0.3V
V
IL2
DD
0 to +70°C
–40 to +85°C
–40 to +125°C
0.2V +0.9
V
DD
V
DD
V
DD
+0.5
+0.5
+0.5
V
V
V
Input high voltage, except XTAL1, RST,
P1.6/SCL, P1.7/SDA
DD
IH
0.2V +1.0
DD
0.2V +1.0
DD
0 to +70°C
–40 to +85°C
–40 to +125°C
0.7V
V
DD
V
DD
V
DD
+0.5
+0.5
+0.5
V
V
V
V
IH1
Input high voltage, XTAL1, RST
DD
0.7V +0.1
DD
0.7V +0.1
DD
6
V
V
Input high voltage, P1.6/SCL, P1.7/SDA
0.7V
6.0
V
V
IH2
DD
8, 9
Output low voltage, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA
I
I
= 1.6mA
0.45
OL
OL
8, 9
V
OL1
V
OL2
V
OH
Output low voltage, port 0, ALE, PSEN
Output low voltage, P1.6/SCL, P1.7/SDA
= 3.2mA
0.45
0.4
V
V
OL
I
= 3.0mA
OL
10
I
I
I
= –60µA
= –25µA
= –10µA
2.4
V
V
V
Output high voltage, ports 1, 2, 3, ALE, PSEN
OH
OH
OH
0.75V
DD
DD
0.9V
I
I
I
= –800µA
= –300µA
= –80µA
2.4
V
V
V
V
OH1
Output high voltage; port 0 in external bus mode
OH
0.75V
OH
DD
DD
0.9V
OH
0 to +70°C
–40 to +85°C
–40 to +125°C
V
IN
= 0.45V
–50
–75
–75
µA
µA
µA
I
IL
Logical 0 input current, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA
0 to +70°C
–40 to +85°C
–40 to +125°C
See note 7
–650
–750
–750
µA
µA
µA
I
TL
Logical 1-to-0 transition current, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA
I
I
Input leakage current, port 0, EA
0.45V < V < V
DD
±10
±10
µA
L1
I
0V < V < 6.0V
µA
µA
Input leakage current, P1.6/SCL, P1.7/SDA
I
L2
0V < V < 6.0V
DD
I
Power supply current:
See note 1
DD
2, 11
Active mode @ 16MHz
Active mode @ 24MHz
Idle mode @ 16MHz
Idle mode @ 24MHz
Power down mode
Power down mode
V
DD
V
DD
=5.5V
=5.5V
28.0
35.0
6
7
50
mA
mA
mA
mA
µA
2, 11
3, 11
3, 11
4, 5
4, 5
–40 to +125°C
100
µA
R
C
Internal reset pull-down resistor
Pin capacitance
50
150
10
kΩ
RST
IO
Freq.=1MHz
pF
NOTES:
1. See Figures 9 through 11 for I test conditions.
DD
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 5ns;
r
f
V
IL
= V + 0.5V; V = V –0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = V . See Figure 9.
SS IH DD DD
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 5ns; V = V + 0.5V;
r
f
IL
SS
V
IH
= V –0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V ; EA = RST = V . See Figure 10.
DD DD SS
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V
;
DD
EA = RST = V . See Figure 11.
SS
5. 2V ≤ V ≤ V max.
PD
DD
2
6. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I C specification, so an input voltage below 0.3V will be recognized as a
DD
logic 0 while an input voltage above 0.7V will be recognized as a logic 1.
DD
10
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
7. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V is approximately 2V.
IN
8. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due
OL
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
9. Under steady state (non-transient) conditions, I must be externally limited as follows: Maximum I = 10mA per port pin; Maximum
OL
OL
I
OL
= 26mA total for Port 0; Maximum I = 15mA total for Ports 1, 2, and 3; Maximum I = 71mA total for all output pins. If I exceeds the
OL OL OL
test conditions, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
OL
10.Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9V specification when the
OH
DD
address bits are stabilizing.
11. I
for other frequencies can be derived from Figure 1, where FREQ is the external oscillator frequency in MHz. I
is given in mA.
DDMAX
DDMAX
50
40
I
I
DD
(mA)
DD
(mA)
40
30
(1)
30
20
10
0
(1)
20
10
(2)
(2)
0
0
4
8
12
16
0
8
12
16
4
24
f
(MHz)
XTAL1
f
(MHz)
XTAL1
(1) MAXIMUM OPERATING MODE: V
DD
= V
DDmax
(1) MAXIMUM OPERATING MODE: V
= V
DD
DDmax
(2) MAXIMUM IDLE MODE: V
= V
DD
DDmax
(2) MAXIMUM IDLE MODE: V
= V
DD
DDmax
These values are valid within the specified
frequency range.
These values are valid within the specified
frequency range.
Figure 1.
I
vs. Frequency
DD
11
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
1, 2
AC ELECTRICAL CHARACTERISTICS
(16 MHz type)
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
1/t
FIGURE
PARAMETER
Oscillator frequency
MIN
MAX
MIN
MAX
UNIT
MHz
ns
2
2
2
2
2
2
2
2
2
2
2
2
3.5
16
CLCL
t
t
t
t
t
t
t
t
t
t
t
ALE pulse width
85
8
2t
–40
LHLL
CLCL
Address valid to ALE low
t
t
–55
ns
AVLL
LLAX
LLIV
CLCL
CLCL
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
28
–35
ns
150
83
4t
3t
–100
ns
CLCL
23
t
–40
ns
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
PSEN pulse width
143
3t
–45
ns
CLCL
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–105
ns
CLCL
0
0
ns
38
208
10
t
–25
ns
CLCL
5t
–105
ns
CLCL
10
ns
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
RD pulse width
275
275
6t
–100
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
DW
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
148
5t
–165
CLCL
0
0
Data float after RD
55
2t
–70
CLCL
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data setup time before WR
Data hold after WR
350
398
238
8t
–150
–165
CLCL
CLCL
9t
138
120
3
3t
–50
3t
+50
CLCL
CLCL
4t
t
–130
–60
CLCL
CLCL
CLCL
CLCL
288
13
7t
t
–150
–50
WHQX
RLAZ
WHLH
RD low to address float
RD or WR high to ALE high
0
0
23
103
t
–40
t
+40
CLCL
CLCL
Shift Register
3
t
t
t
t
t
5
5
5
5
5
Serial port clock cycle time
0.75
492
80
12t
µs
ns
ns
ns
ns
XLXL
CLCL
3
Output data setup to clock rising edge
10t
–133
QVXH
XHQX
XHDX
XHDV
CLCL
3
Output data hold after clock rising edge
2t
CLCL
–117
3
Input data hold after clock rising edge
0
0
3
Clock rising edge to input data valid
492
10t
–133
CLCL
External Clock
3
t
t
t
t
6
6
6
6
High time
20
20
20
20
t
t
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
CLCL – CLCX
3
Low time
t
t
CLCL – CHCX
3
Rise time
20
20
20
3
Fall time
20
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.
12
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
1, 2
AC ELECTRICAL CHARACTERISTICS
(24 MHz type)
24MHz CLOCK
VARIABLE CLOCK
SYMBOL
1/t
FIGURE
PARAMETER
Oscillator frequency
MIN
MAX
MIN
MAX
UNIT
MHz
ns
2
2
2
2
2
2
2
2
2
2
2
2
3.5
24
CLCL
t
t
t
t
t
t
t
t
t
t
t
ALE pulse width
43
17
17
2t
–40
LHLL
CLCL
Address valid to ALE low
t
t
–25
ns
AVLL
LLAX
LLIV
CLCL
CLCL
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
–25
ns
102
65
4t
3t
–65
ns
CLCL
17
80
t
–25
ns
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
PSEN pulse width
3t
–45
ns
CLCL
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–60
ns
CLCL
0
0
ns
17
128
10
t
–25
ns
CLCL
5t
–80
ns
CLCL
10
ns
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
RD pulse width
150
150
6t
–100
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
DW
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
118
5t
2t
–90
–28
CLCL
0
0
Data float after RD
55
CLCL
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data setup time before WR
Data hold after WR
180
210
175
8t
–150
–165
CLCL
CLCL
9t
75
92
3t
–50
–75
3t
CLCL
+50
CLCL
4t
CLCL
12
t
CLCL
7t
CLCL
t
CLCL
–30
162
17
–130
–25
WHQX
RLAZ
WHLH
RD low to address float
RD or WR high to ALE high
0
0
17
67
t
–25
t
+25
CLCL
CLCL
Shift Register
3
t
t
t
t
t
5
5
5
5
5
Serial port clock cycle time
0.5
283
23
0
12t
µs
ns
ns
ns
ns
XLXL
CLCL
3
Output data setup to clock rising edge
10t
2t
–133
–60
QVXH
XHQX
XHDX
XHDV
CLCL
3
Output data hold after clock rising edge
CLCL
3
Input data hold after clock rising edge
0
3
Clock rising edge to input data valid
283
10t
–133
CLCL
External Clock
3
t
t
t
t
6
6
6
6
High time
17
17
17
17
t
t
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
CLCL – CLCX
3
Low time
t
t
CLCL – CHCX
3
Rise time
5
5
5
3
Fall time
5
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.
13
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
2
AC ELECTRICAL CHARACTERISTICS – I C INTERFACE
SYMBOL
PARAMETER
INPUT
OUTPUT
SCL TIMING CHARACTERISTICS
1
t
t
t
t
t
START condition hold time
SCL LOW time
≥ 14 t
> 4.0µs
HD;STA
LOW
HIGH
RC
CLCL
CLCL
CLCL
1
≥ 16 t
≥ 14 t
> 4.7µs
1
SCL HIGH time
SCL rise time
> 4.0µs
2
≤ 1µs
–
3
SCL fall time
≤ 0.3µs
< 0.3µs
FC
SDA TIMING CHARACTERISTICS
t
t
t
t
t
t
t
t
t
Data set-up time
≥ 250ns
≥ 250ns
≥ 250ns
≥ 0ns
> 20 t
– t
SU;DAT1
SU;DAT2
SU;DAT3
HD;DAT
SU;STA
SU;STO
BUF
CLCL
RD
FC
1
SDA set-up time (before rep. START cond.)
SDA set-up time (before STOP cond.)
Data hold time
> 1µs
> 8 t
CLCL
> 8 t
– t
CLCL
1
Repeated START set-up time
STOP condition set-up time
Bus free time
≥ 14 t
≥ 14 t
≥ 14 t
> 4.7µs
> 4.0µs
> 4.7µs
CLCL
CLCL
CLCL
1
1
2
SDA rise time
≤ 1µs
≤ 0.3µs
–
RD
3
SDA fall time
< 0.3µs
FD
NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3 t
will be filtered out. Maximum capacitance on bus-lines SDA and
CLCL
SCL = 400pF.
4. t
= 1/f
= one oscillator clock period at pin XTAL1. For 63ns (42ns) < t
< 285ns (16MHz (24MHz) > f > 3.5MHz) the SIO1
OSC
CLCL
OSC
CLCL
2
interface meets the I C-bus specification for bit-rates up to 100 kbit/s.
2
TIMING SIO1 (I C) INTERFACE
repeated START condition
START or repeated START condition
START condition
t
SU;STA
STOP condition
t
RD
0.7 V
DD
SDA
(INPUT/OUTPUT)
0.3 V
DD
t
BUF
t
t
t
FC
FD
RC
t
SU; STO
0.7 V
DD
SCL
(INPUT/OUTPUT)
0.3 V
DD
t
SU;DAT3
t
t
t
t
SU;DAT1
t
t
SU;DAT2
HD;STA
LOW
HIGH
HD;DAT
14
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The
first character is always ‘t’ (= time). The other
characters, depending on their positions,
indicate the name of a signal or the logical
status of that signal. The designations are:
A – Address
Q – Output data
R – RD signal
t
– Time
V – Valid
W – WR signal
X – No longer a valid logic level
Z – Float
C – Clock
D – Input data
H – Logic level high
Examples: t
= Time for address valid
to ALE low.
AVLL
I
– Instruction (program memory contents)
t
= Time for ALE low
to PSEN low.
LLPL
L – Logic level low, or ALE
P – PSEN
t
LHLL
ALE
t
PLPH
t
AVLL
t
LLPL
LLIV
t
PSEN
t
PLIV
t
PLAZ
t
PXIZ
t
LLAX
t
PXIX
A0–A7
INSTR IN
A0–A7
PORT 0
PORT 2
t
AVIV
A8–A15
A8–A15
Figure 2. External Program Memory Read Cycle
ALE
PSEN
RD
t
WHLH
t
LLDV
t
t
LLWL
RLRH
t
RHDZ
t
t
t
LLAX
RLDV
AVLL
t
RHDX
t
RLAZ
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA IN
A0–A7 FROM PCL
INSTR IN
t
AVWL
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPH
A8–A15 FROM PCH
Figure 3. External Data Memory Read Cycle
15
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
ALE
t
WHLH
PSEN
t
t
WLWH
LLWL
WR
t
LLAX
t
t
WHQX
t
AVLL
QVWX
t
DW
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA OUT
A0–A7 FROM PCL
INSTR IN
t
AVWL
P2.0–P2.7 OR A8–A15 FROM DPH
A8–A15 FROM PCH
Figure 4. External Data Memory Write Cycle
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
t
XLXL
CLOCK
t
XHQX
t
QVXH
OUTPUT DATA
WRITE TO SBUF
t
t
XHDX
XHDV
SET TI
INPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
Figure 5. Shift Register Mode Timing
16
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
V
IH1
0.8V
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
Figure 6. External Clock Drive at XTAL1
V
–0.5
DD
V
V
+0.1V
LOAD
V
V
–0.1V
TIMING
REFERENCE
POINTS
OH
0.2V
0.2V
+0.9
–0.1
DD
V
LOAD
DD
–0.1V
LOAD
+0.1V
OL
0.45V
NOTE:
NOTE:
AC INPUTS DURING TESTING ARE DRIVEN AT V
FOR TIMING PURPOSES, A PORT IS NO LONGER FLOATING WHEN A 100MV
CHANGE FROM LOAD VOLTAGE OCCURS, AND BEGINS TO FLOAT WHEN A
100mV CHANGE FROM THE LOADED V
20mA.
–0.5 FOR A LOGIC ‘1’ AND
DD
0.45V FOR A LOGIC ‘0’. TIMING MEASUREMENTS ARE MADE AT V MIN FOR A
IH
/V
OH OL
LEVEL OCCURS. I /I > +
OH OL
LOGIC ‘1’ AND V MAX FOR A LOGIC ‘0’.
IL
Figure 7. AC Testing Input/Output
Figure 8. Float Waveform
17
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
V
V
DD
DD
I
I
DD
DD
V
V
DD
DD
V
V
DD
V
RST
EA
DD
DD
P0
P0
RST
EA
P1.6
P1.7
P1.6
P1.7
*
*
*
*
(NC)
XTAL2
XTAL1
(NC)
XTAL2
XTAL1
CLOCK SIGNAL
CLOCK SIGNAL
V
V
SS
SS
Figure 9.
I
Test Condition, Active Mode
Figure 10.
I
Test Condition, Idle Mode
DD
DD
All other pins are disconnected
All other pins are disconnected
V
DD
I
DD
V
DD
P0
V
RST
EA
DD
P1.6
P1.7
(NC)
XTAL2
XTAL1
*
*
V
SS
Figure 11.
I
Test Condition, Power Down Mode
DD
All other pins are disconnected. V = 2V to 5.5V
DD
NOTE:
Ports 1.6 and 1.7 should be connected to V through resistors of sufficiently high value such that the sink current into these pins does not
*
CC
exceed the I
specification.
OL1
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent
2
to use the components in the I C system provided the system conforms to the
I C specifications defined by Philips. This specification can be ordered using the
2
code 9398 393 40011.
18
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
19
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
20
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
21
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)
SOT270-1
22
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
NOTES
23
1998 Jan 06
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
83C654
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 06-98
Document order number:
9397 750 04048
Philips
Semiconductors
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