P87C51MC2 [NXP]
80C51 8-bit microcontroller family with extended memory; 80C51的8位微控制器系列具有扩展内存
| 型号： | P87C51MC2 |
| 厂家： | 
NXP |
| 描述： | 80C51 8-bit microcontroller family with extended memory |
| 文件： | 总34页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
SEE THE LAST 2 PAGES OF THIS DATA SHEET FOR A LIST OF ERRATA RELATED TO THIS PART.
P87C51MB2/P87C51MC2
80C51 8-bit microcontroller family with
extended memory
64KB/96KB OTP with 2KB/3KB RAM
Preliminary specification
2001 Apr 06
Philips
Semiconductors
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
GENERAL DESCRIPTION
The P87C51Mx2 represents the first microcontroller based on Philips Semiconductors’ new 51MX core. The P87C51MC2
features 96 Kbytes of OTP program memory and 3 Kbytes of data SRAM, while the P87C51MB2 has 64 Kbytes of OTP and 2
Kbytes of RAM. In addition, both devices are equipped with a Programmable Counter Array (PCA), a watchdog timer that can be
configured to different time ranges through SFR bits, as well as two enhanced UARTs or one enhanced UART and an SPI.
Philips Semiconductors’ 51MX (Memory eXtension) core is an accelerated 80C51 architecture that executes instructions at twice
the rate of standard 80C51 devices. The linear address range of the 51MX has been expanded to support up to 8 Mbytes of
program memory and 8Mbytes of data memory. It retains full program code compatibility to enable design engineers to re-use
80C51 development tools, eliminating the need to move to a new, unfamiliar architecture. The 51MX core also retains 80C51
bus compatibility to allow for the continued use of 80C51-interfaced peripherals and Application Specific Integrated Circuits
(ASICs).
The P87C51Mx2 provides greater functionality, increased performance and overall lower system cost. By offering an embedded
memory solution combined with the enhancements to manage the memory extension, the P87C51Mx2 eliminates the need for
software work-arounds. The increased program memory enables design engineers to develop more complex programs in a high-
level language like C, for example, without struggling to contain the program within the traditional 64 Kbytes of program memory.
These enhancements also greatly improve C Language efficiency for code size below 64 Kbytes.
The 51MX core is described in more details in the 51MX Architecture Reference.
KEY FEATURES
• Extended features of the 51MX Core:
- 23-bit program memory space and 23-bit data memory space - linear program and data address range expanded to sup-
port up to 8 Mbytes each
- Program counter expanded to 23 bits
- Stack pointer extended to 16 bits enabling stack space beyond the 80C51 limitation
- New 23-bit extended data pointer and two 24-bit universal pointers greatly improve C compiler code efficiency in using
pointers to access variables in different spaces.
• 100% binary compatibility with the classic 80C51 so that existing code is completely reusable
• Up to 24 MHz CPU clock with 6 clock cycles per machine cycle
• 96 Kbytes or 64 Kbytes of on-chip OTP
• 3 Kbytes or 2 Kbytes of on-chip RAM
• Programmable Counter Array (PCA)
• Two full-duplex enhanced UARTs
• Industry-standard Serial Peripheral Interface (SPI)
KEY BENEFITS
• Increases program/data address range to 8 Mbytes each
• Enhances performance and efficiency for C programs
• Fully 80C51-compatible microcontroller
• Provides seamless and compelling upgrade path from classic 80C51
• Preserves 80C51 code base, investment/knowledge, and peripherals & ASICs
• Supported by 80C51 development and programming tools (Keil, Nohau, BP Micro, etc.)
• The P87C51Mx2 makes it possible to develop applications at a lower cost and with a reduced time-to-market
2001 Apr 06
2
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
COMPLETE FEATURES
• Fully static
• Up to 24 MHz CPU clock with 6 clock cycles per machine cycle
• 96 Kbytes or 64 Kbytes of on-chip OTP
• 3 Kbytes or 2 Kbytes of on-chip RAM
• 23-bit program memory space and 23-bit data memory space
• Four-level interrupt priority
• 34 I/O lines (5 ports)
• Three Timers: Timer0, Timer1 and Timer2
• Two full-duplex enhanced UARTs with baud rate generator
• Framing error detection
• Automatic address recognition
• Supports industry-standard Serial Peripheral Interface (SPI) with a baud rate up to 6 Mbits/sec
• Power control modes
• Clock can be stopped and resumed
• Idle mode
• Power down mode
• Second DPTR register
• Asynchronous port reset
• Programmable Counter Array (PCA) (compatible with 8xC51Rx+) with five Capture/Compare modules
• Low EMI (inhibit ALE)
• Watchdog timer with programmable prescaler for different time ranges (compatible with 8xC66x with added prescaler)
ORDERING INFORMATION
MEMORY
OTP RAM
FREQUENCY
TEMPERATURE
RANGE AND
PACKAGE
V
VOLTAGE
RANGE
DD
PART ORDER NUMBER
DWG #
V
=
V
=
DD
DD
2.7-5.5V 4.5-5.5V
1
2
P87C51MB2BA
P87C51MC2BA
64 KB 2048 B 0 to +70°C, PLCC44 2.7-5.5V 4.5-5.5V 0-12MHz 0-24MHz SOT187-2
96 KB 3072 B 0 to +70°C, PLCC44 2.7-5.5V 4.5-5.5V 0-12MHz 0-24MHz SOT187-2
2001 Apr 06
3
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
LOGIC SYMBOL
VDD
VSS
T2
T2EX
ECI
CEX0
CEX1
CEX2
CEX3
CEX4
MOSI
SPICLK
RXD0
TXD0
INT0
INT1
T0
P87C51Mx2
T1
WR
RD
MISO
SS
RXD1
TXD1
RST
EA/Vpp
XTAL2
XTAL1
PSEN
ALE/PROG
2001 Apr 06
4
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
PIN CONFIGURATION
Pin Function
Pin Function
1
1
1
(NC/VSS
)
23
(NC/VDD
)
2
3
4
5
6
7
8
9
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3/CEX0
P1.4/CEX1/MOSI
P1.5/CEX2/SPICLK
P1.6/CEX3
P1.7/CEX4
RST
24
25
26
27
28
29
30
31
32
33
P2.0/A8/A16
P2.1/A9/A17
P2.2/A10/A18
P2.3/A11/A19
P2.4/A12/A20
P2.5/A13/A21
P2.6/A14/A22
P2.7/A15
PSEN
ALE
P4.1/TXD1/SS1
EA/Vpp
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
PLCC44
1
6
40
7
39
29
PLASTIC
LEADED
CHIP CARRIER
10
11
P3.0/RXD0
17
12
13
14
15
16
17
18
19
20
21
22
P4.0/RXD1/MISO1
P3.1/TXD0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
34
35
36
37
38
39
40
41
42
43
44
18
28
XTAL2
XTAL1
VSS
1. Pins 1, 12, 23, 34 were not internally connected in some derivatives. Please refer to section on Pin Descriptions for details.
2001 Apr 06
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Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
BLOCK DIAGRAM
High Performance
80C51 CPU
(51MX Core)
96K/64K Byte
Code EPROM
UART 0
Internal Bus
3K/2K Byte
Data RAM
Baud Rate
Generator
Port 4
Configurable I/Os
UART 1
SPI
Port 3
Configurable I/Os
Port 2
Configurable I/Os
Timer0
Timer1
Port 1
Configurable I/Os
Watchdog Timer
PCA
(Programmable
Counter Array)
Port 0
Configurable I/Os
Crystal or
Resonator
Oscillator
Timer2
2001 Apr 06
6
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
PIN DESCRIPTIONS
MNEMONIC
PIN NO.
TYPE NAME AND FUNCTION
P0.0 - P0.7
43 - 36
I/O Port 0: Port 0 is an open drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impendance inputs. Port 0 is also the multiplexed low-
order address and data bus during accesses to external program and data memory. In this
application, it uses strong internal pull-ups when emitting 1s.
P1.0 - P1.7
2 - 9
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins. Port 1 pins
that have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 1 pins that are externally pulled low will source current because of
the internal pull-ups. (Note: When SFR bit SPEN (SPCTL.6) is ’1’, the pull-ups at P1.4 and
P1.5 are disabled.)
2
3
4
5
6
I/O
I
P1.0
P1.1
P1.2
P1.3
P1.4
T2
Timer/Counter 2 external count input/Clockout
Timer/Counter 2 Reload/Capture/Direction Control
External Clock Input to the PCA
T2EX
ECI
I
I/O
I/O
CEX0
CEX1
Capture/Compare External I/O for PCA module 0
Capture/Compare External I/O for PCA module 1 (with pull-up on
pin)
I/O
MOSI
CEX2
SPI Master Out/Slave In (Selected when SFR bit SPEN (SPCTL.6)
is ’1’, in which case the pull-up for this pin is disabled)
7
I/O
I/O
P1.5
Capture/Compare External I/O for PCA module 2 (with pull-up on
pin)
SPICLK SPI Clock (Selected when SFR bit SPEN (SPCTL.6) is ’1’, in which
case the pull-up for this pin is disabled)
8
9
I/O
I/O
P1.6
P1.7
CEX3
CEX4
Capture/Compare External I/O for PCA module 3
Capture/Compare External I/O for PCA module 4
P2.0 - P2.7
24 - 31
I/O Port 2: Port 2 is a 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: IIL ). Port 2 emits the high-order
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses ( MOVX @ DPTR) or 23-bit addresses
(MOVX @EPTR, EMOV). In this application, it uses strong internal pull-ups when emitting
1s. During accesses to external data memory that use 8-bit addresses ( MOV @ Ri), port2
emits the contents of the P2 Special Function Register.
Note that when 23-bit address is used, address bits A16-A22 will be output to P2.0-P2.6
when ALE is High, and address bits A8-A14 are output to P2.0-P2.6 when ALE is Low.
Address bit A15 is output on P2.7 regardless of ALE.
P3.0 - P3.7
11,13 -19
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally pulled low will source current because of the internal
pull-ups.
11
13
14
15
16
17
18
19
I
O
I
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD0
TXD0
INT0
INT1
T0
Serial input port 0
Serial output port 0
External interrupt 0
I
External interrupt 1
I
Timer0 external input
Timer1 external input
External data memory write strobe
External data memory read strobe
I
T1
O
O
WR
RD
2001 Apr 06
7
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
MNEMONIC
PIN NO.
TYPE NAME AND FUNCTION
P4.0 - P4.1
12,34
I/O Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups on all pin. Port 4 pins
that have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 4 pins that are externally pulled low will source current because of
the internal pull-ups. (Note: When SFR bit SPEN (SPCTL.6) is ’1’, the pull-ups at these port
pins are disabled.)
12
34
I
I/O
O
I
P4.0
RXD1
MISO
TXD1
SS
Serial input port 1. (Note: This pin is a no connect pin on some
derivatives.) (with pull-up on pin)
SPI Master In/Slave Out (Selected when SFR bit SPEN (SPCTL.6)
is ’1’, in which case the pull-up for this pin is disabled)
P4.1
Serial output port 1. (Note: This pin is a no connect pin on some
derivatives.) (with pull-up on pin)
SPI Slave Select (Selected when SFR bit SPEN (SPCTL.6) is ’1’,
in which case the pull-up for this pin is disabled)
RST
ALE
10
33
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to VSS permits a power-on reset using only an external
capacitor to VDD.
O
Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency, and can be used for external timing or clocking. Note that one ALE
pulse is skipped during each access to external data memory. If SFR bit AO (AUXR.0) is
’0’, ALE is emitted at the constant rate as indicated above. With this bit set to ’1’, ALE will
be active only during a MOVX instruction.
PSEN
EA/Vpp
XTAL1
32
35
21
O
I
Program Store Enable: The read strobe to external program memory. When executing
code from the external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.
External Access Enable/Programming Supply Voltage: EA must be externally held low
to enable the device to fetch code from external program memory locations. If EA is held
high, the device executes from internal program memory. The value on the EA pin is
latched when RST is released and any subsequent changes have no effect.
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2
VSS
20
22
O
I
Crystal 2: Output from the inverting oscillator amplifier.
Ground: 0V reference.
VDD
44
I
Power Supply: This is the power supply voltage for normal operation as well as Idle and
Power Down modes.
(NC/VSS
)
1
I
No Connect/Ground: This pin is a no connect pin on some derivatives, but is internally
connected to VSS on the P87C51Mx2. If connected externally, this pin must only be
connected to the same VSS as at pin 22. (Note: Connecting the second pair of VSS and VDD
pins is not required. However, they may be connected in addition to the primary VSS and
VDD pins to improve power distribution, reduce noise in output signals, and improve
system-level EMI characteristics.)
(NC/VDD
)
23
I
No Connect/Power Supply: This pin is a no connect pin on some derivatives, but is
internally connected to VDD on the P87C51Mx2. If connected externally, this pin must only
be connected to the same VDD as at pin 44. (Note: Connecting the second pair of VSS and
VDD pins is not required. However, they may be connected in addition to the primary VSS
and VDD pins to improve power distribution, reduce noise in output signals, and improve
system-level EMI characteristics.)
2001 Apr 06
8
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
SPECIAL FUNCTION REGISTERS
Note: Special Function Register (SFR) accesses are restricted in the following ways:
1. User must NOT attempt to access any SFR locations not defined.
2. SFR bits labeled ’-’, ’0’ or ’1’ can ONLY be written and read as follows:
- ’-’ MUST be written with ’0’, but can return any value when read (even if it was written with ’0’). It is a reserved bit and may
be used in future derivatives.
- ’0’ MUST be written with ’0’, and will return a ’0’ when read.
- ’1’ MUST be written with ’1’, and will return a ’1’ when read.
Special Function Registers
BIT ADDRESS, SYMBOL, OR ALTERNATE PORT FUNCTION
DIRECT
ADDRESS
Reset
Value
SYMBOL
DESCRIPTION
MSB
LSB
E0
E7
E6
E5
E4
E3
E2
E1
ACC*
Accumulator
E0H
8EH
A2H
00H
AUXR#
AUXR1#
Auxiliary Function Register
Auxiliary Function Register 1
-
-
-
-
-
-
-
-
-
0
EXTRAM
AO
DPS
F0
00H%
00H%
LPEP
F4
GF2
F3
-
F7
F6
F5
F2
F1
B*
B Register
F0H
00H
BRGR0#§ Baud Rate Generator Rate Low
BRGR1#§ Baud Rate Generator Rate High
86H‡
87H‡
BRATE11 BRATE10 BRATE9 BRATE8 BRATE7 BRATE6 BRATE5 BRATE4
00H
BRATE3 BRATE2 BRATE1 BRATE0
-
-
-
-
00H%
BRGCON# Baud Rate Generator Control
85H‡
-
-
-
-
-
-
S0BRGS BRGEN
00H%
CCAP0H# Module 0 Capture High
CCAP1H# Module 1 Capture High
CCAP2H# Module 2 Capture High
CCAP3H# Module 3 Capture High
CCAP4H# Module 4 Capture High
CCAP0L# Module 0 Capture Low
CCAP1L# Module 1 Capture Low
CCAP2L# Module 2 Capture Low
CCAP3L# Module 3 Capture Low
CCAP4L# Module 4 Capture Low
CCAPM0# Module 0 Mode
FAH
FBH
FCH
FDH
FEH
EAH
EBH
ECH
EDH
EEH
DAH
DBH
DCH
DDH
DEH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
00H%
00H%
00H%
00H%
00H%
-
-
-
-
-
ECOM_0 CAPP_0 CAPN_0
ECOM_1 CAPP_1 CAPN_1
ECOM_2 CAPP_2 CAPN_2
ECOM_3 CAPP_3 CAPN_3
ECOM_4 CAPP_4 CAPN_4
MAT_0
MAT_1
MAT_2
MAT_3
MAT_4
TOG_0
TOG_1
TOG_2
TOG_3
TOG_4
PWM_0 ECCF_0
PWM_1 ECCF_1
PWM_2 ECCF_2
PWM_3 ECCF_3
PWM_4 ECCF_4
CCAPM1# Module 1 Mode
CCAPM2# Module 2 Mode
CCAPM3# Module 3 Mode
CCAPM4# Module 4 Mode
2001 Apr 06
9
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
Special Function Registers (Continued)
BIT ADDRESS, SYMBOL, OR ALTERNATE PORT FUNCTION
DIRECT
ADDRESS
Reset
Value
SYMBOL
DESCRIPTION
MSB
LSB
DF
CF
DE
CR
DD
-
DC
DB
DA
D9
D8
CCON#
CH#
PCA Counter Control
PCA Counter High
PCA Counter Low
PCA Counter Mode
D8H
F9H
E9H
D9H
CCF4
CCF3
CCF2
CCF1
CCF0
00H%
00H
CL#
00H
CMOD#
CIDL
WDTE
-
-
-
CPS1
CPS0
ECF
00H%
DPTR
DPH
DPL
Data Pointer (2 bytes)
Data Pointer High
Data Pointer Low
00H
00H
00H
83H
82H
EPL#
EPM#
EPH#
Extended Data Pointer Low
Extended Data Pointer Middle
Extended Data Pointer High
FCH‡
FDH‡
FEH‡
00H
00H
00H
AF
EA
AE
EC
AD
AC
AB
AA
A9
A8
IEN0*
IEN1*
Interrupt Enable 0
Interrupt Enable 1
ES0/
ES0R
A8H
E8H
ET2
ET1
EX1
ET0
EX0
00H
EF
-
EE
-
ED
-
EC
-
EB
EA
E9
E8
ES1/
ES1R
ESPI
ES1T
ES0T
00H%
BF
-
BE
BD
BC
BB
BA
B9
B8
IP0*
Interrupt Priority
PS0/
PS0R
B8H
B7H
PPC
PT2
PT1
PX1
PT0
PX0
00H
00H
IP0H
Interrupt Priority 0 High
PS0H/
PS0RH
-
PPCH
PT2H
PT1H
PX1H
PT0H
PX0H
F8
FF
-
FE
-
FD
-
FC
-
FB
FA
F9
IP1*
Interrupt Priority 1
PS1/
PS1R
F8H
PSPI
PS1T
PS0T
00H%
IP1H
Interrupt Priority 1 High
PS1H/
PS1RH
F7H
-
-
-
-
PSPIH
PS1TH
PS0TH
00H%
00H%
MXCON# MX Control Register
FFH‡
-
-
-
-
-
EAM
ESMM
EIFM
87
86
85
84
83
82
81
80
P0*
P1*
Port 0
Port 1
80H
90H
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
FFH
FFH
97
96
95
94
93
92
91
90
T2
CEX2/
SPICLK
CEX1/
MOSI
CEX4
CEX3
CEX0
ECI
T2EX
2001 Apr 06
10
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
Special Function Registers (Continued)
BIT ADDRESS, SYMBOL, OR ALTERNATE PORT FUNCTION
DIRECT
ADDRESS
Reset
Value
SYMBOL
DESCRIPTION
MSB
LSB
A7
A6
A5
A4
A3
A2
A1
A0
P2*
Port 2
AD14/
AD22
ADA13/
AD21
AD11/
AD19
AD10/
AD18
AD9/
AD17
AD8/
AD16
A0H
B0H
AD15
AD12/AD20
FFH
FFH
B7
B6
B5
T1
B4
T0
B3
B2
B1
B0
P3*
Port 3
Port 4
RD
WR
INT1
INT0
TxD0
RxD0
C7‡
-
C6‡
-
C5‡
-
C4‡
-
C3‡
-
C2‡
-
C1‡
C0‡
P4*#
RxD1/
MISO
C0H‡
87H
TxD1/SS
FFH
00H/10H&
PCON#
PSW*
Power Control Register
Program Status Word
SMOD1
D7
SMOD0
D6
-
POF
D4
GF1
D3
GF0
D2
PD
D1
F1
IDL
D0
P
D5
F0
D0H
CBH
CAH
CY
AC
RS1
RS0
OV
00H
00H
00H
RCAP2H# Timer2 Capture High
RCAP2L# Timer2 Capture Low
9F
9E
9D
9C
9B
9A
99
98
S0CON*
Serial Port 0 Control
SM0_0/
FE_0
98H
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
00H
S0BUF
Serial Port 0 Data Buffer Register
Serial Port 0 Address Register
Serial Port 0 Address Enable
99H
A9H
B9H
xxH
00H
00H
S0ADDR
S0ADEN
S0STAT# Serial Port 0 Status
DBMOD_
0
8CH‡
INTLO_0 CIDIS_0 DBISEL_0
FE_0
BR_0
OE_0
STINT_0
00H%
87‡
86‡
85‡
84‡
83‡
82‡
81‡
80‡
S1CON#* Serial Port 1 Control
SM0_1/
FE_1
80H‡
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
00H
S1BUF#
Serial Port 1 Data buffer Register
81H‡
82H‡
83H‡
XXH
00H
00H
S1ADDR# Serial Port 1 Address Register
S1ADEN# Serial Port 1 Address Enable
S1STAT# Serial Port 1 Status
DBMOD_
1
84H‡
INTLO_1 CIDIS_1 DBISEL1
FE_1
BR_1
OE_1
STINT_1
00H%
SP
Stack Pointer (or Stack Pointer
Low Byte When EDATA
Supported)
81H
08H
SPCTL#
SPCFG#
SPDAT#
SPI Control Register
SPI Configuration Register
SPI Data
E2H
E1H
E3H
SSIG
SPIF
SPEN
DORD
-
MSTR
-
CPOL
PSC3
CPHA
PSC2
-
-
00H%
00H%
00H
SPWCOL
PSC1
PSC0
SPE#
Stack Pointer High
FBH‡
00H
2001 Apr 06
11
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
Special Function Registers (Continued)
BIT ADDRESS, SYMBOL, OR ALTERNATE PORT FUNCTION
DIRECT
ADDRESS
Reset
Value
SYMBOL
DESCRIPTION
MSB
LSB
8F
8E
8D
8C
8B
8A
89
88
TCON*
Timer Control Register
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00H
CF
CE
CD
CC
CB
CA
C9
C8
T2CON#* Timer2 Control Register
C8H
C9H
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
00H
T2MOD#
Timer2 Mode Control
-
-
-
-
-
-
T2OE
DCEN
00H%
TH0
TH1
TH2
TL0
TL1
TL2
Timer 0 High
Timer 1 High
Timer 2 High
Timer 0 Low
Timer 1 Low
Timer 2 Low
8CH
8DH
CDH
8AH
8BH
CCH
00H
00H
00H
00H
00H
00H
TMOD
Timer 0 and 1 Mode
89H
A6H
8FH‡
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
FFH
WDTRST# Watchdog Timer Reset
WDCON# Watchdog Timer Control
-
-
-
-
-
WDPRE2 WDPRE1 WDPRE0
00H%
Notes:
*
SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
‡ Extended SFRs accessed by preceeding the instruction with 51MX escape (opcode A5h).
Reserved bits, must be written with 0’s.
& Power on reset is 10H. Other reset is 00H.
-
§ BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ’0’. If any of them is written if BRGEN = 1, result is
unpredictable.
% The unimplemented bits (labeled ’-’) in the SFRs are ’X’s (unknown) at all times. ’1’s should NOT be written to these bits, as
they may be used for other purposes in future derivatives. The reset values shown for these bits are ’0’s although they are
unknown when read.
2001 Apr 06
12
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
FUNCTIONAL DESCRIPTION
The following paragraphs briefly describe the features of the P87C51Mx2. For more detailed information, please refer to the
P87C51Mx2 User Manual or the 51MX Architecture Reference.
INTERRUPTS
Table 1 summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, polling priority, and whether each
interrupt may wake up the CPU from Power Down mode.
Interrupt
Flag Bit(s)
Vector
Address
Interrupt
Enable Bit(s)
Interrupt
Priority
Polling
Priority
Power Down
Wakeup
Description
External Interrupt 0
Timer 0 Interrupt
External Interrupt 1
Timer 1 Interrupt
IE0
TF0
IE1
0003h
000Bh
0013h
001Bh
EX0 (IEN0.0)
ET0 (IEN0.1)
EX1 (IEN0.2)
ET1 (IEN0.3)
IP0H.0, IP0.0
IP0H.1, IP0.1
IP0H.2, IP0.2
IP0H.3, IP0.3
1 (highest)
Yes
No
2
3
4
Yes
No
TF1
Serial Port 0 Tx and Rx1,5 TI_0 & RI_05
0023h
ES0(IEN0.4)
IP0H.4, IP0.4
6
No
Serial Port 0 Rx1,5
Timer 2 Interrupt
PCA interrupt
RI_05
TF2, EXF2
002Bh
0033h
ET2 (IEN0.5)
EC (IEN0.6)
IP0H.5, IP0.5
IP0H.6, IP0.6
7
5
No
No
CF, CCFn*
Serial Port 1 Tx and Rx2,6 TI_1 & RI_16
0053h
ES1 (IEN1.0)
IP1H.0, IP1.0
11
No
Serial Port 1 Rx2,6
Serial Port 0 Tx3
Serial Port 1 Tx4
SPI Interrupt
RI_16
TI_0
TI_1
SPI
003Bh
0043h
004Bh
005Bh
0063h
006Bh
0073h
EI10 (IEN1.1)
EI11 (IEN1.2)
EI11 (IEN1.3)
EI12 (IEN1.4)
EI13 (IEN1.5)
EI13 (IEN1.6)
EI14 (IEN1.7)
IP1H.1, IP1.1
IP1H.2, IP1.2
IP1H.3, IP1.3
IP1H.4, IP1.4
IP1H.5, IP1.5
IP1H.6, IP1.6
IP1H.7, IP1.7
8
No
No
No
No
No
No
No
9
10
12
13
Reserved
14
15 (lowest)
1. S0STAT.5 = 0 selects combined Serial Port 0 Tx and Rx interrupt; S0STAT.5 = 1 selects Serial Port 0 Rx interrupt only (and
TX interrupt will be different, see Note 3 below).
2. S1STAT.5 = 0 selects combined Serial Port 1 Tx and Rx interrupt; S1STAT.5 = 1 selects Serial Port 1 Rx interrupt only (and
TX interrupt will be different, see Note 4 below).
3. This interrupt is used as Serial Port 0 Tx interrupt if and only if S0STAT.5 = 1, and is disabled otherwise.
4. This interrupt is used as Serial Port 1 Tx interrupt if and only if S1STAT.5 = 1, and is disabled otherwise.
5. If S0STAT.0 = 1, the following Serial Port 0 additional flag bits can cause this interrupt: FE_0, BR_0, OE_0.
6. If S1STAT.0 = 1, the following Serial Port 1 additional flag bits can cause this interrupt: FE_1, BR_1, OE_1.
Table 1: Summary of Interrupts
2001 Apr 06
13
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
DATA RAM
The P87C51MB2 and P87C51MC2 have 2 Kbytes and 3 K bytes of on-chip RAM respectively. Usages of the different data
segments are described in the 51MX Architecture Reference.
Data Memory
Description
Size (in Bytes)
Type
P87C51MB2 P87C51MC2
DATA
memory that can be addressed directly and indirectly
128
128
128
128
memory that can be addressed indirectly (where direct address is for SFR
only)
IDATA
EDATA
XDATA
memory that can only be addressed indirectly
1024
768
1024
1792
memory (on-chip "External Data") that is accessed using the MOVX
instructions
Total
2048
3072
Table 2: On-Chip Data Memory Usage.
PORT 4
The P87C51Mx2 has a fifth I/O port (Port 4) that is shared with the second UART pins (RXD1 and TXD1) and two of the SPI pins
(MISO and SS). This port is also bit addressable and can be accessed in the same manner as any other ports, except that the
associated SFR is in the extended SFR space. Accesses to this SFR space is the same as those to the conventional SFR space
except that the instructions must be preceeded by an escape code (A5h), as described in the 51MX Architecture Reference.
LOW POWER MODES
The P87C51Mx2 supports the standard 51MX low power modes - Stop Clock Mode, Idle Mode and Power-Down Mode.
The PCON register is the same as the standard 51MX PCON register. Note that bits PCON.7 and PCON.6 are for UART
configurations (see section "UARTs").
ONCE™ MODE
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems without the device having to be removed
from the circuit. It is supported in the P87C51Mx2.
PERIPHERALS
The P87C51Mx2 peripherals are described in more detail in the User Manual. The on-chip peripherals include:
• Timers:
- Timers 0 and 1.
- Timer 2.
Note: When Timer 1 or Timer 2 can only be used as a baud rate generator for UART 0, but not for UART 1.
• Two enhanced UARTs with an independent Baud Rate Generator - The section "UARTs" provides information regarding the
two UARTs.
Note: UART 1 shares the RXD1 and TXD1 with the SPI pins. The SPEN (SPCTL.6) bit must be cleared ’0’ (reset value) to
enable UART 1 operation.
• Serial Peripheral Interface (SPI). Note: The SPI shares pins with the UART 1 shares the RXD1 and TXD1 with the SPI pins.
The SPEN (SPCTL.6) bit must be set to ’1’ to enable SPI operation.
• Watchdog Timer.
• Programmable Counter Array (PCA).
2001 Apr 06
14
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
UARTS
P87C51Mx2 includes two enhanced UART ports with one independent Baud Rate Generator:
• UART 0 is the standard 51MX enhanced UART as described in the User Manual. It can be selected to use Timer1 overflow,
Timer2 overflow or the independent Baud Rate Generator.
• UART 1 only uses the independent Baud Rate Generator to generate its baud rate. It has the same baud rate for both
transmission and reception.
• The Baud Rate Generator is described in the User Manual.
Each of the UARTs has one set of enhanced UART SFRs. Please refer to the descriptions on the corresponding SFRs in the
User Manual:
51MX Extended SFR
Location
See Description in
User Manual on
Register
Description
SFR Location
S0CON
S0BUF
Serial Port 0 Control
Serial Port 0 Data Buffer
98H
99H
A9H
B9H
SCON
SBUF
S0ADDR Serial Port 0 Address
S0ADEN Serial Port 0 Address Enable
S0STAT Serial Port 0 Status
SADDR
SADEN
SSTAT
SCON
SBUF
8CH
80H
81H
82H
83H
84H
S1CON
S1BUF
Serial Port 1 Control
Serial Port 1 Data Buffer
S1ADDR Serial Port 1 Address
S1ADEN Serial Port 1 Address Enable
S1STAT Serial Port 1 Status
SADDR
SADEN
SSTAT
Table 3: UARTs 0 and 1 SFRs.
PCON.7 and PCON.6 SFR Bits
The PCON.7 and PCON.6 SFR bits configure the UARTs as follows:
• PCON.7 (SMOD1) - Baud Rate Control bit for serial port 0. When 0, the baud rate for UART 0 will be the input rate (T1 timer
or baud rate generator, as determined by the BRGCON extended SFR) divided by two. When 1, the baud rate for UART 0 will
be the input rate (T1 timer or baud rate generator). UART 1 is not affected by this bit
• PCON.6 (SMOD0) - Framing Error Location:
- When 0, bit 7 of S0CON and S1CON will function as SM0 for UARTs 0 and 1 respectively.
- When 1, bit 7 of S0CON and S1CON will be used for framing error status for UART 0 and 1 respectively.
PCON.6 also determines when the UART receive interrupts RI_0 and RI_1 occur in UART modes 2 or 3. (Refer to User
Manual for details.)
2001 Apr 06
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Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
Baud Rate Selection
UART 0 and UART 1 selects the baud rate differently as shown in Tables 4 and 5:
T2CON.5/4
(RCLK - Receive
TCLK - Transmit)
S0CON.7
(SM0_0)
S0CON.6
(SM1_0)
PCON.7
(SMOD1)
BRGCON.1
(S0BRGS)
Receive/Transmit Baud Rate for UART 0
0
0
X
0
0
1
1
X
X
0
0
1
1
X
0
1
X
X
0
1
0
1
X
X
X
X
X
0
fOSC/6
T1_rate/32*
T1_rate/16*
0
1
T2_rate/16*
1
fOSC/(BRATE´ 16+16)*
X
X
X
X
0
fOSC/32
1
1
0
1
fOSC/16
T1_rate/32*
T1_rate/16*
T2_rate/16*
1
fOSC/(BRATE´ 16+16)*
*
UART 0 can have different receive and transmit baud rates.
Table 4: Baud Rate Generation for UART 0. Use T2CON.5 (RCLK) in Receive Baud Rate Selection, T2CON.4 (TCLK) in
Transmit Baud Rate Selection
S1CON.7
(SM0_1)
S1CON.6
(SM1_1)
Baud Rate for UART 1
0
0
1
1
0
1
0
1
fOSC/6
fOSC/(BRATE´ 16+16)*
fOSC/(BRATE´ 16+16)*
fOSC/(BRATE´ 16+16)*
*
UART 1 has the same receive and transmit baud rate.
Table 5: Baud Rate Generation for UART 1.
2001 Apr 06
16
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
SECURITY BITS
The P87C51Mx2 has security bits to protect users’ firmware codes. With none of the security bits programmed, the code in the
program memory can be verified. With only security bit 1 (see Table 6) is programmed, MOVC instructions executed from
external program memory are disabled from fetching code bytes from the internal memory. EA is latched on Reset and all further
programming of EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is
disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory
execution is disabled.
Security Bits1,2
Bit 1
Bit 2
Bit 3 Protection Description
1
2
U
U
U
No program security features enabled. EEPROM is programmable and verifiable.
MOVC instructions executed from external program memory are disabled from fetching
code bytes from internal memory, EA is sampled and latched on Reset, and further
programming of the EPROM is disabled.
P
U
U
3
4
P
P
P
P
U
P
Same as 2, also verification is disabled.
Same as 3, external execution is disabled.
Notes:
1. P - programmed. U- unprogrammed.
2. Any other combination of security bits is not defined.
Table 6: EPROM Security Bits
2001 Apr 06
17
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
-55 to +125
-65 to +150
0 to + 13.0
-0.5 to VDD+0.5V
20
UNIT
°C
°C
V
Operating temperature under bias
Storage temperature range
Voltage on EA/VPP pin to VSS
Voltage on any other pin to VSS
V
Maximum IOL per I/O pin
mA
W
Power dissipation (based on package heat transfer, not device power consumption)
1.5
Notes:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any conditions other than those described in the AC and DC
Electrical Characteristics section of this specification are not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of
excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than
the rated maximum.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
2001 Apr 06
18
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
DC ELECTRICAL CHARACTERISTICS
VDD = 2.7V to 5.5V unless otherwise specified;
Tamb = 0 to +70°C for commercial, unless otherwise specified.
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP1
MAX
VIL
VIH
0.2VDD-0.1
Input low voltage
-0.5
V
V
Input high voltage (ports 0, 1, 2, 3,
4, EA)
0.2VDD+0.9
0.7VDD
VDD+0.5
VIH1
VOL
VDD+0.5
0.4
Input high voltage, XTAL1, RST
V
V
Output low voltage, ports 1, 2, 3, 48
Output low voltage, port 0, ALE,
PSEN7,8
VDD = 2.7V, IOL = 1.6mA
VDD = 2.7V, IOL = 3.2mA
VOL1
VOH
VOH1
IIL
ITL
IL1
0.4
-75
V
V
VDD = 4.5V, IOH = -30µA
VDD = 2.7V, IOH = -10µA
VDD - 0.7
Output high voltage, ports 1, 2, 3, 4
Output high voltage (port 0 in
external bus mode), ALE9, PSEN3
VDD = 2.7V, IOH = -3.2mA
VIN = 0.4V
VDD - 0.7
-1
V
Logical 0 input current, ports 1, 2,
3, 4
µA
4.5V < VDD < 5.5V,
VIN = 2.0V, See Note 4
Logical 1 -to-0 transition current,
ports 1, 2, 3, 48
-650
±10
µA
µA
0.45 < VIN < VDD-0.3
Input leakage current, port 0
Power supply current
7 +
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 3.6V
2.7 /MHz × fOSC
Active mode (see Note 5)
Idle mode (see Note 5)
mA
4 +
1.3 /MHz × fOSC
4 +
ICC
1.3 /MHz × fOSC
mA
µA
1 +
1.0 /MHz × fOSC
Power-down mode or clock
stopped (see Figure 16 for
conditions)
VDD = 5.0V
VDD = 5.5V
20
100
225
15
µA
kW
pF
RRST
C10
Internal reset pull-down resistor
Pin capacitance10 (except EA)
40
Notes:
1. Typical ratings are not guaranteed. The values listed are at room temperature (+25°C), 5V, unless otherwise stated.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOL of ALE and ports 1, 3 and 4.
The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0
transitions during bus operations. In the worst cases (capacitive loading>100 pF), the noise pulse on the ALE pin may exceed
0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger
STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two
outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VDD-0.7V
specification when the address bits are stabilizing.
4. Pins of ports 1, 2, 3 and 4 source a transition current when they are being externally driven from 1 to 0. The transition current
reaches its maximum value when VIN is approximately 2 V for 4.5V < VDD < 5.5V.
5. See Figures 13 through 16 for ICC test conditions. fOSC is the oscillator frequency in MHz.
6. This value applies to Tamb = 0°C to +70°C.
2001 Apr 06
19
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80pF
8. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
Maximum IOL per 8-bit port:
Maximum total IOL for all outputs:
15 mA
26 mA
71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current
greater than the listed test conditions.
9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification.
10.Pin capacitance is characterized but not tested.
2001 Apr 06
20
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
AC ELECTRICAL CHARACTERISTICS
Tamb = 0 to +70°C for commercial unless otherwise specified.1,2,3
2.7V < VDD < 5.5V
4.5V < VDD < 5.5V
fOSC=12MHz4
fOSC=24MHz4
SYMBOL FIGURE(S)
PARAMETER
Variable Clock4
MIN MAX
12
Variable Clock4
MIN MAX
24
UNIT
MIN
MAX
MIN
MAX
fOSC
Oscillator frequency
0
0
MHz
ns
tCLCL
tLHLL
tAVLL
tLLAX
tLLIV
15
CLock cycle
83
16
8
41.5
tCLCL-66
tCHCX-25
tCLCX-25
tCLCL-33
tCHCX-12
tCLCX-12
1,2
ALE pulse width
8
4
4
ns
1,2,3, 4,5,6 Address valid to ALE low
1,2,3, 4,5,6 Address hold after ALE low
ns
8
ns
2tCLCL-108
2tCLCL-54
1,2
1,2
ALE low to valid instruction in
ALE low to PSEN low
58
25
29
12
ns
tLLPL
tCLCX-25
tCLCX-12
8
4
ns
tCLCL+tCHCX
-66
tCLCL+tCHCX
-33
tPLPH
tPLIV
1,2
1,2
PSEN pulse width
50
25
ns
ns
tCLCL
+tCHCX-91
tCLCL
+tCHCX-46
PSEN low to valid instruction in
tPXIX
tPXIZ
1,2
1,2
Input instruction hold after PSEN
Input instruction float after PSEN
0
0
0
0
ns
ns
tCLCX-25
tCLCX-12
8
4
2tCLCL
+tCHCX-36
2tCLCL
+tCHCX-28
Address (A8-A15) to valid instruction
in (non-Extended Addressing Mode)
tAVIV
1
180
81
ns
tCLCL
+tCHCX-44
2tCLCL
+tCHCX-34
Address (A8-A15) to valid instruction
in (Extended Addressing Mode)
tAVIV1
tPLAZ
2
89
16
33
8
ns
ns
1,2
PSEN low to address float
16
8
Data Memory
tRLRH
3tCLCL-166
3tCLCL-166
3tCLCL-83
3tCLCL-83
3,4
5,6
RD pulse width
WR pulse width
83
83
41.5
41.5
ns
ns
tWLWH
tRLDV
2tCLCL
+tCHCX-141
2tCLCL
+tCHCX-70
3,4
RD low to valid data in
58
29
ns
tRHDX
tRHDZ
tLLDV
3,4
3,4
3,4
Data hold after RD
Data float after RD
ALE low to valid data in
0
0
0
0
ns
ns
ns
tCLCL-34
tCLCL-17
49
83
24
41
4tCLCL-250
4tCLCL-125
4tCLCL
+tCHCX-36
4tCLCL
+tCHCX-28
Address (A8-A15) to valid data in
(non-Extended Addressing Mode)
tAVDV
3
4
346
255
208
164
116
104
ns
ns
ns
3tCLCL
+tCHCX-44
3tCLCL
+tCHCX-34
Address (A8-A15) to valid data in
(Extended Addressing Mode)
tAVDV1
tCLCL
+tCLCX-83
tCLCL
+tCLCX+83
tCLCL
+tCLCX-41
tCLCL
+tCLCX+41
tLLWL
3,4, 5,6
ALE low to RD or WR low
Address (A8-A15) valid to WR or RD
low (non-Extended Addressing
Mode)
tAVWL
2tCLCL-15
tCLCL-20
2tCLCL-20
tCLCL-25
3,5
4,6
151
63
63
ns
ns
Address (A8-A15) valid to WR orRD
low (Extended Addressing Mode)
tAVWL1
16.5
tQVWX
tWHQX
tCLCX-33
tCHCX-24
tCLCX-16
tCHCX-11
5,6
5,6
Data valid to WR transition
Data hold after WR
0
9
0
5
ns
ns
3tCLCL
+tCLCX-207
3tCLCL
+tCLCX-103
tQVWH
5,6
Data valid to WR high
75
37.5
ns
tRLAZ
3,4
RD low to address float
0
0
0
0
ns
ns
tWHLH
tCHCX-24
tCHCX+25
tCHCX-11
tCHCX+12
3,4, 5,6
RD or WR high to ALE high
9
75
5
37
External Clock
tCHCX
tCLCL-tCLCX
tCLCL-tCLCX
12
12
12
12
High time
Low time
Rise time
Fall Time
33
33
33
33
50
50
8
16
16
16
16
24.5
24.5
4
ns
ns
ns
ns
tCLCX
tCLCH
tCHCL
tCLCL-tCHCX
tCLCL-tCHCX
8
8
4
4
8
4
2001 Apr 06
21
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
2.7V < VDD < 5.5V
4.5V < VDD < 5.5V
fOSC=12MHz4
fOSC=24MHz4
SYMBOL FIGURE(S)
Shift Register
PARAMETER
Variable Clock4
Variable Clock4
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tXLXL
6tCLCL
6tCLCL
7
7
Serial port clock cycle time
500
195
250
98
ns
ns
Output data setup to clock rising
edge
tQVXH
5tCLCL-221
5tCLCL-110
Output data hold after clock rising
edge
tXHQX
tXHDX
tCLCL-50
0
tCLCL-25
0
7
34
0
17
0
ns
Input data hold after clock rising
edge
7
7
ns
ns
tXHDV
5tCLCL-222
5tCLCL-111
Clock rising edge to input data valid
195
97
SPI Interface
Operating frequency
- 3.0MHz
fSPI
0
-
3.0
-
0
-
3.0
-
0
0
3.0
6.0
0
0
3.0
6.0
MHz
ns
- 6.0MHz
Cycle time
tSPICYC
tSPILEAD
tSPILAG
8, 9, 10, 11 - 3.0MHz
- 6.0MHz
333
-
333
-
333
166
333
166
Enable lead time (Slave)
- 3.0MHz
10, 11
10, 11
TBD
-
TBD
-
TBD
TBD
TBD
TBD
ns
- 6.0MHz
Enable lag time (Slave)
- 3.0MHz
TBD
-
TBD
-
TBD
TBD
TBD
TBD
ns
- 6.0MHz
SPICLK high time
tSPICLKH
8, 9, 10, 11 - Master
- Slave
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ns
SPICLK low time
tSPICLKL
8, 9, 10, 11 - Master
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ns
- Slave
tSPIDSU
tSPIDH
tSPIA
8, 9, 10, 11 Data setup time (Master or Slave)
ns
ns
ns
8, 9, 10, 11 Data hold time (Master or Slave)
TBD
TBD
TBD
TBD
10, 11
Access time (Slave)
Disable time (Slave)
- 3.0MHz
TBD
TBD
TBD
TBD
tSPIDIS
10, 11
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ns
- 6.0MHz
Enable to output data valid
tSPIDV
8, 9, 10, 11 - 3.0MHz
- 6.0MHz
TBD
-
TBD
-
TBD
TBD
TBD
TBD
ns
ns
tSPIOH
8, 9, 10, 11 Output data hold time
Rise time
0
0
0
0
- SPI outputs (SPICLK,MOSI, MISO)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tSPIR
8, 9, 10, 11
8, 9, 10, 11
ns
ns
- SPI inputs (SPICLK,MOSI, MISO,
SS)
Fall time
- SPI outputs (SPICLK,MOSI, MISO)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tSPIF
- SPI inputs (SPICLK,MOSI, MISO,
SS)
Notes:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause
damage to Port 0 drivers.
4. Parts are tested down to 2 MHz, but are guaranteed to operate down to 0Hz.
2001 Apr 06
22
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
EXPLANATION OF AC SYMBOLS
Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their
positions, indicate the name of a signal or the logical status of that signal. The designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
P – PSEN
Q – Output data
R – RD signal
t – Time
V – Valid
W– WR signal
X – No longer a valid logic level
Z – Float
Examples:
tAVLL - Time for address valid to ALE low.
tLLPL - Time for ALE low to PSEN low
tLHLL
ALE
tLLPL
tPLPH
tLLIV
PSEN
tPLIV
tPLAZ
tPXIZ
tAVLL
tLLAX
tPXIX
PORT 0
PORT 2
A0-A7
INSTR IN
A0-A7
tAVIV
P2.0-P2.7 OR A8-A15
Figure 1: External Program Memory Read Cycle (Non-Extended Memory Cycle)
2001 Apr 06
23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
tLHLL
ALE
tLLPL
tPLPH
tLLIV
PSEN
tPLIV
tPLAZ
tPXIZ
tAVLL
tLLAX
tPXIX
PORT 0
PORT 2
A0-A7
INSTR IN
A0-A7
tAVIV1
A16-A22,P2.7
A8-A15
Figure 2: External Program Memory Read Cycle (Extended Memory Cycle)
ALE
tWHLH
PSEN
RD
tLLDV
tLLWL
tRLRH
tLLAX
tAVLL
tRLAZ
tRLDV
tRHDZ
tRHDX
PORT 0
A0-A7
DATA in
A0-A7 FROM PCL
INSTR IN
tAVWL
tAVDV
PORT 2
P2.0-P2.7 OR A8-A15
Figure 3: External Data Memory Read Cycle (Non-Extended Memory Cycle)
2001 Apr 06
24
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
ALE
tWHLH
PSEN
tLLDV
tLLWL
tRLRH
RD
tLLAX
tAVLL
tRLAZ
tRLDV
tRHDZ
tRHDX
PORT 0
A0-A7
DATA in
A0-A7 FROM PCL
INSTR IN
tAVWL1
tAVDV1
PORT 2
A16-A22,P2.7
A8-A15
Figure 4: External Data Memory Read Cycle (Extended Memory Cycle)
ALE
tWHLH
PSEN
WR
tLLWL
tWLWH
tLLAX
tAVLL
tQVWX
tWHQX
tQVWH
PORT 0
PORT 2
A0-A7
DATA OUT
A0-A7 FROM PCL
INSTR IN
tAVWL
P2.0-P2.7 OR A8-A15
Figure 5: External Data Memory Write Cycle (Non-Extended Memory Cycle)
2001 Apr 06
25
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
ALE
tWHLH
PSEN
tLLWL
tWLWH
WR
tLLAX
tAVLL
tQVWX
tWHQX
tQVWH
PORT 0
PORT 2
A0-A7
DATA OUT
A0-A7 FROM PCL
INSTR IN
tAVWL1
A16-A22,P2.7
A8-A15
Figure 6: External Data Memory Write Cycle (Extended Memory Cycle)
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tXHQX
tQVXH
OUTPUT DATA
WRITE TO SBUF
0
1
2
3
4
5
6
7
tXHDX
SET TI
tXHDV
VALID
INPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
Figure 7: Shift Register Mode Timing
2001 Apr 06
26
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
SS
tSPICYC
tSPIF
tSPICLKL
tSPIR
tSPICLKH
SPICLK
(CPOL = 0)
(output)
tSPIF
tSPICLKL
tSPIR
tSPICLKH
SPICLK
(CPOL = 1)
(output)
tSPIDSU
tSPIDH
MISO
(input)
MSB/LSB in
LSB/MSB in
tSPIDV
tSPIOH
tSPIDV
tSPIR
tSPIF
MOSI
(output)
Master MSB/LSB out
Master LSB/MSB out
Figure 8: SPI Master Timing (CPHA = 0)
SS
tSPICYC
tSPIF
tSPICLKL
tSPIR
tSPICLKH
SPICLK
(CPOL = 0)
(output)
tSPIF
tSPICLKL
tSPIR
tSPICLKH
SPICLK
(CPOL = 1)
(output)
tSPIDSU
tSPIDH
MISO
(input)
MSB/LSB in
LSB/MSB in
tSPIDV
tSPIDV
tSPIR
tSPIOH
tSPIDV
tSPIF
MOSI
(output)
Master MSB/LSB out
Master LSB/MSB out
Figure 9: SPI Master Timing (CPHA = 1)
2001 Apr 06
27
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
SS
tSPICYC
tSPIR
tSPILEAD
tSPIR
tSPIF
tSPICLKH
tSPICLKL
tSPIR
tSPILAG
SPICLK
(CPOL = 0)
(input)
tSPIF
tSPICLKL
tSPIR
tSPICLKH
SPICLK
(CPOL = 1)
(input)
tSPIDIS
tSPIOH
tSPIDV
tSPIOH
tSPIDV
tSPIOH
tSPIA
MISO
Slave MSB/LSB out
Slave LSB/MSB out
Not defined
(output)
tSPIDSU
tSPIDH
tSPIDSU
tSPIDSU
tSPIDH
MOSI
(input)
MSB/LSB in
LSB/MSB in
Figure 10: SPI Slave Timing (CPHA = 0)
SS
tSPICYC
tSPIR
tSPILEAD
tSPIR
tSPIF
tSPICLKH
tSPICLKL
tSPIR
tSPILAG
SPICLK
(CPOL = 0)
(input)
tSPIF
tSPICLKL
tSPIR
tSPICLKH
SPICLK
(CPOL = 1)
(input)
tSPIDIS
tSPIOH
tSPIDV
tSPIOH
tSPIDV
tSPIOH
tSPIDV
tSPIA
Not defined
MISO
Slave MSB/LSB out
Slave LSB/MSB out
(output)
tSPIDSU
tSPIDH
tSPIDSU
tSPIDSU
tSPIDH
MOSI
(input)
MSB/LSB in
LSB/MSB in
Figure 11: SPI Slave Timing (CPHA = 1)
2001 Apr 06
28
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
VDD-0.5V
0.7VDD
0.45V
0.2VDD-0.1V
tCHCL
tCHCX
tCLCH
tCLCX
tCLCL
Figure 12: External Clock Drive
VDD
VDD
ICC
RST
VDD
VDD
P0
EA
(NC)
XTAL2
XTAL1
VSS
CLOCK SIGNAL
Figure 13: ICC Test Condition, Active Mode (All other pins are disconnected)
2001 Apr 06
29
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
VDD
ICC
RST
VDD
VDD
P0
EA
(NC)
XTAL2
XTAL1
VSS
CLOCK SIGNAL
Figure 14: ICC Test Condition, Idle Mode (All other pins are disconnected)
VDD-0.5V
0.7VDD
0.45V
0.2VDD-0.1V
tCHCL
tCHCX
tCLCH
tCLCX
tCLCL
Figure 15: Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns
2001 Apr 06
30
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
VDD
ICC
RST
VDD
VDD
P0
EA
(NC)
XTAL2
XTAL1
VSS
Figure 16: ICC Test Condition, Power Down Mode (All other pins are disconnected, VDD = 2.0V to 5.5V)
2001 Apr 06
31
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
P87C51MB2/P87C51MC2
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 2001
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 04-01
Document order number:
9397 750 08199
Philips
Semiconductors
Philips Semiconductors
Errata
P87C51MB2/P87C51MC2
Errata sheet
FUNCTIONAL DEVIATIONS
Deviation #1
RxD1 pin is an open drain configuration.
Work-around:
A resistor must be used if this pin is to be used as an output. These pins will become port 4 on the next
release fixing this issue.
Deviation #2
Port 4 does not exist for the RxD1 and TxD1 pins. DC parameters differ from standard port pins.
Work-around:
None. These pins will become port 4 on the next release.
Deviation #3
RxD1, TxD1, and ALE pins will not go into once mode.
Work-around:
None. This will be fixed on the next release.
Deviation #4
In the UART, the contents of RB8 and SBUF change when they shouldn’t if SM2=1 in modes 2 and 3.
Work-around:
None. Will be fixed on the next release.
Deviation #5
The UART double buffering will be implemented on the next release.
Work-around:
None.
Deviation #6
SPI block will be implemented on the next release.
Work-around:
None.
Deviation #7
Security bits are not 100% compatible with past 80c51 products.
Work-around:
The security bits will be compatible on the next release.
1
2001 Apr 06
Version 1.0
Philips Semiconductors
Errata
P87C51MB2/P87C51MC2
Errata sheet
Deviation #8
UART mode 0 receive data is sampled one clock later than standard 80C51 UARTS.
Work-around:
This requires an increased data hold time. This will be fixed on the next release.
Deviation #9
The PCA Watchdog timer function may not function properly at 24 MHz f
when the PCA Count Pulse
OSC
selection is set to “internal clock, f
/2”.
OSC
Work-around:
None. This will be fixed on the next release.
2
2001 Apr 06
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