P87C51TFAA-T_技术文档

INTEGRATED CIRCUITS

80C51/87C51/80C31

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

Product specification

2000 Jan 20

Supersedes data of 1999 Apr 01

IC28 Data Handbook

Philips

Semiconductors

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

DESCRIPTION

FEATURES

The Philips 8XC51/31 is a high-performance static 80C51 design

fabricated with Philips high-density CMOS technology with operation

from 2.7V to 5.5V.

• 8051 Central Processing Unit

– 4k × 8 ROM (80C51)

– 128 × 8 RAM

The 8XC51/31 contains a 4k × 8 ROM, a 128 × 8 RAM, 32 I/O lines,

three 16-bit counter/timers, a six-source, four-priority level nested

interrupt structure, a serial I/O port for either multi-processor

communications, I/O expansion or full duplex UART, and on-chip

oscillator and clock circuits.

– Three 16-bit counter/timers

– Boolean processor

– Full static operation

– Low voltage (2.7V to 5.5V@ 16MHz) operation

In addition, the device is a low power static design which offers a

wide range of operating frequencies down to zero. Two software

selectable modes of power reduction—idle mode and power-down

mode are available. The idle mode freezes the CPU while allowing

the RAM, timers, serial port, and interrupt system to continue

functioning. The power-down mode saves the RAM contents but

freezes the oscillator, causing all other chip functions to be

inoperative. Since the design is static, the clock can be stopped

without loss of user data and then the execution resumed from the

point the clock was stopped.

• Memory addressing capability

– 64k ROM and 64k RAM

• Power control modes:

– Clock can be stopped and resumed

– Idle mode

– Power-down mode

• CMOS and TTL compatible

• TWO speed ranges at V = 5V

CC

– 0 to 16MHz

SELECTION TABLE

For applications requiring more ROM and RAM,

see the 8XC52/54/58/80C32, 8XC51FA/FB/FC/80C51FA,

and 8XC51RA+/RB+/RC+/80C51RA+ data sheet.

– 0 to 33MHz

• Three package styles

• Extended temperature ranges

• Dual Data Pointers

ROM/EPROM

Memory Size

(X by 8)

RAM Size

(X by 8)

Programmable

Timer Counter

(PCA)

Hardware

Watch Dog

Timer

• Security bits:

– ROM (2 bits)

80C31/8XC51

– OTP/EPROM (3 bits)

0K/4K

128

No

• Encryption array—64 bytes

• 4 level priority interrupt

• 6 interrupt sources

80C32/8XC52/54/58

0K/8K/16K/32K

256

80C51FA/8XC51FA/FB/FC

0K/8K/16K/32K 256

80C51RA+/8XC51RA+/RB+/RC+

• Four 8-bit I/O ports

Yes

No

• Full–duplex enhanced UART

– Framing error detection

0K/8K/16K/32K

8XC51RD+

64K

512

Yes

– Automatic address recognition

• Programmable clock out

1024

• Asynchronous port reset

• Low EMI (inhibit ALE)

• Wake-up from Power Down by an external interrupt (8XC51)

2

2000 Jan 20

853–0169 23001

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

80C51/87C51 AND 80C31 ORDERING INFORMATION

MEMORY SIZE

TEMPERATURE RANGE °C

VOLTAGE

RANGE

FREQ.

(MHz)

DWG.

#

ROMless

4K × 8

AND PACKAGE

ROM P80C51SBPN

P80C31SBPN

0 to +70, Plastic Dual In-line Package

2.7V to 5.5V

5V

0 to 16

0 to 33

SOT129-1

SOT187-2

SOT307-2

SOT129-1

SOT187-2

SOT307-2

SOT187-2

SOT129-1

SOT307-2

SOT187-2

SOT129-1

SOT307-2

OTP

ROM P80C51SBAA

OTP P87C51SBAA

ROM P80C51SBBB

OTP P87C51SBBB

ROM P80C51SFPN

OTP P87C51SFPN

ROM P80C51SFA A

OTP P87C51SFA A

ROM P80C51SFBB

OTP P87C51SFBB

ROM P80C51UBAA

OTP P87C51UBAA

ROM P80C51UBPN

OTP P87C51UBPN

ROM P80C51UBBB

OTP P87C51UBBB

ROM P80C51UFAA

OTP P87C51UFAA

ROM P80C51UFPN

OTP P87C51UFPN

ROM P80C51UFBB

OTP P87C51UFBB

P87C51SBPN

P80C31SBAA

P80C31SBBB

P80C31SFPN

P80C31SFA A

P80C31SFBB

P80C31UBAA

P80C31UBPN

P80C31UBBB

P80C31UFAA

P80C31UFPN

P80C31UFBB

0 to +70, Plastic Leaded Chip Carrier

0 to +70, Plastic Quad Flat Pack

–40 to +85, Plastic Dual In-line Package

–40 to +85, Plastic Leaded Chip Carrier

–40 to +85, Plastic Quad Flat Pack

0 to +70, Plastic Leaded Chip Carrier

0 to +70, Plastic Dual In-line Package

0 to +70, Plastic Quad Flat Pack

5V

–40 to +85, Plastic Leaded Chip Carrier

–40 to +85, Plastic Dual In-line Package

–40 to +85, Plastic Quad Flat Pack

5V

80C51/87C51 AND 80C31 ORDERING INFORMATION

DEVICE NUMBER (P87C51)

OPERATING FREQUENCY, MAX (S)

TEMPERATURE RANGE (B)

PACKAGE (AA)

AA = PLCC

BB = PQFP

PN = PDIP

P80C51 ROM

S = 16 MHz

B = 0_ to +70_C

F = –40_C to +85_C

P87C51 OTP

U = 33 MHz

P80C31 ROMless

3

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

BLOCK DIAGRAM

P0.0–P0.7

P2.0–P2.7

PORT 0

DRIVERS

PORT 2

DRIVERS

V

CC

V

SS

RAM ADDR

REGISTER

PORT 0

LATCH

PORT 2

LATCH

ROM/EPROM

RAM

8

B

STACK

POINTER

ACC

REGISTER

PROGRAM

ADDRESS

REGISTER

TMP1

TMP2

BUFFER

ALU

SFRs

PC

INCRE-

MENTER

TIMERS

PSW

8

16

PROGRAM

COUNTER

PSEN

ALE/PROG

DPTR’S

MULTIPLE

TIMING

AND

CONTROL

EAV

PP

RST

PORT 1

LATCH

PORT 3

LATCH

PD

OSCILLATOR

PORT 1

DRIVERS

PORT 3

DRIVERS

XTAL1

XTAL2

P1.0–P1.7

P3.0–P3.7

SU00845

4

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

LOGIC SYMBOL

PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS

6

1

40

V

SS

CC

XTAL1

7

39

ADDRESS AND

DATA BUS

LCC

XTAL2

RST

17

29

T2

T2EX

18

28

EA/V

PP

PSEN

Pin Function

ALE/PROG

31

32

33

34

35

36

37

38

39

40

41

42

43

44

P2.7/A15

PSEN

ALE

NIC*

EA/V

PP

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

NIC*

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

P1.0/T2

P1.1/T2EX

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

P3.0/RxD

NIC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

RxD

TxD

INT0

INT1

T0

T1

WR

RD

ADDRESS BUS

SU00830

XTAL1

V

SS

NIC*

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

V

CC

PIN CONFIGURATIONS

* NO INTERNAL CONNECTION

SU01062

T2/P1.0

40

39

V

CC

1

2

3

PLASTIC QUAD FLAT PACK

PIN FUNCTIONS

T2EX/P1.1

P0.0/AD0

P1.2

P1.3

P1.4

38 P0.1/AD1

37

44

34

4

5

P0.2/AD2

36 P0.3/AD3

35

1

33

P1.5

P1.6

P1.7

RST

6

7

8

9

P0.4/AD4

34 P0.5/AD5

33

PQFP

P0.6/AD6

11

23

32 P0.7/AD7

DUAL

IN-LINE

PACKAGE

31 EA/V

PP

RxD/P3.0 10

TxD/P3.1 11

INT0/P3.2 12

12

22

30 ALE

Pin Function

29

PSEN

28 P2.7/A15

27

1

2

P1.5

P1.6

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

NIC*

31

32

33

34

35

36

37

38

39

40

41

42

43

44

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

SS

13

INT1/P3.3

3

P1.7

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE

NIC*

EA/V

P0.7/AD7

P2.6/A14

T0/P3.4 14

T1/P3.5 15

WR/P3.6 16

RD/P3.7 17

XTAL2 18

XTAL1 19

4

RST

5

6

P3.0/RxD

NIC*

26 P2.5/A13

25 P2.4/A12

7

8

9

10

11

12

13

14

15

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

V

CC

NIC*

24

P2.3/A11

23 P2.2/A10

22

P1.0/T2

P1.1/T2EX

P1.2

P1.3

P1.4

P2.1/A9

21 P2.0/A8

PP

V

20

SS

* NO INTERNAL CONNECTION

SU01063

SU01064

5

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC DIP

LCC

22

QFP

16

TYPE NAME AND FUNCTION

V

SS

V

CC

20

40

I

Ground: 0V reference.

44

38

Power Supply: This is the power supply voltage for normal, idle, and power-down operation.

P0.0–0.7

39–32 43–36 37–30

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to

them float and can be used as high-impedance inputs. Port 0 is also the multiplexed

low-order address and data bus during accesses to external program and data memory. In

this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the

code bytes during program verification and received code bytes during EPROM

programming. External pull-ups are required during program verification.

P1.0–P1.7

1–8

2–9

40–44,

1–3

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,

port 1 pins that are externally pulled low will source current because of the internal pull-ups.

(See DC Electrical Characteristics: I ). Port 1 also receives the low-order address byte

IL

during program memory verification. Alternate functions for Port 1 include:

T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable Clock-Out).

T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control.

1

2

3

40

41

I/O

I

P2.0–P2.7

21–28 24–31 18–25

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,

port 2 pins that are externally being pulled low will source current because of the internal

pull-ups. (See DC Electrical Characteristics: I ). Port 2 emits the high-order address byte

IL

during fetches from external program memory and during accesses to external data memory

that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal

pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses

(MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins

receive the high order address bits during EPROM programming and verification.

P3.0–P3.7

10–17

11,

5,

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,

port 3 pins that are externally being pulled low will source current because of the pull-ups.

13–19 7–13

(See DC Electrical Characteristics: I ). Port 3 also serves the special features of the 80C51

IL

family, as listed below:

10

11

12

13

14

15

16

17

11

13

14

15

16

17

18

19

5

7

8

I

O

I

O

RxD (P3.0): Serial input port

TxD (P3.1): Serial output port

INT0 (P3.2): External interrupt

INT1 (P3.3): External interrupt

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

9

10

11

12

13

RST

9

10

4

I

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the

device. An internal diffused resistor to V permits a power-on reset using only an external

SS

capacitor to V

.

CC

ALE/PROG

30

33

27

O

Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the

address during an access to external memory. In normal operation, ALE is emitted at a

constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.

Note that one ALE pulse is skipped during each access to external data memory. This pin is

also the program pulse input (PROG) during EPROM programming. ALE can be disabled by

setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.

PSEN

29

31

32

35

26

29

O

I

Program Store Enable: The read strobe to external program memory. When the 8XC51/31

is executing code from the external program memory, PSEN is activated twice each

machine cycle, except that two PSEN activations are skipped during each access to

external data memory. PSEN is not activated during fetches from internal program memory.

EA/V

External Access Enable/Programming Supply Voltage: EA must be externally held low

to enable the device to fetch code from external program memory locations 0000H and

0FFFH. If EA is held high, the device executes from internal program memory unless the

program counter contains an address greater than 0FFFH. This pin also receives the

PP

12.75V programming supply voltage (V ) during EPROM programming. If security bit 1 is

PP

programmed, EA will be internally latched on Reset.

XTAL1

19

18

21

20

15

14

I

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator

circuits.

XTAL2

O

Crystal 2: Output from the inverting oscillator amplifier.

NOTE:

To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V + 0.5V or V – 0.5V, respectively.

CC

SS

6

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

Table 1.

8XC51/80C31 Special Function Registers

DIRECT

DESCRIPTION

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

RESET

VALUE

SYMBOL

ADDRESS MSB

LSB

ACC*

AUXR#

AUXR1#

B*

Accumulator

Auxiliary

E0H

8EH

A2H

F0H

E7

–

E6

–

E5

–

E4

–

E3

–

E2

–

E1

–

E0

00H

AO

DPS

F0

xxxxxxx0B

xxx000x0B

00H

2

3

Auxiliary 1

B register

–

LPEP

F4

WUPD

F3

0

–

F7

F6

F5

F2

F1

DPTR:

DPH

DPL

Data Pointer (2 bytes)

Data Pointer High

Data Pointer Low

83H

82H

00H

AF

EA

BF

–

AE

–

AD

ET2

BD

AC

ES

BC

PS

B4

AB

ET1

BB

AA

EX1

BA

A9

ET0

B9

A8

EX0

B8

IE*

Interrupt Enable

Interrupt Priority

Interrupt Priority High

Port 0

A8H

B8H

B7H

80H

90H

A0H

0x000000B

xx000000B

FFH

BE

–

IP*

PT2

B5

PT1

B3

PX1

B2

PT0

B1

PX0

B0

B7

–

B6

–

IPH#

P0*

P1*

P2*

P3*

PT2H

85

PSH

84

PT1H

83

PX1H PT0H

PX0H

80

87

86

82

AD2

92

81

AD1

91

AD7

97

AD6

96

AD5

95

AD4

94

AD3

93

AD0

90

Port 1

–

T2EX

A1

T2

FFH

A7

AD15

B7

RD

A6

AD14

B6

WR

A5

A4

A3

A2

A0

Port 2

AD13

B5

AD12

B4

AD11

B3

AD10

B2

AD9

B1

AD8

B0

FFH

Port 3

B0H

87H

T1

T0

INT1

INT0

TxD

RxD

FFH

1

PCON#

Power Control

SMOD1

D7

SMOD0

D6

–

POF

D4

GF1

D3

GF0

D2

PD

D1

–

IDL

D0

P

00xx0000B

D5

F0

PSW*

Program Status Word

D0H

CY

AC

RS1

RS0

OV

000000x0B

RACAP2H# Timer 2 Capture High

CBH

CAH

00H

RACAP2L#

Timer 2 Capture Low

SADDR#

SADEN#

Slave Address

Slave Address Mask

A9H

B9H

00H

SBUF

Serial Data Buffer

99H

xxxxxxxxB

9F

9E

9D

9C

9B

9A

99

TI

98

RI

SM0/FE

SCON*

SP

Serial Control

Stack Pointer

98H

81H

SM1

SM2

REN

TB8

RB8

00H

07H

8F

TF1

CF

TF2

–

8E

TR1

CE

8D

TF0

CD

8C

TR0

CC

8B

IE1

CB

8A

IT1

CA

TR2

–

89

IE0

88

IT0

C8

TCON*

Timer Control

88H

C8H

00H

C9

T2CON*

Timer 2 Control

EXF2

–

RCLK

–

TCLK

–

EXEN2

–

C/T2

T2OE

CP/RL2 00H

DCEN xxxxxx00B

T2MOD#

TH0

TH1

TH2#

TL0

TL1

Timer 2 Mode Control

Timer High 0

Timer High 1

Timer High 2

Timer Low 0

C9H

8CH

8DH

CDH

8AH

8BH

CCH

00H

Timer Low 1

Timer Low 2

TL2#

TMOD

Timer Mode

89H

GATE

C/T

M1

M0

GATE

C/T

M1

M0

00H

*

SFRs are bit addressable.

#

–

SFRs are modified from or added to the 80C51 SFRs.

Reserved bits.

1. Reset value depends on reset source.

2. LPEP – Low Power EPROM operation (OTP/EPROM only)

3. Not available on 80C31.

7

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

interrupt allows both the SFRs and the on-chip RAM to retain their

values. WUPD (AUXR1.3–Wakeup from Power Down) enables or

disables the wakeup from power down with external interrupt.

Where:

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an

inverting amplifier. The pins can be configured for use as an on-chip

oscillator, as shown in the logic symbol.

WUPD = 0 Disable

WUPD = 1 Enable

To drive the device from an external clock source, XTAL1 should be

driven while XTAL2 is left unconnected. There are no requirements

on the duty cycle of the external clock signal, because the input to

the internal clock circuitry is through a divide-by-two flip-flop.

However, minimum and maximum high and low times specified in

the data sheet must be observed.

To properly terminate Power Down the reset or external interrupt

should not be executed before V is restored to its normal

operating level and must be held active long enough for the

oscillator to restart and stabilize (normally less than 10ms).

CC

With an external interrupt, INT0 or INT1 must be enabled and

configured as level-sensitive. Holding the pin low restarts the

oscillator but bringing the pin back high completes the exit. Once the

interrupt is serviced, the next instruction to be executed after RETI

will be the one following the instruction that put the device into

Power Down.

Reset

A reset is accomplished by holding the RST pin high for at least two

machine cycles (24 oscillator periods), while the oscillator is running.

To insure a good power-up reset, the RST pin must be high long

enough to allow the oscillator time to start up (normally a few

milliseconds) plus two machine cycles.

For the 80C31, wakeup from power down is always enabled.

Stop Clock Mode

The static design enables the clock speed to be reduced down to

0 MHz (stopped). When the oscillator is stopped, the RAM and

Special Function Registers retain their values. This mode allows

step-by-step utilization and permits reduced system power

consumption by lowering the clock frequency down to any value. For

lowest power consumption the Power Down mode is suggested.

LPEP

The eprom array contains some analog circuits that are not required

when V is less than 4V, but are required for a V greater than

4V. The LPEP bit (AUXR.4), when set, will powerdown these analog

circuits resulting in a reduced supply current. This bit should be set

CC

ONLY for applications that operate at a V less tan 4V.

CC

Design Consideration

Idle Mode

• When the idle mode is terminated by a hardware reset, the device

normally resumes program execution, from where it left off, up to

two machine cycles before the internal reset algorithm takes

control. On-chip hardware inhibits access to internal RAM in this

event, but access to the port pins is not inhibited. To eliminate the

possibility of an unexpected write when Idle is terminated by reset,

the instruction following the one that invokes Idle should not be

one that writes to a port pin or to external memory.

In idle mode (see Table 2), the CPU puts itself to sleep while all of

the on-chip peripherals stay active. The instruction to invoke the idle

mode is the last instruction executed in the normal operating mode

before the idle mode is activated. The CPU contents, the on-chip

RAM, and all of the special function registers remain intact during

this mode. The idle mode can be terminated either by any enabled

interrupt (at which time the process is picked up at the interrupt

service routine and continued), or by a hardware reset which starts

the processor in the same manner as a power-on reset.

ONCE Mode

The ONCE (“On-Circuit Emulation”) Mode facilitates testing and

debugging of systems without the device having to be removed from

the circuit. The ONCE Mode is invoked by:

Power-Down Mode

To save even more power, a Power Down mode (see Table 2) can

be invoked by software. In this mode, the oscillator is stopped and

the instruction that invoked Power Down is the last instruction

executed. The on-chip RAM and Special Function Registers retain

1. Pull ALE low while the device is in reset and PSEN is high;

2. Hold ALE low as RST is deactivated.

their values down to 2.0V and care must be taken to return V to

CC

While the device is in ONCE Mode, the Port 0 pins go into a float

state, and the other port pins and ALE and PSEN are weakly pulled

high. The oscillator circuit remains active. While the 8XC51/31 is in

this mode, an emulator or test CPU can be used to drive the circuit.

Normal operation is restored when a normal reset is applied.

the minimum specified operating voltages before the Power Down

Mode is terminated.

For the 87C51 and 80C51 either a hardware reset or external

interrupt can be used to exit from Power Down. Reset redefines all

the SFRs but does not change the on-chip RAM. An external

Table 2. External Pin Status During Idle and Power-Down Modes

MODE

PROGRAM MEMORY

Internal

ALE

PSEN

PORT 0

Data

PORT 1

Data

PORT 2

Data

PORT 3

Data

Idle

1

0

1

0

External

Float

Data

Address

Data

Power-down

Internal

Data

External

Float

Data

8

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

TH2, to be captured into registers RCAP2L and RCAP2H,

Programmable Clock-Out

respectively. In addition, the transition at T2EX causes bit EXF2 in

T2CON to be set, and EXF2 like TF2 can generate an interrupt

(which vectors to the same location as Timer 2 overflow interrupt.

The Timer 2 interrupt service routine can interrogate TF2 and EXF2

to determine which event caused the interrupt). The capture mode is

illustrated in Figure 2 (There is no reload value for TL2 and TH2 in

this mode. Even when a capture event occurs from T2EX, the

counter keeps on counting T2EX pin transitions or osc/12 pulses.).

A 50% duty cycle clock can be programmed to come out on P1.0.

This pin, besides being a regular I/O pin, has two alternate

functions. It can be programmed:

1. to input the external clock for Timer/Counter 2, or

2. to output a 50% duty cycle clock ranging from 61Hz to 4MHz at a

16MHz operating frequency.

To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in

T2CON) must be cleared and bit T20E in T2MOD must be set. Bit

TR2 (T2CON.2) also must be set to start the timer.

Auto-Reload Mode (Up or Down Counter)

In the 16-bit auto-reload mode, Timer 2 can be configured (as either

a timer or counter (C/T2* in T2CON)) then programmed to count up

or down. The counting direction is determined by bit DCEN(Down

Counter Enable) which is located in the T2MOD register (see

Figure 3). When reset is applied the DCEN=0 which means Timer 2

will default to counting up. If DCEN bit is set, Timer 2 can count up

or down depending on the value of the T2EX pin.

The Clock-Out frequency depends on the oscillator frequency and

the reload value of Timer 2 capture registers (RCAP2H, RCAP2L)

as shown in this equation:

Oscillator Frequency

4 (65536 * RCAP2H, RCAP2L)

Where:

Figure 4 shows Timer 2 which will count up automatically since

DCEN=0. In this mode there are two options selected by bit EXEN2

in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH

and sets the TF2 (Overflow Flag) bit upon overflow. This causes the

Timer 2 registers to be reloaded with the 16-bit value in RCAP2L

and RCAP2H. The values in RCAP2L and RCAP2H are preset by

software means.

(RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L

taken as a 16-bit unsigned integer.

In the Clock-Out mode Timer 2 roll-overs will not generate an

interrupt. This is similar to when it is used as a baud-rate generator.

It is possible to use Timer 2 as a baud-rate generator and a clock

generator simultaneously. Note, however, that the baud-rate and the

Clock-Out frequency will be the same.

If EXEN2=1, then a 16-bit reload can be triggered either by an

overflow or by a 1-to-0 transition at input T2EX. This transition also

sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be

generated when either TF2 or EXF2 are 1.

TIMER 2 OPERATION

In Figure 5 DCEN=1 which enables Timer 2 to count up or down.

This mode allows pin T2EX to control the direction of count. When a

logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will

overflow at 0FFFFH and set the TF2 flag, which can then generate

an interrupt, if the interrupt is enabled. This timer overflow also

causes the 16–bit value in RCAP2L and RCAP2H to be reloaded

into the timer registers TL2 and TH2.

Timer 2

Timer 2 is a 16-bit Timer/Counter which can operate as either an

event timer or an event counter, as selected by C/T2* in the special

function register T2CON (see Figure 1). Timer 2 has three operating

modes:Capture, Auto-reload (up or down counting) ,and Baud Rate

Generator, which are selected by bits in the T2CON as shown in

Table 3.

When a logic 0 is applied at pin T2EX this causes Timer 2 to count

down. The timer will underflow when TL2 and TH2 become equal to

the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets

the TF2 flag and causes 0FFFFH to be reloaded into the timer

registers TL2 and TH2.

Capture Mode

In the capture mode there are two options which are selected by bit

EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or

counter (as selected by C/T2* in T2CON) which, upon overflowing

sets bit TF2, the timer 2 overflow bit. This bit can be used to

generate an interrupt (by enabling the Timer 2 interrupt bit in the

IE register). If EXEN2= 1, Timer 2 operates as described above, but

with the added feature that a 1- to -0 transition at external input

T2EX causes the current value in the Timer 2 registers, TL2 and

The external flag EXF2 toggles when Timer 2 underflows or

overflows. This EXF2 bit can be used as a 17th bit of resolution if

needed. The EXF2 flag does not generate an interrupt in this mode

of operation.

Table 3. Timer 2 Operating Modes

RCLK + TCLK

CP/RL2

TR2

1

MODE

16-bit Auto-reload

16-bit Capture

0

1

X

0

1

X

1

Baud rate generator

(off)

0

9

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

(MSB)

(LSB)

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

Symbol

Position

Name and Significance

TF2

T2CON.7

T2CON.6

Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set

when either RCLK or TCLK = 1.

EXF2

Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and

EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2

interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down

counter mode (DCEN = 1).

RCLK

TCLK

T2CON.5

T2CON.4

T2CON.3

Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock

in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock

in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

EXEN2

Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative

transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to

ignore events at T2EX.

TR2

T2CON.2

T2CON.1

Start/stop control for Timer 2. A logic 1 starts the timer.

C/T2

Timer or counter select. (Timer 2)

0 = Internal timer (OSC/12)

1 = External event counter (falling edge triggered).

CP/RL2

T2CON.0

Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When

cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when

EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload

on Timer 2 overflow.

SU00728

Figure 1. Timer/Counter 2 (T2CON) Control Register

OSC

÷ 12

C/T2 = 0

TL2

(8-bits)

TH2

(8-bits)

TF2

C/T2 = 1

T2 Pin

Control

TR2

Capture

Transition

Detector

Timer 2

Interrupt

RCAP2L

RCAP2H

T2EX Pin

EXF2

Control

EXEN2

SU00066

Figure 2. Timer 2 in Capture Mode

10

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

T2MOD

Address = 0C9H

Not Bit Addressable

—

Reset Value = XXXX XX00B

—

6

—

5

—

4

—

3

—

2

T2OE

DCEN

0

Bit

7

1

Symbol

Function

—

Not implemented, reserved for future use.*

Timer 2 Output Enable bit.

T2OE

DCEN

Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.

*

User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.

In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is

indeterminate.

SU00729

Figure 3. Timer 2 Mode (T2MOD) Control Register

OSC

÷ 12

C/T2 = 0

C/T2 = 1

TL2

(8-BITS)

TH2

(8-BITS)

T2 PIN

CONTROL

TR2

RELOAD

TRANSITION

DETECTOR

RCAP2L

RCAP2H

TF2

TIMER 2

INTERRUPT

T2EX PIN

EXF2

CONTROL

EXEN2

SU00067

Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)

11

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

(DOWN COUNTING RELOAD VALUE)

FFH

TOGGLE

EXF2

OSC

÷12

C/T2 = 0

C/T2 = 1

OVERFLOW

TL2

TH2

TF2

INTERRUPT

T2 PIN

CONTROL

TR2

COUNT

DIRECTION

1 = UP

0 = DOWN

RCAP2L

RCAP2H

(UP COUNTING RELOAD VALUE)

T2EX PIN

SU00730

Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)

Timer 1

Overflow

÷ 2

NOTE: OSC. Freq. is divided by 2, not 12.

“0”

“1”

OSC

÷ 2

C/T2 = 0

SMOD

RCLK

“1”

“0”

TL2

(8-bits)

TH2

(8-bits)

C/T2 = 1

T2 Pin

Control

÷ 16

RX Clock

TCLK

“1”

“0”

TR2

Reload

Transition

Detector

RCAP2L

RCAP2H

÷ 16

TX Clock

Timer 2

Interrupt

T2EX Pin

EXF2

Control

EXEN2

Note availability of additional external interrupt.

SU00068

Figure 6. Timer 2 in Baud Rate Generator Mode

12

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

under these conditions, a read or write of TH2 or TL2 may not be

accurate. The RCAP2 registers may be read, but should not be

written to, because a write might overlap a reload and cause write

and/or reload errors. The timer should be turned off (clear TR2)

before accessing the Timer 2 or RCAP2 registers.

Baud Rate Generator Mode

Bits TCLK and/or RCLK in T2CON (Table 3) allow the serial port

transmit and receive baud rates to be derived from either Timer 1 or

Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit

baud rate generator. When TCLK= 1, Timer 2 is used as the serial

port transmit baud rate generator. RCLK has the same effect for the

serial port receive baud rate. With these two bits, the serial port can

have different receive and transmit baud rates – one generated by

Timer 1, the other by Timer 2.

Table 4 shows commonly used baud rates and how they can be

obtained from Timer 2.

Table 4. Timer 2 Generated Commonly Used

Baud Rates

Figure 6 shows the Timer 2 in baud rate generation mode. The baud

rate generation mode is like the auto-reload mode, in that a rollover

in TH2 causes the Timer 2 registers to be reloaded with the 16-bit

value in registers RCAP2H and RCAP2L, which are preset by

software.

Timer 2

Baud Rate

Osc Freq

RCAP2H

RCAP2L

375K

9.6K

2.8K

2.4K

1.2K

300

110

300

110

12MHz

6MHz

FF

FE

FB

F2

FD

F9

FF

D9

B2

64

C8

1E

AF

8F

57

The baud rates in modes 1 and 3 are determined by Timer 2’s

overflow rate given below:

Timer 2 Overflow Rate

Modes 1 and 3 Baud Rates +

16

The timer can be configured for either “timer” or “counter” operation.

In many applications, it is configured for “timer” operation (C/T2*=0).

Timer operation is different for Timer 2 when it is being used as a

baud rate generator.

6MHz

Usually, as a timer it would increment every machine cycle (i.e., 1/12

the oscillator frequency). As a baud rate generator, it increments

every state time (i.e., 1/2 the oscillator frequency). Thus the baud

rate formula is as follows:

Summary Of Baud Rate Equations

Timer 2 is in baud rate generating mode. If Timer 2 is being clocked

through pin T2(P1.0) the baud rate is:

Timer 2 Overflow Rate

Modes 1 and 3 Baud Rates =

Baud Rate +

16

Oscillator Frequency

If Timer 2 is being clocked internally , the baud rate is:

[32 [65536 * (RCAP2H, RCAP2L)]]

Where: (RCAP2H, RCAP2L)= The content of RCAP2H and

RCAP2L taken as a 16-bit unsigned integer.

f_OSC

Baud Rate +

[32 [65536 * (RCAP2H, RCAP2L)]]

The Timer 2 as a baud rate generator mode shown in Figure 6, is

valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a

rollover in TH2 does not set TF2, and will not generate an interrupt.

Thus, the Timer 2 interrupt does not have to be disabled when

Timer 2 is in the baud rate generator mode. Also if the EXEN2

(T2 external enable flag) is set, a 1-to-0 transition in T2EX

(Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but

will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2).

Therefore when Timer 2 is in use as a baud rate generator, T2EX

can be used as an additional external interrupt, if needed.

Where f

= Oscillator Frequency

OSC

To obtain the reload value for RCAP2H and RCAP2L, the above

equation can be rewritten as:

f_OSC

_{RCAP2H, RCAP2L + 65536 *}ǒ

Ǔ

32 Baud Rate

Timer/Counter 2 Set-up

Except for the baud rate generator mode, the values given for

T2CON do not include the setting of the TR2 bit. Therefore, bit TR2

must be set, separately, to turn the timer on. See Table 5 for set-up

of Timer 2 as a timer. Also see Table 6 for set-up of Timer 2 as a

counter.

When Timer 2 is in the baud rate generator mode, one should not try

to read or write TH2 and TL2. As a baud rate generator, Timer 2 is

incremented every state time (osc/2) or asynchronously from pin T2;

13

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

Table 5. Timer 2 as a Timer

T2CON

MODE

INTERNAL CONTROL (Note 1)

EXTERNAL CONTROL (Note 2)

16-bit Auto-Reload

00H

01H

34H

24H

14H

08H

09H

36H

26H

16H

16-bit Capture

Baud rate generator receive and transmit same baud rate

Receive only

Transmit only

Table 6. Timer 2 as a Counter

TMOD

MODE

INTERNAL CONTROL (Note 1)

EXTERNAL CONTROL (Note 2)

16-bit

02H

03H

0AH

0BH

Auto-Reload

NOTES:

1. Capture/reload occurs only on timer/counter overflow.

2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate

generator mode.

SADDR are to b used and which bits are “don’t care”. The SADEN

mask can be logically ANDed with the SADDR to create the “Given”

Enhanced UART

The UART operates in all of the usual modes that are described in

address which the master will use for addressing each of the slaves.

the first section of Data Handbook IC20, 80C51-Based 8-Bit

Use of the Given address allows multiple slaves to be recognized

Microcontrollers. In addition the UART can perform framing error

while excluding others. The following examples will help to show the

detect by looking for missing stop bits, and automatic address

versatility of this scheme:

recognition. The 8XC51/31 UART also fully supports multiprocessor

communication.

Slave 0

Slave 1

SADDR

SADEN

Given

=

1100 0000

1111 1101

1100 00X0

When used for framing error detect the UART looks for missing stop

bits in the communication. A missing bit will set the FE bit in the

SCON register. The FE bit shares the SCON.7 bit with SM0 and the

function of SCON.7 is determined by PCON.6 (SMOD0) (see

Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7

functions as SM0 when SMOD0 is cleared. When used as FE

SCON.7 can only be cleared by software. Refer to Figure 8.

SADDR

SADEN

Given

=

1100 0000

1111 1110

1100 000X

In the above example SADDR is the same and the SADEN data is

used to differentiate between the two slaves. Slave 0 requires a 0 in

bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is

ignored. A unique address for Slave 0 would be 1100 0010 since

slave 1 requires a 0 in bit 1. A unique address for slave 1 would be

1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be

selected at the same time by an address which has bit 0 = 0 (for

slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed

with 1100 0000.

Automatic Address Recognition

Automatic Address Recognition is a feature which allows the UART

to recognize certain addresses in the serial bit stream by using

hardware to make the comparisons. This feature saves a great deal

of software overhead by eliminating the need for the software to

examine every serial address which passes by the serial port. This

feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART

modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be

automatically set when the received byte contains either the “Given”

address or the “Broadcast” address. The 9 bit mode requires that

the 9th information bit is a 1 to indicate that the received information

is an address and not data. Automatic address recognition is shown

in Figure 9.

In a more complex system the following could be used to select

slaves 1 and 2 while excluding slave 0:

Slave 0

Slave 1

Slave 2

SADDR

SADEN

Given

=

1100 0000

1111 1001

1100 0XX0

SADDR

SADEN

Given

=

1110 0000

1111 1010

1110 0X0X

The 8 bit mode is called Mode 1. In this mode the RI flag will be set

if SM2 is enabled and the information received has a valid stop bit

following the 8 address bits and the information is either a Given or

Broadcast address.

SADDR

SADEN

Given

=

1110 0000

1111 1100

1110 00XX

Mode 0 is the Shift Register mode and SM2 is ignored.

Using the Automatic Address Recognition feature allows a master to

selectively communicate with one or more slaves by invoking the

Given slave address or addresses. All of the slaves may be

contacted by using the Broadcast address. Two special Function

Registers are used to define the slave’s address, SADDR, and the

address mask, SADEN. SADEN is used to define which bits in the

In the above example the differentiation among the 3 slaves is in the

lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be

uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and

it can be uniquely addressed by 1110 and 0101. Slave 2 requires

that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0

14

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

and 1 and exclude Slave 2 use address 1110 0100, since it is

necessary to make bit 2 = 1 to exclude slave 2.

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR

address 0B9H) are leaded with 0s. This produces a given address

of all “don’t cares” as well as a Broadcast address of all “don’t

cares”. This effectively disables the Automatic Addressing mode and

allows the microcontroller to use standard 80C51 type UART drivers

which do not make use of this feature.

The Broadcast Address for each slave is created by taking the

logical OR of SADDR and SADEN. Zeros in this result are trended

as don’t-cares. In most cases, interpreting the don’t-cares as ones,

the broadcast address will be FF hexadecimal.

SCON Address = 98H

Reset Value = 0000 0000B

Bit Addressable

SM0/FE

SM1

SM2

REN

TB8

RB8

Tl

Rl

Bit:

7

6

5

4

3

2

1

0

(SMOD0 = 0/1)*

Symbol

FE

Function

Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid

frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.

SM0

SM1

Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)

Serial Port Mode Bit 1

SM0

SM1

Mode

Description

Baud Rate**

f /12

OSC

0

1

0

1

0

1

0

1

2

3

shift register

8-bit UART

9-bit UART

variable

/64 or f

f

/32

OSC

variable

SM2

Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the

received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.

In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a

Given or Broadcast Address. In Mode 0, SM2 should be 0.

REN

TB8

RB8

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.

In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.

In Mode 0, RB8 is not used.

Tl

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the

other modes, in any serial transmission. Must be cleared by software.

Rl

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in

the other modes, in any serial reception (except see SM2). Must be cleared by software.

NOTE:

*SMOD0 is located at PCON6.

**f = oscillator frequency

OSC

SU00043

Figure 7. SCON: Serial Port Control Register

15

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

D0

D1

D2

D3

D4

D5

D6

D7

D8

START

BIT

DATA BYTE

ONLY IN

MODE 2, 3

STOP

BIT

SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)

SM0 TO UART MODE CONTROL

SCON

(98H)

SM0 / FE

SMOD1

SM1

SM2

REN

POF

TB8

GF1

RB8

GF0

TI

RI

PCON

(87H)

SMOD0

–

PD

IDL

0 : SCON.7 = SM0

1 : SCON.7 = FE

SU01191

Figure 8. UART Framing Error Detection

D0

D1

D2

D3

D4

D5

D6

D7

D8

SCON

(98H)

SM0

SM1

SM2

REN

1

TB8

X

RB8

TI

RI

1

0

1

RECEIVED ADDRESS D0 TO D7

PROGRAMMED ADDRESS

COMPARATOR

IN UART MODE 2 OR MODE 3 AND SM2 = 1:

INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”

– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES

– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.

SU00045

Figure 9. UART Multiprocessor Communication, Automatic Address Recognition

16

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

An interrupt will be serviced as long as an interrupt of equal or

higher priority is not already being serviced. If an interrupt of equal

or higher level priority is being serviced, the new interrupt will wait

until it is finished before being serviced. If a lower priority level

interrupt is being serviced, it will be stopped and the new interrupt

serviced. When the new interrupt is finished, the lower priority level

interrupt that was stopped will be completed.

Interrupt Priority Structure

The 8XC51 and 80C31 only have a 6-source four-level interrupt

structure. They are the IE, IP and IPH. (See Figures 10, 11, and 12.)

The IPH (Interrupt Priority High) register that makes the four-level

interrupt structure possible. The IPH is located at SFR address B7H.

The structure of the IPH register and a description of its bits is

shown in Figure 12.

The function of the IPH SFR is simple and when combined with the

IP SFR determines the priority of each interrupt. The priority of each

interrupt is determined as shown in the following table:

PRIORITY BITS

INTERRUPT PRIORITY LEVEL

IPH.x

IP.x

0

1

Level 0 (lowest priority)

Level 1

1

0

Level 2

1

Level 3 (highest priority)

Table 7.

Interrupt Table

SOURCE

POLLING PRIORITY

REQUEST BITS

HARDWARE CLEAR?

VECTOR ADDRESS

1

2

X0

T0

X1

T1

SP

T2

1

2

3

4

5

6

IE0

TP0

N (L) Y (T)

03H

0BH

13H

1BH

23H

2BH

Y

IE1

N (L) Y (T)

TF1

Y

N

RI, TI

TF2, EXF2

NOTES:

1. L = Level activated

2. T = Transition activated

7

6

5

4

3

2

1

0

IE (0A8H)

EA

—

ET2

ES

ET1

EX1

ET0

EX0

Enable Bit = 1 enables the interrupt.

Enable Bit = 0 disables it.

BIT

SYMBOL FUNCTION

IE.7

EA

Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually

enabled or disabled by setting or clearing its enable bit.

Not implemented. Reserved for future use.

Timer 2 interrupt enable bit.

Serial Port interrupt enable bit.

Timer 1 interrupt enable bit.

IE.6

IE.5

IE.4

IE.3

IE.2

IE.1

IE.0

—

ET2

ES

ET1

EX1

ET0

EX0

External interrupt 1 enable bit.

Timer 0 interrupt enable bit.

External interrupt 0 enable bit.

SU00571

Figure 10. IE Registers

17

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

7

6

5

4

3

2

1

0

IP (0B8H)

—

PT2

PS

PT1

PX1

PT0

PX0

Priority Bit = 1 assigns higher priority

Priority Bit = 0 assigns lower priority

BIT

IP.7

IP.6

IP.5

IP.4

IP.3

IP.2

IP.1

IP.0

SYMBOL FUNCTION

—

Not implemented, reserved for future use.

Timer 2 interrupt priority bit.

Serial Port interrupt priority bit.

Timer 1 interrupt priority bit.

PT2

PS

PT1

PX1

PT0

PX0

External interrupt 1 priority bit.

Timer 0 interrupt priority bit.

External interrupt 0 priority bit.

SU00572

Figure 11. IP Registers

7

6

5

4

3

2

1

0

IPH (B7H)

—

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

Priority Bit = 1 assigns higher priority

Priority Bit = 0 assigns lower priority

BIT

SYMBOL FUNCTION

IPH.7

IPH.6

IPH.5

IPH.4

IPH.3

IPH.2

IPH.1

IPH.0

—

Not implemented, reserved for future use.

Timer 2 interrupt priority bit high.

Serial Port interrupt priority bit high.

Timer 1 interrupt priority bit high.

External interrupt 1 priority bit high.

Timer 0 interrupt priority bit high.

External interrupt 0 priority bit high.

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

SU01058

Figure 12. IPH Registers

18

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

Note that bit 2 is not writable and is always read as a zero. This

allows the DPS bit to be quickly toggled simply by executing an INC

DPTR insstruction without affecting the WOPD or LPEP bits.

Reduced EMI Mode

The AO bit (AUXR.0) in the AUXR register when set disables the

ALE output.

Reduced EMI Mode

AUXR (8EH)

DPS

BIT0

7

–

6

–

5

–

4

–

3

–

2

–

1

–

0

AUXR1

DPTR1

DPTR0

AO

AUXR.0

AO

Turns off ALE output.

DPH

DPL

(83H)

(82H)

EXTERNAL

DATA

MEMORY

Dual DPTR

SU00745A

The dual DPTR structure (see Figure 13) enables a way to specify

the address of an external data memory location. There are two

16-bit DPTR registers that address the external memory, and a

single bit called DPS = AUXR1/bit0 that allows the program code to

switch between them.

Figure 13.

DPTR Instructions

The instructions that refer to DPTR refer to the data pointer that is

currently selected using the AUXR1/bit 0 register. The six

instructions that use the DPTR are as follows:

• New Register Name: AUXR1#

• SFR Address: A2H

• Reset Value: xxx000x0B

INC DPTR

Increments the data pointer by 1

AUXR1 (A2H)

MOV DPTR, #data16 Loads the DPTR with a 16-bit constant

7

–

6

–

5

–

4

3

2

0

1

–

0

MOV A, @ A+DPTR

MOVX A, @ DPTR

Move code byte relative to DPTR to ACC

LPEP

WUPD

DPS

Move external RAM (16-bit address) to

ACC

Where:

DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.

MOVX @ DPTR , A

JMP @ A + DPTR

Move ACC to external RAM (16-bit

address)

Select Reg

DPS

Jump indirect relative to DPTR

DPTR0

DPTR1

0

1

The data pointer can be accessed on a byte-by-byte basis by

specifying the low or high byte in an instruction which accesses the

SFRs. See application note AN458 for more details.

The DPS bit status should be saved by software when switching

between DPTR0 and DPTR1.

19

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

1, 2, 3

ABSOLUTE MAXIMUM RATINGS

PARAMETER

Operating temperature under bias

RATING

0 to +70 or –40 to +85

–65 to +150

0 to +13.0

–0.5 to +6.5

15

UNIT

°C

V

Storage temperature range

Voltage on EA/V pin to V

PP

SS

Voltage on any other pin to V

V

SS

Maximum I per I/O pin

mA

W

OL

Power dissipation (based on package heat transfer limitations, not device power consumption)

NOTES:

1.5

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section

of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise

SS

noted.

AC ELECTRICAL CHARACTERISTICS

T

amb

= 0°C to +70°C or –40°C to +85°C

CLOCK FREQUENCY

RANGE –f

SYMBOL

1/t

FIGURE

PARAMETER

MIN

MAX

UNIT

29

Oscillator frequency

CLCL

Speed versions : S (16MHz)

U (33MHz)

0

16

33

MHz

20

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

DC ELECTRICAL CHARACTERISTICS

T

amb

= 0°C to +70°C or –40°C to +85°C, V = 2.7V to 5.5V, V = 0V (16MHz devices)

CC SS

LIMITS

TEST

CONDITIONS

SYMBOL

PARAMETER

UNIT

1

MIN

–0.5

TYP

MAX

4.0V < V < 5.5V

0.2V –0.1

V

CC

V

IL

Input low voltage

2.7V<V < 4.0V

0.7

CC

V

Input high voltage (ports 0, 1, 2, 3, EA)

Input high voltage, XTAL1, RST

0.2V +0.9

V

+0.5

IH

CC

0.7V

IH1

CC

V

OL

= 2.7V

= 1.6mA

CC

8

V

Output low voltage, ports 1, 2,

0.4

V

OL

2

I

V

CC

= 2.7V

8, 7

V

OL1

Output low voltage, port 0, ALE, PSEN

0.4

2

= 3.2mA

OL

V

CC

= 2.7V

= –20µA

V

CC

V

CC

V

CC

– 0.7

I

OH

3

V

Output high voltage, ports 1, 2, 3

OH

V

CC

= 4.5V

= –30µA

I

OH

Output high voltage (port 0 in external bus mode),

V

CC

= 2.7V

= –3.2mA

V

OH1

9

3

ALE , PSEN

I

OH

I

Logical 0 input current, ports 1, 2, 3

Logical 1-to-0 transition current, ports 1, 2, 3

Input leakage current, port 0

V

= 0.4V

= 2.0V

–1

–50

–650

±10

µA

IL

IN

6

TL

See note 4

I

0.45 < V < V – 0.3

LI

IN

CC

Power supply current (see Figure 21):

Active mode @ 16MHz

Idle mode @ 16MHz

Power-down mode or clock stopped (see Figure 25

for conditions)

See note 5

CC

µA

T

= 0°C to 70°C

3

50

75

amb

T

= –40°C to +85°C

amb

R

C

Internal reset pull-down resistor

40

225

15

kΩ

RST

IO

10

Pin capacitance (except EA)

pF

NOTES:

1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due

OL

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the

worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify

ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no

OL

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the V –0.7 specification when the

OH

CC

address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V is approximately 2V.

IN

5. See Figures 22 through 25 for I test conditions.

CC

Active mode:

Idle mode:

I

= 0.9 × FREQ. + 1.1mA

= 0.18 × FREQ. +1.01mA; See Figure 21.

CC

6. This value applies to T

= 0°C to +70°C. For T = –40°C to +85°C, I = –750µA.

amb TL

amb

7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

8. Under steady state (non-transient) conditions, I must be externally limited as follows:

OL

Maximum I per port pin:

15mA (*NOTE: This is 85°C specification.)

OL

Maximum I per 8-bit port:

26mA

71mA

OL

Maximum total I for all outputs:

OL

If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

OL

test conditions.

9. ALE is tested to V

, except when ALE is off then V is the voltage specification.

OH

OH1

10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF

(except EA is 25pF).

21

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

DC ELECTRICAL CHARACTERISTICS

T

amb

= 0°C to +70°C or –40°C to +85°C, 33MHz devices; 5V ±10%; V = 0V

SS

LIMITS

TEST

CONDITIONS

SYMBOL

PARAMETER

UNIT

1

MIN

TYP

MAX

0.2V –0.1

V

Input low voltage

4.5V < V < 5.5V

–0.5

V

IL

CC

Input high voltage (ports 0, 1, 2, 3, EA)

Input high voltage, XTAL1, RST

0.2V +0.9

V

CC

V

CC

+0.5

IH

CC

0.7V

IH1

CC

V

OL

= 4.5V

= 1.6mA

CC

8

V

Output low voltage, ports 1, 2, 3

0.4

V

OL

2

I

V

CC

= 4.5V

7, 8

Output low voltage, port 0, ALE, PSEN

0.4

OL1

OH

2

= 3.2mA

OL

V

CC

= 4.5V

= –30µA

3

Output high voltage, ports 1, 2, 3

V

– 0.7

CC

I

OH

Output high voltage (port 0 in external bus mode),

V

CC

= 4.5V

= –3.2mA

V

OH1

CC

9

3

ALE , PSEN

I

OH

I

Logical 0 input current, ports 1, 2, 3

Logical 1-to-0 transition current, ports 1, 2, 3

Input leakage current, port 0

V

= 0.4V

= 2.0V

–1

–50

–650

±10

µA

IL

IN

6

TL

See note 4

I

0.45 < V < V – 0.3

LI

IN

CC

Power supply current (see Figure 21):

Active mode (see Note 5)

See note 5

CC

Idle mode (see Note 5)

Power-down mode or clock stopped (see Figure 25

for conditions)

T

= 0°C to 70°C

= –40°C to +85°C

3

50

75

µA

amb

T

amb

R

C

Internal reset pull-down resistor

40

225

15

kΩ

RST

IO

10

Pin capacitance (except EA)

pF

NOTES:

1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due

OL

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the

worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify

ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no

OL

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the V –0.7 specification when the

OH

CC

address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V is approximately 2V.

IN

5. See Figures 22 through 25 for I test conditions.

CC

Active mode:

Idle mode:

I

= 0.9 × FREQ. + 1.1mA

= 0.18 × FREQ. +1.0mA; See Figure 21.

CC(MAX)

6. This value applies to T

= 0°C to +70°C. For T = –40°C to +85°C, I = –750µA.

amb TL

amb

7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

8. Under steady state (non-transient) conditions, I must be externally limited as follows:

OL

Maximum I per port pin:

15mA (*NOTE: This is 85°C specification.)

OL

Maximum I per 8-bit port:

26mA

71mA

OL

Maximum total I for all outputs:

OL

If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

OL

test conditions.

9. ALE is tested to V

, except when ALE is off then V is the voltage specification.

OH

OH1

10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF

(except EA is 25pF).

22

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

AC ELECTRICAL CHARACTERISTICS

1, 2, 3

T

amb

= 0°C to +70°C or –40°C to +85°C, V = +2.7V to +5.5V, V = 0V

CC SS

16MHz CLOCK

VARIABLE CLOCK

SYMBOL

1/t

FIGURE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

5

14

Oscillator frequency

Speed versions :S

CLCL

3.5

16

MHz

ns

t

14

ALE pulse width

85

22

32

2t

–40

LHLL

CLCL

Address valid to ALE low

Address hold after ALE low

ALE low to valid instruction in

ALE low to PSEN low

t

–40

AVLL

LLAX

LLIV

CLCL

t

–30

150

82

4t

3t

–100

CLCL

32

t

–30

LLPL

PLPH

PLIV

PXIX

PXIZ

CLCL

PSEN pulse width

142

3t

–45

CLCL

PSEN low to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address to valid instruction in

PSEN low to address float

–105

CLCL

0

37

207

10

t

–25

CLCL

4

5t

–105

AVIV

CLCL

10

PLAZ

Data Memory

t

15, 16

16

RD pulse width

275

6t

–100

ns

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

CLCL

WR pulse width

6t

CLCL

RD low to valid data in

Data hold after RD

147

5t

–165

CLCL

0

Data float after RD

65

2t

–60

CLCL

ALE low to valid data in

Address to valid data in

ALE low to RD or WR low

Address valid to WR low or RD low

Data valid to WR transition

Data hold after WR

350

397

239

8t

–150

–165

CLCL

9t

AVDV

LLWL

137

122

13

3t

–50

3t

+50

CLCL

4t

t

–130

–50

AVWL

QVWX

WHQX

QVWH

RLAZ

WHLH

CLCL

13

t

–50

Data valid to WR high

RD low to address float

RD or WR high to ALE high

287

7t

–150

15, 16

0

23

103

t

–40

t

+40

CLCL

External Clock

t

18

High time

Low time

Rise time

Fall time

20

t

–t

ns

CHCX

CLCX

CLCH

CHCL

CLCL CLCX

t

–t

CLCL CHCX

20

Shift Register

t

17

Serial port clock cycle time

750

492

8

12t

ns

XLXL

CLCL

Output data setup to clock rising edge

10t

–133

QVXH

XHQX

XHDX

XHDV

CLCL

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

2t

CLCL

–117

0

492

10t

–133

CLCL

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

3. Interfacing the 8XC51 and 80C31 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to

Port 0 drivers.

4. See application note AN457 for external memory interface.

5. Parts are guaranteed to operate down to 0Hz.

23

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

AC ELECTRICAL CHARACTERISTICS

1, 2, 3

T

amb

= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V

CC SS

4

VARIABLE CLOCK

16MHz to f

33MHz CLOCK

max

SYMBOL

FIGURE

14

PARAMETER

MIN

2t –40

CLCL

MAX

MIN

21

5

MAX

UNIT

ns

t

ALE pulse width

LHLL

AVLL

LLAX

LLIV

14

Address valid to ALE low

Address hold after ALE low

ALE low to valid instruction in

ALE low to PSEN low

t

–25

ns

CLCL

14

ns

14

4t

3t

–65

–60

55

30

ns

CLCL

14

t

–25

5

ns

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLCL

14

PSEN pulse width

3t

CLCL

–45

45

ns

14

PSEN low to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address to valid instruction in

PSEN low to address float

ns

CLCL

14

0

ns

14

t

–25

5

ns

CLCL

14

5t

–80

70

10

ns

CLCL

14

10

ns

Data Memory

t

15, 16

16

RD pulse width

6t

–100

82

ns

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

CLCL

WR pulse width

6t

CLCL

RD low to valid data in

Data hold after RD

5t

2t

–90

–28

60

CLCL

0

Data float after RD

32

90

CLCL

ALE low to valid data in

Address to valid data in

ALE low to RD or WR low

Address valid to WR low or RD low

Data valid to WR transition

Data hold after WR

8t

–150

–165

CLCL

9t

105

140

AVDV

LLWL

3t

–50

–75

3t

CLCL

+50

40

45

0

CLCL

4t

AVWL

QVWX

WHQX

QVWH

RLAZ

WHLH

CLCL

t

–30

CLCL

t

–25

5

Data valid to WR high

RD low to address float

RD or WR high to ALE high

7t

–130

80

15, 16

0

t

–25

t

+25

5

55

CLCL

External Clock

t

18

High time

Low time

Rise time

Fall time

0.38t

t –t

CLCL CLCX

ns

CHCX

CLCX

CLCH

CHCL

CLCL

t

–t

CLCL

CLCL CHCX

5

Shift Register

t

17

Serial port clock cycle time

12t

360

167

ns

XLXL

CLCL

Output data setup to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

10t

–133

–80

QVXH

XHQX

XHDX

XHDV

CLCL

2t

CLCL

0

10t

–133

167

CLCL

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

3. Interfacing the 8XC51 and 80C31 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to

Port 0 drivers.

4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz

“AC Electrical Characteristics”, page 23.

5. Parts are guaranteed to operate down to 0Hz.

24

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always

‘t’ (= time). The other characters, depending on their positions,

indicate the name of a signal or the logical status of that signal. The

designations are:

P – PSEN

Q – Output data

R – RD signal

t – Time

A – Address

V – Valid

C – Clock

W– WR signal

D – Input data

H – Logic level high

X – No longer a valid logic level

Z – Float

I – Instruction (program memory contents)

L – Logic level low, or ALE

Examples: t

= Time for address valid to ALE low.

=Time for ALE low to PSEN low.

AVLL

t

LLPL

t

LHLL

ALE

t

LLPL

AVLL

t

PLPH

t

LLIV

t

PLIV

PSEN

t

LLAX

t

PXIZ

t

PLAZ

t

PXIX

A0–A7

INSTR IN

A0–A7

PORT 0

PORT 2

t

AVIV

A0–A15

A8–A15

SU00006

Figure 14. External Program Memory Read Cycle

ALE

PSEN

RD

t

WHLH

t

LLDV

t

LLWL

RLRH

t

RHDZ

t

LLAX

t

RLDV

AVLL

t

RLAZ

t

RHDX

A0–A7

FROM RI OR DPL

PORT 0

PORT 2

DATA IN

A0–A7 FROM PCL

INSTR IN

t

AVWL

t

AVDV

P2.0–P2.7 OR A8–A15 FROM DPF

A0–A15 FROM PCH

SU00025

Figure 15. External Data Memory Read Cycle

25

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

ALE

t

WHLH

PSEN

t

WLWH

LLWL

WR

t

LLAX

t

WHQX

t

AVLL

QVWX

t

QVWH

A0–A7

FROM RI OR DPL

PORT 0

PORT 2

DATA OUT

A0–A7 FROM PCL

INSTR IN

t

AVWL

P2.0–P2.7 OR A8–A15 FROM DPF

A0–A15 FROM PCH

SU00026

Figure 16. External Data Memory Write Cycle

INSTRUCTION

ALE

0

1

2

3

4

5

6

7

8

t

XLXL

CLOCK

t

XHQX

t

QVXH

OUTPUT DATA

0

1

2

3

4

5

6

7

WRITE TO SBUF

t

XHDX

t

SET TI

VALID

XHDV

INPUT DATA

CLEAR RI

VALID

SET RI

SU00027

Figure 17. Shift Register Mode Timing

V

–0.5

CC

0.7V

CC

0.45V

0.2V

–0.1

t

CHCX

t

CHCL

CLCX

CLCH

t

CLCL

SU00009

Figure 18. External Clock Drive

26

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

V

–0.5

CC

V

+0.1V

LOAD

V

–0.1V

TIMING

REFERENCE

POINTS

OH

0.2V

+0.9

–0.1

CC

V

LOAD

CC

–0.1V

LOAD

+0.1V

OL

0.45V

NOTE:

For timing purposes, a port is no longer floating when a 100mV change from

load voltage occurs, and begins to float when a 100mV change from the loaded

AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.

Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.

CC

IH

IL

V

/V level occurs. I /I ≥ ±20mA.

OH OL

SU00717

SU00718

Figure 19. AC Testing Input/Output

Figure 20. Float Waveform

35

30

25

MAX ACTIVE

MODE (EXCEPT

8XC51RD+)

I

ACTIVE MODE

(8XC51RD+)

= 0.9 X FREQ + 2.1

CCMAX

20

15

10

5

I

MAX = 0.9 X

CC

I

FREQ. + 1.1

CCMAX

TYP ACTIVE MODE

MAX IDLE MODE

TYP IDLE MODE

24 28 32

FREQ AT XTAL1 (MHz)

4

8

12

16

20

36

SU00837A

Figure 21. I vs. FREQ

CC

Valid only within frequency specifications of the device under test

27

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

V

CC

I

CC

V

CC

V

RST

V

CC

P0

EA

P0

EA

RST

(NC)

XTAL2

XTAL1

(NC)

XTAL2

XTAL1

CLOCK SIGNAL

V

SS

SU00719

SU00720

Figure 22. I Test Condition, Active Mode

Figure 23. I Test Condition, Idle Mode

CC

All other pins are disconnected

V

–0.5

CC

0.7V

CC

–0.1

0.45V

0.2V

CC

t

CHCX

t

CLCH

CHCL

CLCX

t

CLCL

SU00009

Figure 24. Clock Signal Waveform for I Tests in Active and Idle Modes

CC

t

= t

= 5ns

CHCL

CLCH

V

CC

I

CC

V

CC

V

RST

P0

EA

(NC)

XTAL2

XTAL1

V

SS

SU00016

Figure 25. I Test Condition, Power Down Mode

CC

All other pins are disconnected. V = 2V to 5.5V

CC

28

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

If the 64 byte encryption table has been programmed, the data

presented at port 0 will be the exclusive NOR of the program byte

with one of the encryption bytes. The user will have to know the

encryption table contents in order to correctly decode the verification

data. The encryption table itself cannot be read out.

EPROM CHARACTERISTICS

All these devices can be programmed by using a modified Improved

Quick-Pulse Programming algorithm. It differs from older methods

in the value used for V (programming supply voltage) and in the

PP

width and number of the ALE/PROG pulses.

Reading the Signature Bytes

The family contains two signature bytes that can be read and used

by an EPROM programming system to identify the device. The

signature bytes identify the device as being manufactured by

Philips.

The signature bytes are read by the same procedure as a normal

verification of locations 030H and 031H, except that P3.6 and P3.7

need to be pulled to a logic low. The values are:

(030H) = 15H indicates manufactured by Philips

(031H) = 92H indicates 87C51

Table 8 shows the logic levels for reading the signature byte, and for

programming the program memory, the encryption table, and the

security bits. The circuit configuration and waveforms for quick-pulse

programming are shown in Figures 26 and 27. Figure 28 shows the

circuit configuration for normal program memory verification.

Program/Verify Algorithms

Any algorithm in agreement with the conditions listed in Table 8, and

which satisfies the timing specifications, is suitable.

Quick-Pulse Programming

Erasure Characteristics

The setup for microcontroller quick-pulse programming is shown in

Figure 26. Note that the device is running with a 4 to 6MHz

oscillator. The reason the oscillator needs to be running is that the

device is executing internal address and program data transfers.

Erasure of the EPROM begins to occur when the chip is exposed to

light with wavelengths shorter than approximately 4,000 angstroms.

Since sunlight and fluorescent lighting have wavelengths in this

range, exposure to these light sources over an extended time (about

1 week in sunlight, or 3 years in room level fluorescent lighting)

could cause inadvertent erasure. For this and secondary effects,

it is recommended that an opaque label be placed over the

window. For elevated temperature or environments where solvents

are being used, apply Kapton tape Fluorglas part number 2345–5, or

equivalent.

The address of the EPROM location to be programmed is applied to

ports 1 and 2, as shown in Figure 26. The code byte to be

programmed into that location is applied to port 0. RST, PSEN and

pins of ports 2 and 3 specified in Table 8 are held at the ‘Program

Code Data’ levels indicated in Table 8. The ALE/PROG is pulsed

low 5 times as shown in Figure 27.

The recommended erasure procedure is exposure to ultraviolet light

To program the encryption table, repeat the 5 pulse programming

sequence for addresses 0 through 1FH, using the ‘Pgm Encryption

Table’ levels. Do not forget that after the encryption table is

programmed, verification cycles will produce only encrypted data.

2

(at 2537 angstroms) to an integrated dose of at least 15W-s/cm .

2

Exposing the EPROM to an ultraviolet lamp of 12,000µW/cm rating

for 20 to 39 minutes, at a distance of about 1 inch, should be

sufficient.

To program the security bits, repeat the 5 pulse programming

sequence using the ‘Pgm Security Bit’ levels. After one security bit is

programmed, further programming of the code memory and

encryption table is disabled. However, the other security bits can still

be programmed.

Erasure leaves the array in an all 1s state.

Security Bits

With none of the security bits programmed the code in the program

memory can be verified. If the encryption table is programmed, the

code will be encrypted when verified. When only security bit 1 (see

Table 9) is programmed, MOVC instructions executed from external

program memory are disabled from fetching code bytes from the

internal memory, EA is latched on Reset and all further programming

of the EPROM is disabled. When security bits 1 and 2 are

programmed, in addition to the above, verify mode is disabled.

When all three security bits are programmed, all of the conditions

above apply and all external program memory execution is disabled.

Note that the EA/V pin must not be allowed to go above the

PP

maximum specified V level for any amount of time. Even a narrow

PP

glitch above that voltage can cause permanent damage to the

device. The V source should be well regulated and free of glitches

PP

and overshoot.

Program Verification

If security bits 2 and 3 have not been programmed, the on-chip

program memory can be read out for program verification. The

address of the program memory locations to be read is applied to

ports 1 and 2 as shown in Figure 28. The other pins are held at the

‘Verify Code Data’ levels indicated in Table 8. The contents of the

address location will be emitted on port 0. External pull-ups are

required on port 0 for this operation.

Encryption Array

64 bytes of encryption array are initially unprogrammed (all 1s).

Trademark phrase of Intel Corporation.

2000 Jan 20

29

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

Table 8. EPROM Programming Modes

MODE

Read signature

RST

1

PSEN

ALE/PROG

EA/V

P2.7

P2.6

P3.7

P3.6

PP

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Program code data

Verify code data

1

0*

1

V

PP

1

Pgm encryption table

Pgm security bit 1

Pgm security bit 2

1

0*

V

PP

1

V

1

Pgm security bit 3

1

NOTES:

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.

2. V = 12.75V ±0.25V.

PP

3. V = 5V±10% during programming and verification.

CC

*

ALE/PROG receives 5 programming pulses for code data (also for user array; 5 pulses for encryption or security bits) while V is held at

PP

12.75V. Each programming pulse is low for 100µs (±10µs) and high for a minimum of 10µs.

Table 9. Program Security Bits for EPROM Devices

1, 2

PROGRAM LOCK BITS

SB1

SB2

SB3

PROTECTION DESCRIPTION

1

2

U

No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if

programmed.)

P

U

MOVC instructions executed from external program memory are disabled from fetching code bytes

from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM

is disabled.

3

P

U

P

Same as 2, also verify is disabled.

4

Same as 3, external execution is disabled. Internal data RAM is not accessible.

NOTES:

1. P – programmed. U – unprogrammed.

2. Any other combination of the security bits is not defined.

30

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

+5V

V

CC

P0

A0–A7

P1

PGM DATA

1

RST

P3.6

+12.75V

EA/V

PP

5 PULSES TO GROUND

ALE/PROG

PSEN

P3.7

0

1

EPROM/OTP

XTAL2

P2.7

0

P2.6

4–6MHz

XTAL1

A8–A13

P2.0–P2.5

V

SS

SU00873

Figure 26. Programming Configuration

5 PULSES

1

0

1

2

3

4

5

ALE/PROG:

SEE EXPLODED VIEW BELOW

t

= 10µs MIN

GHGL

t

= 100µs±10µs

GLGH

1

0

1

ALE/PROG:

SU00875

Figure 27. PROG Waveform

+5V

V

CC

P0

A0–A7

PGM DATA

P1

1

RST

P3.6

1

0

EA/V

PP

ALE/PROG

PSEN

P3.7

EPROM/OTP

0

ENABLE

XTAL2

P2.7

P2.6

P2.0–P2.5

P3.4

4–6MHz

XTAL1

A8–A13

A14

V

SS

SU00839A

Figure 28. Program Verification

31

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

T

amb

= 21°C to +27°C, V = 5V±10%, V = 0V (See Figure 29)

CC SS

SYMBOL

PARAMETER

MIN

MAX

UNIT

V

PP

Programming supply voltage

Programming supply current

Oscillator frequency

12.5

13.0

1

I

PP

50

mA

MHz

1/t

CLCL

4

6

t

Address setup to PROG low

Address hold after PROG

Data setup to PROG low

Data hold after PROG

48t

AVGL

CLCL

48t

GHAX

DVGL

GHDX

EHSH

SHGL

GHSL

GLGH

AVQV

ELQZ

EHQZ

GHGL

P2.7 (ENABLE) high to V

PP

V

PP

V

PP

setup to PROG low

hold after PROG

10

90

µs

PROG width

110

Address to data valid

48t

CLCL

ENABLE low to data valid

Data float after ENABLE

PROG high to PROG low

48t

0

10

µs

NOTE:

1. Not tested.

PROGRAMMING*

VERIFICATION*

ADDRESS

P1.0–P1.7

P2.0–P2.5

P3.4

ADDRESS

(A0 – A14)

t

AVQV

PORT 0

P0.0 – P0.7

(D0 – D7)

DATA IN

DATA OUT

t

DVGL

GHDX

GHAX

t

AVGL

ALE/PROG

t

GLGH

GHGL

t

SHGL

GHSL

LOGIC 1

EA/V

PP

LOGIC 0

t

EHSH

ELQV

EHQZ

P2.7

**

SU00871

NOTES:

*

FOR PROGRAMMING CONFIGURATION SEE FIGURE 26.

FOR VERIFICATION CONDITIONS SEE FIGURE 28.

** SEE TABLE 8.

Figure 29. EPROM Programming and Verification

32

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

MASK ROM DEVICES

from the internal memory, EA is latched on Reset and all further

programming of the EPROM is disabled. When security bits 1 and 2

are programmed, in addition to the above, verify mode is disabled.

Security Bits

With none of the security bits programmed the code in the program

memory can be verified. If the encryption table is programmed, the

code will be encrypted when verified. When only security bit 1 (see

Table 10) is programmed, MOVC instructions executed from

external program memory are disabled from fetching code bytes

Encryption Array

64 bytes of encryption array are initially unprogrammed (all 1s).

Table 10. Program Security Bits

1, 2

PROGRAM LOCK BITS

SB1

SB2

PROTECTION DESCRIPTION

1

U

No Program Security features enabled.

(Code verify will still be encrypted by the Encryption Array if programmed.)

2

P

U

MOVC instructions executed from external program memory are disabled from fetching code bytes from

internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled.

NOTES:

1. P – programmed. U – unprogrammed.

2. Any other combination of the security bits is not defined.

ROM CODE SUBMISSION

When submitting ROM code for the 80C51, the following must be specified:

1. 4k byte user ROM data

2. 64 byte ROM encryption key

3. ROM security bits.

ADDRESS

0000H to 0FFFH

1000H to 103FH

1040H

CONTENT

DATA

KEY

BIT(S)

7:0

0

COMMENT

User ROM Data

ROM Encryption Key

ROM Security Bit 1

ROM Security Bit 2

SEC

1040H

SEC

1

Security Bit 1: When programmed, this bit has two effects on masked ROM parts:

1. External MOVC is disabled, and

2. EA is latched on Reset.

Security Bit 2: When programmed, this bit inhibits Verify User ROM.

NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled.

If the ROM Code file does not include the options, the following information must be included with the ROM code.

For each of the following, check the appropriate box, and send to Philips along with the code:

Security Bit #1:

Security Bit #2:

Encryption:

V Enabled

V No

V Disabled

V Yes

If Yes, must send key file.

33

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

DIP40: plastic dual in-line package; 40 leads (600 mil)

SOT129-1

34

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

35

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

SOT307-2

36

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

NOTES

37

2000 Jan 20

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

80C51/87C51/80C31

Data sheet status

[1]

Data sheet

status

Product

status

Definition

Objective

specification

Development

This data sheet contains the design target or goal specifications for product development.

Specification may change in any manner without notice.

Preliminary

specification

Qualification

This data sheet contains preliminary data, and supplementary data will be published at a later date.

Philips Semiconductors reserves the right to make changes at any time without notice in order to

improve design and supply the best possible product.

Product

specification

Production

This data sheet contains final specifications. Philips Semiconductors reserves the right to make

changes at any time without notice in order to improve design and supply the best possible product.

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Copyright Philips Electronics North America Corporation 2000

Sunnyvale, California 94088–3409

Telephone 800-234-7381

Date of release: 01-00

Document order number:

9397 750 06795

Philips

Semiconductors

38

2000 Jan 20


型号：	P87C51TFAA-T
厂家：	NXP
描述：	IC 8-BIT, OTPROM, MICROCONTROLLER, PQCC44, Microcontroller 外围集成电路光电二极管微控制器可编程只读存储器时钟
文件：	总38页 (文件大小：353K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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