P87C528EBBA [NXP]
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| 型号： | P87C528EBBA |
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NXP |
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INTEGRATED CIRCUITS
87C524/87C528
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
Product specification
1999 Jul 23
Replaces data sheets 87C524 of 1998 May 01 and 87C528 of 1998 May 01
IC28 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
FEATURES
• 80C51 instruction set
– 512 × 8 RAM
– Memory addressing capability
64k ROM and 64k RAM
– Three 16-bit counter/timers
– On-chip watchdog timer with oscillator
– Full duplex UART
2
– I C serial interface
DESCRIPTION
• Power control modes:
– Idle mode
The 87C528 single-chip 8-bit microcontroller is manufactured in an
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The 87C528 has the same instruction set as
the 80C51. Three versions of the derivative exist:
– Power-down mode
– Warm start from power-down
• 83C528—32k bytes ROM
• 83C524—16k bytes ROM
• 80C528—ROMless version of the 83C528
• 87C528—32k bytes EPROM
• 83C524—16k bytes EPROM
• CMOS and TTL compatible
• Extended temperature ranges
• EPROM code protection
• OTP package available
• 16 MHz speed at V = 5 V
CC
This device provides architectural enhancements that make it
applicable in a variety of applications in consumer, telecom and
general control systems, especially in those systems which need
large ROM and RAM capacity on-chip.
The 87C528 contains a 32k × 8 EPROM and the 87C524 contains a
16k x 8 EPROM. Both devices have a 512 × 8 RAM, four 8-bit I/O
ports, two 16-bit timer/event counters (identical to the timers of the
80C51), a 16-bit timer (identical to the timer 2 of the 80C52), a
watchdog timer with a separate oscillator, a multi-source,
two-priority-level, nested interrupt structure, two serial interfaces
2
(UART and I C-bus), and on-chip oscillator and timing circuits.
In addition, the 87C524/87C528 has two software selectable modes
of power reduction—idle mode and power-down mode. The idle
mode freezes the CPU while allowing the RAM, timers, serial port,
and interrupt system to continue functioning. The power-down mode
saves the RAM contents but freezes the oscillator, causing all other
chip functions to be inoperative.
ORDERING INFORMATION
o
TEMPERATURE C RANGE
FREQ
(MHz)
Drawing
Number
EPROM
AND PACKAGE
P87C528EBP N
P87C528EBA A
P87C528EBB B
P87C528EFP N
P87C528EFB B
P87C524EBA A
0 to +70, Plastic Dual In-line Package
16
16
16
16
16
16
16
SOT129-1
SOT187-2
SOT307-2
SOT129-1
SOT307-2
SOT187-2
SOT307-2
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Plastic Quad Flat Pack
–40 to +85, Plastic Dual In-line Package
–40 to +85, Plastic Quad Flat Pack
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Plastic Quad Flat Pack
P87C524EBB B
NOTE:
1. For ROM & ROMless devices, see data sheet P8X524/528.
2
1999 Jul 23
853-1687 22041
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
BLOCK DIAGRAM
FREQUENCY
REFERENCE
COUNTERS
T0 T1
RST
XTAL2 XTAL1
T2
T2EX
RAM
AUX–RAM
PROGRAM
MEMORY
(32K x 8
OSCILLATOR
AND
TIMING
DATA
MEMORY
(256 x 8)
DATA
MEMORY
(256 x 8)
TWO 16-BIT
TIMER/EVENT
COUNTERS
WATCHDOG
TIMER
16-BIT TIMER/
EVENT COUNTER
EPROM)
CPU
PROGRAMMABLE
SERIAL PORT
FULL DUPLEX UART
64K-BYTE BUS
EXPANSION
CONTROL
BIT-LEVEL
I C
INTERFACE
2
PROGRAMMABLE I/O
INTERNAL
INTERRUPTS
SYNCHRONOUS SHIFT
SERIAL IN
SERIAL OUT
INT0 INT1
CONTROL
PARALLEL PORTS,
ADDRESS/DATA BUS
AND I/O PINS
SDA
SCL
SHARED WITH
PORT 3
EXTERNAL
INTERRUPTS
SU00166
LOGIC SYMBOL
V
V
SS
DD
XTAL1
ADDRESS AND
DATA BUS
XTAL2
T2
T2EX
RST
EA
PSEN
ALE
SCL
SDA
RxD
TxD
INT0
INT1
T0
ADDRESS BUS
T1
WR
RD
SU00165
3
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
PIN CONFIGURATIONS
PLASTIC LEADED CHIP CARRIER
PIN FUNCTIONS
40
39
38
37
V
DD
1
2
3
T2/P1.0
6
1
40
T2EX/P1.1
P0.0/AD0
P0.1/AD1
P0.2/AD2
P1.2
7
39
29
P1.3
P1.4
4
5
LCC
36 P0.3/AD3
35 P0.4/AD4
34 P0.5/AD5
P1.5
SCL/P1.6
SDA/P1.7
RST
6
7
8
9
17
33
32
P0.6/AD6
P0.7/AD7
18
28
Pin Function
Pin Function
DUAL
IN-LINE
PACKAGE
31 EA
RxD/P3.0 10
TxD/P3.1 11
INT0/P3.2 12
INT1/P3.3 13
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
1
2
3
NC*
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NC*
P1.0/T2
P1.1/T2EX
P1.2
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
30 ALE
29 PSEN
4
5
P1.3
6
P1.4
28
P2.7/A15
7
P1.5
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
8
9
P1.6/SCL
P1.7/SDA
RST
10
11
12
13
14
15
16
17
18
19
20
21
22
P3.0/RxD
NC*
ALE
NC*
EA
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
23
22
P2.2/A10
P2.1/A9
P2.0/A8
XTAL1 19
21
V
20
SS
XTAL1
SU00162
V
V
DD
SS
* NO INTERNAL CONNECTIONS
SU00163A
4
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
44
34
1
33
23
QFP
11
12
Pin Function
22
Pin Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
P1.5
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
NC*
P1.6/SCL
P1.7/SDA
RST
P3.0/RxD
NC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
V
DD
NC*
P1.0/T2
P1.1/T2EX
P1.2
XTAL1
V
SS
NC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P1.3
P1.4
SU00164
* NO INTERNAL CONNECTIONS
5
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
PIN DESCRIPTIONS
PIN NO.
MNEMONIC
DIP
LCC
QFP
TYPE
NAME AND FUNCTION
V
V
20
40
22
44
16
38
I
I
Ground: circuit ground potential.
Power Supply: +5 V power supply pin during normal operation, Idle mode and
Power-down mode.
SS
DD
P0.0–0.7
39–32 43–36 37–30
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s.
P1.0–P1.7
1–8
2–9
40–44
1–3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7
which have open drain. Port 1 pins that have 1s written to them are pulled high by the
internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled
low will source current because of the internal pull-ups. (See DC Electrical Characteristics:
I ). Port 1 can sink/source one TTL (4 LSTTL) inputs. Port 1 receives the low-order
IL
address byte during program memory verification. Port 1 also serves alternate functions for
timer 2:
1
2
7
8
2
3
8
9
40
41
2
I
I
T2 (P1.0): Timer/counter 2 external count input (following edge triggered).
T2EX (P1.1): Timer/counter 2 trigger input.
2
I/O
I/O
SCL (P1.6): I C serial port clock line.
2
3
SDA (P1.7): I C serial port data line.
P2.0–P2.7
21–28 24–31 18–25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: I ). Port 2 emits the high-order
IL
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.
P3.0–P3.7
10–17
11,
5,
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
13–19 7–13
pull-ups. (See DC Electrical Characteristics: I ). Port 3 also serves the special features of
IL
the SC80C51 family, as listed below:
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
I
O
I
I
I
I
O
O
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
9
10
11
12
13
RST
ALE
PSEN
EA
9
10
33
32
35
4
I/O
I/O
O
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V permits a power-on reset using only an external
SS
capacitor to V . After a watchdog timer overflow, this pin is pulled high while the internal
DD
reset signal is active.
30
29
31
27
26
29
Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency, and can be used for external timing or clocking. Note that one ALE
pulse is skipped during each access to external data memory.
Program Store Enable: The read strobe to external program memory. When the device is
executing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.
I
External Access Enable: EA must be externally held low during RESET to enable the
device to fetch code from external program memory locations 0000H to 7FFFH. If EA is
held high during RESET, the device executes from internal program memory unless the
program counter contains an address greater than 7FFFH. EA is don’t care after RESET.
XTAL1
XTAL2
19
18
21
20
15
14
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
O
Crystal 2: Output from the inverting oscillator amplifier.
6
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
Table 1.
8XC524/8XC528 Special Function Registers
DIRECT
DESCRIPTION
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
ADDRESS MSB
RESET
VALUE
SYMBOL
LSB
E0
ACC*
B*
Accumulator
B register
E0H
F0H
E7
F7
E6
F6
E5
F5
E4
F4
E3
F3
E2
F2
E1
F1
00H
F0
00H
DPTR:
DPH
DPL
Data pointer (2 bytes):
Data pointer high
Data pointer low
83H
82H
00H
00H
AF
EA
BF
–
AE
ES1
BE
AD
ET2
BD
AC
ES0
BC
AB
ET1
BB
AA
EX1
BA
A9
ET0
B9
A8
EX0
B8
IE*#
IP*#
Interrupt enable
Interrupt priority
A8H
B8H
00H
PS1
PT2
PS0
PT1
PX1
PT0
PX0
x0000000B
87
86
85
84
83
82
81
80
P0*
P1*
P2*
Port 0
Port 1
Port 2
80H
90H
A0H
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
FFH
FFH
FFH
97
96
95
–
94
–
93
–
92
–
91
90
T2
SDA
SEL
T2EX
A7
A6
A5
A4
A3
A2
A1
A9
A0
A8
A15
A14
A13
A12
A11
A10
B7
RD
B6
WR
–
B5
T1
–
B4
T0
–
B3
B2
B1
TxD
PD
B0
RxD
IDL
P3*
Port 3
B0H
87H
INT1
GF1
INT0
GF0
FFH
PCON
Power control
SMOD
0xxx0000B
D7
CY
D6
AC
D5
F0
D4
D3
D2
D1
F1
D0
P
PSW*
Program status word
D0H
RS1
RS0
OV
00H
RCAP2H# Capture high
RCAP2L# Capture low
CBH
CAH
99H
00H
00H
xxxxxxxxB
SBUF
Serial data buffer
9F
SM0
SDI
SD0
INT
DF
9E
SM1
0
9D
SM2
0
9C
REN
0
9B
TB8
0
9A
RB8
0
99
TI
98
RI
SCON*
S1BIT#
Serial controller
98H
D9H/RD
WR
00H
2
Serial I C data
0
0
x0000000B
0xxxxxxxB
0xxxxxxxB
X
X
X
X
X
X
X
2
S1INT#
S1SCS*#
SP
Serial I C interrupt
DAH
X
X
X
X
X
X
X
DE
SCI
SC0
DD
CLH
CLH
DC
BB
X
DB
RBF
X
DA
WBF
X
D9
STR
STR
D8
ENS
ENS
2
Serial I C control
D8H/RD
WR
SDI
SD0
xxxx0000B
00xxxx00B
07H
Stack pointer
Timer control
Timer 2 control
81H
8F
TF1
CF
8E
TR1
CE
8D
TF0
8C
TR0
CC
8B
IE1
8A
IT1
CA
89
IE0
C9
88
TCON*
T2CON*#
88H
C8H
IT0
00H
00H
CD
CB
C8
CP/RL2
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
TH0
TH1
TH2#
TL0
TL1
TL2#
T3#
Timer high 0
Timer high 1
Timer high 2
Timer low 0
Timer low 1
Timer low 2
Watchdog timer
8CH
8DH
CDH
8AH
8BH
CCH
FFH
00H
00H
00H
00H
00H
00H
00H
TMOD
Timer mode
89H
A5H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
A5H
WDCON# Watchdog control
*
SFRs are bit addressable.
#
SFRs are modified from or added to the 80C51 SFRs.
7
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
Table 2. Internal and External Program Memory Access with Security Bit Set
ACCESS TO INTERNAL
PROGRAM MEMORY
ACCESS TO EXTERNAL
PROGRAM MEMORY
INSTRUCTION
MOVC in internal program memory
MOVC in external program memory
YES
NO
YES
YES
the watchdog timer, the user program has to reload the watchdog
timer within periods that are shorter than the programmed watchdog
timer internal. This time interval is determined by an 8-bit value that
has to be loaded in register T3 while at the same time the prescaler
is cleared by hardware.
INTERNAL DATA MEMORY
The internal data memory is divided into three physically separated
segments: 256 bytes of RAM, 256 bytes of AUX-RAM, and a
128 bytes special function area. These can be addressed each in a
different way.
– RAM 0 to 127 can be addressed directly and indirectly as in the
80C51. Address pointers are R0 and R1 of the selected register
bank.
[256 * (T3)] 2048
Watchdog timer interval =
on * chip oscillator frequency
– RAM 128 to 255 can only be addressed indirectly as in the 80C51.
Address pointers are R0 and R1 of the selected register bank.
– AUX-RAM 0 to 255 is indirectly addressed in the same way as
external data memory with the MOVX instructions. Address
pointers are R0, R1 of the selected register bank and DPTR. An
access to AUX-RAM 0 to 255 will not affect ports P0, P2, P3.6
and P3.7.
2
BIT-LEVEL I C INTERFACE
2
This bit-level serial I/O interface supports the I C-bus. P1.6/SCL and
P1.7/SDA are the serial I/O pins. These two pins meet the I C
specification concerning the input levels and output drive capability.
Consequently, these pins have an open drain output configuration.
All the four modes of the I C-bus are supported:
– master transmitter
– master receiver
– slave transmitter
– slave receiver
2
2
An access to external data memory locations higher than 255 will be
performed with the MOVX DPTR instructions in the same way as in
the 8051 structure, so with P0 and P2 as data/address bus and P3.6
and P3.7 as write and read timing signals. Note that these external
data memory cannot be accessed with R0 and R1 as address
pointer.
2
The advantages of the bit-level I C hardware compared with a full
software I C implementation are:
– the hardware can generate the SCL pulse
2
TIMER 2
– Testing a single bit (RBF respectively, WBF) is sufficient as a
check for error free transmission.
Timer 2 is functionally equal to the Timer 2 of the 8052AH. Timer 2 is
a 16-bit timer/counter. These 16 bits are formed by two special
function registers TL2 and TH2. Another pair of special function
register RCAP2L and RCAP2H form a 16-bit capture register or a
16-bit reload register. Like Timer 0 and 1, it can operate either as a
timer or as an event counter. This is selected by bit C/T2N in the
special function register T2CON. It has three operating modes:
capture, autoload, and baud rate generator mode which are selected
by bits in T2CON.
2
The bit-level I C hardware operates on serial bit level and performs
the following functions:
– filtering the incoming serial data and clock signals
– recognizing the START condition
– generating a serial interrupt request SI after reception of a START
condition and the first falling edge of the serial clock
– recognizing the STOP condition
– recognizing a serial clock pulse on the SCL line
– latching a serial bit on the SDA line (SDI)
WATCHDOG TIMER T3
The watchdog timer consists of an 11-bit prescaler and an 8-bit timer
formed by special function register T3. The prescaler is incremented
by an on-chip oscillator with a fixed frequency of 1MHz. The
maximum tolerance on this frequency is –50% and +100%. The 8-bit
timer increments every 2048 cycles of the on-chip oscillator. When a
timer overflow occurs, the microcontroller is reset and a reset output
pulse of 16 × 2048 cycles of the on-chip oscillator is generated at pin
RST. The internal RESET signal is not inhibited when the external
RST pin is kept low by, for example, an external reset circuit. The
RESET signal drives port 1, 2, 3 into the high state and port 0 into
the high impedance state.
– stretching the SCL LOW period of the serial clock to suspend the
transfer of the next serial data bit
– setting Read Bit Finished (RBF) when the SCL clock pulse has
finished and Write Bit Finished (WBF) if there is no arbitration loss
detected (i.e., SDA = 0 while SDO = 1)
– setting a serial clock Low-to-High detected (CLH) flag
– setting a Bus Busy (BB) flag on a START condition and clearing
this flag on a STOP condition
– releasing the SCL line and clearing the CLH, RBF and WBF flags
to resume transfer of the next serial data bit
– generating an automatic clock if the single bit data register S1BIT
is used in master mode.
The watchdog timer is controlled by one special function register
WDCON with the direct address location A5H. WDCON can be read
and written by software. A value of A5H in WDCON halts the
on-chip oscillator and clears both the prescaler and timer T3. After
the RESET signal, WDCON contains A5H. Every value other than
A5H in WDCON enables the watchdog timer. When the watchdog
timer is enabled, it runs independently of the XTAL-clock.
The following functions must be done in software:
2
– handling the I C START interrupts
– converting serial to parallel data when receiving
– converting parallel to serial data when transmitting
– comparing the received slave address with its own
– interpreting the acknowledge information
Timer T3 can be read on the fly. Timer T3 can only be written if
WDCON contains the value 5AH. A successful write operation to T3
will clear the prescaler and WDCON, leaving the watchdog enabled
and preventing inadvertent changes of T3. To prevent an overflow of
2
– guarding the I C status if RBF or WBF = 0.
8
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
Additionally, if acting as master:
– generating START and STOP conditions
IE: Interrupt Enable Register
This register is located at address A8H. Refer to Table 3.
– handling bus arbitration
IE SFR (A8H)
– generating serial clock pulses if S1BIT is not used.
7
6
5
4
3
2
1
0
2
Three SFRs control the bit-level I C interface: S1INT, S1BIT and
S1SCS.
EA
ES1
ET2
ES
ET1
EX1
ET0
EX0
IP: Interrupt Priority Register
This register is located at address B8H. Refer to Table 4.
INTERRUPT SYSTEM
The interrupt structure of the 8XC528 is the same as that used in the
80C51, but includes two additional interrupt sources: one for the
third timer/counter, T2, and one for the I C interface. The interrupt
enable and interrupt priority registers are IE and IP.
IP SFR (B8H)
7
–
6
5
4
3
2
1
0
2
PS1
PT2
PS
PT1
PX1
PT0
PX0
Table 3. Description of IE Bits
MNEMONIC
BIT
FUNCTION
EA
IE.7
General enable/disable control:
0 = NO interrupt is enabled.
1 = ANY individually enabled interrupt will be accepted.
ES1
ET2
ES
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
Enable bit-level I C I/O interrupt
2
Enable Timer 2 interrupt
Enable Serial Port interrupt
Enable Timer 1 interrupt
Enable External interrupt 1
Enable Timer 0 interrupt
Enable External interrupt 0
ET1
EX1
ET0
EX0
Table 4. Description of IP Bits
MNEMONIC
–
BIT
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
FUNCTION
Reserved.
2
PS1
PT2
Bit-level I C interrupt priority level
Timer 2 interrupt priority level
Serial Port interrupt priority level
Timer 1 interrupt priority level
External Interrupt 1 priority level
Timer 0 interrupt priority level
External Interrupt 0 priority level
PS
PT1
PX1
PT0
PX0
The interrupt vector locations and the interrupt priorities are:
Source
Vector
0003H
Priority within Level
Address
IE0
Highest
002BH TF2+EXF2
2
0053H
000BH TF0
0013H IE1
001BH TF1
SI (I C)
0023H
RI+TI
Lowest
9
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
OSCILLATOR CHARACTERISTICS
POWER-DOWN MODE
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol.
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
The power-down mode can be terminated by a RESET in the same
way as in the 80C51 or in addition by one of two external interrupts,
INT0 or INT1. A termination with an external interrupt does not affect
the internal data memory and does not affect the special function
registers. This makes it possible to exit power-down without
changing the port output levels. To terminate the power-down mode
with an external interrupt INT0 or INT1 must be switched to
level-sensitive and must be enabled. The external interrupt input
signal INT0 and INT1 must be kept low until the oscillator has
restarted and stabilized. An instruction following the instruction that
puts the device in the power-down mode will be executed. A reset
generated by the watchdog timer terminates the power-down mode
in the same way as an external RESET, and only the contents of the
on-chip RAM are preserved. The control bits for the reduced power
modes are in the special function register PCON.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-up, the voltage on
V
DD
and RST must come up at the same time for a proper start-up.
DESIGN CONSIDERATIONS
IDLE MODE
At power-on, the voltage on V and RST must come up at the
DD
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
same time for a proper start-up.
When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes control.
On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of
an unexpected write when idle is terminated by reset, the instruction
following the one that invokes idle should not be one that writes to a
port pin or to external memory.
Table 5 shows the state of I/O ports during low current operating
modes.
Table 5. External Pin Status During Idle and Power-Down Modes
MODE
PROGRAM MEMORY
Internal
ALE
PSEN
PORT 0
Data
PORT 1
Data
PORT 2
Data
PORT 3
Data
Idle
Idle
1
1
0
0
1
1
0
0
External
Float
Data
Address
Data
Data
Power-down
Power-down
Internal
Data
Data
Data
External
Float
Data
Data
Data
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
0 to +70, or
–40 to +85
Operating temperature under bias
Storage temperature range
°C
–65 to +150
°C
V
Voltage on any other pin to V
–0.5 to V +0.5
SS
DD
Input, output current on any two pins
±10
mA
Power dissipation
1.0
W
(based on package heat transfer limitations, not device power consumption)
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise noted.
SS
10
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C (V = 5 V ±10%), –40°C to +85°C (V = 5 V ±10%), V =0 V
DD DD SS
TEST
LIMITS
SYMBOL
PARAMETER
PART TYPE
CONDITIONS
MIN
MAX
0.2V –0.1
UNIT
V
IL
Input low voltage,
0°C to 70°C
–40°C to +85°C
–0.5
–0.5
V
V
CC
except EA, P1.6/SCL, P1.7/SDA
0.2V –0.15
CC
V
IL1
Input low voltage to EA
0°C to 70°C
–40°C to +85°C
0
0
0.2V –0.3
V
V
CC
0.2V –0.35
CC
5
V
V
Input low voltage to P1.6/SCL, P1.7/SDA
–0.5
0.3 V
V
IL2
Input high voltage,
0°C to 70°C
–40°C to +85°C
0.2V +0.9
V
V
+0.5
+0.5
V
V
IH
CC
CC
CC
except XTAL1, RST, P1.6/SCL, P1.7/SDA
Input high voltage, XTAL1, RST
0.2V +1.0
CC
V
IH1
0°C to 70°C
–40°C to +85°C
0.7V
V
V
+0.5
+0.5
V
V
CC
CC
CC
0.7V +0.1
CC
5
V
V
Input high voltage, P1.6/SCL, P1.7/SDA
3.0
6.0
V
V
IH2
1
Output low voltage, ports 1, 2, 3, except
I
OL
= 1.6 mA
0.45
OL
1
P1.6/SCL, P1.7/SDA
1
1
1
V
OL1
V
OL2
V
OH
Output low voltage, port 0, ALE, PSEN
I
I
= 3.2 mA
= 3.0 mA
0.45
0.4
V
V
OL
Output low voltage, P1.6/SCL, P1.7/SDA
Output high voltage, ports 1, 2, 3
OL
I
= –60 µA
= –25 µA
2.4
0.75V
V
V
OH
OH
I
CC
V
OH1
Output high voltage, Port 0 in external bus mode,
ALE, PSEN, RST
I
= –800 µA
= –300 µA
2.4
0.75V
V
V
OH
I
OH
CC
I
IL
Logical 0 input current, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA
0°C to 70°C
–40°C to +85°C
V
IN
= 0.45 V
–50
–75
µA
µA
I
Logical 1-to-0 transition current, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA
0°C to 70°C
–40°C to +85°C
See Note 3
= V or V
IH
–650
–750
µA
µA
TL
I
I
Input leakage current, port 0
V
IN
µA
±10
±10
IL1
IL
Input leakage current, P1.6/SCL, P1.7/SDA
0 V<Vi<6.0 V
µA
µA
IL2
0 V<V <6.0 V
CC
I
Power supply current:
Active mode @ 16 MHz
Idle mode @ 16 MHz
See Note 4
CC
o
o
0 C to 70 C
25
35
5
6
mA
mA
o
o
–40 C to +85 C
o
o
0 C to 70 C
o
o
–40 C to +85 C
Power down mode
50
300
10
µA
kΩ
pF
R
C
Internal reset pull-down resistor
Pin Capacitance
50
RST
IO
NOTES:
1. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the V s of ALE and ports 1 and 3. The
OL
noise is due to external bus capacitance discharging into the port and port 2 pins when these pins make 1-to-0 transactions during bus
operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be
desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. Under steady state
(non-transient) conditions, I must be externally limited as follows: 10 mA per port pin, port 0 total (all bits) 26 mA, ports 1, 2, and total each
OL
(all bits) 15 mA.
2. Capacitive loading on Ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9V specification when the
OH
CC
address bits are stabilizing.
3. Pins of ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V is approximately 2 V.
IN
4. See Figures 10 through 13 for I test conditions.
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I C specification, so an input voltage below 1.5 V will be recognized as a
logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.
CC
2
11
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
1, 2
AC ELECTRICAL CHARACTERISTICS
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
1/t
FIGURE
PARAMETER
Oscillator frequency:
MIN
MAX
MIN
MAX
UNIT
1
Speed Versions
CLCL
87C528
P878C528EXX
3.5
16
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
1
1
1
1
1
1
1
1
1
1
1
ALE pulse width
85
8
2t
–40
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
t
t
–55
AVLL
LLAX
LLIV
CLCL
CLCL
28
–35
150
83
4t
3t
–100
CLCL
23
t
–40
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
143
3t
–45
CLCL
PSEN low to valid instruction in
–105
CLCL
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
0
0
38
208
10
t
–25
CLCL
5t
–105
CLCL
10
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
RD pulse width
275
275
6t
–100
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDZ
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
148
5t
–165
CLCL
0
0
Data float after RD
55
2t
–70
CLCL
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
350
398
238
8t
CLCL
9t
CLCL
–150
–165
AVDV
LLWL
AVWL
QVWX
WHQX
RLAZ
WHLH
138
120
3
3t
–50
3t
+50
CLCL
CLCL
4t
t
–130
–60
CLCL
CLCL
CLCL
13
t
–50
RD low to address float
RD or WR high to ALE high
0
0
23
103
t
–40
t
+40
CLCL
CLCL
External Clock
t
t
t
t
6
6
6
6
High time
Low time
Rise time
Fall time
20
20
20
20
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
20
20
20
20
Shift Register
t
t
t
t
t
4
4
4
4
4
Serial port clock cycle time
750
492
8
12t
ns
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10t
–133
QVXH
XHQX
XHDX
XHDV
CLCL
2t
CLCL
–117
0
0
492
10t
–133
CLCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
12
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
2
AC ELECTRICAL CHARACTERISTICS – I C INTERFACE
2
SYMBOL
PARAMETER
INPUT
OUTPUT
I C SPECIFICATION
SCL TIMING CHARACTERISTICS
1
t
t
t
t
t
START condition hold time
SCL LOW time
≥ 14 t
Note 2
Note 2
≥ 4.0µs
≥ 4.7µs
≥ 4.0µs
≤ 1.0µs
≤ 0.3µs
HD;STA
LOW
HIGH
RC
CLCL
≥ 16 t
CLCL
1
3
SCL HIGH time
SCL rise time
≥ 14 t
≥ 80 t
CLCL
CLCL
1
≤ 1µs
Note 5
1
6
SCL fall time
≤ 0.3µs
≤ 0.3µs
FC
SDA TIMING CHARACTERISTICS
t
t
t
t
t
t
t
Data set-up time
≥ 250ns
≥ 0ns
Note 2
Note 2
Note 2
Note 2
Note 2
Note 5
≤ 0.3µs
≥ 250ns
≥ 0ns
SU;DAT1
HD;DAT
SU;STA
SU;STO
BUF
Data hold time
1
1
1
Repeated START set-up time
STOP condition set-up time
Bus free time
≥ 14 t
≥ 4.7µs
≥ 4.0µs
≥ 4.7µs
≤ 1.0µs
≤ 0.3µs
CLCL
CLCL
≥ 14 t
≥ 14 t
CLCL
4
SDA rise time
≤ 1µs
RD
4
6
SDA fall time
≤ 0.3µs
FD
NOTES:
1. At f
2
2
= 3.5MHz, this evaluates to 14 × 286ns = 4µs, i.e., the bit-level I C interface can respond to the I C protocol for f
≥ 3.5 MHz.
CLK
CLK
2
2. This parameter is determined by the user software, it has to comply with the I C.
3. This value gives the autoclock pulse length which meets the I C specification for the specified XTAL clock frequency range. Alternatively, the
SCL pulse may be timed by software.
2
4. Spikes on SDA and SCL lines with a duration of less than 4 × f
will be filtered out.
CLK
5. The rise time is determined by the external bus line capacitance and pull-up resistor, it must be ≤ 1µs.
6. The maximum capacitance on bus lines SDA and SCL is 400pF.
13
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
P – PSEN
Q – Output data
R – RD signal
t – Time
A – Address
V – Valid
C – Clock
D – Input data
H – Logic level high
W– WR signal
X – No longer a valid logic level
Z – Float
I – Instruction (program memory contents)
L – Logic level low, or ALE
Examples: t
= Time for address valid to ALE low.
= Time for ALE low to PSEN low.
AVLL
LLPL
t
t
LHLL
ALE
t
t
LLPL
AVLL
t
PLPH
t
LLIV
t
PLIV
PSEN
t
LLAX
t
PXIZ
t
PLAZ
t
PXIX
A0–A7
INSTR IN
A0–A7
PORT 0
PORT 2
t
AVIV
A0–A15
A8–A15
SU00006
Figure 1. External Program Memory Read Cycle
ALE
PSEN
RD
t
WHLH
t
LLDV
t
t
LLWL
RLRH
t
RHDZ
t
LLAX
t
t
RLDV
AVLL
t
RLAZ
t
RHDX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA IN
A0–A7 FROM PCL
INSTR IN
t
AVWL
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPH
A0–A15 FROM PCH
SU00007
Figure 2. External Data Memory Read Cycle
14
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
ALE
t
WHLH
PSEN
t
t
WLWH
LLWL
WR
t
LLAX
t
t
WHQX
t
AVLL
QVWX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA OUT
A0–A7 FROM PCL
INSTR IN
t
AVWL
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00069
Figure 3. External Data Memory Write Cycle
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
t
XLXL
CLOCK
t
XHQX
t
QVXH
OUTPUT DATA
0
1
2
3
4
5
6
7
WRITE TO SBUF
t
XHDX
t
SET TI
VALID
XHDV
INPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
SU00027
Figure 4. Shift Register Mode Timing
15
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
repeated START condition
STOP condition
START or repeated START condition
START condition
t
SU;STA
t
RD
0.7 V
0.3 V
CC
SDA
(INPUT/OUTPUT)
CC
t
BUF
t
t
t
FC
FD
RC
t
SU;STO
0.7 V
CC
SCL
(INPUT/OUTPUT)
0.3 V
CC
t
SU;DAT3
t
t
t
t
SU;DAT1
t
t
HD;STA
LOW
HIGH
HD;DAT
SU;DAT2
SU00107A
2
Figure 5. Timing SIO1 (I C) Interface
V
–0.5
CC
0.7V
CC
CC
0.45V
0.2V
–0.1
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
SU00009
Figure 6. External Clock Drive
V
–0.5
DD
V
+0.1V
V
V
–0.1V
LOAD
OH
TIMING
REFERENCE
POINTS
0.2V +0.9
DD
V
LOAD
0.2V –0.1
V
–0.1V
+0.1V
OL
DD
LOAD
0.45V
NOTE:
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from load
voltage occurs, and begins to float when a 100mV change from the loaded V /V
AC inputs during testing are driven at V
–0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
DD
OH OL
Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.
IH IL
level occurs. I /I ≥ ±20mA.
OH OL
SU00011
SU00167
Figure 7. AC Testing Input/Output
Figure 8. Float Waveform
30
25
20
15
10
MAX ACTIVE MODE
TYP ACTIVE MODE
I
mA
CC
MAX IDLE MODE
TYP IDLE MODE
5
4 MHz
8 MHz 12 MHz 16 MHz
FREQ AT XTAL1
SU00168
Figure 9. I vs. FREQ.
CC
Valid only within frequency specifications of the device under test
16
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
V
DD
DD
V
DD
DD
I
DD
I
DD
V
V
DD
DD
V
RST
EA
V
V
DD
P0
EA
P0
RST
(NC)
XTAL2
XTAL1
(NC)
XTAL2
XTAL1
P1.6
P1.7
P1.6
P1.7
*
*
*
*
CLOCK SIGNAL
CLOCK SIGNAL
V
V
SS
SS
SU00169
SU00170
Figure 10. I Test Condition, Active Mode
Figure 11. I Test Condition, Idle Mode
DD
DD
All other pins are disconnected
All other pins are disconnected
V
–0.5
CC
0.7V
CC
–0.1
0.45V
0.2V
CC
t
CHCX
t
t
t
CLCH
CHCL
CLCX
t
CLCL
SU00009
Figure 12. Clock Signal Waveform for
Tests in Active and Idle Modes
I
DD
t
= t
= 5ns
CHCL
CLCH
V
DD
I
DD
V
DD
RST
EA
V
DD
P0
(NC)
XTAL2
XTAL1
P1.6
P1.7
*
*
V
SS
SU00171
Figure 13. I Test Condition, Power Down Mode
DD
All other pins are disconnected. V = 2V to 5.5V
DD
NOTE:
Ports 1.6 and 1.7 should be connected to V through resistors of sufficiently high value such that the sink current into these pins does not
*
DD
exceed the I
specifications.
OL1
17
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
Note that the EA/V pin must not be allowed to 90 above the
EPROM CHARACTERISTICS FOR 87C528
The 87C528 is programmed by using a modified Quick-Pulse
Programming algorithm. It differs from older methods in the value
PP
maximum specified V level for any amount of time. Even a narrow
PP
glitch above that voltage can cause permanent damage to the
device. The V source should be well regulated and free of glitches
PP
used for V (programming supply voltage) and in the width and
PP
and overshoot.
number of the ALE/PROG pulses.
The 87C528 contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as an 87C528 manufactured by
Philips.
Program Verification
If lock bit 2 has not been programmed, the on-chip program memory
can be read out for program verification. The address of the program
memory locations to be read is applied to ports 1, 2 and 3 as shown
in Figure 16. The other pins are held at the ‘Verify Code Data’ levels
indicated in Table 6. The contents of the address location will be
emitted on port 0. External pull ups are required on port 0 for this
operation.
Table 6 shows the logic levels for reading the signature byte, and for
programming the program memory, the encryption table, and the
lock bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 14 and 15. Figure 16 shows the
circuit configuration for normal program memory verification.
If the encryption table has been programmed, the data presented at
port 0 will be the exclusive NOR of the program byte with one of the
encryption bytes. The user will have to know the encryption table
contents in order to correctly decode the verification data. The
encryption table itself cannot be read out.
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in
Figure 14. Note that the 87C528 is running with a 4 to 6MHz
oscillator The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031 H, except that P3.6 and P3.7
need to be pulled to a logic low. The values are:
The address of the EPROM location to be programmed is applied to
ports 1, 2 and 3, as shown in Figure 14. The code byte to be
programmed into that location is applied to port 0. RST, PSEN and
pins of ports 2 and 3 specified in Table 6 are held at the ’Program
Code Data’ levels indicated in Table 6. The ALE/PROG is pulsed
low 25 times as shown in Figure 15.
(030H) = 15H indicates manufactured by Philips
(031H) = 9BH indicates 87C528
Program Lock Bits
The 87C528 has 3 programmable lock bits that will provide different
levels of protection for the on-chip code and data (see Table 7).
To program the encryption table, repeat the 25 pulse programming
sequence for addresses 0 through 3FH, using the ‘Pgm Encryption
Table’ levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.
Erasing the EPROM also erases the encryption array and the
program lock bits, returning the part to full functionality.
To program the lock bits, repeat the 25 pulse programming
sequence using the ‘Pgm Lock Bit’ levels. After one lock bit is
programmed, further programming of the code memory and
encryption table is disabled. However, the other lock bit can still be
programmed.
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 6, and
which satisfies the timing specifications, is suitable.
Table 6. EPROM Programming Modes
MODE
Read signature
Program code data
Verify code data
Pgm encryption table
Pgm lock bit 1
Pgm lock bit 2
Pgm lock bit 3
NOTES:
RST
1
PSEN
ALE/PROG
EA/V
P2.7
P2.6
P3.7
P3.6
PP
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
0
1
1
0
1
0
1
1
0*
1
V
PP
1
1
1
0*
0*
0*
0*
V
PP
PP
PP
PP
1
V
V
V
1
1
1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. V = 12.75 V ±0.25 V.
PP
3. Vcc = 5 V ±10% during programming and verification.
*
ALE/PROG receives 25 programming pulses while V is held at 12.75 V. Each programming pulse is low for 100 µs (±10 µs) and high for a
minimum of 10 µs.
PP
18
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
in Figure 16. The other pins are held at the ‘Verify Code Data’ levels
indicated in Table 6. The contents of the address location will be
emitted on port 0. External pull-ups are required on port 0 for this
operation.
EPROM CHARACTERISTICS FOR 87C524
The 87C524 is programmed by using a modified Quick-Pulse
Programming algorithm. It differs from older methods in the value
used for V (programming supply voltage) and in the width and
PP
number of the ALE/PROG pulses.
If the encryption table has been programmed, the data presented at
port 0 will be the exclusive NOR of the program byte with one of the
encryption bytes. The user will have to know the encryption table
contents in order to correctly decode the verification data. The
encryption table itself cannot be read out.
The 87C524 contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as an 87C524 manufactured by
Philips.
Program Lock Bits
The 87C524 has 3 programmable lock bits that will provide different
levels of protection for the on-chip code and data (see Table 7).
Table 6 shows the logic levels for reading the signature byte, and for
programming the program memory, the encryption table, and the
lock bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 14 and 15. Figure 16 shows the
circuit configuration for normal program memory verification.
Erasing the EPROM also erases the encryption array and the
program lock bits, returning the part to full functionality.
Quick-Pulse Programming
Reading the Signature Bytes
The setup for microcontroller quick-pulse programming is shown in
Figure 14. Note that the 87C524 is running with a 4 to 6 MHz
oscillator. The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031H, except that P3.6 and P3.7
need to be pulled to a logic low. The values are:
(030H) = 15H indicates manufactured by
Philips
(031H) = 9DH indicates 87C524
The address of the EPROM location to be programmed is applied to
ports 1, 2 and 3, as shown in Figure 14. The code byte to be
programmed into that location is applied to port 0. RST, PSEN and
pins of ports 2 and 3 specified in Table 6 are held at the ‘Program
Code Data’ levels indicated in Table 6. The ALE/PROG is pulsed
low 25 times as shown in Figure 15.
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 6, and
which satisfies the timing specifications, is suitable.
To program the encryption table, repeat the 25 pulse programming
sequence for addresses 0 through 3FH, using the ‘Pgm Encryption
Table’ levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.
Erasure Characteristics
Erasure of the EPROM begins to occur when the chip is exposed to
light with wavelengths shorter than approximately 4,000 angstroms.
Since sunlight and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about
1 week in sunlight, or 3 years in room level fluorescent lighting)
could cause inadvertent erasure. For this and secondary effects,
it is recommended that an opaque label be placed over the
window. For elevated temperature or environments where solvents
are being used, apply Kapton tape Fluorglas part number 2345–5, or
equivalent.
To program the lock bits, repeat the 25 pulse programming
sequence using the ‘Pgm Lock Bit’ levels. After one lock bit is
programmed, further programming of the code memory and
encryption table is disabled. However, the other lock bit can still be
programmed.
Note that the EA/V pin must not be allowed to go above the
PP
maximum specified V level for any amount of time. Even a narrow
PP
glitch above that voltage can cause permanent damage to the
The recommended erasure procedure is exposure to ultraviolet light
2
device. The V source should be well regulated and free of glitches
(at 2537 angstroms) to an integrated dose of at least 15W-sec/cm .
PP
2
and overshoot.
Exposing the EPROM to an ultraviolet lamp of 12,000uW/cm rating
for 20 to 39 minutes, at a distance of about 1 inch, should be
sufficient.
Program Verification
If lock bit 2 has not been programmed, the on-chip program memory
can be read out for program verification. The address of the program
memory locations to be read is applied to ports 1, 2 and 3 as shown
Erasure leaves the array in an all 1s state.
Trademark phrase of Intel Corporation.
1999 Jul 23
19
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
Table 7. Program Lock Bits
1,2
PROGRAM LOCK BITS
LB1 LB2 LB3 PROTECTION DESCRIPTION
1
2
U
P
U
U
U
U
No Program Lock features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.)
MOVC instructions executed from external program memory are disabled from fetching code bytes from
Internal memory, EA is jumped and latched on Reset, and further programming of the EPROM Is disabled.
3
4
P
P
P
P
U
P
Same as 2, also verify is disabled.
Same as 3, external execution is disabled. Internal data RAM is not accessible.
NOTES:
1. P - programmed. U - unprogrammed.
2. Any other combination of the lock bits is not defined.
+5 V
V
CC
P0
A0–A7
PGM DATA
P1
1
1
1
RST
+12.75 V
EA/V
PP
P3.6
25 100 µs PULSES TO GROUND
ALE/PROG
PSEN
0
1
87C524/8
P3.7
XTAL2
P2.7
0
P2.6
P2.0–P2.5
P3.4
4–6 MHz
XTAL1
A8–A13
A14
V
SS
SU00172
Figure 14. Programming Configuration
25 PULSES
1
0
ALE/PROG:
ALE/PROG:
10µs MIN
100µs+10
1
0
SU00018
Figure 15. PROG Waveform
+5 V
V
CC
P0
A0–A7
PGM DATA
P1
1
1
1
RST
P3.6
1
1
0
EA/V
PP
ALE/PROG
PSEN
87C524/8
P3.7
0
0
ENABLE
XTAL2
P2.7
P2.6
P2.0–P2.5
P3.4
4–6 MHz
XTAL1
A8–A13
A14
V
SS
SU00173
Figure 16. Program Verification
20
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
T
amb
= 21°C to +27°C, Vcc = 5 V±10%, V = 0 V (See Figure 17)
SS
SYMBOL
PARAMETER
MIN
MAX
13.0
50
UNIT
V
V
Programming supply voltage
Programming supply current
Oscillator frequency
12.5
PP
PP
I
mA
MHz
1/t
4
6
CLCL
AVGL
t
Address setup to PROG low
Address hold after PROG
Data setup to PROG low
Data hold after PROG
48t
CLCL
CLCL
CLCL
CLCL
CLCL
t
48t
48t
48t
48t
GHAX
t
DVGL
GHDX
t
t
P2.7 (ENABLE) high to V
PP
EHSH
t
t
V
V
setup to PROG low
hold after PROG
10
10
90
µs
µs
µs
SHGL
GHSL
GLGH
PP
PP
t
PROG width
110
t
Address to data valid
48t
AVQV
CLCL
CLCL
CLCL
t
ENABLE low to data valid
Data float after ENABLE
PROG high to PROG low
48t
48t
ELQZ
t
0
EHQZ
GHGL
t
10
µs
PROGRAMMING*
VERIFICATION*
ADDRESS
P1.0–P1.7
P2.0–P2.5
ADDRESS
t
AVQV
PORT 0
DATA IN
DATA OUT
t
t
t
DVGL
GHDX
GHAX
t
AVGL
ALE/PROG
t
t
t
GHGL
GLGH
t
SHGL
GHSL
LOGIC 1
LOGIC 1
EA/V
PP
LOGIC 0
t
t
t
EHSH
ELQV
EHQZ
P2.7
ENABLE
SU00174
NOTE:
*
FOR PROGRAMMING VERIFICATION SEE FIGURE 14.
FOR VERIFICATION CONDITIONS SEE FIGURE 16.
Figure 17. EPROM Programing and Verification
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent
2
to use the components in the I C system provided the system conforms to the
I C specifications defined by Philips. This specification can be ordered using the
2
code 9398 393 40011.
21
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
22
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
23
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
24
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
NOTES
25
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers
87C524/87C528
16K/32K, 512 OTP, I2C, watchdog timer
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 07-99
Document order number:
9397 750 06229
Philips
Semiconductors
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