P87C554SFBD_技术文档

INTEGRATED CIRCUITS

80C554/83C554/87C554

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C,

PWM, capture/compare, high I/O, 64L LQFP

Preliminary specification

Replaces data of 1999 Apr 07

IC20 Data Handbook

2000 Nov 10

Philips

Semiconductors

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

DESCRIPTION

FEATURES

This data sheet describes the 6 clock version of the 8xC554. This

device is only available in 64L LQFP. The 8xC554 Single-Chip 8-Bit

Microcontroller is manufactured in an advanced CMOS process and

is a derivative of the 80C51 microcontroller family. The 87C554 has

the same instruction set as the 80C51. Three versions of the

derivative exist:

• 80C51 central processing unit

• 16k × 8 EPROM expandable externally to 64k bytes

• An additional 16-bit timer/counter coupled to four capture registers

and three compare registers

• Two standard 16-bit timer/counters

• 83C554—16k bytes ROM

• 80C554—ROMless version

• 87C554—16k bytes EPROM

• 512 × 8 RAM, expandable externally to 64k bytes

• Capable of producing eight synchronized, timed outputs

• A 10-bit ADC with seven multiplexed analog inputs

• Fast 8-bit ADC option – 9 µS at 16 MHz

The 87C554 contains a 16k × 8 non-volatile EPROM, a 512 × 8

read/write data memory, five 8-bit I/O ports, one 8-bit input port, two

16-bit timer/event counters (identical to the timers of the 80C51), an

additional 16-bit timer coupled to capture and compare latches, a

15-source, four-priority-level, nested interrupt structure, an 7-input

ADC, a dual DAC pulse width modulated interface, two serial

• Two 8-bit resolution, pulse width modulation outputs

• Five 8-bit I/O ports plus one 8-bit input port shared with analog

inputs

2

interfaces (UART and I C-bus), a “watchdog” timer and on-chip

2

• I C-bus serial I/O port with byte oriented master and slave

oscillator and timing circuits. For systems that require extra

capability, the 8xC554 can be expanded using standard TTL

compatible memories and logic.

functions

• On-chip watchdog timer

• Extended temperature ranges

• Full static operation – 0 to 16 MHz

In addition, the 8xC554 has two software selectable modes of power

reduction—idle mode and power-down mode. The idle mode freezes

the CPU while allowing the RAM, timers, serial ports, and interrupt

system to continue functioning. Optionally, the ADC can be operated

in Idle mode. The power-down mode saves the RAM contents but

freezes the oscillator, causing all other chip functions to be

inoperative.

• Operating voltage range: 2.7 V to 5.5 V (0 to 8 MHz) and

4.5 V to 5.5 V (8 to 16 MHz) commercial temperature

• Security bits:

– ROM – 2 bits

The device also functions as an arithmetic processor having

facilities for both binary and BCD arithmetic plus bit-handling

capabilities. The instruction set consists of over 100 instructions:

49 one-byte, 45 two-byte, and 17 three-byte. With an 8 MHz crystal,

58% of the instructions are executed in 0.75 µs and 40% in 1.5 µs.

Multiply and divide instructions require 3 µs.

– OTP/EPROM – 3 bits

• 4 level priority interrupt

• 15 interrupt sources

• Full-duplex enhanced UART

– Framing error detection

– Automatic address recognition

• Power control modes

– Clock can be stopped and resumed

– Idle mode

– Power down mode

• Second DPTR register

• EMI reduction – 6 clock operation and ALE inhibit

• Programmable I/O pins

• Wake-up from power-down by external interrupts

• Software reset

• Power-on detect reset

• ADC charge pump disable

• ONCE mode

• ADC active in Idle mode

2

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

ORDERING INFORMATION

FREQ.

(MHz)

DRAWING

NUMBER

OTP/EPROM

P87C554SBBD

P87C554SFBD

ROM

ROMless

P80C554SBBD

P80C554SFBD

TEMPERATURE °C AND PACKAGE

P83C554SBBD

P83C554SFBD

0 to +70, Low Profile Quad Flat Package

16

SOT314–2

–40 to +85, Low Profile Quad Flat

Package

PART NUMBER DERIVATION

DEVICE NUMBER

OPERATING FREQUENCY MAX

TEMPERATURE RANGE

PACKAGE

P87C554 OTP

B= 0_C to 70_C

P83C554 ROM

S = 16 MHz

BD=64L LQFP

F = –40_C to +85_C

P80C554 ROMless

BLOCK DIAGRAM

T0

T1

INT0

INT1

PWM0 PWM1

ADC0-7 SDA SCL

AV

REF

SS

–

+

V

SS

5

1

DD

STADC

3

AV

DD

XTAL1

T0, T1

PROGRAM

MEMORY

16k x 8

DATA

MEMORY

512 x 8 RAM

DUAL

PWM

SERIAL

C PORT

TWO 16-BIT

TIMER/EVENT

COUNTERS

XTAL2

EA

ADC

2

CPU

I

OTP/ROM

ALE

80C51 CORE

EXCLUDING

ROM/RAM

PSEN

3

WR

RD

8-BIT INTERNAL BUS

3

0

16

AD0-7

T2

16-BIT

TIMER/

EVENT

FOUR

16-BIT

CAPTURE

16-BIT

COMPARA-

TORS

WITH

REGISTERS

COMPARA-

TOR

OUTPUT

T3

16

PARALLEL I/O

PORTS AND

EXTERNAL BUS

SERIAL

UART

PORT

8-BIT

PORT

WATCHDOG

TIMER

2

LATCHES

SELECTION

COUNTERS

A8-15

3

1

4

P0

P1

P2

P3

TxD

RxD

P5

P4

CT0I-CT3I

T2

RT2

CMSR0-CMSR5 RST EW

CMT0, CMT1

3

4

5

0

1

2

ALTERNATE FUNCTION OF PORT 3

ALTERNATE FUNCTION OF PORT 4

ALTERNATE FUNCTION OF PORT 5

ALTERNATE FUNCTION OF PORT 0

ALTERNATE FUNCTION OF PORT 1

ALTERNATE FUNCTION OF PORT 2

SU00951

3

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

PIN CONFIGURATIONS

Plastic Quad Flat Pack pin functions

Pin Function

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

16.

AV

17.

18.

19.

20.

21.

22.

23.

24.

25.

26.

27.

28.

29.

30.

31.

32.

P4.3/CMSR3

33.

34.

35.

36.

37.

38.

39.

40.

41.

42.

43.

44.

45.

46.

47.

48.

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

49.

50.

51.

52.

53.

54.

55.

56.

57.

58.

59.

60.

61.

62.

63.

64.

P2.6/A14

P2.7/A15

PSEN

ALE/PROG

EA/V

PP

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

AVref–

DD

P5.6/ADC6

P5.5/ADC5

P5.4/ADC4

P5.3/ADC3

P5.2/ADC2

P5.1/ADC1

P5.0/ADC0

P4.4/CMSR4

P4.5/CMSR5

P4.6/CMT0

P4.7/CMT1

RST

P1.0/CT0I

P1.1/CT1I

P1.2/CT2I

P1.3/CT3I

P1.4/T2

P1.5/RT2

P1.6/SCL

P1.7/SDA

P3.0/RxD

P3.1/TxD

48

33

49

64

32

17

XTAL1

V

DD

SS

STADC

PWM0

PWM1

EW

P4.0/CMSR0

P4.1/CMSR1

P4.2/CMSR2

LQFP64

SS

P2.0/A08

P2.1/A09

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

AVref+

AV

SS

1

16

SU01444

LOGIC SYMBOL

V

SS

V

DD

XTAL1

XTAL2

EA/V

PP

LOW ORDER

ALE/PROG

PSEN

ADDRESS AND

DATA BUS

AV

SS

AV

DD

AVref+

AVref–

STADC

PWM0

PWM1

CT0I

CT1I

CT2I

CT3I

T2

RT2

SCL

SDA

ADC0-7

HIGH ORDER

ADDRESS AND

DATA BUS

CMSR0-5

RxD/DATA

TxD/CLOCK

INT0

INT1

T0

T1

CMT0

CMT1

WR

RD

RST

EW

SU00210

4

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

PIN DESCRIPTION

PIN NO.

MNEMONIC

LQFP

TYPE

NAME AND FUNCTION

V

DD

9

I

Digital Power Supply: Positive voltage power supply pin during normal operation, idle and

power-down mode.

STADC

10

I

Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be

started by software).

PWM0

PWM1

EW

11

12

O

Pulse Width Modulation: Output 0.

Pulse Width Modulation: Output 1.

13

I

Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.

P0.0-P0.7

54–61

I/O

Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them

float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address

and data bus during accesses to external program and data memory. In this application it uses

strong internal pull-ups when emitting 1s. Port 0 is also used to input the code byte during

programming and to output the code byte during verification.

P1.0-P1.7

23–30

23–28

29–30

23–26

27

I/O

I

Port 1: 8-bit I/O port. Alternate functions include:

(P1.0-P1.5): Programmable I/O port pins.

(P1.6, P1.7): Open drain port pins.

CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.

T2 (P1.4): T2 event input.

I

28

I

RT2 (P1.5): T2 timer reset signal. Rising edge triggered.

2

29

I/O

SCL (P1.6): Serial port clock line I C-bus.

2

30

SDA (P1.7): Serial port data line I C-bus.

Port 1 has four modes selected on a per bit basis by writing to the P1M1 and P1M2 registers as

follows:

P1M1.x

P1M2.x

Mode Description

0

1

0

1

0

1

Pseudo–bidirectional (standard c51 configuration; default)

Push-Pull

High impedance

Open drain

Port 1 is also used to input the lower order address byte during EPROM programming and

verification. A0 is on P1.0, etc.

P2.0-P2.7

43–50

I/O

Port 2: 8-bit programmable I/O port.

Alternate function: High-order address byte for external memory (A08-A15). Port 2 is also used to

input the upper order address during EPROM programming and verification. A8 is on P2.0, A9 on

P2.1, through A13 on P2.5.

Port 2 has four output modes selected on a per bit basis by writing to the P2M1 and P2M2 registers

as follows:

P2M1.x

P2M2.x

Mode Description

0

1

0

1

0

1

Pseudo–bidirectional (standard c51 configuration; default)

Push-Pull

High impedance

Open drain

P3.0-P3.7

31–38

31

I/O

Port 3: 8-bit programmable I/O port. Alternate functions include:

RxD(P3.0): Serial input port.

32

TxD (P3.1): Serial output port.

33

INT0 (P3.2): External interrupt.

34

INT1 (P3.3): External interrupt.

35

T0 (P3.4): Timer 0 external input.

36

T1 (P3.5): Timer 1 external input.

37

WR (P3.6): External data memory write strobe.

RD (P3.7): External data memory read strobe.

38

Port 3 has four modes selected on a per bit basis by writing to the P3M1 and P3M2 registers as

follows:

P3M1.x

P3M2.x

Mode Description

0

1

0

1

0

1

Pseudo–bidirectional (standard c51 configuration; default)

Push–Pull

High impedance

Open drain

5

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

PIN DESCRIPTION (Continued)

PIN NO.

MNEMONIC

LQFP

TYPE

NAME AND FUNCTION

P4.0-P4.7

14–21

14–19

20, 21

I/O

O

Port 4: 8-bit programmable I/O port. Alternate functions include:

CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with timer T2.

CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.

O

Port 4 has four modes selected on a per bit basis by writing to the P4M1 and P4M2 registers as

follows:

P4M1.x

P4M2.x

Mode Description

0

1

0

1

0

1

Pseudo-bidirectional (standard c51 configuration; default)

Push-Pull

High impedance

Open drain

P5.0-P5.6

2–8

I

Port 5: 8-bit input port.

ADC0-ADC7 (P5.0-P5.7): Alternate function: Seven input channels to the ADC.

RST

22

40

I/O

I

Reset: Input to reset the 87C554. It also provides a reset pulse as output when timer T3 overflows.

XTAL1

Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal

clock generator. Receives the external clock signal when an external oscillator is used.

XTAL2

39

O

Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit when an

external clock is used.

V

41–42

51

I

Digital ground.

SS

PSEN

O

Program Store Enable: Active-low read strobe to external program memory.

ALE/PROG

52

Address Latch Enable: Latches the low byte of the address during accesses to external memory.

It is activated every six oscillator periods. During an external data memory access, one ALE pulse

is skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external

pull-up. This pin is also the program pulse input (PROG) during EPROM programming.

EA/V

53

I

External Access: When EA is held at TTL level high, the CPU executes out of the internal program

ROM provided the program counter is less than 16,384. When EA is held at TTL low level, the CPU

executes out of external program memory. EA is not allowed to float. This pin also receives the

PP

12.75 V programming supply voltage (V ) during EPROM programming.

PP

AV

62

63

64

1

I

Analog to Digital Conversion Reference Resistor: Low-end.

Analog to Digital Conversion Reference Resistor: High-end.

Analog Ground

REF–

REF+

SS

Analog Power Supply

DD

NOTE:

1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than V + 0.5 V or V – 0.5 V,

DD

SS

respectively.

6

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

Table 1.

87C554 Special Function Registers

DIRECT

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

RESET

VALUE

SYMBOL

DESCRIPTION

ADDRESS

E0H

C6H

C5H

8EH

A2H

F0H

MSB

LSB

ACC*

Accumulator

E7

E6

E5

E4

E3

E2

E1

E0

00H

ADCH#

ADCON#

AUXR

A/D converter high

A/D control

xxxxxxxxB

xx000000B

xxxxx110B

000000x0B

00H

ADC.1

–

ADC.0

–

ADEX

–

ADCI

–

ADCS

–

AADR2

LVADC

O

AADR1

EXTRAM

–

AADR0

A0

Auxiliary

AUXR1

B*

Auxiliary

ADC8

F7

AIDL

F6

SRST

F5

GF2

F4

WUPD

F3

DPS

F0

B register

F2

F1

CTCON#

CTH3#

CTH2#

CTH1#

CTH0#

CMH2#

CMH1#

CMH0#

CTL3#

CTL2#

CTL1#

CTL0#

CML2#

CML1#

CML0#

DPTR:

Capture control

Capture high 3

Capture high 2

Capture high 1

Capture high 0

Compare high 2

Compare high 1

Compare high 0

Capture low 3

Capture low 2

Capture low 1

Capture low 0

Compare low 2

Compare low 1

Compare low 0

EBH

CFH

CEH

CDH

CCH

CBH

CAH

C9H

AFH

AEH

ADH

ACH

ABH

AAH

A9H

CTN3

CTP3

CTN2

CTP2

CTN1

CTP1

CTN0

CTP0

00H

xxxxxxxxB

00H

xxxxxxxxB

00H

Data pointer

(2 bytes):

DPH

DPL

Data pointer high

Data pointer low

83H

82H

00H

AF

EA

AE

EAD

EE

AD

ES1

ED

AC

ES0

EC

AB

ET1

EB

AA

EX1

EA

A9

ET0

E9

A8

EX0

E8

IEN0*#

IEN1*#

IP0*#

Interrupt enable 0

Interrupt enable 1

Interrupt priority 0

A8H

E8H

B8H

00H

EF

ET2

BF

ECM2

BE

ECM1

BD

ECM0

BC

ECT3

BB

ECT2

BA

ECT1

B9

ECT0

B8

00H

–

PAD

FE

PS1

FD

PS0

FC

PT1

FB

PX1

FA

PT0

F9

PX0

F8

x0000000B

FF

IP0H

IP1*#

IP1H

P5#

Interrupt priority 0 high

Interrupt priority1

Interrupt priority 1 high

Port 5

B7H

F8H

F7H

C4H

–

PADH

PCM2

PCM2H

ADC6

C6

PS1H

PCM1

PCM1H

ADC5

C5

PS0H

PCM0

PCM0H

ADC4

C4

PT1H

PCT3

PCT3H

ADC3

C3

PX1H

PCT2

PCT2H

ADC2

C2

PT0H

PCT1

PCT1H

ADC1

C1

PX0H

PCT0

PCT0H

ADC0

C0

x0000000B

00H

PT2

PT2H

ADC7

C7

00H

xxxxxxxxB

P4#*

P3*

P2*

P1*

P0*

Port 4

Port 3

Port 2

Port 1

Port 0

C0H

B0H

A0H

90H

80H

CMT1

B7

CMT0

B6

CMSR5

B5

CMSR4

B4

CMSR3

B3

CMSR2

B2

CMSR1

B1

CMSR0 FFH

B0

RD

A7

WR

T1

T0

INT1

A3

INT0

A2

TXD

A1

RXD

A0

FFH

A6

A5

A4

A15

97

A14

96

A13

95

A12

94

A11

A10

A9

A8

93

92

91

90

SDA

87

SCL

86

RT2

85

T2

CT3I

83

CT2I

82

CT1I

81

CT0I

80

84

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

7

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

RESET

SYMBOL

DESCRIPTION

MSB

LSB

VALUE

xx000000B

00H

P1M1

Port 1 output mode 1

Port 1 output mode 2

Port 2 output mode 1

Port 2 output mode 2

Port 3 output mode 1

Port 3 output mode 2

Port 4 output mode 1

Port 4 output mode 2

Power control

92H

93H

94H

95H

9AH

9BH

9CH

9DH

87H

D0H

FEH

FDH

FCH

EFH

F9H

B9H

99H

P1M2

P2M1

P2M2

00H

P3M1

00H

P3M2

00H

P4M1

00H

P4M2

00H

PCON

PSW

SMOD1

CY

SMOD0

AC

POF

FO

WLE

RS1

GF1

RS0

GFO

OV

PD

F1

IDL

P

00x00000B

00H

Program status word

PWM prescaler

PWMP#

PWM1#

PWM0#

RTE#

00H

PWM register 1

00H

PWM register 0

00H

Reset/toggle enable

Serial 0 slave address

Slave address mask

Serial 0 data buffer

TP47

TP46

RP45

RP44

RP43

RP42

RP41

RP40

00H

S0ADDR

S0ADEN

S0BUF

00H

xxxxxxxxB

9F

9E

9D

9C

REN

9B

9A

99

TI

98

RI

S0CON*

S1ADR#

SIDAT#

S1STA#

Serial 0 control

Serial 1 address

Serial 1 data

98H

DBH

DAH

D9H

SM0/FE

SM1

SM2

TB8

RB8

00H

F8H

SLAVE ADDRESS

GC

Serial 1 status

SC4

DF

SC3

DE

SC2

DD

SC1

DC

SC0

DB

SI

0

DA

AA

D9

D8

SICON#*

SP

Serial 1 control

Stack pointer

Set enable

D8H

81H

EEH

CR2

ENS1

STA

ST0

CR1

CR0

00H

07H

C0H

STE#

TG47

TG46

SP45

SP44

SP43

SP42

SP41

SP40

TH1

TH0

TL1

TL0

TMH2#

TML2#

Timer high 1

Timer high 0

Timer low 1

Timer low 0

Timer high 2

Timer low 2

8DH

8CH

8BH

8AH

EDH

ECH

00H

TMOD

Timer mode

89H

GATE

8F

C/T

8E

M1

8D

M0

8C

GATE

8B

C/T

8A

M1

89

M0

88

00H

TCON*

Timer control

88H

TF1

TR1

T2IS0

CE

TF0

T2ER

CD

TR0

T2B0

CC

IE1

IT1

IE0

IT0

00H

TM2CON# Timer 2 control

EAH

T2IS1

CF

T2P1

CB

T2P0

CA

T2MS1

C9

T2MS0

C8

TM2IR#*

T3#

Timer 2 int flag reg

Timer 3

C8H

FFH

T20V

CMI2

CMI1

CMI0

CTI3

CTI2

CTI1

CTI0

00H

*

#

SFRs are bit addressable.

SFRs are modified from or added to the 80C51 SFRs.

8

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

OSCILLATOR CHARACTERISTICS

V

DD

XTAL1 and XTAL2 are the input and output, respectively, of an

inverting amplifier. The pins can be configured for use as an on-chip

oscillator, as shown in the logic symbol.

V

DD

To drive the device from an external clock source, XTAL1 should be

driven while XTAL2 is left unconnected. The minimum and maximum

high and low times specified in the data sheet must be observed.

+

2.2 µF

8XC554

RESET

RST

A reset is accomplished by either (1) externally holding the RST pin

high for at least two machine cycles (12 oscillator periods) or (2)

internally by an on-chip power-on detect (POD) circuit which detects

R

RST

V

CC

ramping up from 0 V.

To insure a good external power-on reset, the RST pin must be high

long enough for the oscillator to start up (normally a few

milliseconds) plus two machine cycles. The voltage on V and the

DD

RST pin must come up at the same time for a proper startup.

SU00953

For a successful internal power-on reset, the V voltage must

CC

Figure 2. Power-On Reset

ramp up from 0 V smoothly at a ramp rate greater than 5 V/100 ms.

The RST line can also be pulled HIGH internally by a pull-up

transistor activated by the watchdog timer T3. The length of the

output pulse from T3 is 3 machine cycles. A pulse of such short

duration is necessary in order to recover from a processor or system

fault as fast as possible.

LOW POWER MODES

Stop Clock Mode

The static design enables the clock speed to be reduced down to

0 MHz (stopped). When the oscillator is stopped, the RAM and

Special Function Registers retain their values. This mode allows

step-by-step utilization and permits reduced system power

consumption by lowering the clock frequency down to any value. For

lowest power consumption the Power Down mode is suggested.

Note that the short reset pulse from Timer T3 cannot discharge the

power-on reset capacitor (see Figure 2). Consequently, when the

watchdog timer is also used to set external devices, this capacitor

arrangement should not be connected to the RST pin, and a

different circuit should be used to perform the power-on reset

operation. A timer T3 overflow, if enabled, will force a reset condition

to the 8xC554 by an internal connection, independent of the level of

the RST pin.

Idle Mode

In the idle mode (see Table 2), the CPU puts itself to sleep while

some of the on-chip peripherals stay active. The instruction to

invoke the idle mode is the last instruction executed in the normal

operating mode before the idle mode is activated. The CPU

contents, the on-chip RAM, and all of the special function registers

remain intact during this mode. The idle mode can be terminated

either by any enabled interrupt (at which time the process is picked

up at the interrupt service routine and continued), or by a hardware

reset which starts the processor in the same manner as a power-on

reset.

A reset may be performed in software by setting the software reset

bit, SRST (AUXR1.5).

V

DD

OVERFLOW

TIMER T3

Power-Down Mode

SCHMITT

TRIGGER

To save even more power, a Power Down mode (see Table 2) can

be invoked by software. In this mode, the oscillator is stopped and

the instruction that invoked Power Down is the last instruction

executed. The on-chip RAM and Special Function Registers retain

RESET

CIRCUITRY

RST

their values down to 2.0 V and care must be taken to return V to

CC

the minimum specified operating voltages before the Power Down

Mode is terminated.

ON-CHIP

RESISTOR

R

RST

Either a hardware reset or external interrupt can be used to exit from

Power Down. The Wake-up from Power-down bit, WUPD (AUXR1.3)

must be set in order for an external interrupt to cause a wake-up

from power-down. Reset redefines all the SFRs but does not

change the on-chip RAM. An external interrupt allows both the SFRs

and the on-chip RAM to retain their values.

SU00952

Figure 1. On-Chip Reset Configuration

To properly terminate Power Down the reset or external interrupt

should not be executed before V is restored to its normal

CC

operating level and must be held active long enough for the

oscillator to restart and stabilize (normally less than 10 ms).

9

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

Table 2. External Pin Status During Idle and Power-Down Modes

PROGRAM

MEMORY

PWM0/

MODE

Idle

ALE

PSEN

PORT 0

Data

PORT 1

Data

PORT 2

Data

PORT 3

Data

PORT 4

Data

PWM1

High

Internal

1

0

1

0

Idle

External

Internal

Float

Data

Address

Data

Power-down

Data

External

Float

Data

With an external interrupt, INT0 and INT1 must be enabled and

ONCE Mode

configured as level-sensitive. Holding the pin low restarts the oscillator

but bringing the pin back high completes the exit. Once the interrupt

is serviced, the next instruction to be executed after RETI will be the

one following the instruction that put the device into Power Down.

The ONCE (“On-Circuit Emulation”) Mode facilitates testing and

debugging of systems without the device having to be removed from

the circuit. The ONCE Mode is invoked by:

1. Pull ALE low while the device is in reset and PSEN is high;

2. Hold ALE low as RST is deactivated.

POWER OFF FLAG

The Power Off Flag (POF) is set by on-chip circuitry when the V

level on the 8xC554 rises from 0 to 5 V. The POF bit can be set or

cleared by software allowing a user to determine if the reset is the

While the device is in ONCE Mode, the Port 0 pins go into a float

state, and the other port pins and ALE and PSEN are weakly pulled

high. The oscillator circuit remains active. While the device is in this

mode, an emulator or test CPU can be used to drive the circuit.

Normal operation is restored when a normal reset is applied.

CC

result of a power-on or a warm start after powerdown. The V level

CC

must remain above 3 V for the POF to remain unaffected by the V

level.

CC

Reduced EMI Mode

Design Consideration

The ALE-Off bit, AO (AUXR.0) can be set to disable the ALE output.

It will automatically become active when required for external

memory accesses and resume to the OFF state after completing the

external memory access.

• When the idle mode is terminated by a hardware reset, the device

normally resumes program execution, from where it left off, up to

two machine cycles before the internal reset algorithm takes

control. On-chip hardware inhibits access to internal RAM in this

event, but access to the port pins is not inhibited. To eliminate

the possibility of an unexpected write when Idle is terminated by

reset, the instruction following the one that invokes Idle should not

be one that writes to a port pin or to external memory.

7

6

5

4

3

2

1

0

PCON

(87H)

SMOD1 SMOD0

(MSB)

POF

WLE

GF1

GF0

PD

IDL

(LSB)

BIT

SYMBOL FUNCTION

PCON.7

SMOD1

Double Baud rate bit. When set to logic 1, the baud rate is doubled when the serial port SIO0 is being

used in modes 1, 2, or 3.

PCON.6

PCON.5

PCON.4

SMOD0

POF

WLE

Selects SM0/FE for SCON.7 bit.

Power Off Flag

Watchdog Load Enable. This flag must be set by software prior to loading timer T3 (watchdog timer). It is

cleared when timer T3 is loaded.

PCON.3

PCON.2

PCON.1

PCON.0

GF1

GF0

PD

General-purpose flag bit.

Power-down bit. Setting this bit activates the power-down mode. It can only be set if input EW is high.

Idle mode bit. Setting this bit activates the Idle mode.

IDL

If logic 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (00X00000).

SU00954

Figure 3. Power Control Register (PCON)

10

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

For example:

Expanded Data RAM Addressing

The 8xC554 has internal data memory that is mapped into four

separate segments: the lower 128 bytes of RAM, upper 128 bytes of

RAM, 128 bytes Special Function Register (SFR), and 256 bytes

expanded RAM (EXTRAM).

MOV @R0,#data

where R0 contains 0A0H, accesses the data byte at address 0A0H,

rather than P2 (whose address is 0A0H).

The ERAM can be accessed by indirect addressing, with EXTRAM

bit cleared and MOVX instructions. This part of memory is physically

located on-chip, logically occupies the first 256-bytes of external

data memory.

The four segments are:

1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are

directly and indirectly addressable.

With EXTRAM = 0, the EXTRAM is indirectly addressed, using the

MOVX instruction in combination with any of the registers R0, R1 of

the selected bank or DPTR. An access to ERAM will not affect ports

P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is output during expanded

RAM addressing. For example, with EXTRAM = 0,

2. The Upper 128 bytes of RAM (addresses 80H to FFH) are

indirectly addressable only.

3. The Special Function Registers, SFRs, (addresses 80H to FFH)

are directly addressable only.

4. The 256-bytes expanded RAM (ERAM, 00H – FFH) are indirectly

accessed by move external instruction, MOVX, and with the

EXTRAM bit cleared, see Figure 4.

MOVX @R0,#data

where R0 contains 0A0H, accesses the ERAM at address 0A0H

rather than external memory. An access to external data memory

locations higher than FFH (i.e., 0100H to FFFFH) will be performed

with the MOVX DPTR instructions in the same way as in the

standard 80C51, so with P0 and P2 as data/address bus, and P3.6

and P3.7 as write and read timing signals. Refer to Figure 5.

The Lower 128 bytes can be accessed by either direct or indirect

addressing. The Upper 128 bytes can be accessed by indirect

addressing only. The Upper 128 bytes occupy the same address

space as the SFR. That means they have the same address, but are

physically separate from SFR space.

With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar

to the standard 80C51. MOVX @ Ri will provide an 8-bit address

multiplexed with data on Port 0 and any output port pins can be

used to output higher order address bits. This is to provide the

external paging capability. MOVX @DPTR will generate a 16-bit

address. Port 2 outputs the high-order eight address bits (the

contents of DPH) while Port 0 multiplexes the low-order eight

address bits (DPL) with data. MOVX @Ri and MOVX @DPTR will

generate either read or write signals on P3.6 (#WR) and P3.7 (#RD).

When an instruction accesses an internal location above address

7FH, the CPU knows whether the access is to the upper 128 bytes

of data RAM or to SFR space by the addressing mode used in the

instruction. Instructions that use direct addressing access SFR

space. For example:

MOV 0A0H,#data

accesses the SFR at location 0A0H (which is P2). Instructions that

use indirect addressing access the Upper 128 bytes of data RAM.

The stack pointer (SP) may be located anywhere in the 256 bytes

RAM (lower and upper RAM) internal data memory. The stack may

not be located in the ERAM address space.

AUXR

Address = 8EH

Reset Value = xxxx x110B

Not Bit Addressable

—

6

—

5

—

4

—

3

LVADC EXTRAM

AO

Bit:

Function

Disable/Enable ALE

7

2

1

0

Symbol

AO

0

1

Operating Mode

ALE is emitted at a constant rate of 1/6 the oscillator frequency.

ALE is active only during a MOVX or MOVC instruction.

EXTRAM

LVADC

Internal/External RAM (00H – FFH) access using MOVX @Ri/@DPTR

EXTRAM

Operating Mode

0

1

Internal ERAM (00H–FFH) access using MOVX @Ri/@DPTR

External data memory access.

Enable A/D low voltage operation

LVADC

Operating Mode

0

1

Turns off A/D charge pump.

Turns on A/D charge pump. Required for operation below 4V.

—

Not implemented, reserved for future use*.

NOTE:

*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that

case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

SU00979A

Figure 4. AUXR: Auxiliary Register

11

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

FF

FFFF

UPPER

128 BYTES

INTERNAL RAM

SPECIAL

FUNCTION

REGISTER

EXTERNAL

DATA

MEMORY

80

ERAM

256 BYTES

LOWER

128 BYTES

INTERNAL RAM

0100

0000

00

SU00980

Figure 5. Internal and External Data Memory Address Space with EXTRAM = 0

Note that bit 2 is not writable and is always read as a zero. This

allows the DPS bit to be quickly toggled simply by executing an

INC AUXR1 instruction without affecting the other bits.

Dual DPTR

The dual DPTR structure (see Figure 6) is a way by which the chip

will specify the address of an external data memory location. There

are two 16-bit DPTR registers that address the external memory,

and a single bit called DPS = AUXR1/bit0 that allows the program

code to switch between them.

DPTR Instructions

The instructions that refer to DPTR refer to the data pointer that is

currently selected using the AUXR1/bit 0 register. The six

instructions that use the DPTR are as follows:

The DPS bit status should be saved by software when switching

between DPTR0 and DPTR1.

INC DPTR

Increments the data pointer by 1

MOV DPTR, #data16 Loads the DPTR with a 16-bit constant

MOV A, @ A+DPTR

MOVX A, @ DPTR

Move code byte relative to DPTR to ACC

DPS

BIT0

Move external RAM (16-bit address) to

ACC

AUXR1

DPTR1

DPTR0

MOVX @ DPTR , A

JMP @ A + DPTR

Move ACC to external RAM (16-bit

address)

DPH

(83H)

DPL

(82H)

EXTERNAL

DATA

MEMORY

Jump indirect relative to DPTR

SU00745A

The data pointer can be accessed on a byte-by-byte basis by

specifying the low or high byte in an instruction which accesses the

SFRs. See application note AN458 for more details.

Figure 6.

12

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

AUXR1

Address = A2H

Reset Value = 0000 00x0B

Not Bit Addressable

ADC8

AIDL

SRST

GF2

WUPD

0

—

1

DSP

Bit:

Function

Data Pointer Switch—switches between DPRT0 and DPTR1.

7

6

5

4

3

2

0

Symbol

DPS

0

1

Operating Mode

DPTR0

DPTR1

WUPD

GF2

Enable wakeup from powerdown.

General Purpose Flag—set and cleared by the user.

Software Reset

SRST

AIDL

ADC8

Enables the ADC during idle mode.

ADC Mode Switch—switches between 10-bit conversion and 8-bit conversion.

ADC8

Operating Mode

0

1

10-bit conversion (50 machine cycles)

8-bit conversion (24 machine cycles)

NOTE:

*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that

case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

SU01081

Figure 7. AUXR1: DPTR Control Register

13

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

hardware to make the comparisons. This feature saves a great deal

of software overhead by eliminating the need for the software to

examine every serial address which passes by the serial port. This

feature is enabled by setting the SM2 bit in S0CON. In the 9 bit

UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI)

will be automatically set when the received byte contains either the

“Given” address or the “Broadcast” address. The 9 bit mode

requires that the 9th information bit is a 1 to indicate that the

received information is an address and not data. Automatic address

recognition is shown in Figure 10.

Enhanced UART

The UART operates in all of the usual modes that are described in

the first section of Data Handbook IC20, 80C51-Based 8-Bit

Microcontrollers. In addition the UART can perform framing error

detect by looking for missing stop bits, and automatic address

recognition. The UART also fully supports multiprocessor

communication as does the standard 80C51 UART.

When used for framing error detect the UART looks for missing stop

bits in the communication. A missing bit will set the FE bit in the

S0CON register. The FE bit shares the S0CON.7 bit with SM0 and

the function of S0CON.7 is determined by PCON.6 (SMOD0) (see

Figure 8). If SMOD0 is set then S0CON.7 functions as FE.

The 8 bit mode is called Mode 1. In this mode the RI flag will be set

if SM2 is enabled and the information received has a valid stop bit

following the 8 address bits and the information is either a Given or

Broadcast address.

S0CON.7 functions as SM0 when SMOD0 is cleared. When used as

FE S0CON.7 can only be cleared by software. Refer to Figure 9.

Automatic Address Recognition

Automatic Address Recognition is a feature which allows the UART

to recognize certain addresses in the serial bit stream by using

S0CON Address = 98H

Reset Value = 0000 0000B

Bit Addressable

SM0/FE

SM1

SM2

REN

TB8

RB8

Tl

Rl

Bit:

7

6

5

4

3

2

1

0

(SMOD0 = 0/1)*

Symbol

FE

Function

Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid

frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.

SM0

SM1

Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)

Serial Port Mode Bit 1

SM0

SM1

Mode

Description

Baud Rate**

f /6

OSC

0

1

0

1

0

1

0

1

2

3

shift register

8-bit UART

9-bit UART

variable

/32 or f

f

/16

OSC

variable

SM2

Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the

received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.

In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a

Given or Broadcast Address. In Mode 0, SM2 should be 0.

REN

TB8

RB8

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.

In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.

In Mode 0, RB8 is not used.

Tl

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the

other modes, in any serial transmission. Must be cleared by software.

Rl

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in

the other modes, in any serial reception (except see SM2). Must be cleared by software.

NOTE:

*SMOD0 is located at PCON6.

**f = oscillator frequency

OSC

SU01445

Figure 8. S0CON: Serial Port Control Register

14

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

D0

D1

D2

D3

D4

D5

D6

D7

D8

START

BIT

DATA BYTE

ONLY IN

MODE 2, 3

STOP

BIT

SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)

SM0 TO UART MODE CONTROL

SCON

(98H)

SM0 / FE

SMOD1

SM1

SM2

POF

REN

WLE

TB8

GF1

RB8

GF0

TI

RI

PCON

(87H)

SMOD0

PD

IDL

0 : S0CON.7 = SM0

1 : S0CON.7 = FE

SU00982

Figure 9. UART Framing Error Detection

D0

D1

D2

D3

D4

D5

D6

D7

D8

SCON

(98H)

SM0

SM1

SM2

REN

1

TB8

X

RB8

TI

RI

1

0

1

RECEIVED ADDRESS D0 TO D7

PROGRAMMED ADDRESS

COMPARATOR

IN UART MODE 2 OR MODE 3 AND SM2 = 1:

INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”

– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES

– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.

SU00045

Figure 10. UART Multiprocessor Communication, Automatic Address Recognition

Mode 0 is the Shift Register mode and SM2 is ignored.

Slave 1

SADDR

SADEN

Given

=

1100 0000

1111 1110

1100 000X

Using the Automatic Address Recognition feature allows a master to

selectively communicate with one or more slaves by invoking the

Given slave address or addresses. All of the slaves may be

contacted by using the Broadcast address. Two special Function

Registers are used to define the slave’s address, SADDR, and the

address mask, SADEN. SADEN is used to define which bits in the

SADDR are to b used and which bits are “don’t care”. The SADEN

mask can be logically ANDed with the SADDR to create the “Given”

address which the master will use for addressing each of the slaves.

Use of the Given address allows multiple slaves to be recognized

while excluding others. The following examples will help to show the

versatility of this scheme:

In the above example SADDR is the same and the SADEN data is

used to differentiate between the two slaves. Slave 0 requires a 0 in

bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is

ignored. A unique address for Slave 0 would be 1100 0010 since

slave 1 requires a 0 in bit 1. A unique address for slave 1 would be

1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be

selected at the same time by an address which has bit 0 = 0 (for

slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed

with 1100 0000.

Slave 0

SADDR

SADEN

Given

=

1100 0000

1111 1101

1100 00X0

15

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

In a more complex system the following could be used to select

slaves 1 and 2 while excluding slave 0:

Either or both of these overflows can be programmed to request an

interrupt. In both cases, the interrupt vector will be the same. When

the lower byte (TML2) overflows, flag T2B0 (TM2CON) is set and

flag T20V (TM2IR) is set when TMH2 overflows. These flags are set

one cycle after an overflow occurs. Note that when T20V is set,

T2B0 will also be set. To enable the byte overflow interrupt, bits ET2

(IEN1.7, enable overflow interrupt, see Figure 11) and T2IS0

(TM2CON.6, byte overflow interrupt select) must be set. Bit TWB0

(TM2CON.4) is the Timer T2 byte overflow flag.

Slave 0

SADDR

SADEN

Given

=

1100 0000

1111 1001

1100 0XX0

Slave 1

Slave 2

SADDR

SADEN

Given

=

1110 0000

1111 1010

1110 0X0X

SADDR

SADEN

Given

=

1110 0000

1111 1100

1110 00XX

To enable the 16-bit overflow interrupt, bits ET2 (IE1.7, enable

overflow interrupt) and T2IS1 (TM2CON.7, 16-bit overflow interrupt

select) must be set. Bit T2OV (TM2IR.7) is the Timer T2 16-bit

overflow flag. All interrupt flags must be reset by software. To enable

both byte and 16-bit overflow, T2IS0 and T2IS1 must be set and two

interrupt service routines are required. A test on the overflow flags

indicates which routine must be executed. For each routine, only the

corresponding overflow flag must be cleared.

In the above example the differentiation among the 3 slaves is in the

lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be

uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and

it can be uniquely addressed by 1110 and 0101. Slave 2 requires

that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0

and 1 and exclude Slave 2 use address 1110 0100, since it is

necessary to make bit 2 = 1 to exclude slave 2.

Timer T2 may be reset by a rising edge on RT2 (P1.5) if the Timer

T2 external reset enable bit (T2ER) in T2CON is set. This reset also

clears the prescaler. In the idle mode, the timer/counter and

prescaler are reset and halted. Timer T2 is controlled by the

TM2CON special function register (see Figure 12).

The Broadcast Address for each slave is created by taking the

logical OR of SADDR and SADEN. Zeros in this result are trended

as don’t-cares. In most cases, interpreting the don’t-cares as ones,

the broadcast address will be FF hexadecimal.

Timer T2 Extension: When a 6 MHz oscillator is used, a 16-bit

overflow on Timer T2 occurs every 65.5, 131, 262, or 524 ms,

depending on the prescaler division ratio; i.e., the maximum cycle

time is approximately 0.5 seconds. In applications where cycle times

are greater than 0.5 seconds, it is necessary to extend Timer T2.

This is achieved by selecting fosc/12 as the clock source (set

T2MS0, reset T2MS1), setting the prescaler division ration to 1/8

(set T2P0, set T2P1), disabling the byte overflow interrupt (reset

T2IS0) and enabling the 16-bit overflow interrupt (set T2IS1). The

following software routine is written for a three-byte extension which

gives a maximum cycle time of approximately 2400 hours.

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR

address 0B9H) are leaded with 0s. This produces a given address

of all “don’t cares” as well as a Broadcast address of all “don’t

cares”. This effectively disables the Automatic Addressing mode and

allows the microcontroller to use standard 80C51 type UART drivers

which do not make use of this feature.

Timer T2

Timer T2 is a 16-bit timer consisting of two registers TMH2 (HIGH

byte) and TML2 (LOW byte). The 16-bit timer/counter can be

switched off or clocked via a prescaler from one of two sources:

OVINT: PUSH

PUSH

ACC

PSW

;save accumulator

;save status

f

/6 or an external signal. When Timer T2 is configured as a

OSC

counter, the prescaler is clocked by an external signal on T2 (P1.4).

A rising edge on T2 increments the prescaler, and the maximum

repetition rate is one count per machine cycle (0.5 MHz with a

12 MHz oscillator).

INC

TIMEX1 ;increment first byte (low order)

;of extended timer

MOV

JNZ

A,TIMEX1

INTEX

;jump to INTEX if ;there is no overflow

The maximum repetition rate for Timer T2 is twice the maximum

repetition rate for Timer 0 and Timer 1. T2 (P1.4) is sampled at

S2P1 and again at S5P1 (i.e., twice per machine cycle). A rising

edge is detected when T2 is LOW during one sample and HIGH

during the next sample. To ensure that a rising edge is detected, the

input signal must be LOW for at least 1/2 cycle and then HIGH for at

least 1/2 cycle. If a rising edge is detected before the end of S2P1,

the timer will be incremented during the following cycle; otherwise it

will be incremented one cycle later. The prescaler has a

programmable division factor of 1, 2, 4, or 8 and is cleared if its

division factor or input source is changed, or if the timer/counter is

reset.

INC

MOV

JNZ

INC

TIMEX2 ;increment second byte

A,TIMEX2

INTEX

;jump to INTEX if there is no overflow

TIMEX3 ;increment third byte (high order)

INTEX: CLR

POP

T2OV

PSW

ACC

;reset interrupt flag

;restore status

;restore accumulator

;return from interrupt

POP

RETI

Timer T2, Capture and Compare Logic: Timer T2 is connected to

four 16-bit capture registers and three 16-bit compare registers. A

capture register may be used to capture the contents of Timer T2

when a transition occurs on its corresponding input pin. A compare

register may be used to set, reset, or toggle port 4 output pins at

certain pre-programmable time intervals.

Timer T2 may be read “on the fly” but possesses no extra read

latches, and software precautions may have to be taken to avoid

misinterpretation in the event of an overflow from least to most

significant byte while Timer T2 is being read. Timer T2 is not

loadable and is reset by the RST signal or by a rising edge on the

input signal RT2, if enabled. RT2 is enabled by setting bit T2ER

(TM2CON.5).

The combination of Timer T2 and the capture and compare logic is

very powerful in applications involving rotating machinery,

automotive injection systems, etc. Timer T2 and the capture and

compare logic are shown in Figure 13.

When the least significant byte of the timer overflows or when a

16-bit overflow occurs, an interrupt request may be generated.

16

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

Reset Value = 00H

7

6

5

4

3

2

1

0

IEN1 (E8H)

ET2

ECM2

ECM1

ECM0

ECT3

ECT2

ECT1

ECT0

(LSB)

(MSB)

BIT

SYMBOL FUNCTION

IEN1.7

IEN1.6

IEN1.5

IEN1.4

IEN1.3

IEN1.2

IEN1.1

IEN1.0

ET2

Enable Timer T2 overflow interrupt(s)

Enable T2 Comparator 2 interrupt

Enable T2 Comparator 1 interrupt

Enable T2 Comparator 0 interrupt

Enable T2 Capture register 3 interrupt

Enable T2 Capture register 2 interrupt

Enable T2 Capture register 1 interrupt

Enable T2 Capture register 0 interrupt

ECM2

ECM1

ECM0

ECT3

ECT2

ECT1

ECT0

SU01083

Figure 11. Timer T2 Interrupt Enable Register (IEN1)

Reset Value = 00H

7

6

5

4

3

2

1

0

TM2CON (EAH)

T2IS1

(MSB)

T2IS0

T2ER

T2BO

T2P1

T2P0 T2MS1 T2MS0

(LSB)

BIT

SYMBOL

FUNCTION

TM2CON.7

TM2CON.6

TM2CON.5

TSIS1

T2IS0

T2ER

Timer T2 16-bit overflow interrupt select

Timer T2 byte overflow interrupt select

Timer T2 external reset enable. When this bit is set,

Timer T2 may be reset by a rising edge on RT2 (P1.5).

TM2CON.4

TM2CON.3

TM2CON.2

T2BO

T2P1

T2P0

Timer T2 byte overflow interrupt flag

Timer T2 prescaler select

T2P1

T2P0

Timer T2 Clock

0

1

0

1

0

1

Clock source

Clock source/2

Clock source/4

Clock source/8

TM2CON.1

TM2CON.0

T2MS1

T2MS0

Timer T2 mode select

T2MS1 T2MS0

Mode Selected

0

1

0

1

0

1

Timer T2 halted (off)

T2 clock source = f

/6

OSC

Test mode; do not use

T2 clock source = pin T2

SU01446

Figure 12. T2 Control Register (TM2CON)

17

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

CT0I

INT

CT1I

INT

CT2I

INT

CT3I

INT

CTI0

CTI1

CTI2

CTI3

CT0

CT1

CT2

CT3

off

8-bit overflow interrupt

16-bit overflow interrupt

Prescaler

T2 Counter

f

1/6

osc

T2

RT2

T2ER

External reset

enable

COMP

INT

S

R

P4.0

R

P4.1

CMO (S)

CM1 (R)

CM2 (T)

S

R

P4.2

P4.3

P4.4

P4.5

I/O port 4

S

=

set

T2 SFR address:

TML2

TMH2

=

lower 8 bits

higher 8 bits

R

reset

TG

T

P4.6

P4.7

T

toggle

TG

toggle status

STE

RTE

SU01447

Figure 13. Block Diagram of Timer 2

Capture Logic: The four 16-bit capture registers that Timer T2 is

connected to are: CT0, CT1, CT2, and CT3. These registers are

loaded with the contents of Timer T2, and an interrupt is requested

upon receipt of the input signals CT0I, CT1I, CT2I, or CT3I. These

input signals are shared with port 1. The four interrupt flags are in

the Timer T2 interrupt register (TM2IR special function register). If

the capture facility is not required, these inputs can be regarded as

additional external interrupt inputs.

can be measured using Timer T2 and a capture register. When an

event occurs, the contents of Timer T2 are copied into the relevant

capture register and an interrupt request is generated. The interrupt

service routine may then compute the interval time if it knows the

previous contents of Timer T2 when the last event occurred. With a

12 MHz oscillator, Timer T2 can be programmed to overflow every

524 ms. When event interval times are shorter than this, computing

the interval time is simple, and the interrupt service routine is short.

For longer interval times, the Timer T2 extension routine may be

used.

Using the capture control register CTCON (see Figure 14), these

inputs may capture on a rising edge, a falling edge, or on either a

rising or falling edge. The inputs are sampled during S1P1 of each

cycle. When a selected edge is detected, the contents of Timer T2

are captured at the end of the cycle.

Compare Logic: Each time Timer T2 is incremented, the contents

of the three 16-bit compare registers CM0, CM1, and CM2 are

compared with the new counter value of Timer T2. When a match is

found, the corresponding interrupt flag in TM2IR is set at the end of

the following cycle. When a match with CM0 occurs, the controller

sets bits 0-5 of port 4 if the corresponding bits of the set enable

register STE are at logic 1.

Measuring Time Intervals Using Capture Registers: When a

recurring external event is represented in the form of rising or falling

edges on one of the four capture pins, the time between two events

18

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

Reset Value = 00H

7

CTCON (EBH) CTN3

(MSB)

6

5

4

3

2

1

0

CTP3

CTN2

CTP2

CTN1

CTP1

CTN1

CTP0

(LSB)

BIT

SYMBOL CAPTURE/INTERRUPT ON:

CTCON.7 CTN3

Capture Register 3 triggered by a falling edge on CT3I

Capture Register 3 triggered by a rising edge on CT3I

Capture Register 2 triggered by a falling edge on CT2I

Capture Register 2 triggered by a rising edge on CT2I

Capture Register 1 triggered by a falling edge on CT1I

Capture Register 1 triggered by a rising edge on CT1I

Capture Register 0 triggered by a falling edge on CT0I

Capture Register 0 triggered by a rising edge on CT0I

CTCON.6 CTP3

CTCON.5 CTN2

CTCON.4 CTP2

CTCON.3 CTN1

CTCON.2 CTP1

CTCON.1 CTN0

CTCON.0 CTP0

SU01085

Figure 14. Capture Control Register (CTCON)

When a match with CM1 occurs, the controller resets bits 0-5 of port

4 if the corresponding bits of the reset/toggle enable register RTE

are at logic 1 (see Figure 15 for RTE register function). If RTE is “0”,

then P4.n is not affected by a match between CM1 or CM2 and

Timer 2. When a match with CM2 occurs, the controller “toggles”

bits 6 and 7 of port 4 if the corresponding bits of the RTE are at

logic 1. The port latches of bits 6 and 7 are not toggled.

Two additional flip-flops store the last operation, and it is these

flip-flops that are toggled.

Timer T2 Interrupt Flag Register TM2IR: Eight of the nine Timer

T2 interrupt flags are located in special function register TM2IR (see

Figure 17). The ninth flag is TM2CON.4.

The CT0I and CT1I flags are set during S4 of the cycle in which the

contents of Timer T2 are captured. CT0I is scanned by the interrupt

logic during S2, and CT1I is scanned during S3. CT2I and CT3I are

set during S6 and are scanned during S4 and S5. The associated

interrupt requests are recognized during the following cycle. If these

flags are polled, a transition at CT0I or CT1I will be recognized one

cycle before a transition on CT2I or CT3I since registers are read

during S5. The CMI0, CMI1, and CMI2 flags are set during S6 of the

cycle following a match. CMI0 is scanned by the interrupt logic

during S2; CMI1 and CMI2 are scanned during S3 and S4. A match

will be recognized by the interrupt logic (or by polling the flags) two

cycles after the match takes place.

Thus, if the current operation is “set,” the next operation will be

“reset” even if the port latch is reset by software before the “reset”

operation occurs. The first “toggle” after a chip RESET will set the

port latch. The contents of these two flip-flops can be read at STE.6

and STE.7 (corresponding to P4.6 and P4.7, respectively). Bits

STE.6 and STE.7 are read only (see Figure 16 for STE register

function). A logic 1 indicates that the next toggle will set the port

latch; a logic 0 indicates that the next toggle will reset the port latch.

CM0, CM1, and CM2 are reset by the RST signal.

The 16-bit overflow flag (T2OV) and the byte overflow flag (T2BO)

are set during S6 of the cycle in which the overflow occurs. These

flags are recognized by the interrupt logic during the next cycle.

The modified port latch information appears at the port pin during

S5P1 of the cycle following the cycle in which a match occurred. If

the port is modified by software, the outputs change during S1P1 of

the following cycle. Each port 4 bit can be set or reset by software at

any time. A hardware modification resulting from a comparator

match takes precedence over a software modification in the same

cycle. When the comparator results require a “set” and a “reset” at

the same time, the port latch will be reset.

Special function register IP1 (Figure 17) is used to determine the

Timer T2 interrupt priority. Setting a bit high gives that function a

high priority, and setting a bit low gives the function a low priority.

The functions controlled by the various bits of the IP1 register are

shown in Figure 17.

Reset Value = 00H

7

6

5

4

3

2

1

0

RTE (EFH)

TP47

(MSB)

TP46

RP45

RP44

RP43

RP42

RO41

RP40

(LSB)

BIT

SYMBOL FUNCTION

RTE.7

RTE.6

RTE.5

RTE.4

RTE.3

RTE.2

RTE.1

RTE.0

TP47

TP46

RP45

RP44

RP43

RP42

RP41

RP40

If “1” then P4.7 toggles on a match between CM1 and Timer T2

If “1” then P4.6 toggles on a match between CM1 and Timer T2

If “1” then P4.5 is reset on a match between CM1 and Timer T2

If “1” then P4.4 is reset on a match between CM1 and Timer T2

If “1” then P4.3 is reset on a match between CM1 and Timer T2

If “1” then P4.2 is reset on a match between CM1 and Timer T2

If “1” then P4.1 is reset on a match between CM1 and Timer T2

If “1” then P4.0 is reset on a match between CM1 and Timer T2

SU01086

Figure 15. Reset/Toggle Enable Register (RTE)

19

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

7

6

5

4

3

2

1

0

Reset Value = C0H

STE (EEH)

TG47

(MSB)

TG46

SP45

SP44

SP43

SP42

SP41

SP40

(LSB)

BIT

SYMBOL FUNCTION

STE.7

STE.6

STE.5

STE.4

STE.3

STE.2

STE.1

STE.0

TG47

TG46

SP45

SP44

SP43

SP42

SP41

SP40

Toggle flip-flops

If “1” then P4.5 is set on a match between CM0 and Timer T2

If “1” then P4.4 is set on a match between CM0 and Timer T2

If “1” then P4.3 is set on a match between CM0 and Timer T2

If “1” then P4.2 is set on a match between CM0 and Timer T2

If “1” then P4.1 is set on a match between CM0 and Timer T2

If “1” then P4.0 is set on a match between CM0 and Timer T2

SU01087

Figure 16. Set Enable Register (STE)

Reset Value = 00H

7

6

5

4

3

2

1

0

TM2IR (C8H) T2OV

CMI2

CMI1

CMI0

CTI3

CTI2

CTI1

CTI0

(LSB)

(MSB)

BIT

SYMBOL FUNCTION

TM2IR.7

TM2IR.6

TM2IR.5

TM2IR.4

TM2IR.3

TM2IR.2

TM2IR.1

TM2IR.0

T2OV

CMI2

CMI1

CMI0

CTI3

CTI2

CTI1

CTI0

Timer T2 16-bit overflow interrupt flag

CM2 interrupt flag

CM1 interrupt flag

CM0 interrupt flag

CT3 interrupt flag

CT2 interrupt flag

CT1 interrupt flag

CT0 interrupt flag

Interrupt Flag Register (TM2IR)

7

6

5

4

3

2

1

0

Reset Value = 00H

IP1 (F8H)

PT2

PCM2

PCM1

PCM0

PCT3

PCT2

PCT1

PCT0

(LSB)

(MSB)

BIT

SYMBOL FUNCTION

IP1.7

IP1.6

IP1.5

IP1.4

IP1.3

IP1.2

IP1.1

IP1.0

PT2

Timer T2 overflow interrupt(s) priority level

Timer T2 comparator 2 interrupt priority level

Timer T2 comparator 1 interrupt priority level

Timer T2 comparator 0 interrupt priority level

Timer T2 capture register 3 interrupt priority level

Timer T2 capture register 2 interrupt priority level

Timer T2 capture register 1 interrupt priority level

Timer T2 capture register 0 interrupt priority level

PCM2

PCM1

PCM0

PCT3

PCT2

PCT1

PCT0

Timer 2 Interrupt Priority Register (IP1)

SU01088

Figure 17. Interrupt Flag Register (TM2IR) and Timer T2 Interrupt Priority Register (IP1)

20

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

Timer T3, The Watchdog Timer

between 0.75 ms and 196 ms. When using a 24 MHz oscillator, the

watchdog interval is programmable between 0.5 ms and 127.5 ms.

In addition to Timer T2 and the standard timers, a watchdog timer is

also incorporated on the 8xC554. The purpose of a watchdog timer

is to reset the microcontroller if it enters erroneous processor states

(possibly caused by electrical noise or RFI) within a reasonable

period of time. An analogy is the “dead man’s handle” in railway

locomotives. When enabled, the watchdog circuitry will generate a

system reset if the user program fails to reload the watchdog timer

within a specified length of time known as the “watchdog interval.”

In order to prepare software for watchdog operation, a programmer

should first determine how long his system can sustain an

erroneous processor state. The result will be the maximum

watchdog interval. As the maximum watchdog interval becomes

shorter, it becomes more difficult for the programmer to ensure that

the user program always reloads the watchdog timer within the

watchdog interval, and thus it becomes more difficult to implement

watchdog operation.

Watchdog Circuit Description: The watchdog timer (Timer T3)

consists of an 8-bit timer with an 11-bit prescaler as shown in

Figure 18. The prescaler is fed with a signal whose frequency is 1/6

the oscillator frequency (0.5 MHz with a 12 MHz oscillator). The 8-bit

timer is incremented every “t” seconds, where:

The programmer must now partition the software in such a way that

reloading of the watchdog is carried out in accordance with the above

requirements. The programmer must determine the execution times

of all software modules. The effect of possible conditional branches,

subroutines, external and internal interrupts must all be taken into

account. Since it may be very difficult to evaluate the execution

times of some sections of code, the programmer should use worst

case estimations. In any event, the programmer must make sure

that the watchdog is not activated during normal operation.

t = 6 × 2048 × 1/f

OSC

(= 0.75 ms at f

= 16 MHz; = 0.5 ms at f

= 24 MHz)

OSC

If the 8-bit timer overflows, a short internal reset pulse is generated

which will reset the 8xC554. A short output reset pulse is also

generated at the RST pin. This short output pulse (3 machine

cycles) may be destroyed if the RST pin is connected to a capacitor.

This would not, however, affect the internal reset operation.

The watchdog timer is reloaded in two stages in order to prevent

erroneous software from reloading the watchdog. First PCON.4

(WLE) must be set. The T3 may be loaded. When T3 is loaded,

PCON.4 (WLE) is automatically reset. T3 cannot be loaded if

PCON.4 (WLE) is reset. Reload code may be put in a subroutine as

it is called frequently. Since Timer T3 is an up-counter, a reload

value of 00H gives the maximum watchdog interval (255 ms with a

12 MHz oscillator), and a reload value of 0FFH gives the minimum

watchdog interval (1 ms with a 12 MHz oscillator).

Watchdog operation is activated when external pin EW is tied low.

When EW is tied low, it is impossible to disable the watchdog

operation by software.

How to Operate the Watchdog Timer: The watchdog timer has to

be reloaded within periods that are shorter than the programmed

watchdog interval; otherwise the watchdog timer will overflow and a

system reset will be generated. The user program must therefore

continually execute sections of code which reload the watchdog

timer. The period of time elapsed between execution of these

sections of code must never exceed the watchdog interval. When

using a 16 MHz oscillator, the watchdog interval is programmable

In the idle mode, the watchdog circuitry remains active. When

watchdog operation is implemented, the power-down mode cannot

be used since both states are contradictory. Thus, when watchdog

operation is enabled by tying external pin EW low, it is impossible to

enter the power-down mode, and an attempt to set the power-down

bit (PCON.1) will have no effect. PCON.1 will remain at logic 0.

INTERNAL BUS

V

DD

P

OVERFLOW

f

/6

OSC

PRESCALER (11-BIT)

CLEAR

TIMER T3 (8-BIT)

LOAD LOADEN

RST

INTERNAL

RESET

WRITE T3

R

RST

CLEAR

WLE

PD

LOADEN

PCON.1

PCON.4

EW

INTERNAL BUS

SU00955

Figure 18. Watchdog Timer

21

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

During the early stages of software development/debugging, the

watchdog may be disabled by tying the EW pin high. At a later

stage, EW may be tied low to complete the debugging process.

Buffered PWM outputs may be used to drive DC motors. The

rotation speed of the motor would be proportional to the contents of

PWMn. The PWM outputs may also be configured as a dual DAC. In

this application, the PWM outputs must be integrated using

conventional operational amplifier circuitry. If the resulting output

voltages have to be accurate, external buffers with their own analog

supply should be used to buffer the PWM outputs before they are

Watchdog Software Example: The following example shows how

watchdog operation might be handled in a user program.

;at the program start:

integrated. The repetition frequency f

give by:

, at the PWMn outputs is

PWM

T3

PCON

EQU 0FFH ;address of watchdog timer T3

EQU 087H ;address of PCON SFR

WATCH-INTV EQU 156 ;watchdog interval (e.g., 100 ms)

f_OSC

f_PWM

+

(1 ) PWMP) 255

This gives a repetition frequency range of 246 Hz to 62.8 kHz

(f = 16 MHz). At f = 24 MHz, the frequency range is 368 Hz

;to be inserted at each watchdog reload location within

;the user program:

OSC

LCALL WATCHDOG

to 83.4 Hz. By loading the PWM registers with either 00H or FFH,

the PWM channels will output a constant HIGH or LOW level,

respectively. Since the 8-bit counter counts modulo 255, it can never

actually reach the value of the PWM registers when they are loaded

with FFH.

;watchdog service routine:

WATCHDOG: ORL PCON,#10H ;set condition flag (PCON.4)

MOV T3,WATCH-INV

RET

;load T3 with watchdog interval

When a compare register (PWM0 or PWM1) is loaded with a new

value, the associated output is updated immediately. It does not

have to wait until the end of the current counter period. Both PWMn

output pins are driven by push-pull drivers. These pins are not used

for any other purpose.

If it is possible for this subroutine to be called in an erroneous state,

then the condition flag WLE should be set at different parts of the

main program.

Serial I/O

The 8xC554 is equipped with two independent serial ports: SIO0

and SIO1. SIO0 is a full duplex UART port and is similar to the

Enhanced UART serial port. SIO1 accommodates the I C bus.

Prescaler frequency control register PWMP

Reset Value = 00H

2

PWMP (FEH)

7

6

5

4

3

2

1

0

MSB

LSB

SIO0: SIO0 is a full duplex serial I/O port identical to that of the

Enhanced UART except Time 2 cannot be used as a baud rate

generator. Its operation is the same, including the use of timer 1 as a

baud rate generator.

PWMP.0-7

Prescaler division factor = PWMP + 1.

Reading PWMP gives the current reload value. The actual count of

the prescaler cannot be read.

Port 5 Operation

Reset Value = 00H

Port 5 may be used to input up to 8 analog signals to the ADC.

Unused ADC inputs may be used to input digital inputs. These

inputs have an inherent hysteresis to prevent the input logic from

drawing excessive current from the power lines when driven by

analog signals. Channel to channel crosstalk (Ct) should be taken

into consideration when both analog and digital signals are

simultaneously input to Port 5 (see, D.C. characteristics in data

sheet).

PWM0 (FCH)

PWM1 (FDH)

7

6

5

4

3

2

1

0

MSB

LSB

(PWMn)

255 * (PWMn)

PWM0/1.0-7} Low/high ratio of PWMn +

Analog-to-Digital Converter

The analog input circuitry consists of an 8-input analog multiplexer

and a 10-bit, straight binary, successive approximation ADC. The

A/D can also be operated in 8-bit mode with faster conversion times

by setting bit ADC8 (AUXR1.7). The 8-bit results will be contained in

the ADCH register. The analog reference voltage and analog power

supplies are connected via separate input pins. For 10-bit accuracy,

the conversion takes 50 machine cycles, i.e., 18.75 µs at an

oscillator frequency of 16 MHz, 12.5 µs at an oscillator frequency of

24 MHz. For the 8-bit mode, the conversion takes 24 machine

cycles. Input voltage swing is from 0 V to +5 V. Because the internal

DAC employs a ratiometric potentiometer, there are no

Port 5 is not bidirectional and may not be configured as an output

port. All six ports are multifunctional, and their alternate functions

are listed in the Pin Descriptions section of this datasheet.

Pulse Width Modulated Outputs

The 8xC554 contains two pulse width modulated output channels

(see Figure 19). These channels generate pulses of programmable

length and interval. The repetition frequency is defined by an 8-bit

prescaler PWMP, which supplies the clock for the counter. The

prescaler and counter are common to both PWM channels. The 8-bit

counter counts modulo 255, i.e., from 0 to 254 inclusive. The value

of the 8-bit counter is compared to the contents of two registers:

PWM0 and PWM1. Provided the contents of either of these registers

is greater than the counter value, the corresponding PWM0 or

PWM1 output is set LOW. If the contents of these registers are

equal to, or less than the counter value, the output will be HIGH. The

pulse-width-ratio is therefore defined by the contents of the registers

PWM0 and PWM1. The pulse-width-ratio is in the range of 0 to 1

and may be programmed in increments of 1/255.

discontinuities in the converter characteristic. Figure 20 shows a

functional diagram of the analog input circuitry.

The ADC has the option of either being powered off in idle mode for

reduced power consumption or being active in idle mode for

reducing internal noise during the conversion. This option is selected

by the AIDL bit of AUXR1 register (AUXR1.6). With the AIDL bit set,

the ADC is active in the idle mode, and with the AIDL bit cleared, the

ADC is powered off in idle mode.

22

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

PWM0

OUTPUT

BUFFER

8-BIT COMPARATOR

PWM0

f

OSC

PRESCALER

PWMP

8-BIT COUNTER

OUTPUT

BUFFER

PWM1

8-BIT COMPARATOR

PWM1

SU01448

Figure 19. Functional Diagram of Pulse Width Modulated Outputs

STADC

ADC0

ADC1

+

–

ANALOG REF.

ADC2

ADC3

ADC4

ADC5

ANALOG INPUT

MULTIPLEXER

10-BIT A/D CONVERTER

ANALOG SUPPLY

ANALOG GROUND

ADC6

ADCON

ADCH

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

INTERNAL BUS

SU01467

Figure 20. Functional Diagram of Analog Input Circuitry

10-Bit Analog-to-Digital Conversion: Figure 21 shows the

elements of a successive approximation (SA) ADC. The ADC

contains a DAC which converts the contents of a successive

approximation register to a voltage (VDAC) which is compared to

the analog input voltage (Vin). The output of the comparator is fed to

the successive approximation control logic which controls the

successive approximation register. A conversion is initiated by

setting ADCS in the ADCON register. ADCS can be set by software

only or by either hardware or software.

The software only start mode is selected when control bit ADCON.5

(ADEX) = 0. A conversion is then started by setting control bit

ADCON.3 (ADCS). The hardware or software start mode is selected

when ADCON.5 = 1, and a conversion may be started by setting

ADCON.3 as above or by applying a rising edge to external pin

STADC. When a conversion is started by applying a rising edge, a

low level must be applied to STADC for at least one machine cycle

followed by a high level for at least one machine cycle.

23

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

+

–

V

in

V

DAC

SUCCESSIVE

APPROXIMATION

REGISTER

SUCCESSIVE

APPROXIMATION

CONTROL LOGIC

DAC

START

15/16

STOP

59/64

FULL SCALE

1

V

in

3/4

29/32

7/8

1/2

V

DAC

0

1

2

3

4

5

6

t/tau

SU00958

Figure 21. Successive Approximation ADC

The low-to-high transition of STADC is recognized at the end of a

machine cycle, and the conversion commences at the beginning of

the next cycle. When a conversion is initiated by software, the

conversion starts at the beginning of the machine cycle which

follows the instruction that sets ADCS. ADCS is actually

implemented with two flip-flops: a command flip-flop which is

affected by set operations, and a status flag which is accessed

during read operations.

previous result), and VDAC is compared to Vin again. If the input

voltage is greater than VDAC, then the bit being tested remains set;

otherwise the bit being tested is cleared. This process is repeated

until all ten bits have been tested, at which stage the result of the

conversion is held in the successive approximation register.

Figure 22 shows a conversion flow chart. The bit pointer identifies

the bit under test. The conversion takes four machine cycles per bit.

The end of the 10-bit conversion is flagged by control bit ADCON.4

(ADCI). The upper 8 bits of the result are held in special function

register ADCH, and the two remaining bits are held in ADCON.7

(ADC.1) and ADCON.6 (ADC.0). The user may ignore the two least

significant bits in ADCON and use the ADC as an 8-bit converter (8

upper bits in ADCH). In any event, the total actual conversion time is

50 machine cycles for the 8xC554. ADCI will be set and the ADCS

status flag will be reset 50 cycles after the command flip-flop

(ADCS) is set.

The next two machine cycles are used to initiate the converter. At

the end of the first cycle, the ADCS status flag is set and a value of

“1” will be returned if the ADCS flag is read while the conversion is in

progress. Sampling of the analog input commences at the end of the

second cycle.

During the next eight machine cycles, the voltage at the previously

selected pin of port 5 is sampled, and this input voltage should be

stable in order to obtain a useful sample. In any event, the input

voltage slew rate must be less than 10 V/ms in order to prevent an

undefined result.

Control bits ADCON.0, ADCON.1, and ADCON.2 are used to control

an analog multiplexer which selects one of seven analog channels

(see Figure 23). An ADC conversion in progress is unaffected by an

external or software ADC start. The result of a completed

conversion remains unaffected provided ADCI = logic 1; a new ADC

conversion already in progress is aborted when the idle or

The successive approximation control logic first sets the most

significant bit and clears all other bits in the successive

approximation register (10 0000 0000B). The output of the DAC

(50% full scale) is compared to the input voltage Vin. If the input

voltage is greater than VDAC, then the bit remains set; otherwise it

is cleared.

power-down mode is entered. The result of a completed conversion

(ADCI = logic 1) remains unaffected when entering the idle mode.

The successive approximation control logic now sets the next most

significant bit (11 0000 0000B or 01 0000 0000B, depending on the

24

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

Start of Conversion

SOC

RESET SAR

[BIT POINTER] = MSB

[BIT] = 1

N

CONVERSION TIME

1

0

TEST

COMPLETE

[BIT] = 0

N

[BIT POINTER] + 1

END

TEST BIT

POINTER

END

EOC END OF CONVERSION

SU00959

Figure 22. A/D Conversion Flowchart

25

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

7

6

5

4

3

2

1

0

Reset Value = xx00 0000B

ADCON (C5H) ADC.1 ADC.0 ADEX ADCI ADCS AADR2 AADR1 AADR0

(MSB)

(LSB)

Bit

Symbol

Function

ADCON.7 ADC.1

ADCON.6 ADC.0

ADCON.5 ADEX

Bit 1 of ADC result

Bit 0 of ADC result

Enable external start of conversion by STADC

0 = Conversion can be started by software only (by setting ADCS)

1 = Conversion can be started by software or externally (by a rising edge on STADC)

ADCON.4 ADCI

ADCON.3 ADCS

ADC interrupt flag: this flag is set when an A/D conversion result is ready to be read. An interrupt is

invoked if it is enabled. The flag may be cleared by the interrupt service routine. While this flag is set,

the ADC cannot start a new conversion. ADCI cannot be set by software.

ADC start and status: setting this bit starts an A/D conversion. It may be set by software or by the

external signal STADC. The ADC logic ensures that this signal is HIGH while the ADC is busy. On

completion of the conversion, ADCS is reset immediately after the interrupt flag has been set. ADCS

cannot be reset by software. A new conversion may not be started while either ADCS or ADCI is high.

ADCI

ADCS

ADC Status

0

1

0

1

0

1

ADC not busy; a conversion can be started

ADC busy; start of a new conversion is blocked

Conversion completed; start of a new conversion requires ADCI=0

If ADCI is cleared by software while ADCS is set at the same time, a new A/D conversion with the

same channel number may be started.

But it is recommended to reset ADCI before ADCS is set.

ADCON.2 AADR2

ADCON.1 AADR1

ADCON.0 AADR0

Analogue input select: this binary coded address selects one of the

eight analogue port bits of P5 to be input to the converter. It can only

be changed when ADCI and ADCS are both LOW.

AADR2 AADR1 AADR0

Selected Analog Channel

0

1

0

1

0

1

0

1

0

1

0

1

0

ADC0 (P5.0)

ADC1 (P5.1)

ADC2 (P5.2)

ADC3 (P5.3)

ADC4 (P5.4)

ADC5 (P5.5)

ADC6 (P5.6)

SU01468

Figure 23. ADC Control Register (ADCON)

26

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

10-Bit ADC Resolution and Analog Supply: Figure 24 shows how

the ADC is realized. The ADC has its own supply pins (AV and

Power Reduction Modes

The 8xC554 has two reduced power modes of operation: the idle

mode and the power-down mode. These modes are entered by

setting bits in the PCON special function register. When the 8xC554

enters the idle mode, the following functions are disabled:

DD

AV ) and two pins (Vref+ and Vref–) connected to each end of the

SS

DAC’s resistance-ladder. The ladder has 1023 equally spaced taps,

separated by a resistance of “R”. The first tap is located 0.5 x R

above Vref–, and the last tap is located 1.5 x R below Vref+. This

gives a total ladder resistance of 1024 x R. This structure ensures

that the DAC is monotonic and results in a symmetrical quantization

error as shown in Figure 26.

CPU

(halted)

Timer T2

PWM0, PWM1

ADC

(halted and reset)

(reset; outputs are high)

(may be enabled for operation in Idle mode

by setting bit AIDC (AUXR1.6) ).

For input voltages between Vref– and (Vref–) + 1/2 LSB, the 10-bit

result of an A/D conversion will be 00 0000 0000B = 000H. For input

voltages between (Vref+) – 3/2 LSB and Vref+, the result of a

conversion will be 11 1111 1111B = 3FFH. AVref+ and AVref– may

be between AV + 0.2 V and AV – 0.2 V. AVref+ should be

In idle mode, the following functions remain active:

Timer 0

Timer 1

DD

SS

positive with respect to AVref–, and the input voltage (Vin) should be

between AVref+ and AVref–. If the analog input voltage range is from

2 V to 4 V, then 10-bit resolution can be obtained over this range if

AVref+ = 4 V and AVref– = 2 V.

Timer T3

SIO0 SIO1

External interrupts

When the 8xC554 enters the power-down mode, the oscillator is

stopped. The power-down mode is entered by setting the PD bit in

the PCON register. The PD bit can only be set if the EW input is tied

HIGH.

The result can always be calculated from the following formula:

V

_IN* AV_ref*

Result + 1024

AV_ref)* AV_ref*

AV

ref+

R/2

1023

1022

MSB

R

START

1021

SUCCESSIVE

APPROXIMATION

REGISTER

SUCCESSIVE

APPROXIMATION

CONTROL LOGIC

DECODER

TOTAL RESISTANCE

=

1023R + 2 x R/

1024R

3

2

READY

R

1

0

LSB

R/2

V

–

ref

AV

ref–

COMPARATOR

+

V

in

Value 0000 0000 00

Value 1111 1111 11

is output for voltages V

is output for voltages (V

ref+

to (V

+ 1/2 LSB)

ref–

– 3/2 LSB) to V

ref+

SU00961

Figure 24. ADC Realization

27

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

Sm

Rm

N+1

I

N+1

N

TO COMPARATOR

I

N

+

MULTIPLEXER

R

S

C

S

V

ANALOG

INPUT

Rm = 0.5 - 3 kΩ

C

R

+ C = 15 pF maximum

= Recommended < 9.6 kΩ for 1 LSB @ 12 MHz

S

C

NOTE:

Because the analog to digital converter has a sampled-data comparator, the input looks capacitive to a source. When a conversion

is initiated, switch Sm closes for 8t (4 µs @ 12 MHz crystal frequency) during which time capacitance C + C is charged. It

CY

S

C

should be noted that the sampling causes the analog input to present a varying load to an analog source.

SU01449

Figure 25. A/D Input: Equivalent Circuit

CODE

101

OUT

100

011

010

001

000

0

q

2q

3q

4q

5q

V

in

QUANTIZATION ERROR

q = LSB = 5 mV

V

– V

digital

in

+ q/2

– q/2

V

in

SYMMETRICAL QUANTIZATION ERROR

SU00963

Figure 26. Effective Conversion Characteristic

28

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

Interrupts

interrupt enable special function registers IEN0 and IEN1. All

interrupt sources can also be globally enabled or disabled by setting

or clearing bit EA in IEN0. The interrupt enable registers are

described in Figures 27 and 28.

The 8xC554 has fifteen interrupt sources, each of which can be

assigned one of four priority levels. The five interrupt sources

common to the 80C51 are the external interrupts (INT0 and INT1),

the timer 0 and timer 1 interrupts (IT0 and IT1), and the serial I/O

interrupt (RI or TI). In the 8xC554, the standard serial interrupt is

called SIO0.

There are 3 SFRs associated with each of the four-level interrupts.

They are the IENx, IPx, and IPxH. (See Figures 29, 30, and 31.) The

IPxH (Interrupt Priority High) register makes the four-level interrupt

structure possible.

The eight Timer T2 interrupts are generated by flags CTI0-CT13,

CMI0-CMI2, and by the logical OR of flags T2OV and T2BO. Flags

CTI0 to CT13 are set by input signals CT0I to CT3i. Flags CMI0 to

CMI2 are set when a match occurs between Timer T2 and the

compare registers CM0, CM1, and CM2. When an 8-bit or 16-bit

overflow occurs, flags T2BO and T2OV are set, respectively. These

nine flags are not cleared by hardware and must be reset by

software to avoid recurring interrupts.

The function of the IPxH SFR is simple and when combined with the

IPx SFR determines the priority of each interrupt. The priority of

each interrupt is determined as shown in the following table:

PRIORITY BITS

INTERRUPT PRIORITY LEVEL

IPxH.x

IPx.x

0

1

0

1

0

1

Level 0 (lowest priority)

Level 1

The ADC interrupt is generated by the ADCI flag in the ADC control

register (ADCON). This flag is set when an ADC conversion result is

ready to be read. ADCI is not cleared by hardware and must be

reset by software to avoid recurring interrupts.

Level 2

Level 3 (highest priority)

2

The SIO1 (I C) interrupt is generated by the SI flag in the SIO1

control register (S1CON). This flag is set when S1STA is loaded

with a valid status code.

The priority scheme for servicing the interrupts is the same as that

for the 80C51, except there are four interrupt levels rather than two

as on the 80C51. An interrupt will be serviced as long as an interrupt

of equal or higher priority is not already being serviced. If an

interrupt of equal or higher level priority is being serviced, the new

interrupt will wait until it is finished before being serviced. If a lower

priority level interrupt is being serviced, it will be stopped and the

new interrupt serviced. When the new interrupt is finished, the lower

priority level interrupt that was stopped will be completed.

The ADCI flag may be reset by software. It cannot be set by

software. All other flags that generate interrupts may be set or

cleared by software, and the effect is the same as setting or

resetting the flags by hardware. Thus, interrupts may be generated

by software and pending interrupts can be canceled by software.

Interrupt Enable Registers: Each interrupt source can be

individually enabled or disabled by setting or clearing a bit in the

7

6

5

4

3

2

1

0

IEN0 (A8H)

EA

EAD

ES1

ES0

ET1

EX1

ET0

EX0

(LSB)

(MSB)

BIT

SYMBOL FUNCTION

IEN0.7

EA

Global enable/disable control

0 = No interrupt is enabled

1 = Any individually enabled interrupt will be accepted

IEN0.6

IEN0.5

IEN0.4

IEN0.3

IEN0.2

IEN0.1

IEN0.0

EAD

ES1

ES0

ET1

EX1

ET0

EX0

Eanble ADC interrupt

Enable SIO1 (I C) interrupt

Enable SIO0 (UART) interrupt

Enable Timer 1 interrupt

Enable External interrupt 1

Enable Timer 0 interrupt

2

Enable External interrupt 0

SU00762

Figure 27. Interrupt Enable Register (IEN0)

29

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

7

6

5

4

3

2

1

0

IEN1 (E8H)

ET2

ECM2

ECM1

ECM0

ECT3

ECT2

ECT1

ECT0

(LSB)

(MSB)

BIT

SYMBOL FUNCTION

IEN1.7

IEN1.6

IEN1.5

IEN1.4

IEN1.3

IEN1.2

IEN1.1

IEN1.0

ET2

Enable Timer T2 overflow interrupt(s)

Enable T2 Comparator 2 interrupt

Enable T2 Comparator 1 interrupt

Enable T2 Comparator 0 interrupt

Enable T2 Capture register 3 interrupt

Enable T2 Capture register 2 interrupt

Enable T2 Capture register 1 interrupt

Enable T2 Capture register 0 interrupt

ECM2

ECM1

ECM0

ECT3

ECT2

ECT1

ECT0

SU00755

In all cases, if the enable bit is 0, then the interrupt is disabled, and if the enable bit is 1, then the interrupt is enabled.

Figure 28. Interrupt Enable Register (IEN1)

7

–

6

5

4

3

2

1

0

IP0 (B8H)

PAD

PS1

PS0

PT1

PX1

PT0

PX0

(LSB)

(MSB)

BIT

SYMBOL FUNCTION

IP0.7

IP0.6

IP0.5

IP0.4

IP0.3

IP0.2

IP0.1

IP0.0

–

Unused

PAD

PS1

PS0

PT1

PX1

PT0

PX0

ADC interrupt priority level

2

SIO1 (I C) interrupt priority level

SIO0 (UART) interrupt priority level

Timer 1 interrupt priority level

External interrupt 1 priority level

Timer 0 interrupt priority level

External interrupt 0 priority level

SU00763

Figure 29. Interrupt Priority Register (IP0)

7

–

6

5

4

3

2

1

0

IP0H (B7H)

PADH

PS1H

PS0H

PT1H

PX1H

PT0H

PX0H

(LSB)

(MSB)

BIT

SYMBOL FUNCTION

IP0H.7

IP0H.6

IP0H.5

IP0H.4

IP0H.3

IP0H.2

IP0H.1

IP0H.0

–

Unused

PADH

PS1H

PS0H

PT1H

PX1H

PT0H

PX0H

ADC interrupt priority level high

2

SIO1 (I C) interrupt priority level high

SIO0 (UART) interrupt priority level high

Timer 1 interrupt priority level high

External interrupt 1 priority level high

Timer 0 interrupt priority level high

External interrupt 0 priority level high

SU00983

Figure 30. Interrupt Priority Register High (IP0H)

30

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

7

6

5

4

3

2

1

0

IP1 (F8H)

PT2

PCM2

PCM1

PCM0

PCT3

PCT2

PCT1

PCT0

(LSB)

(MSB)

BIT

SYMBOL FUNCTION

IP1.7

IP1.6

IP1.5

IP1.4

IP1.3

IP1.2

IP1.1

IP1.0

PT2

T2 overflow interrupt(s) priority level

PCM2

PCM1

PCM0

PCT3

PCT2

PCT1

PCT0

T2 comparator 2 interrupt priority level

T2 comparator 1 interrupt priority level

T2 comparator 0 interrupt priority level

T2 capture register 3 interrupt priority level

T2 capture register 2 interrupt priority level

T2 capture register 1 interrupt priority level

T2 capture register 0 interrupt priority level

SU00764

Figure 31. Interrupt Priority Register (IP1)

7

6

5

4

3

2

1

0

IP1H (F7H)

PT2H PCM2H PCM1H PCM0H PCT3H PCT2H PCT1H PCT0H

(MSB) (LSB)

BIT

SYMBOL FUNCTION

IP1H.7

IP1H.6

IP1H.5

IP1H.4

IP1H.3

IP1H.2

IP1H.1

IP1H.0

PT2H

T2 overflow interrupt(s) priority level high

PCM2H

PCM1H

PCM0H

PCT3H

PCT2H

PCT1H

PCT0H

T2 comparator 2 interrupt priority level high

T2 comparator 1 interrupt priority level high

T2 comparator 0 interrupt priority level high

T2 capture register 3 interrupt priority level high

T2 capture register 2 interrupt priority level high

T2 capture register 1 interrupt priority level high

T2 capture register 0 interrupt priority level high

SU00984

Figure 32. Interrupt Priority Register High (IP1H)

Table 3.

Interrupt Priority Structure

Table 4.

Interrupt Vector Addresses

SOURCE

NAME

PRIORITY WITHIN LEVEL

SOURCE

NAME

VECTOR ADDRESS

(highest)

External interrupt 0

Timer 0 overflow

External interrupt 1

Timer 1 overflow

SIO0 (UART)

X0

T0

0003H

000BH

0013H

001BH

0023H

002BH

0033H

003BH

0043H

004BH

0053H

005BH

0063H

006BH

0073H

External interrupt 0

SIO1 (I C)

X0

S1

ADC

T0

CT0

CM0

X1

CT1

CM1

T1

CT2

CM2

S0

CT3

T2

↑

2

X1

ADC completion

Timer 0 overflow

T2 capture 0

T2 compare 0

External interrupt 1

T2 capture 1

T2 compare 1

Timer 1 overflow

T2 capture 2

T2 compare 2

SIO0 (UART)

T1

S0

2

SIO1 (I C)

S1

T2 capture 0

T2 capture 1

T2 capture 2

T2 capture 3

ADC completion

T2 compare 0

T2 compare 1

T2 compare 2

T2 overflow

CT0

CT1

CT2

CT3

ADC

CM0

CM1

CM2

T2

T2 capture 3

Timer T2 overflow

↓

(lowest)

31

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

2

SIO1, I C Serial I/O: The I C bus uses two wires (SDA and SCL) to

transfer information between devices connected to the bus. The

main features of the bus are:

Modes of Operation: The on-chip SIO1 logic may operate in the

following four modes:

1. Master Transmitter Mode:

– Bidirectional data transfer between masters and slaves

Serial data output through P1.7/SDA while P1.6/SCL outputs the

serial clock. The first byte transmitted contains the slave address

of the receiving device (7 bits) and the data direction bit. In this

case the data direction bit (R/W) will be logic 0, and we say that

a “W” is transmitted. Thus the first byte transmitted is SLA+W.

Serial data is transmitted 8 bits at a time. After each byte is

transmitted, an acknowledge bit is received. START and STOP

conditions are output to indicate the beginning and the end of a

serial transfer.

– Multimaster bus (no central master)

– Arbitration between simultaneously transmitting masters without

corruption of serial data on the bus

– Serial clock synchronization allows devices with different bit rates

to communicate via one serial bus

– Serial clock synchronization can be used as a handshake

mechanism to suspend and resume serial transfer

2

– The I C bus may be used for test and diagnostic purposes

2. Master Receiver Mode:

The output latches of P1.6 and P1.7 must be set to logic 1 in order

to enable SIO1.

The first byte transmitted contains the slave address of the

transmitting device (7 bits) and the data direction bit. In this case

the data direction bit (R/W) will be logic 1, and we say that an “R”

is transmitted. Thus the first byte transmitted is SLA+R. Serial

data is received via P1.7/SDA while P1.6/SCL outputs the serial

clock. Serial data is received 8 bits at a time. After each byte is

received, an acknowledge bit is transmitted. START and STOP

conditions are output to indicate the beginning and end of a

serial transfer.

2

The 8xC554 on-chip I C logic provides a serial interface that meets

2

the I C bus specification and supports all transfer modes (other than

the low-speed mode) from and to the I C bus. The SIO1 logic

handles bytes transfer autonomously. It also keeps track of serial

transfers, and a status register (S1STA) reflects the status of SIO1

2

and the I C bus.

2

The CPU interfaces to the I C logic via the following four special

function registers: S1CON (SIO1 control register), S1STA (SIO1

status register), S1DAT (SIO1 data register), and S1ADR (SIO1

slave address register). The SIO1 logic interfaces to the external I C

bus via two port 1 pins: P1.6/SCL (serial clock line) and P1.7/SDA

(serial data line).

3. Slave Receiver Mode:

2

Serial data and the serial clock are received through P1.7/SDA

and P1.6/SCL. After each byte is received, an acknowledge bit is

transmitted. START and STOP conditions are recognized as the

beginning and end of a serial transfer. Address recognition is

performed by hardware after reception of the slave address and

direction bit.

2

A typical I C bus configuration is shown in Figure 33, and Figure 34

shows how a data transfer is accomplished on the bus. Depending

on the state of the direction bit (R/W), two types of data transfers are

2

possible on the I C bus:

4. Slave Transmitter Mode:

1. Data transfer from a master transmitter to a slave receiver. The

first byte transmitted by the master is the slave address. Next

follows a number of data bytes. The slave returns an

acknowledge bit after each received byte.

The first byte is received and handled as in the slave receiver

mode. However, in this mode, the direction bit will indicate that

the transfer direction is reversed. Serial data is transmitted via

P1.7/SDA while the serial clock is input through P1.6/SCL.

START and STOP conditions are recognized as the beginning

and end of a serial transfer.

2. Data transfer from a slave transmitter to a master receiver. The

first byte (the slave address) is transmitted by the master. The

slave then returns an acknowledge bit. Next follows the data

bytes transmitted by the slave to the master. The master returns

an acknowledge bit after all received bytes other than the last

byte. At the end of the last received byte, a “not acknowledge” is

returned.

In a given application, SIO1 may operate as a master and as a

slave. In the slave mode, the SIO1 hardware looks for its own slave

address and the general call address. If one of these addresses is

detected, an interrupt is requested. When the microcontroller wishes

to become the bus master, the hardware waits until the bus is free

before the master mode is entered so that a possible slave action is

not interrupted. If bus arbitration is lost in the master mode, SIO1

switches to the slave mode immediately and can detect its own

slave address in the same serial transfer.

The master device generates all of the serial clock pulses and the

START and STOP conditions. A transfer is ended with a STOP

condition or with a repeated START condition. Since a repeated

START condition is also the beginning of the next serial transfer, the

2

I C bus will not be released.

32

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

V

DD

R

P

SDA

SCL

2

I

C bus

P1.7/SDA

P1.6/SCL

OTHER DEVICE WITH

2

OTHER DEVICE WITH

8XC554

2

I

C INTERFACE

I

C INTERFACE

SU00964

2

Figure 33. Typical I C Bus Configuration

STOP

CONDITION

SDA

REPEATED

START

CONDITION

MSB

SLAVE ADDRESS

R/W

DIRECTION

BIT

ACKNOWLEDGMENT

SIGNAL FROM RECEIVER

ACKNOWLEDGMENT

SIGNAL FROM RECEIVER

CLOCK LINE HELD LOW WHILE

INTERRUPTS ARE SERVICED

SCL

1

2

7

8

9

1

2

3–8

9

ACK

S

P/S

REPEATED IF MORE BYTES

ARE TRANSFERRED

START

CONDITION

SU00965

2

Figure 34. Data Transfer on the I C Bus

SIO1 Implementation and Operation: Figure 35 shows how the

on-chip I C bus interface is implemented, and the following text

COMPARATOR

2

The comparator compares the received 7-bit slave address with its

own slave address (7 most significant bits in S1ADR). It also

compares the first received 8-bit byte with the general call address

(00H). If an equality is found, the appropriate status bits are set and

an interrupt is requested.

describes the individual blocks.

INPUT FILTERS AND OUTPUT STAGES

2

The input filters have I C compatible input levels. If the input voltage

is less than 1.5 V, the input logic level is interpreted as 0; if the input

voltage is greater than 3.0 V, the input logic level is interpreted as 1.

SHIFT REGISTER, S1DAT

Input signals are synchronized with the internal clock (f

/2), and

This 8-bit special function register contains a byte of serial data to

be transmitted or a byte which has just been received. Data in

S1DAT is always shifted from right to left; the first bit to be

transmitted is the MSB (bit 7) and, after a byte has been received,

the first bit of received data is located at the MSB of S1DAT. While

data is being shifted out, data on the bus is simultaneously being

shifted in; S1DAT always contains the last byte present on the bus.

Thus, in the event of lost arbitration, the transition from master

transmitter to slave receiver is made with the correct data in S1DAT.

OSC

spikes shorter than three oscillator periods are filtered out.

The output stages consist of open drain transistors that can sink

3 mA at V < 0.4 V. These open drain outputs do not have

OUT

2

clamping diodes to V . Thus, if the device is connected to the I C

DD

2

bus and V is switched off, the I C bus is not affected.

DD

ADDRESS REGISTER, S1ADR

This 8-bit special function register may be loaded with the 7-bit slave

address (7 most significant bits) to which SIO1 will respond when

programmed as a slave transmitter or receiver. The LSB (GC) is

used to enable general call address (00H) recognition.

33

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

8

S1ADR

ADDRESS REGISTER

P1.7

COMPARATOR

INPUT

FILTER

P1.7/SDA

S1DAT

OUTPUT

STAGE

SHIFT REGISTER

ACK

8

ARBITRATION &

SYNC LOGIC

INPUT

FILTER

TIMING

&

CONTROL

LOGIC

f

/4

OSC

P1.6/SCL

SERIAL CLOCK

GENERATOR

OUTPUT

STAGE

INTERRUPT

TIMER 1

OVERFLOW

S1CON

CONTROL REGISTER

P1.6

8

STATUS BITS

STATUS

DECODER

S1STA

STATUS REGISTER

8

su00966

2

Figure 35. I C Bus Serial Interface Block Diagram

34

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

ARBITRATION AND SYNCHRONIZATION LOGIC

In the master transmitter mode, the arbitration logic checks that

every transmitted logic 1 actually appears as a logic 1 on the I C

bus. If another device on the bus overrules a logic 1 and pulls the

SDA line low, arbitration is lost, and SIO1 immediately changes from

master transmitter to slave receiver. SIO1 will continue to output

clock pulses (on SCL) until transmission of the current serial byte is

complete.

The synchronization logic will synchronize the serial clock generator

with the clock pulses on the SCL line from another device. If two or

more master devices generate clock pulses, the “mark” duration is

determined by the device that generates the shortest “marks,” and

the “space” duration is determined by the device that generates the

longest “spaces.” Figure 37 shows the synchronization procedure.

2

A slave may stretch the space duration to slow down the bus

master. The space duration may also be stretched for handshaking

purposes. This can be done after each bit or after a complete byte

transfer. SIO1 will stretch the SCL space duration after a byte has

been transmitted or received and the acknowledge bit has been

transferred. The serial interrupt flag (SI) is set, and the stretching

continues until the serial interrupt flag is cleared.

Arbitration may also be lost in the master receiver mode. Loss of

arbitration in this mode can only occur while SIO1 is returning a “not

acknowledge: (logic 1) to the bus. Arbitration is lost when another

device on the bus pulls this signal LOW. Since this can occur only at

the end of a serial byte, SIO1 generates no further clock pulses.

Figure 36 shows the arbitration procedure.

(3)

(1)

(2)

SDA

SCL

2

3

4

8

9

1

ACK

1. Another device transmits identical serial data.

2. Another device overrules a logic 1 (dotted line) transmitted by SIO1 (master) by pulling the SDA line low. Arbitration is

lost, and SIO1 enters the slave receiver mode.

3. SIO1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted. SIO1 will

not generate clock pulses for the next byte. Data on SDA originates from the new master once it has won arbitration.

SU00967

Figure 36. Arbitration Procedure

SDA

(1)

(3)

(1)

SCL

(2)

MARK

DURATION

SPACE DURATION

1. Another service pulls the SCL line low before the SIO1 “mark” duration is complete. The serial clock generator is immediately

reset and commences with the “space” duration by pulling SCL low.

2. Another device still pulls the SCL line low after SIO1 releases SCL. The serial clock generator is forced into the wait state

until the SCL line is released.

3. The SCL line is released, and the serial clock generator commences with the mark duration.

SU00968

Figure 37. Serial Clock Synchronization

35

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

SERIAL CLOCK GENERATOR

read from and write to this 8-bit, directly addressable SFR while it is

not in the process of shifting a byte. This occurs when SIO1 is in a

defined state and the serial interrupt flag is set. Data in S1DAT

remains stable as long as SI is set. Data in S1DAT is always shifted

from right to left: the first bit to be transmitted is the MSB (bit 7), and,

after a byte has been received, the first bit of received data is

located at the MSB of S1DAT. While data is being shifted out, data

on the bus is simultaneously being shifted in; S1DAT always

contains the last data byte present on the bus. Thus, in the event of

lost arbitration, the transition from master transmitter to slave

receiver is made with the correct data in S1DAT.

This programmable clock pulse generator provides the SCL clock

pulses when SIO1 is in the master transmitter or master receiver

mode. It is switched off when SIO1 is in a slave mode. The

programmable output clock frequencies are: f

/60, f

/4800,

OSC

and the Timer 1 overflow rate divided by eight. The output clock

pulses have a 50% duty cycle unless the clock generator is

synchronized with other SCL clock sources as described above.

TIMING AND CONTROL

The timing and control logic generates the timing and control signals

for serial byte handling. This logic block provides the shift pulses for

S1DAT, enables the comparator, generates and detects start and

stop conditions, receives and transmits acknowledge bits, controls

the master and slave modes, contains interrupt request logic, and

7

6

5

4

3

2

1

0

S1DAT (DAH)

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

shift direction

2

monitors the I C bus status.

SD7 - SD0:

CONTROL REGISTER, S1CON

This 7-bit special function register is used by the microcontroller to

control the following SIO1 functions: start and restart of a serial

transfer, termination of a serial transfer, bit rate, address recognition,

and acknowledgment.

Eight bits to be transmitted or just received. A logic 1 in S1DAT

corresponds to a high level on the I C bus, and a logic 0

corresponds to a low level on the bus. Serial data shifts through

S1DAT from right to left. Figure 38 shows how data in S1DAT is

serially transferred to and from the SDA line.

2

STATUS DECODER AND STATUS REGISTER

The status decoder takes all of the internal status bits and

compresses them into a 5-bit code. This code is unique for each I C

S1DAT and the ACK flag form a 9-bit shift register which shifts in or

shifts out an 8-bit byte, followed by an acknowledge bit. The ACK

flag is controlled by the SIO1 hardware and cannot be accessed by

the CPU. Serial data is shifted through the ACK flag into S1DAT on

the rising edges of serial clock pulses on the SCL line. When a byte

has been shifted into S1DAT, the serial data is available in S1DAT,

and the acknowledge bit is returned by the control logic during the

ninth clock pulse. Serial data is shifted out from S1DAT via a buffer

(BSD7) on the falling edges of clock pulses on the SCL line.

2

bus status. The 5-bit code may be used to generate vector

addresses for fast processing of the various service routines. Each

service routine processes a particular bus status. There are 26

possible bus states if all four modes of SIO1 are used. The 5-bit

status code is latched into the five most significant bits of the status

register when the serial interrupt flag is set (by hardware) and

remains stable until the interrupt flag is cleared by software. The

three least significant bits of the status register are always zero. If

the status code is used as a vector to service routines, then the

routines are displaced by eight address locations. Eight bytes of

code is sufficient for most of the service routines (see the software

example in this section).

When the CPU writes to S1DAT, BSD7 is loaded with the content of

S1DAT.7, which is the first bit to be transmitted to the SDA line (see

Figure 39). After nine serial clock pulses, the eight bits in S1DAT will

have been transmitted to the SDA line, and the acknowledge bit will

be present in ACK. Note that the eight transmitted bits are shifted

back into S1DAT.

The Four SIO1 Special Function Registers: The microcontroller

interfaces to SIO1 via four special function registers. These four

SFRs (S1ADR, S1DAT, S1CON, and S1STA) are described

individually in the following sections.

The Control Register, S1CON: The CPU can read from and write

to this 8-bit, directly addressable SFR. Two bits are affected by the

SIO1 hardware: the SI bit is set when a serial interrupt is requested,

and the STO bit is cleared when a STOP condition is present on the

The Address Register, S1ADR: The CPU can read from and write

to this 8-bit, directly addressable SFR. S1ADR is not affected by the

SIO1 hardware. The contents of this register are irrelevant when

SIO1 is in a master mode. In the slave modes, the seven most

significant bits must be loaded with the microcontroller’s own slave

address, and, if the least significant bit is set, the general call

address (00H) is recognized; otherwise it is ignored.

2

I C bus. The STO bit is also cleared when ENS1 = “0”.

7

6

5

4

3

2

1

0

S1CON (D8H) CR2

ENS1

STA

STO

SI

AA

CR1

CR0

ENS1, THE SIO1 ENABLE BIT

ENS1 = “0”: When ENS1 is “0”, the SDA and SCL outputs are in a

high impedance state. SDA and SCL input signals are ignored, SIO1

is in the “not addressed” slave state, and the STO bit in S1CON is

forced to “0”. No other bits are affected. P1.6 and P1.7 may be used

as open drain I/O ports.

7

6

5

4

3

2

1

0

S1ADR (DBH)

X

GC

own slave address

The most significant bit corresponds to the first bit received from the

ENS1 = “1”: When ENS1 is “1”, SIO1 is enabled. The P1.6 and P1.7

port latches must be set to logic 1.

2

I C bus after a start condition. A logic 1 in S1ADR corresponds to a

2

high level on the I C bus, and a logic 0 corresponds to a low level

ENS1 should not be used to temporarily release SIO1 from the I2C

bus since, when ENS1 is reset, the I2C bus status is lost. The AA

flag should be used instead (see description of the AA flag in the

following text).

on the bus.

The Data Register, S1DAT: S1DAT contains a byte of serial data to

be transmitted or a byte which has just been received. The CPU can

36

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

INTERNAL BUS

SDA

8

BSD7

S1DAT

ACK

SCL

SHIFT PULSES

SU00969

Figure 38. Serial Input/Output Configuration

SDA

SCL

D7

D6

D5

D4

D3

D2

D1

D0

A

SHIFT ACK & S1DAT

SHIFT IN

ACK

(2)

A

S1DAT

(1)

(2)

(1)

SHIFT BSD7

SHIFT OUT

BSD7

D7

D6

D5

D4

D3

D2

D1

D0

(3)

LOADED BY THE CPU

(1) Valid data in S1DAT

(2) Shifting data in S1DAT and ACK

(3) High level on SDA

SU00970

Figure 39. Shift-in and Shift-out Timing

In the following text, it is assumed that ENS1 = “1”.

STA = “0”: When the STA bit is reset, no START condition or

repeated START condition will be generated.

STA, THE START FLAG

STA = “1”: When the STA bit is set to enter a master mode, the SIO1

hardware checks the status of the I2C bus and generates a START

condition if the bus is free. If the bus is not free, then SIO1 waits for

a STOP condition (which will free the bus) and generates a START

condition after a delay of a half clock period of the internal serial

clock generator.

STO, THE STOP FLAG

STO = “1”: When the STO bit is set while SIO1 is in a master mode,

a STOP condition is transmitted to the I C bus. When the STOP

2

condition is detected on the bus, the SIO1 hardware clears the STO

flag. In a slave mode, the STO flag may be set to recover from an

error condition. In this case, no STOP condition is transmitted to the

2

I C bus. However, the SIO1 hardware behaves as if a STOP

If STA is set while SIO1 is already in a master mode and one or

more bytes are transmitted or received, SIO1 transmits a repeated

START condition. STA may be set at any time. STA may also be set

when SIO1 is an addressed slave.

condition has been received and switches to the defined “not

addressed” slave receiver mode. The STO flag is automatically

cleared by hardware.

37

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

If the STA and STO bits are both set, the a STOP condition is

transmitted to the I C bus if SIO1 is in a master mode (in a slave

mode, SIO1 generates an internal STOP condition which is not

transmitted). SIO1 then transmits a START condition.

When SIO1 is in the addressed slave transmitter mode, state C8H

will be entered after the last serial is transmitted (see Figure 43).

When SI is cleared, SIO1 leaves state C8H, enters the not

addressed slave receiver mode, and the SDA line remains at a high

level. In state C8H, the AA flag can be set again for future address

recognition.

2

STO = “0”: When the STO bit is reset, no STOP condition will be

generated.

When SIO1 is in the not addressed slave mode, its own slave

address and the general call address are ignored. Consequently, no

acknowledge is returned, and a serial interrupt is not requested.

SI, THE SERIAL INTERRUPT FLAG

SI = “1”: When the SI flag is set, then, if the EA and ES1 (interrupt

enable register) bits are also set, a serial interrupt is requested. SI is

set by hardware when one of 25 of the 26 possible SIO1 states is

entered. The only state that does not cause SI to be set is state

F8H, which indicates that no relevant state information is available.

2

Thus, SIO1 can be temporarily released from the I C bus while the

bus status is monitored. While SIO1 is released from the bus,

START and STOP conditions are detected, and serial data is shifted

in. Address recognition can be resumed at any time by setting the

AA flag. If the AA flag is set when the part’s own slave address or

the general call address has been partly received, the address will

be recognized at the end of the byte transmission.

While SI is set, the low period of the serial clock on the SCL line is

stretched, and the serial transfer is suspended. A high level on the

SCL line is unaffected by the serial interrupt flag. SI must be reset

by software.

CR0, CR1, AND CR2, THE CLOCK RATE BITS

SI = “0”: When the SI flag is reset, no serial interrupt is requested,

and there is no stretching of the serial clock on the SCL line.

These three bits determine the serial clock frequency when SIO1 is

in a master mode. The various serial rates are shown in Table 5.

2

AA, THE ASSERT ACKNOWLEDGE FLAG

A 12.5 kHz bit rate may be used by devices that interface to the I C

AA = “1”: If the AA flag is set, an acknowledge (low level to SDA) will

be returned during the acknowledge clock pulse on the SCL line

when:

bus via standard I/O port lines which are software driven and slow.

100 kHz is usually the maximum bit rate and can be derived from a

8 MHz, 6 MHz, or a 3 MHz oscillator. A variable bit rate (0.24 kHz to

62.5 kHz) may also be used if Timer 1 is not required for any other

purpose while SIO1 is in a master mode.

– The “own slave address” has been received

– The general call address has been received while the general call

bit (GC) in S1ADR is set

The frequencies shown in Table 5 are unimportant when SIO1 is in a

slave mode. In the slave modes, SIO1 will automatically synchronize

with any clock frequency up to 100 kHz.

– A data byte has been received while SIO1 is in the master

receiver mode

– A data byte has been received while SIO1 is in the addressed

slave receiver mode

The Status Register, S1STA: S1STA is an 8-bit read-only special

function register. The three least significant bits are always zero.

The five most significant bits contain the status code. There are 26

possible status codes. When S1STA contains F8H, no relevant state

information is available and no serial interrupt is requested. All other

S1STA values correspond to defined SIO1 states. When each of

these states is entered, a serial interrupt is requested (SI = “1”). A

valid status code is present in S1STA one machine cycle after SI is

set by hardware and is still present one machine cycle after SI has

been reset by software.

AA = “0”: if the AA flag is reset, a not acknowledge (high level to

SDA) will be returned during the acknowledge clock pulse on SCL

when:

– A data has been received while SIO1 is in the master receiver

mode

– A data byte has been received while SIO1 is in the addressed

slave receiver mode

Table 5.

Serial Clock Rates

BIT FREQUENCY (kHz) AT f

OSC

2

CR2

CR1

CR0

3 MHz

6 MHz

8 MHz

12 MHz

15 MHz

f

DIVIDED BY

OSC

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

23

27

31

37

6.25

50

47

54

63

62.5

71

83.3

100

17

94

107

125

150

25

200

400

117

128

112

96

80

48

1

134

1

156

1

75

188

12.5

100

200

31

1

133

250

60

30

1

100

0.24 < 62.5

0 < 255

267

500

0.49 < 62.5

0 < 254

0.65 < 55.6

0 < 253

0.98 < 50.0

0 < 251

1.22 < 52.1

0 < 250

48 × (256 – (reload value Timer 1))

Reload value Timer 1 in Mode 2.

NOTES:

2

1. These frequencies exceed the upper limit of 100 kHz of the I C-bus specification and cannot be used in an I C-bus application.

2

2. At f

= 12 MHz/15 MHz the maximum I C bus rate of 100 kHz cannot be realized due to the fixed divider rates.

OSC

38

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

More Information on SIO1 Operating Modes: The four operating

modes are:

may switch to the master receiver mode by loading S1DAT with

SLA+R).

– Master Transmitter

Master Receiver Mode: In the master receiver mode, a number of

data bytes are received from a slave transmitter (see Figure 41).

The transfer is initialized as in the master transmitter mode. When

the start condition has been transmitted, the interrupt service routine

must load S1DAT with the 7-bit slave address and the data direction

bit (SLA+R). The SI bit in S1CON must then be cleared before the

serial transfer can continue.

– Master Receiver

– Slave Receiver

– Slave Transmitter

Data transfers in each mode of operation are shown in Figures

40–43. These figures contain the following abbreviations:

Abbreviation

S

SLA

R

W

A

Data

P

Explanation

Start condition

7-bit slave address

Read bit (high level at SDA)

Write bit (low level at SDA)

Acknowledge bit (low level at SDA)

Not acknowledge bit (high level at SDA)

8-bit data byte

When the slave address and the data direction bit have been

transmitted and an acknowledgment bit has been received, the

serial interrupt flag (SI) is set again, and a number of status codes in

S1STA are possible. These are 40H, 48H, or 38H for the master

mode and also 68H, 78H, or B0H if the slave mode was enabled

(AA = logic 1). The appropriate action to be taken for each of these

status codes is detailed in Table 7. ENS1, CR1, and CR0 are not

affected by the serial transfer and are not referred to in Table 7. After

a repeated start condition (state 10H), SIO1 may switch to the

master transmitter mode by loading S1DAT with SLA+W.

Stop condition

In Figures 40-43, circles are used to indicate when the serial

interrupt flag is set. The numbers in the circles show the status code

held in the S1STA register. At these points, a service routine must

be executed to continue or complete the serial transfer. These

service routines are not critical since the serial transfer is suspended

until the serial interrupt flag is cleared by software.

Slave Receiver Mode: In the slave receiver mode, a number of

data bytes are received from a master transmitter (see Figure 42).

To initiate the slave receiver mode, S1ADR and S1CON must be

loaded as follows:

When a serial interrupt routine is entered, the status code in S1STA

is used to branch to the appropriate service routine. For each status

code, the required software action and details of the following serial

transfer are given in Tables 6-10.

7

6

5

4

3

2

1

0

S1ADR (DBH)

X

GC

own slave address

Master Transmitter Mode: In the master transmitter mode, a

number of data bytes are transmitted to a slave receiver (see

Figure 40). Before the master transmitter mode can be entered,

S1CON must be initialized as follows:

The upper 7 bits are the address to which SIO1 will respond when

addressed by a master. If the LSB (GC) is set, SIO1 will respond to

the general call address (00H); otherwise it ignores the general call

address.

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

S1CON (D8H)

CR2

ENS1

STA

STO

SI

AA

CR1

CR0

S1CON (D8H) CR2

ENS1

STA

STO

SI

AA

CR1

CR0

bit

rate

bit rate

1

0

X

1

0

1

X

CR0, CR1, and CR2 define the serial bit rate. ENS1 must be set to

logic 1 to enable SIO1. If the AA bit is reset, SIO1 will not

acknowledge its own slave address or the general call address in

the event of another device becoming master of the bus. In other

words, if AA is reset, SIO0 cannot enter a slave mode. STA, STO,

and SI must be reset.

CR0, CR1, and CR2 do not affect SIO1 in the slave mode. ENS1

must be set to logic 1 to enable SIO1. The AA bit must be set to

enable SIO1 to acknowledge its own slave address or the general

call address. STA, STO, and SI must be reset.

When S1ADR and S1CON have been initialized, SIO1 waits until it

is addressed by its own slave address followed by the data direction

bit which must be “0” (W) for SIO1 to operate in the slave receiver

mode. After its own slave address and the W bit have been

received, the serial interrupt flag (I) is set and a valid status code

can be read from S1STA. This status code is used to vector to an

interrupt service routine, and the appropriate action to be taken for

each of these status codes is detailed in Table 8. The slave receiver

mode may also be entered if arbitration is lost while SIO1 is in the

master mode (see status 68H and 78H).

The master transmitter mode may now be entered by setting the

STA bit using the SETB instruction. The SIO1 logic will now test the

2

I C bus and generate a start condition as soon as the bus becomes

free. When a START condition is transmitted, the serial interrupt flag

(SI) is set, and the status code in the status register (S1STA) will be

08H. This status code must be used to vector to an interrupt service

routine that loads S1DAT with the slave address and the data

direction bit (SLA+W). The SI bit in S1CON must then be reset

before the serial transfer can continue.

When the slave address and the direction bit have been transmitted

and an acknowledgment bit has been received, the serial interrupt

flag (SI) is set again, and a number of status codes in S1STA are

possible. There are 18H, 20H, or 38H for the master mode and also

68H, 78H, or B0H if the slave mode was enabled (AA = logic 1). The

appropriate action to be taken for each of these status codes is

detailed in Table 6. After a repeated start condition (state 10H). SIO1

If the AA bit is reset during a transfer, SIO1 will return a not

acknowledge (logic 1) to SDA after the next received data byte.

While AA is reset, SIO1 does not respond to its own slave address

2

or a general call address. However, the I C bus is still monitored

and address recognition may be resumed at any time by setting AA.

This means that the AA bit may be used to temporarily isolate SIO1

2

from the I C bus.

39

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

MT

SUCCESSFUL TRANSMISSION

TO A SLAVE RECEIVER

S

SLA

W

A

DATA

A

P

28H

08H

18H

NEXT TRANSFER STARTED WITH A REPEATED START CONDITION

NOT ACKNOWLEDGE RECEIVED AFTER THE SLAVE ADDRESS

S

SLA

W

R

10H

A

P

20H

TO MST/REC MODE

ENTRY = MR

NOT ACKNOWLEDGE RECEIVED AFTER A DATA BYTE

A

P

30H

ARBITRATION LOST IN SLAVE ADDRESS OR DATA BYTE

OTHER MST

CONTINUES

OTHER MST

CONTINUES

A or A

38H

A or A

38H

ARBITRATION LOST AND ADDRESSED AS SLAVE

OTHER MST

CONTINUES

A

TO CORRESPONDING

STATES IN SLAVE MODE

68H

78H

80H

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

Data

n

A

ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS

2

THIS NUMBER (CONTAINED IN S1STA) CORRESPONDS TO A DEFINED STATE OF THE I C BUS. SEE TABLE 6.

SU00971

Figure 40. Format and States in the Master Transmitter Mode

40

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

MR

SUCCESSFUL RECEPTION

FROM A SLAVE TRANSMITTER

S

SLA

R

A

DATA

A

DATA

A

P

50H

58H

08H

40H

NEXT TRANSFER STARTED WITH A

REPEATED START CONDITION

S

SLA

R

10H

NOT ACKNOWLEDGE RECEIVED

AFTER THE SLAVE ADDRESS

A

P

W

48H

TO MST/TRX MODE

ENTRY = MT

ARBITRATION LOST IN SLAVE ADDRESS

OR ACKNOWLEDGE BIT

OTHER MST

CONTINUES

OTHER MST

CONTINUES

A

A or A

38H

ARBITRATION LOST AND ADDRESSED AS SLAVE

OTHER MST

CONTINUES

A

TO CORRESPONDING

STATES IN SLAVE MODE

68H

78H

80H

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS

DATA

n

A

2

THIS NUMBER (CONTAINED IN S1STA) CORRESPONDS TO A DEFINED STATE OF THE I C BUS. SEE TABLE 7.

SU00972

Figure 41. Format and States in the Master Receiver Mode

41

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

RECEPTION OF THE OWN SLAVE ADDRESS

AND ONE OR MORE DATA BYTES

ALL ARE ACKNOWLEDGED.

S

SLA

W

A

DATA

A

DSALTAA

A

P or S

A0H

80H

60H

LAST DATA BYTE RECEIVED IS

NOT ACKNOWLEDGED

P or S

A

88H

ARBITRATION LOST AS MST AND

ADDRESSED AS SLAVE

A

68H

RECEPTION OF THE GENERAL CALL ADDRESS

AND ONE OR MORE DATA BYTES

GENERAL

CALL

DATA

A

DATA

A

P or S

A0H

90H

70H

LAST DATA BYTE IS NOT ACKNOWLEDGED

P or S

A

98H

ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE BY GENERAL CALL

A

78H

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

Data

A

ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS

2

THIS NUMBER (CONTAINED IN S1STA) CORRESPONDS TO A DEFINED STATE OF THE I C BUS. SEE TABLE 8.

n

SU00973

Figure 42. Format and States in the Slave Receiver Mode

42

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

RECEPTION OF THE

OWN SLAVE ADDRESS

S

SLA

R

A

DATA

A

DATA

A

P or S

AND TRANSMISSION

OF ONE OR MORE

DATA BYTES

B8H

C0H

A8H

ARBITRATION LOAST AS MST

AND ADDRESSED AS SLAVE

A

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

B0H

LAST DATA BYTE TRANSMITTED.

SWITCHED TO NOT ADDRESSED

SLAVE (AA BIT IN S1CON = “0”

P or S

A

All “1”s

C8H

DATA

n

A

ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS

2

THIS NUMBER (CONTAINED IN S1STA) CORRESPONDS TO A DEFINED STATE OF THE I C BUS. SEE TABLE 9.

SU00974

Figure 43. Format and States of the Slave Transmitter Mode

43

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

Table 6.

Master Transmitter Mode

APPLICATION SOFTWARE RESPONSE

STATUS

CODE

(S1STA)

STATUS OF THE

I C BUS AND

SIO1 HARDWARE

2

TO S1CON

NEXT ACTION TAKEN BY SIO1 HARDWARE

TO/FROM S1DAT

STA STO

SI

AA

08H

10H

A START condition has

been transmitted

Load SLA+W

X

0

X

SLA+W will be transmitted;

ACK bit will be received

Load SLA+W or

Load SLA+R

X

0

X

As above

SLA+W will be transmitted;

SIO1 will be switched to MST/REC mode

A repeated START

condition has been

transmitted

Load data byte or

0

X

Data byte will be transmitted;

ACK bit will be received

Repeated START will be transmitted;

STOP condition will be transmitted;

STO flag will be reset

STOP condition followed by a

START condition will be transmitted;

STO flag will be reset

18H

20H

28H

30H

38H

SLA+W has been

transmitted; ACK has

been received

no S1DAT action or

1

0

1

0

X

no S1DAT action

1

0

X

Load data byte or

0

X

Data byte will be transmitted;

ACK bit will be received

Repeated START will be transmitted;

STOP condition will be transmitted;

STO flag will be reset

STOP condition followed by a

START condition will be transmitted;

STO flag will be reset

SLA+W has been

transmitted; NOT ACK

has been received

no S1DAT action or

1

0

1

0

X

no S1DAT action

1

0

X

Load data byte or

0

X

Data byte will be transmitted;

ACK bit will be received

Repeated START will be transmitted;

STOP condition will be transmitted;

STO flag will be reset

STOP condition followed by a

START condition will be transmitted;

STO flag will be reset

Data byte in S1DAT has

been transmitted; ACK

has been received

no S1DAT action or

1

0

1

0

X

no S1DAT action

1

0

X

Load data byte or

0

X

Data byte will be transmitted;

ACK bit will be received

Repeated START will be transmitted;

STOP condition will be transmitted;

STO flag will be reset

STOP condition followed by a

START condition will be transmitted;

STO flag will be reset

Data byte in S1DAT has

been transmitted; NOT

ACK has been received

no S1DAT action or

1

0

1

0

X

no S1DAT action

1

0

X

2

No S1DAT action or

No S1DAT action

0

1

0

X

I C bus will be released;

Arbitration lost in

SLA+R/W or

Data bytes

not addressed slave will be entered

A START condition will be transmitted when the

bus becomes free

44

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

Table 7.

Master Receiver Mode

APPLICATION SOFTWARE RESPONSE

TO S1CON

2

STATUS

CODE

(S1STA)

STATUS OF THE I C

NEXT ACTION TAKEN BY SIO1 HARDWARE

BUS AND

TO/FROM S1DAT

SIO1 HARDWARE

STA STO

SI

AA

08H

10H

A START condition has

been transmitted

Load SLA+R

X

0

X

SLA+R will be transmitted;

ACK bit will be received

Load SLA+R or

Load SLA+W

X

0

X

As above

SLA+W will be transmitted;

SIO1 will be switched to MST/TRX mode

A repeated START

condition has been

transmitted

2

No S1DAT action or

No S1DAT action

0

1

0

X

I C bus will be released;

38H

40H

48H

Arbitration lost in

NOT ACK bit

SIO1 will enter a slave mode

A START condition will be transmitted when the

bus becomes free

No S1DAT action or

no S1DAT action

0

1

Data byte will be received;

NOT ACK bit will be returned

Data byte will be received;

ACK bit will be returned

SLA+R has been

transmitted; ACK has

been received

No S1DAT action or

no S1DAT action or

1

0

1

0

X

Repeated START condition will be transmitted

STOP condition will be transmitted;

STO flag will be reset

SLA+R has been

transmitted; NOT ACK

has been received

no S1DAT action

1

0

X

STOP condition followed by a

START condition will be transmitted;

STO flag will be reset

Read data byte or

read data byte

0

1

Data byte will be received;

NOT ACK bit will be returned

Data byte will be received;

ACK bit will be returned

50H

58H

Data byte has been

received; ACK has been

returned

Read data byte or

read data byte or

1

0

1

0

X

Repeated START condition will be transmitted

STOP condition will be transmitted;

STO flag will be reset

Data byte has been

received; NOT ACK has

been returned

read data byte

1

0

X

STOP condition followed by a

START condition will be transmitted;

STO flag will be reset

45

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

Table 8.

Slave Receiver Mode

APPLICATION SOFTWARE RESPONSE

STATUS

CODE

(S1STA)

STATUS OF THE

I C BUS AND

SIO1 HARDWARE

2

TO S1CON

NEXT ACTION TAKEN BY SIO1 HARDWARE

TO/FROM S1DAT

STA STO

SI

AA

No S1DAT action or

X

0

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

60H

68H

Own SLA+W has

been received; ACK

has been returned

no S1DAT action

X

0

1

0

No S1DAT action or

Data byte will be received and NOT ACK will be

returned

Arbitration lost in

SLA+R/W as master;

Own SLA+W has

been received, ACK

returned

no S1DAT action

X

0

1

0

Data byte will be received and ACK will be returned

No S1DAT action or

Data byte will be received and NOT ACK will be

returned

70H

78H

General call address

(00H) has been

received; ACK has

been returned

no S1DAT action

X

0

1

0

Data byte will be received and ACK will be returned

No S1DAT action or

Data byte will be received and NOT ACK will be

returned

Arbitration lost in

SLA+R/W as master;

General call address

has been received,

ACK has been

no S1DAT action

Read data byte or

X

0

1

0

Data byte will be received and ACK will be returned

returned

Data byte will be received and NOT ACK will be

returned

80H

88H

Previously addressed

with own SLV

address; DATA has

been received; ACK

has been returned

read data byte

X

0

1

Data byte will be received and ACK will be returned

Read data byte or

read data byte or

0

1

Switched to not addressed SLV mode; no recognition

of own SLA or General call address

Switched to not addressed SLV mode; Own SLA will

be recognized; General call address will be

recognized if S1ADR.0 = logic 1

Previously addressed

with own SLA; DATA

byte has been

received; NOT ACK

has been returned

read data byte or

read data byte

1

0

1

Switched to not addressed SLV mode; no recognition

of own SLA or General call address. A START

condition will be transmitted when the bus becomes

free

Switched to not addressed SLV mode; Own SLA will

be recognized; General call address will be

recognized if S1ADR.0 = logic 1. A START condition

will be transmitted when the bus becomes free.

Read data byte or

read data byte

X

0

1

Data byte will be received and NOT ACK will be

returned

90H

98H

Previously addressed

with General Call;

DATA byte has been

received; ACK has

been returned

Data byte will be received and ACK will be returned

Read data byte or

read data byte or

0

1

Switched to not addressed SLV mode; no recognition

of own SLA or General call address

Switched to not addressed SLV mode; Own SLA will

be recognized; General call address will be

recognized if S1ADR.0 = logic 1

Previously addressed

with General Call;

DATA byte has been

received; NOT ACK

has been returned

read data byte or

read data byte

1

0

1

Switched to not addressed SLV mode; no recognition

of own SLA or General call address. A START

condition will be transmitted when the bus becomes

free

Switched to not addressed SLV mode; Own SLA will

be recognized; General call address will be

recognized if S1ADR.0 = logic 1. A START condition

will be transmitted when the bus becomes free.

46

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

Table 8.

Slave Receiver Mode (Continued)

APPLICATION SOFTWARE RESPONSE

STATUS

CODE

(S1STA)

STATUS OF THE

I C BUS AND

SIO1 HARDWARE

2

TO S1CON

NEXT ACTION TAKEN BY SIO1 HARDWARE

TO/FROM S1DAT

STA STO

SI

AA

No STDAT action or

0

Switched to not addressed SLV mode; no recognition

of own SLA or General call address

Switched to not addressed SLV mode; Own SLA will

be recognized; General call address will be

recognized if S1ADR.0 = logic 1

Switched to not addressed SLV mode; no recognition

of own SLA or General call address. A START

condition will be transmitted when the bus becomes

free

Switched to not addressed SLV mode; Own SLA will

be recognized; General call address will be

A0H

A STOP condition or

repeated START

condition has been

received while still

addressed as

0

1

0

SLV/REC or SLV/TRX

No STDAT action or

No STDAT action

1

0

1

recognized if S1ADR.0 = logic 1. A START condition

will be transmitted when the bus becomes free.

Table 9.

Slave Transmitter Mode

APPLICATION SOFTWARE RESPONSE

STATUS

CODE

(S1STA)

STATUS OF THE

I C BUS AND

SIO1 HARDWARE

2

TO S1CON

NEXT ACTION TAKEN BY SIO1 HARDWARE

TO/FROM S1DAT

STA STO

SI

AA

Load data byte or

X

0

Last data byte will be transmitted and ACK bit will be

received

Data byte will be transmitted; ACK will be received

A8H

B0H

Own SLA+R has

been received; ACK

has been returned

load data byte

X

0

1

0

Load data byte or

Last data byte will be transmitted and ACK bit will be

received

Arbitration lost in

SLA+R/W as master;

Own SLA+R has

been received, ACK

has been returned

load data byte

X

0

1

0

Data byte will be transmitted; ACK bit will be received

Load data byte or

Last data byte will be transmitted and ACK bit will be

received

B8H

C0H

Data byte in S1DAT

has been transmitted;

ACK has been

load data byte

X

0

1

Data byte will be transmitted; ACK bit will be received

received

No S1DAT action or

01 Switched to not addressed SLV mode; no recognition

of own SLA or General call address

1

Data byte in S1DAT

has been transmitted;

NOT ACK has been

received

no S1DAT action or

0

1

0

Switched to not addressed SLV mode; Own SLA will

be recognized; General call address will be

recognized if S1ADR.0 = logic 1

Switched to not addressed SLV mode; no recognition

of own SLA or General call address. A START

condition will be transmitted when the bus becomes

free

0

no S1DAT action

1

0

1

Switched to not addressed SLV mode; Own SLA will

be recognized; General call address will be

recognized if S1ADR.0 = logic 1. A START condition

will be transmitted when the bus becomes free.

No S1DAT action or

no S1DAT action or

0

1

Switched to not addressed SLV mode; no recognition

of own SLA or General call address

Switched to not addressed SLV mode; Own SLA will

be recognized; General call address will be

recognized if S1ADR.0 = logic 1

C8H

Last data byte in

S1DAT has been

transmitted (AA = 0);

ACK has been

received

no S1DAT action or

no S1DAT action

1

0

1

Switched to not addressed SLV mode; no recognition

of own SLA or General call address. A START

condition will be transmitted when the bus becomes

free

Switched to not addressed SLV mode; Own SLA will

be recognized; General call address will be

recognized if S1ADR.0 = logic 1. A START condition

will be transmitted when the bus becomes free.

47

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

Table 10. Miscellaneous States

APPLICATION SOFTWARE RESPONSE

STATUS

CODE

(S1STA)

STATUS OF THE

I C BUS AND

SIO1 HARDWARE

2

TO S1CON

NEXT ACTION TAKEN BY SIO1 HARDWARE

TO/FROM S1DAT

STA STO

SI

AA

F8H

00H

No relevant state

information available;

SI = 0

No S1DAT action

No S1CON action

Wait or proceed current transfer

Bus error during MST No S1DAT action

or selected slave

modes, due to an

0

1

0

X

Only the internal hardware is affected in the MST or

addressed SLV modes. In all cases, the bus is

released and SIO1 is switched to the not addressed

SLV mode. STO is reset.

illegal START or

STOP condition. State

00H can also occur

when interference

causes SIO1 to enter

an undefined state.

Slave Transmitter Mode: In the slave transmitter mode, a number

of data bytes are transmitted to a master receiver (see Figure 43).

Data transfer is initialized as in the slave receiver mode. When

S1ADR and S1CON have been initialized, SIO1 waits until it is

addressed by its own slave address followed by the data direction

bit which must be “1” (R) for SIO1 to operate in the slave transmitter

mode. After its own slave address and the R bit have been received,

the serial interrupt flag (SI) is set and a valid status code can be

read from S1STA. This status code is used to vector to an interrupt

service routine, and the appropriate action to be taken for each of

these status codes is detailed in Table 9. The slave transmitter mode

may also be entered if arbitration is lost while SIO1 is in the master

mode (see state B0H).

SDA and SCL lines are released (a STOP condition is not

transmitted).

Some Special Cases: The SIO1 hardware has facilities to handle

the following special cases that may occur during a serial transfer:

Simultaneous Repeated START Conditions from Two Masters

A repeated START condition may be generated in the master

transmitter or master receiver modes. A special case occurs if

another master simultaneously generates a repeated START

condition (see Figure 44). Until this occurs, arbitration is not lost by

either master since they were both transmitting the same data.

2

If the SIO1 hardware detects a repeated START condition on the I C

bus before generating a repeated START condition itself, it will

release the bus, and no interrupt request is generated. If another

master frees the bus by generating a STOP condition, SIO1 will

transmit a normal START condition (state 08H), and a retry of the

total serial data transfer can commence.

If the AA bit is reset during a transfer, SIO1 will transmit the last byte

of the transfer and enter state C0H or C8H. SIO1 is switched to the

not addressed slave mode and will ignore the master receiver if it

continues the transfer. Thus the master receiver receives all 1s as

serial data. While AA is reset, SIO1 does not respond to its own

2

slave address or a general call address. However, the I C bus is still

DATA TRANSFER AFTER LOSS OF ARBITRATION

monitored, and address recognition may be resumed at any time by

setting AA. This means that the AA bit may be used to temporarily

isolate SIO1 from the I C bus.

Arbitration may be lost in the master transmitter and master receiver

modes (see Figure 36). Loss of arbitration is indicated by the

following states in S1STA; 38H, 68H, 78H, and B0H (see Figures 40

and 41).

2

Miscellaneous States: There are two S1STA codes that do not

correspond to a defined SIO1 hardware state (see Table 10). These

are discussed below.

If the STA flag in S1CON is set by the routines which service these

states, then, if the bus is free again, a START condition (state 08H)

is transmitted without intervention by the CPU, and a retry of the

total serial transfer can commence.

S1STA = F8H:

This status code indicates that no relevant information is available

because the serial interrupt flag, SI, is not yet set. This occurs

between other states and when SIO1 is not involved in a serial

transfer.

FORCED ACCESS TO THE I²C BUS

In some applications, it may be possible for an uncontrolled source

to cause a bus hang-up. In such situations, the problem may be

caused by interference, temporary interruption of the bus or a

temporary short-circuit between SDA and SCL.

S1STA = 00H:

This status code indicates that a bus error has occurred during an

SIO1 serial transfer. A bus error is caused when a START or STOP

condition occurs at an illegal position in the format frame. Examples

of such illegal positions are during the serial transfer of an address

byte, a data byte, or an acknowledge bit. A bus error may also be

caused when external interference disturbs the internal SIO1

signals. When a bus error occurs, SI is set. To recover from a bus

error, the STO flag must be set and SI must be cleared. This causes

SIO1 to enter the “not addressed” slave mode (a defined state) and

to clear the STO flag (no other bits in S1CON are affected). The

If an uncontrolled source generates a superfluous START or masks

a STOP condition, then the I C bus stays busy indefinitely. If the

2

STA flag is set and bus access is not obtained within a reasonable

2

amount of time, then a forced access to the I C bus is possible. This

is achieved by setting the STO flag while the STA flag is still set. No

STOP condition is transmitted. The SIO1 hardware behaves as if a

STOP condition was received and is able to transmit a START

condition. The STO flag is cleared by hardware (see Figure 45).

48

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

OTHER MST

CONTINUES

S

SLA

W

A

DATA

A

S

P

S

SLA

08H

18H

28H

08H

OTHER MASTER SENDS REPEATED

START CONDITION EARLIER

RETRY

SU00975

Figure 44. Simultaneous Repeated START Conditions from 2 Masters

TIME LIMIT

STA FLAG

STO FLAG

SDA LINE

SCL LINE

START CONDITION

SU00976

2

Figure 45. Forced Access to a Busy I C Bus

I²C BUS OBSTRUCTED BY A LOW LEVEL ON SCL OR SDA

An I C bus hang-up occurs if SDA or SCL is pulled LOW by an

uncontrolled source. If the SCL line is obstructed (pulled LOW) by a

device on the bus, no further serial transfer is possible, and the

SIO1 hardware cannot resolve this type of problem. When this

occurs, the problem must be resolved by the device that is pulling

the SCL bus line LOW.

hardware performs the same action as described above. In each

case, state 08H is entered after a successful START condition is

transmitted and normal serial transfer continues. Note that the CPU

is not involved in solving these bus hang-up problems.

2

BUS ERROR

A bus error occurs when a START or STOP condition is present at

an illegal position in the format frame. Examples of illegal positions

are during the serial transfer of an address byte, a data or an

acknowledge bit.

If the SDA line is obstructed by another device on the bus (e.g., a

slave device out of bit synchronization), the problem can be solved

by transmitting additional clock pulses on the SCL line (see Figure

46). The SIO1 hardware transmits additional clock pulses when the

STA flag is set, but no START condition can be generated because

The SIO1 hardware only reacts to a bus error when it is involved in

a serial transfer either as a master or an addressed slave. When a

bus error is detected, SIO1 immediately switches to the not

addressed slave mode, releases the SDA and SCL lines, sets the

interrupt flag, and loads the status register with 00H. This status

code may be used to vector to a service routine which either

attempts the aborted serial transfer again or simply recovers from

the error condition as shown in Table 10.

2

the SDA line is pulled LOW while the I C bus is considered free.

The SIO1 hardware attempts to generate a START condition after

every two additional clock pulses on the SCL line. When the SDA

line is eventually released, a normal START condition is transmitted,

state 08H is entered, and the serial transfer continues.

If a forced bus access occurs or a repeated START condition is

transmitted while SDA is obstructed (pulled LOW), the SIO1

49

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

STA FLAG

(2)

(3)

(1)

SDA LINE

SCL LINE

START CONDITION

(1) Unsuccessful attempt to send a Start condition

(2) SDA line released

(3) Successful attempt to send a Start condition; state 08H is entered

SU00977

Figure 46. Recovering from a Bus Obstruction Caused by a Low Level on SDA

Software Examples of SIO1 Service Routines: This section

SIO1 INTERRUPT ROUTINE

consists of a software example for:

– Initialization of SIO1 after a RESET

When the SIO1 interrupt is entered, the PSW is first pushed on the

stack. Then S1STA and HADD (loaded with the high-order address

byte of the 26 service routines by the initialization routine) are

pushed on to the stack. S1STA contains a status code which is the

lower byte of one of the 26 service routines. The next instruction is

RET, which is the return from subroutine instruction. When this

instruction is executed, the high and low order address bytes are

popped from stack and loaded into the program counter.

– Entering the SIO1 interrupt routine

– The 26 state service routines for the

– Master transmitter mode

– Master receiver mode

– Slave receiver mode

– Slave transmitter mode

The next instruction to be executed is the first instruction of the state

service routine. Seven bytes of program code (which execute in

eight machine cycles) are required to branch to one of the 26 state

service routines.

INITIALIZATION

In the initialization routine, SIO1 is enabled for both master and

slave modes. For each mode, a number of bytes of internal data

RAM are allocated to the SIO to act as either a transmission or

reception buffer. In this example, 8 bytes of internal data RAM are

reserved for different purposes. The data memory map is shown in

Figure 47. The initialization routine performs the following functions:

– S1ADR is loaded with the part’s own slave address and the

general call bit (GC)

SI

PUSH PSW

Save PSW

PUSH S1STA

Push status code

(low order address byte)

Push high order address byte

Jump to state service routine

PUSH HADD

RET

The state service routines are located in a 256-byte page of program

memory. The location of this page is defined in the initialization

routine. The page can be located anywhere in program memory by

loading data RAM register HADD with the page number. Page 01 is

chosen in this example, and the service routines are located

between addresses 0100H and 01FFH.

– P1.6 and P1.7 bit latches are loaded with logic 1s

– RAM location HADD is loaded with the high-order address byte of

the service routines

– The SIO1 interrupt enable and interrupt priority bits are set

– The slave mode is enabled by simultaneously setting the ENS1

and AA bits in S1CON and the serial clock frequency (for master

modes) is defined by loading CR0 and CR1 in S1CON. The

master routines must be started in the main program.

THE STATE SERVICE ROUTINES

The state service routines are located 8 bytes from each other. Eight

bytes of code are sufficient for most of the service routines. A few of

the routines require more than 8 bytes and have to jump to other

locations to obtain more bytes of code. Each state routine is part of

the SIO1 interrupt routine and handles one of the 26 states. It ends

with a RETI instruction which causes a return to the main program.

2

The SIO1 hardware now begins checking the I C bus for its own

slave address and general call. If the general call or the own slave

address is detected, an interrupt is requested and S1STA is loaded

with the appropriate state information. The following text describes a

fast method of branching to the appropriate service routine.

50

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

SPECIAL FUNCTION REGISTERS

S1ADR

S1DAT

GC

DB

DA

0

S1STA

D9

D8

S1CON

CR2

ENS1 STA

ST0

SI

AA

CR!

CR0

PSW

IPO

D0

B8

PS1

ES1

IEN0

P1

AB

EA

90

80

P1.7

P1.6

INTERNAL DATA RAM

7F

BACKUP

ORIGINAL VALUE OF NUMBYTMST

53

52

51

NUMBYTMST

SLA

NUMBER OF BYTES AS MASTER

SLA+R/W TO BE TRANSMITTED TO SLA

50

4F

HADD

HIGHER ADDRESS BYTE INTERRUPT ROUTINE

SLAVE TRANSMITTER DATA RAM

48

STD

SLAVE RECEIVER DATA RAM

MASTER RECEIVER DATA RAM

MASTER TRANSMITTER DATA RAM

40

38

30

SRD

MRD

MTD

R1

R0

19

18

00

SU00978

Figure 47. SIO1 Data Memory Map

51

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

MASTER TRANSMITTER AND MASTER RECEIVER MODES

In the slave receiver mode, a maximum of 8 received data bytes can

be stored in the internal data RAM. A maximum of 8 bytes ensures

that other RAM locations are not overwritten if a master sends more

bytes. If more than 8 bytes are transmitted, a not acknowledge is

returned, and SIO1 enters the not addressed slave receiver mode. A

maximum of one received data byte can be stored in the internal

data RAM after a general call address is detected. If more than one

byte is transmitted, a not acknowledge is returned and SIO1 enters

the not addressed slave receiver mode.

The master mode is entered in the main program. To enter the

master transmitter mode, the main program must first load the

internal data RAM with the slave address, data bytes, and the

number of data bytes to be transmitted. To enter the master receiver

mode, the main program must first load the internal data RAM with

the slave address and the number of data bytes to be received. The

R/W bit determines whether SIO1 operates in the master transmitter

or master receiver mode.

Master mode operation commences when the STA bit in S1CION is

set by the SETB instruction and data transfer is controlled by the

master state service routines in accordance with Table 6, Table 7,

Figure 40, and Figure 41. In the example below, 4 bytes are

transferred. There is no repeated START condition. In the event of

lost arbitration, the transfer is restarted when the bus becomes free.

If a bus error occurs, the I C bus is released and SIO1 enters the

not selected slave receiver mode. If a slave device returns a not

acknowledge, a STOP condition is generated.

In the slave transmitter mode, data to be transmitted is obtained

from the same locations in the internal data RAM that were

previously loaded by the main program. After a not acknowledge

has been returned by a master receiver device, SIO1 enters the not

addressed slave mode.

2

ADAPTING THE SOFTWARE FOR DIFFERENT APPLICATIONS

The following software example shows the typical structure of the

interrupt routine including the 26 state service routines and may be

used as a base for user applications. If one or more of the four

modes are not used, the associated state service routines may be

removed but, care should be taken that a deleted routine can never

be invoked.

A repeated START condition can be included in the serial transfer if

the STA flag is set instead of the STO flag in the state service

routines vectored to by status codes 28H and 58H. Additional

software must be written to determine which data is transferred after

a repeated START condition.

This example does not include any time-out routines. In the slave

modes, time-out routines are not very useful since, in these modes,

SIO1 behaves essentially as a passive device. In the master modes,

an internal timer may be used to cause a time-out if a serial transfer

is not complete after a defined period of time. This time period is

SLAVE TRANSMITTER AND SLAVE RECEIVER MODES

2

After initialization, SIO1 continually tests the I C bus and branches

to one of the slave state service routines if it detects its own slave

address or the general call address (see Table 8, Table 9, Figure 42,

and Figure 43). If arbitration was lost while in the master mode, the

master mode is restarted after the current transfer. If a bus error

2

defined by the system connected to the I C bus.

2

occurs, the I C bus is released and SIO1 enters the not selected

slave receiver mode.

52

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

!********************************************************************************************************

! SI01 EQUATE LIST

!********************************************************************************************************

! LOCATIONS OF THE SI01 SPECIAL FUNCTION REGISTERS

!********************************************************************************************************

00D8

00D9

00DA

00DB

S1CON

S1STA

S1DAT

S1ADR

–0xd8

–0xd9

–0xda

–0xdb

00A8

00B8

IEN0

IP0

–0xa8

–02b8

!********************************************************************************************************

! BIT LOCATIONS

!********************************************************************************************************

00DD

00BD

STA

SI01HP

–0xdd

–0xbd

! STA bit in S1CON

! IP0, SI01 Priority bit

!********************************************************************************************************

! IMMEDIATE DATA TO WRITE INTO REGISTER S1CON

!********************************************************************************************************

00D5

00C5

00C1

00E5

ENS1_NOTSTA_STO_NOTSI_AA_CR0

ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

ENS1_NOTSTA_NOTSTO_NOTSI_NOTAA_CR0

ENS1_STA_NOTSTO_NOTSI_AA_CR0

–0xd5

–0xc5

–0xc1

–0xe5

! Generates STOP

! (CR0 = 100 kHz)

! Releases BUS and

! ACK

! Releases BUS and

! NOT ACK

! Releases BUS and

! set STA

!********************************************************************************************************

! GENERAL IMMEDIATE DATA

!********************************************************************************************************

0031

00A0

OWNSLA –0x31

! Own SLA+General Call

! must be written into S1ADR

! EA+ES1, enable SIO1 interrupt

! must be written into IEN0

! select PAG1 as HADD

! SLA+W to be transmitted

! SLA+R to be transmitted

! Select Register Bank 3

ENSI01

–0xa0

0001

00C0

00C1

0018

PAG1

SLAW

SLAR

–0x01

–0xc0

–0xc1

SELRB3 –0x18

!********************************************************************************************************

! LOCATIONS IN DATA RAM

!********************************************************************************************************

0030

0038

0040

0048

MTD

MRD

SRD

STD

–0x30

–0x38

–0x40

–0x48

! MST/TRX/DATA base address

! MST/REC/DATA base address

! SLV/REC/DATA base address

! SLV/TRX/DATA base address

0053

BACKUP

–0x53

! Backup from NUMBYTMST

! To restore NUMBYTMST in case

! of an Arbitration Loss.

! Number of bytes to transmit

! or receive as MST.

! Contains SLA+R/W to be

! transmitted.

! High Address byte for STATE 0

! till STATE 25.

0052

0051

0050

NUMBYTMST –0x52

SLA

–0x51

–0x50

HADD

53

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

!********************************************************************************************************

! INITIALIZATION ROUTINE

! Example to initialize IIC Interface as slave receiver or slave transmitter and

! start a MASTER TRANSMIT or a MASTER RECEIVE function. 4 bytes will be transmitted or received.

!********************************************************************************************************

.sect

strt

.base

0x00

0000

0200

4100

ajmp INIT

! RESET

.sect

.base

INIT:

initial

0x200

75DB31

mov S1ADR,#OWNSLA

! Load own SLA + enable

! general call recognition

! P1.6 High level.

0203

0205

0207

020A

020D

020F

D296

D297

755001

43A8A0

C2BD

setb P1(6)

setb P1(7)

mov HADD,#PAG1

! P1.7 High level.

orl

clr

IEN0,#ENSI01

SI01HP

! Enable SI01 interrupt

! SI01 interrupt low priority

75D8C5

mov S1CON, #ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

! Initialize SLV funct.

!********************************************************************************************************

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! START MASTER TRANSMIT FUNCTION

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

0212

0215

0218

755204

7551C0

D2DD

mov NUMBYTMST,#0x4

mov SLA,#SLAW

setb STA

! Transmit 4 bytes.

! SLA+W, Transmit funct.

! set STA in S1CON

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! START MASTER RECEIVE FUNCTION

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

021A

021D

0220

755204

7551C1

D2DD

mov NUMBYTMST,#0x4

mov SLA,#SLAR

setb STA

! Receive 4 bytes.

! SLA+R, Receive funct.

! set STA in S1CON

!********************************************************************************************************

! SI01 INTERRUPT ROUTINE

!********************************************************************************************************

.sect

.base

intvec

0x00

! SI01 interrupt vector

! S1STA and HADD are pushed onto the stack.

! They serve as return address for the RET instruction.

! The RET instruction sets the Program Counter to address HADD,

! S1STA and jumps to the right subroutine.

002B

002D

002F

0031

C0D0

C0D9

C050

22

push psw

push S1STA

push HADD

ret

! save psw

! JMP to address HADD,S1STA.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE : 00, Bus error.

! ACTION : Enter not addressed SLV mode and release bus. STO reset.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

st0

.base

0x100

0100

75D8D5

mov S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0 ! clr SI

! set STO,AA

0103

0105

D0D0

32

pop psw

reti

54

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

!********************************************************************************************************

! MASTER STATE SERVICE ROUTINES

!********************************************************************************************************

! State 08 and State 10 are both for MST/TRX and MST/REC.

! The R/W bit decides whether the next state is within

! MST/TRX mode or within MST/REC mode.

!********************************************************************************************************

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE

: 08, A, START condition has been transmitted.

! ACTION : SLA+R/W are transmitted, ACK bit is received.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

mts8

.base

0x108

0108

010B

8551DA

75D8C5

mov S1DAT,SLA

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

! Load SLA+R/W

! clr SI

010E

01A0

ajmp INITBASE1

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE

!

: 10, A repeated START condition has been

transmitted.

! ACTION : SLA+R/W are transmitted, ACK bit is received.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

.base

mts10

0x110

0110

0113

8551DA

75D8C5

mov S1DAT,SLA

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

! Load SLA+R/W

! clr SI

010E

01A0

ajmp INITBASE1

.sect

.base

ibase1

0xa0

00A0

00A3

00A5

00A7

00AA

00AC

75D018

7930

7838

855253

D0D0

32

INITBASE1:

mov psw,#SELRB3

mov r1,#MTD

mov r0,#MRD

mov BACKUP,NUMBYTMST

pop psw

reti

! Save initial value

!********************************************************************************************************

! MASTER TRANSMITTER STATE SERVICE ROUTINES

!********************************************************************************************************

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE

!

: 18, Previous state was STATE 8 or STATE 10, SLA+W have been transmitted,

ACK has been received.

! ACTION : First DATA is transmitted, ACK bit is received.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

.base

mts18

0x118

0118

011B

011D

75D018

87DA

01B5

mov psw,#SELRB3

mov S1DAT,@r1

ajmp CON

55

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE : 20, SLA+W have been transmitted, NOT ACK has been received

! ACTION : Transmit STOP condition.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

.base

mts20

0x120

0120

75D8D5

mov S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0

! set STO, clr SI

0123

0125

D0D0

32

pop psw

reti

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE : 28, DATA of S1DAT have been transmitted, ACK received.

! ACTION : If Transmitted DATA is last DATA then transmit a STOP condition,

else transmit next DATA.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

!

.sect

.base

mts28

0x128

0128

012B

D55285

75D8D5

djnz NUMBYTMST,NOTLDAT1

mov S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0

! JMP if NOT last DATA

! clr SI, set AA

012E

01B9

ajmp RETmt

.sect

.base

mts28sb

0x0b0

00B0

00B3

00B5

75D018

87DA

75D8C5

NOTLDAT1:

mov psw,#SELRB3

mov S1DAT,@r1

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

! clr SI, set AA

CON:

00B8

00B9

00BB

09

D0D0

32

inc

pop psw

reti

r1

RETmt

:

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE : 30, DATA of S1DAT have been transmitted, NOT ACK received.

! ACTION : Transmit a STOP condition.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

.base

mts30

0x130

0130

75D8D5

mov S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0

! set STO, clr SI

0133

0135

D0D0

32

pop psw

reti

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE : 38, Arbitration lost in SLA+W or DATA.

! ACTION : Bus is released, not addressed SLV mode is entered.

A new START condition is transmitted when the IIC bus is free again.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

!

.sect

.base

mts38

0x138

0138

013B

013E

75D8E5

855352

01B9

mov S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0

mov NUMBYTMST,BACKUP

ajmp RETmt

56

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

!********************************************************************************************************

! MASTER RECEIVER STATE SERVICE ROUTINES

!********************************************************************************************************

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE

!

: 40, Previous state was STATE 08 or STATE 10,

SLA+R have been transmitted, ACK received.

! ACTION : DATA will be received, ACK returned.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

.base

mts40

0x140

0140

0143

75D8C5

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

! clr STA, STO, SI set AA

pop psw

reti

D0D0

32

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE : 48, SLA+R have been transmitted, NOT ACK received.

! ACTION : STOP condition will be generated.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

.base

mts48

0x148

0148

75D8D5

STOP:

mov S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0

! set STO, clr SI

014B

014D

D0D0

32

pop psw

reti

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE : 50, DATA have been received, ACK returned.

! ACTION : Read DATA of S1DAT.

DATA will be received, if it is last DATA

then NOT ACK will be returned else ACK will be returned.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

!

.sect

.base

mrs50

0x150

0150

0153

0155

75D018

A6DA

01C0

mov psw,#SELRB3

mov @r0,S1DAT

ajmp REC1

! Read received DATA

.sect

.base

mrs50s

0xc0

00C0

00C3

D55205

75D8C1

REC1:

djnz NUMBYTMST,NOTLDAT2

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_NOTAA_CR0

! clr SI,AA

00C6

00C8

8003

75D8C5

sjmp RETmr

NOTLDAT2:

RETmr:

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

! clr SI, set AA

00CB

08

inc

r0

00CC D0D0

pop psw

reti

00CE

32

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE : 58, DATA have been received, NOT ACK returned.

! ACTION : Read DATA of S1DAT and generate a STOP condition.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

.base

mrs58

0x158

0158

015B

015D

75D018

A6DA

80E9

mov psw,#SELRB3

mov @R0,S1DAT

sjmp STOP

57

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

!********************************************************************************************************

! SLAVE RECEIVER STATE SERVICE ROUTINES

!********************************************************************************************************

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE

: 60, Own SLA+W have been received, ACK returned.

! ACTION : DATA will be received and ACK returned.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

srs60

.base

0x160

0160

75D8C5

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

! clr SI, set AA

0163

0166

75D018

01D0

mov psw,#SELRB3

ajmp INITSRD

.sect

.base

insrd

0xd0

00D0

00D2

00D4

00D6

7840

7908

D0D0

32

INITSRD:

mov r0,#SRD

mov r1,#8

pop psw

reti

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE

!

: 68, Arbitration lost in SLA and R/W as MST

Own SLA+W have been received, ACK returned

! ACTION : DATA will be received and ACK returned.

STA is set to restart MST mode after the bus is free again.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

!

.sect

srs68

.base

0x168

0168

016B

016E

75D8E5

75D018

01D0

mov S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0

mov psw,#SELRB3

ajmp INITSRD

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE : 70, General call has been received, ACK returned.

! ACTION : DATA will be received and ACK returned.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

srs70

.base

0x170

0170

75D8C5

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

! clr SI, set AA

0173

0176

75D018

01D0

mov psw,#SELRB3

ajmp initsrd

! Initialize SRD counter

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE

!

: 78, Arbitration lost in SLA+R/W as MST.

General call has been received, ACK returned.

! ACTION : DATA will be received and ACK returned.

STA is set to restart MST mode after the bus is free again.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

!

.sect

srs78

.base

0x178

0178

017B

017E

75D8E5

75D018

01D0

mov S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0

mov psw,#SELRB3

ajmp INITSRD

! Initialize SRD counter

58

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE : 80, Previously addressed with own SLA. DATA received, ACK returned.

! ACTION : Read DATA.

!

IF received DATA was the last

THEN superfluous DATA will be received and NOT ACK returned

ELSE next DATA will be received and ACK returned.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

srs80

.base

0x180

0180

0183

0185

75D018

A6DA

01D8

mov psw,#SELRB3

mov @r0,S1DAT

ajmp REC2

! Read received DATA

.sect

.base

srs80s

0xd8

00D8

00DA

D906

75D8C1

REC2:

LDAT:

djnz r1,NOTLDAT3

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_NOTAA_CR0

! clr SI,AA

00DD D0D0

pop psw

00DF

00E0

32

75D8C5

reti

NOTLDAT3:

RETsr:

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

! clr SI, set AA

inc

pop psw

reti

00E3

00E4

00E6

08

D0D0

32

r0

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE : 88, Previously addressed with own SLA. DATA received NOT ACK returned.

! ACTION : No save of DATA, Enter NOT addressed SLV mode.

Recognition of own SLA. General call recognized, if S1ADR. 0–1.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

!

.sect

srs88

.base

0x188

0188

018B

75D8C5

01E4

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

! clr SI, set AA

ajmp RETsr

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE

!

: 90, Previously addressed with general call.

DATA has been received, ACK has been returned.

! ACTION : Read DATA.

After General call only one byte will be received with ACK

!

the second DATA will be received with NOT ACK.

DATA will be received and NOT ACK returned.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

srs90

.base

0x190

0190

0193

0195

75D018

A6DA

01DA

mov psw,#SELRB3

mov @r0,S1DAT

ajmp LDAT

! Read received DATA

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE

!

: 98, Previously addressed with general call.

DATA has been received, NOT ACK has been returned.

! ACTION : No save of DATA, Enter NOT addressed SLV mode.

Recognition of own SLA. General call recognized, if S1ADR. 0–1.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

srs98

.base

0x198

0198

75D8C5

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

! clr SI, set AA

019B

019D

D0D0

32

pop psw

reti

59

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE

!

: A0, A STOP condition or repeated START has been received,

while still addressed as SLV/REC or SLV/TRX.

! ACTION : No save of DATA, Enter NOT addressed SLV mode.

Recognition of own SLA. General call recognized, if S1ADR. 0–1.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

!

.sect

.base

srsA0

0x1a0

01A0

75D8C5

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

! clr SI, set AA

01A3

01A5

D0D0

32

pop psw

reti

!********************************************************************************************************

! SLAVE TRANSMITTER STATE SERVICE ROUTINES

!********************************************************************************************************

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE

: A8, Own SLA+R received, ACK returned.

! ACTION : DATA will be transmitted, A bit received.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

stsa8

.base

0x1a8

01A8

01AB

8548DA

75D8C5

mov S1DAT,STD

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

! load DATA in S1DAT

! clr SI, set AA

01AE

01E8

ajmp INITBASE2

.sect

.base

ibase2

0xe8

00E8

00EB

00ED

00EE

00F0

75D018

7948

09

D0D0

32

INITBASE2:

mov psw,#SELRB3

mov r1, #STD

inc

r1

pop psw

reti

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE : B0, Arbitration lost in SLA and R/W as MST. Own SLA+R received, ACK returned.

! ACTION : DATA will be transmitted, A bit received.

!

STA is set to restart MST mode after the bus is free again.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

stsb0

.base

0x1b0

01B0

01B3

01B6

8548DA

75D8E5

01E8

mov S1DAT,STD

mov S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0

ajmp INITBASE2

! load DATA in S1DAT

60

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE : B8, DATA has been transmitted, ACK received.

! ACTION : DATA will be transmitted, ACK bit is received.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

stsb8

.base

0x1b8

01B8

01BB

01BD

75D018

87DA

01F8

mov psw,#SELRB3

mov S1DAT,@r1

ajmp SCON

.sect

scn

.base

0xf8

00F8

75D8C5

SCON:

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

! clr SI, set AA

00FB

00FC

00FE

09

D0D0

32

inc

pop psw

reti

r1

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE : C0, DATA has been transmitted, NOT ACK received.

! ACTION : Enter not addressed SLV mode.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

stsc0

.base

0x1c0

01C0

75D8C5

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

! clr SI, set AA

01C3

01C5

D0D0

32

pop psw

reti

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

! STATE : C8, Last DATA has been transmitted (AA=0), ACK received.

! ACTION : Enter not addressed SLV mode.

!– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

.sect

stsc8

.base

0x1c8

01C8

01CB

75D8C5

D0D0

mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0

! clr SI, set AA

pop psw

reti

01CD 32

!********************************************************************************************************

! END OF SI01 INTERRUPT ROUTINE

!********************************************************************************************************

61

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

1, 2, 3

ABSOLUTE MAXIMUM RATINGS

PARAMETER

RATING

UNIT

°C

V

Storage temperature range

–65 to +150

–0.5 to +13

–0.5 to +6.5

5.0

Voltage on EA/V to V

PP

SS

Voltage on any other pin to V

V

SS

Input, output DC current on any single I/O pin

mA

W

Power dissipation (based on package heat transfer limitations, not device power

consumption)

1.0

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section

of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise

SS

noted.

62

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

DEVICE SPECIFICATIONS

SUPPLY VOLTAGE (V)

FREQUENCY (MHz)

SUPPLY VOLTAGE (V)

FREQUENCY (MHz)

TEMPERATURE

RANGE (°C), T

TYPE

amb

MIN

2.7

MAX

5.5

MIN

0

MAX

MIN

4.5 V

MAX

5.5 V

MIN

0

MAX

16

P87C554 SBBD

P87C554 SFBD

8

0 to +70

3.0

5.5

0

16

–40 to +85

DC ELECTRICAL CHARACTERISTICS

V

SS

, AV = 0 V; V and T

minimum and maximum, per device specifications table.

SS

DD

amb

LIMITS

SYMBOL PARAMETER

TEST CONDITIONS

UNIT

MIN

MAX

See notes 1 and 2

I

Supply current operating

mA

f

= 8 MHz

= 16 MHz

16

32

DD

OSC

f

OSC

See notes 1 and 3

I

Idle mode

mA

f

= 8 MHz

= 16 MHz

4

8

ID

OSC

f

OSC

See notes 1 and 4;

2 V < V < V max

Power-down current

50

µA

PD

DD

Inputs

V

Input low voltage, except EA, P1.6, P1.7

Input low voltage to EA

–0.5

0.2V –0.1

V

IL

DD

0.2V –0.3

IL1

IL2

IH

DD

5

Input low voltage to P1.6/SCL, P1.7/SDA

Input high voltage, except XTAL1, RST

Input high voltage, XTAL1, RST

0.3V

V

DD

0.2V +0.9

V

DD

V

DD

+0.5

V

DD

0.7 V

V

IH1

IH2

DD

5

Input high voltage, P1.6/SCL, P1.7/SDA

6.0

V

I

Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7

Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7

Input leakage current, port 0, EA, STADC, EW

V

= 0.45 V

–50

–650

10

µA

IL

TL

IN

See note 6

0.45 V < V < V

DD

±I

IL1

IL2

I

0 V < V < 6 V

0 V < V < 5.5 V

I

±I

Input leakage current, P1.6/SCL, P1.7/SDA

10

µA

DD

±I

Input leakage current, port 5

0.45 V < V < V

DD

1

µA

IL3

I

Input leakage current, ports 1, 2, 3, 4 in high impedance mode

0.45 V < V < V

10

IL4

in

DD

Outputs

7

V

Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7

Output low voltage, port 0, ALE, PSEN, PWM0, PWM1

Output low voltage, P1.6/SCL, P1.7/SDA

I

= 1.6 mA

= 3.2 mA

= 3.0 mA

0.4

V

OL

OL1

OL2

OH

Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA

V

= 2.7 V

= –20 µA

CC

V

CC

– 0.7

V

I

OH

V

= 4.5

= –30 µA

CC

V

– 0.7

V

CC

I

OH

V

Output high voltage (port 0 in external bus mode, ALE, PSEN,

PWM0, PWM1)

V

CC

= 2.7 V

= –3.2 mA

OH1

CC

8

I

OH

2.4

Output high voltage (RST)

–I = 400 µA

–I = 120 µA

OH

V

OH2

OH

0.8 V

40

DD

R

C

Internal reset pull-down resistor

Pin capacitance

225

10

kΩ

RST

IO

Test freq = 1 MHz,

pF

T

amb

= 25°C

Analog Inputs

AV Analog supply voltage: 87C554

9

AV = V ±0.2 V

2.7

5.5

1.2

50

V

DD

AI

Analog supply current: operating:

Idle mode: 87C554

Port 5 = 0 to AV

mA

µA

DD

ID

Power-down mode: 87C554

2 V < AV < AV max

50

PD

DD

63

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

DC ELECTRICAL CHARACTERISTICS (Continued)

V

DD

and T

minimum and maximum, per device specifications table.

amb

TEST

LIMITS

SYMBOL

Analog Inputs (Continued)

PARAMETER

CONDITIONS

MIN

MAX

UNIT

AV

Analog input voltage

Reference voltage:

AV –0.2

AV +0.2

V

IN

SS

DD

AV

REF

AV

AV –0.2

V

REF–

REF+

SS

AV +0.2

DD

R

C

Resistance between AV

and AV

REF–

10

50

15

kΩ

pF

REF

REF+

Analog input capacitance

Sampling time (10 bit mode)

Sampling time (8 bit mode)

IA

t

8t

CY

5t

CY

µs

ADS

ADS8

ADC

ADC8

µs

Conversion time (including sampling time, 10 bit mode)

Conversion time (including sampling time, 8 bit mode)

50t

24t

µs

CY

µs

10, 11, 12

DL

Differential non-linearity

±1

LSB

%

e

10, 13

IL

Integral non-linearity

(10 bit mode)

±2

±1

e

Integral non-linearity (8 bit mode)

e8

10, 14

OS

Offset error

(10 bit mode)

±2

e

Offset error (8 bit mode)

±1

e8

10, 15

G

Gain error

±0.4

±3

e

10, 16

A

e

Absolute voltage error

LSB

dB

M

CTC

Channel to channel matching

Crosstalk between inputs of port 5

±1

17, 18

C

0–100 kHz

–60

t

NOTES FOR DC ELECTRICAL CHARACTERISTICS:

1. See Figures 57 through 61 for I test conditions.

DD

2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10 ns; V = V + 0.5 V;

r

f

IL

SS

V

IH

= V – 0.5 V; XTAL2 not connected; EA = RST = Port 0 = EW = V ; STADC = V

.

DD

SS

3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10 ns; V = V + 0.5 V;

r

f

IL

SS

V

IH

= V – 0.5 V; XTAL2 not connected; Port 0 = EW = V ; EA = RST = STADC = V

.

DD

SS

4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = V

;

DD

EA = RST = STADC = XTAL1 = V

.

SS

2

5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I C specification, so an input voltage below 1.5 V will be recognized as a

logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.

6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition

current reaches its maximum value when V is approximately 2 V.

IN

7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due

OL

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the

worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify

ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no

OL

single output sinks more than 5 mA and no more than two outputs exceed the test conditions.

8. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9 V specification when the

OH

DD

address bits are stabilizing.

9. The following condition must not be exceeded: V – 0.2 V < AV < V + 0.2 V.

DD

10.Conditions: AV

= 0 V; AV = 5.0 V. Measurement by continuous conversion of AV = –20 mV to 5.12 V in steps of 0.5 mV, deriving

REF–

DD

IN

parameters from collected conversion results of ADC. AV

(87C554) = 5.12 V. ADC is monotonic with no missing codes.

REF+

11. The differential non-linearity (DL ) is the difference between the actual step width and the ideal step width. (See Figure 48.)

e

12.The ADC is monotonic; there are no missing codes.

13.The integral non-linearity (IL ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

e

appropriate adjustment of gain and offset error. (See Figure 48.)

14.The offset error (OS ) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and

e

a straight line which fits the ideal transfer curve. (See Figure 48.)

15.The gain error (G ) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),

e

and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 48.)

16.The absolute voltage error (A ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

e

ADC and the ideal transfer curve.

17.This should be considered when both analog and digital signals are simultaneously input to port 5.

18.This parameter is guaranteed by design and characterized, but is not production tested.

64

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

Offset

error

Gain

error

OS

e

G

e

1023

1022

1021

1020

1019

1018

(2)

7

(1)

Code

Out

6

5

(5)

4

(4)

3

(3)

2

1

1 LSB

(ideal)

0

1

2

3

4

5

6

7

1018

1019

1020

1021

1022

)

1023

1024

AV (LSB

IN

ideal

Offset

error

OS

e

AV

– AV

REF–

REF+

1024

1 LSB =

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential non-linearity (DL ).

e

(4) Integral non-linearity (IL ).

e

(5) Center of a step of the actual transfer curve.

SU00212

Figure 48. ADC Conversion Characteristic

65

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

AC ELECTRICAL CHARACTERISTICS

V

DD

and T

minimum and maximum, per device specifications table; V = 0 V; C = 100 pF for Port 0, ALE and PSEN; C = 80 pF for all

amb

SS

L

other outputs unless otherwise specified.

16 MHz CLOCK

VARIABLE CLOCK

SYMBOL

FIGURE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

External Program Memory

1/f

49

System clock frequency, see Note 1

ALE pulse width

3.5

16

–

MHz

ns

CLK

t

37.5

6.25

–

t

–25

LHLL

CLK

Address valid to ALE LOW

Address hold after ALE LOW

ALE LOW to valid instruction in

ALE LOW to PSEN LOW

0.5 t

–25

–

AVLL

LLAX

LLIV

CLK

–

–25

–

CLK

60

–

2 t

–65

CLK

6.25

48.75

–

0.5 t

1.5 t

–25

–45

–

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLK

PSEN pulse width

–

CLK

PSEN LOW to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address to valid instruction in

PSEN LOW to address float

33.75

–

1.5 t

–60

CLK

0

–

6.25

76.25

10

0.5 t

2.5 t

–25

–80

CLK

–

CLK

–

10

External Data Memory

t

50, 51

51

RD pulse width

87.5

–

3 t

–100

–

ns

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

CLK

WR pulse width

–

66.25

–

CLK

RD LOW to valid data in

Data hold after RD

–

2.5 t

–90

CLK

0

–

Data float after RD

–

42.5

100

116.25

143.75

–

t

–20

CLK

ALE LOW to valid data in

Address to valid data in

ALE LOW to RD or WR LOW

Address valid to RD low or WR LOW

Data valid to WR transition

Data hold after WR

–

4 t

–150

CLK

–

4.5 t

–165

AVDV

LLWL

CLK

43.75

50

1.5 t

–50

1.5 t

+50

CLK

2 t

–75

–

AVWL

QVWX

WHQX

QVWH

RLAZ

WHLH

CLK

1.25

6.25

88.75

–

0.5 t

–30

–25

–

0

CLK

–

CLK

50, 51

Data valid time WR HIGH

RD LOW to address float

RD or WR HIGH to ALE HIGH

–

3.5 t

–130

CLK

0

–

6.25

56.25

0.5 t

–25

0.5 t

+25

CLK

External Clock

t

52

High time

Low time

Rise time

Fall time

33.3

–

50

20

t

0.4

–

t

0.6

ns

CHCX

CLCX

CLCH

CHCL

CLK

20

–

20

UART Timing – Shift Register Mode

t

53

Serial port clock cycle time

500

179.5

32.5

0

–

6 t

–

ns

XLXL

CLK

Output data setup to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

–

5 t

t

–133

–30

QVXH

XHQX

XHDX

XHDV

CLK

–

0

–

179.5

–

5 t

–133

CLK

66

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

2

Table 11. I C-bus interface timing

5

All values referred to V

and V

levels; see Figure 56 .

IH(min)

IL(max)

2

I C-BUS

SYMBOL

PARAMETER

INPUT

OUTPUT

1

t

START condition hold time

LOW period of the SCL clock

HIGH period of the SCL clock

Rise time of SCL signals

≥ 7 t

≥ 8 t

≥ 7 t

> 4.0 µs

HD;STA

LOW

CLK

1

> 4.7 µs

1

> 4.0 µs

HIGH

2

≤ 1 µs

≤ 0.3 µs

≥ 250 ns

≥ 0 ns

–

RC

3

Fall time of SCL signals

< 0.3 µs

FC

Data set-up time

> 10 t

–t

SU;DAT1

SU;DAT2

SU;DAT3

HD;DAT

SU;STA

SU;STO

BUF

CLK RD

1

SDA set-up time (before repeated START condition)

SDA set-up time (before STOP condition)

Data hold time

> 1 µs

> 4 t

CLK

> 4 t

–t

CLK FC

1

Set-up time for a repeated START condition

Set-up time for STOP condition

Bus free time between

≥ 7 t

> 4.7 µs

CLK

1

> 4.0 µs

> 4.7 µs

2

Rise time of SDA signals

≤ 1 µs

–

RD

3

Fall time of SDA signals

≤ 0.3 µs

< 0.3 µs

FD

NOTES

1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.

2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 µs.

3. Spikes of the SDA and SCL lines with a duration of less than 3 t

will be filtered out. Maximum capacitance on bus-lines SDA and

CLK

SCL = 400 pF.

4. t

= 1/f

= one oscillator clock period at pin XTAL1. For 83 ns < t

< 285 ns (12 MHz > f

> 3.5 MHz) the SI01 interface meets the

CLK

2

I C-bus specification for bit-rates up to 100 kbit/s.

5. These values are guaranteed but not 100% production tested.

6. See application note AN457 for external memory interface.

7. Parts are guaranteed to operate down to 0Hz.

67

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always

Q – Output data

R – RD signal

‘t’ (= time). The other characters, depending on their positions,

indicate the name of a signal or the logical status of that signal. The

t – Time

designations are:

A – Address

V – Valid

W – WR signal

C – Clock

D – Input data

H – Logic level high

X – No longer a valid logic level

Z – Float

Examples: t

= Time for address valid to ALE low.

AVLL

LLPL

I

– Instruction (program memory contents)

t

= Time for ALE low to PSEN low.

L – Logic level low, or ALE

P – PSEN

t

LHLL

ALE

t

LLPL

AVLL

t

PLPH

t

LLIV

t

PLIV

PSEN

t

LLAX

t

PXIZ

t

PLAZ

t

PXIX

A0–A7

INSTR IN

A0–A7

PORT 0

PORT 2

t

AVIV

A0–A15

A8–A15

SU00006

Figure 49. External Program Memory Read Cycle

ALE

PSEN

RD

t

WHLH

t

LLDV

t

LLWL

RLRH

t

RHDZ

t

LLAX

t

RLDV

AVLL

t

RLAZ

t

RHDX

A0–A7

FROM RI OR DPL

PORT 0

PORT 2

DATA IN

A0–A7 FROM PCL

INSTR IN

t

AVWL

t

AVDV

P2.0–P2.7 OR A8–A15 FROM DPH

A0–A15 FROM PCH

SU00007

Figure 50. External Data Memory Read Cycle

68

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

ALE

t

WHLH

PSEN

t

WLWH

LLWL

WR

t

LLAX

WHQX

t

AVLL

QVWX

t

DW

A0–A7

FROM RI OR DPL

PORT 0

PORT 2

DATA OUT

A0–A7 FROM PCL

INSTR IN

t

AVWL

P2.0–P2.7 OR A8–A15 FROM DPH

A8–A15 FROM PCH

SU00213

Figure 51. External Data Memory Write Cycle

V

–0.5

CC

0.7V

CC

–0.1

0.45V

0.2V

CC

t

CHCX

t

CHCL

CLCX

CLCH

t

CLCL

SU00009

Figure 52. External Clock Drive XTAL1

INSTRUCTION

ALE

0

1

2

3

4

5

6

7

8

t

XLXL

CLOCK

t

XHQX

t

QVXH

OUTPUT DATA

0

1

2

3

4

5

6

7

WRITE TO SBUF

t

XHDX

t

SET TI

VALID

XHDV

INPUT DATA

CLEAR RI

VALID

SET RI

SU00027

Figure 53. Shift Register Mode Timing

69

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

2.4V

2.0V

0.8V

2.0V

0.8V

Test Points

0.45V

NOTE:

AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.45V for a logic ‘0’.

Timing measurements are made at 2.0V for a logic ‘1’ and 0.8V for a logic ‘0’.

SU00215

Figure 54. AC Testing Input/Output

Float

2.4V

2.0V

0.8V

2.0V

0.8V

0.45V

NOTE:

The float state is defined as the point at which a port 0 pin sinks 3.2mA or sources 400µA at the voltage test levels.

SU00216

Figure 55. AC Testing Input, Float Waveform

repeated START condition

START or repeated START condition

START condition

t

SU;STA

STOP condition

t

RD

0.7 V

CC

SDA

(INPUT/OUTPUT)

0.3 V

CC

t

BUF

t

FC

FD

RC

t

SU;STO

0.7 V

CC

SCL

(INPUT/OUTPUT)

0.3 V

CC

t

SU;DAT3

t

HIGH

t

SU;DAT1

t

SU;DAT2

HD;STA

LOW

HD;DAT

SU00107A

2

Figure 56. Timing SIO1 (I C) Interface

70

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

32

28

24

20

16

12

8

MAXIMUM ACTIVE MODE

TYPICAL ACTIVE MODE

MAXIMUM IDLE MODE

TYPICAL IDLE MODE

4

0

2

4

6

8

10

12

14

16

SU01471

FREQ AT XTAL1 (MHz)

Figure 57. 16 MHz Version Supply Current (I ) as a Function of Frequency at XTAL1 (f

)

DD

OSC

V

DD

I

DD

P1.6

P1.7

V

DD

P0

V

DD

RST

EA

STADC

EW

(NC)

XTAL2

XTAL1

CLOCK SIGNAL

AV

SS

V

SS

AV

ref–

SU00218

Figure 58. I Test Condition, Active Mode

DD

1

All other pins are disconnected

1. Active Mode:

a. The following pins must be forced to V : EA, RST, Port 0, and EW.

DD

b. The following pins must be forced to V : STADC, AV , and AV .

ref–

SS

ss

c. Ports 1.6 and 1.7 should be connected to V through resistors of sufficiently high value such that the sink current into these pins

DD

cannot exceed the I

spec of these pins.

OL1

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

71

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

V

DD

I

DD

P1.6

P1.7

V

DD

P0

RST

V

DD

STADC

EW

EA

(NC)

XTAL2

XTAL1

CLOCK SIGNAL

AV

SS

V

SS

AV

ref–

SU00219

Figure 59. I Test Condition, Idle Mode

DD

2

All other pins are disconnected

2. Idle Mode:

a. The following pins must be forced to V : Port 0 and EW.

DD

b. The following pins must be forced to V : RST, STADC, AV , AV , and EA.

SS

ss

ref–

c. Ports 1.6 and 1.7 should be connected to V through resistors of sufficiently high value such that the sink current into these pins

DD

cannot exceed the I

spec of these pins. These pins must not have logic 0 written to them prior to this measurement.

OL1

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

V

–0.5

DD

0.7V

DD

0.5V

0.2V

–0.1

DD

t

CHCX

t

CHCL

t

CLCX

CLCH

t

CLCL

SU00220

Figure 60. Clock Signal Waveform for I Tests in Active and Idle Modes

DD

t

= t

= 5 ns

CHCL

CLCH

V

DD

I

DD

P1.6

P1.7

V

DD

V

RST

DD

STADC

P0

EW

EA

(NC)

XTAL2

XTAL1

AV

SS

V

SS

AV

ref–

SU00221

Figure 61. I Test Condition, Power Down Mode

DD

3

All other pins are disconnected. V = 2 V to 5.5 V

DD

3. Power Down Mode:

a. The following pins must be forced to V : Port 0 and EW.

DD

b. The following pins must be forced to V : RST, STADC, XTAL1, AV , AV , and EA.

SS

ss

ref–

c. Ports 1.6 and 1.7 should be connected to V through resistors of sufficiently high value such that the sink current into these pins

DD

cannot exceed the I

spec of these pins. These pins must not have logic 0 written to them prior to this measurement.

OL1

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

72

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

EPROM CHARACTERISTICS

Security Bits

The 87C554 contains three signature bytes that can be read and

used by an EPROM programming system to identify the device. The

signature bytes identify the device as an 87C554 manufactured by

Philips:

With none of the security bits programmed the code in the program

memory can be verified. When only security bit 1 (see Table 12) is

programmed, MOVC instructions executed from external program

memory are disabled from fetching code bytes from the internal

memory, EA is latched on Reset and all further programming of the

EPROM is disabled. When security bits 1 and 2 are programmed, in

addition to the above, verify mode is disabled.

(030H) = 15H indicates manufactured by Philips Components

(031H) = 93H indicates 87C554

(60H) = 01H

When all three security bits are programmed, all of the conditions

above apply and all external program memory execution is disabled.

Program Verification

If security bits 2 or 3 have not been programmed, the on-chip

program memory can be read out for program verification.

Table 12. Program Security Bits for EPROM Devices

1, 2

PROGRAM LOCK BITS

SB1

SB2

SB3 PROTECTION DESCRIPTION

1

2

3

U

No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if

programmed.)

P

U

MOVC instructions executed from external program memory are disabled from fetching code bytes from

internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled.

P

U

P

Same as 2, also verify is disabled.

4

Same as 3, external execution is disabled.

NOTES:

1. P – programmed. U – unprogrammed.

2. Any other combination of the security bits is not defined.

73

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

ROM CODE SUBMISSION FOR 16K ROM DEVICES

When submitting ROM code for the 16k ROM devices, the following must be specified:

1. 16k byte user ROM data

2. ROM security bits.

ADDRESS

CONTENT

DATA

BIT(S)

7:0

COMMENT

0000H to 3FFFH

4000H to 403FH

User ROM Data

KEY

7:0

ROM Encryption Key

FFH = no encryption

4040H

SEC

0

1

2

ROM Security Bit 1

0 = enable security

1 = disable security

ROM Security Bit 2

0 = enable security

1 = disable security

ROM Security Bit 3

0 = enable security

1 = disable security

Security Bit 1: When programmed, this bit has two effects on masked ROM parts:

1. External MOVC is disabled, and

2. EA is latched on Reset.

Security Bit 2: When programmed, this bit inhibits Verify User ROM.

NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled.

Security Bit 3: When programmed, inhibits external execution.

If the ROM Code file does not include the options, the following information must be included with the ROM code.

For each of the following, check the appropriate box, and send to Philips along with the code:

Security Bit #1:

Security Bit #2:

Security Bit #3:

V Enabled

V Disabled

2

Purchase of Philips I C components conveys a license under the Philips’ I C patent

2

to use the components in the I C system provided the system conforms to the

I C specifications defined by Philips. This specification can be ordered using the

2

code 9398 393 40011.

74

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

75

2000 Nov 10

Philips Semiconductors

Preliminary specification

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,

capture/compare, high I/O, 64L LQFP

80C554/83C554/87C554

Data sheet status

[1]

Data sheet

status

Product

status

Definition

Objective

specification

Development

This data sheet contains the design target or goal specifications for product development.

Specification may change in any manner without notice.

Preliminary

specification

Qualification

This data sheet contains preliminary data, and supplementary data will be published at a later date.

Philips Semiconductors reserves the right to make changes at any time without notice in order to

improve design and supply the best possible product.

Product

specification

Production

This data sheet contains final specifications. Philips Semiconductors reserves the right to make

changes at any time without notice in order to improve design and supply the best possible product.

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Copyright Philips Electronics North America Corporation 2000

Sunnyvale, California 94088–3409

Telephone 800-234-7381

Date of release: 11-00

Document order number:

9397 750 07505

Philips

Semiconductors

76

2000 Nov 10


型号：	P87C554SFBD
厂家：	NXP
描述：	80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP 80C51的8位微控制器。 6时钟操作16K / 512 OTP / ROM /无ROM ， 7通道10位A / D ， I2C ， PWM ，捕获/比较，高I / O， 64L LQFP 微控制器时钟
文件：	总76页 (文件大小：396K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

P87C554SFBD [NXP]

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