P89C535NBAA-T [NXP]
IC 8-BIT, FLASH, MICROCONTROLLER, PQCC44, Microcontroller;
| 型号： | P89C535NBAA-T |
| 厂家： | 
NXP |
| 描述： | IC 8-BIT, FLASH, MICROCONTROLLER, PQCC44, Microcontroller 闪存 存储 微控制器 |
| 文件： | 总35页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
89C535/89C536/89C538
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
Preliminary specification
IC20 Data Handbook
1997 June 05
Philips
Semiconductors
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
DESCRIPTION
LOGIC SYMBOL
The 89C535/89C536/89C538 are Single-Chip 8-Bit Microcontrollers
manufactured in advanced CMOS process and are derivatives of
the 80C51 microcontroller family. All the devices have the same
instruction set as the 80C51.
V
V
SS
CC
XTAL1
ADDRESS AND
DATA BUS
The devices also have four 8-bit I/O ports, three 16-bit timer/event
counters, a multi-source, two-priority-level, nested interrupt
structure, UART and on-chip oscillator and timing circuits. For
systems that require extra data memory capability up to 64k bytes,
each can be expanded using standard TTL-compatible memories
and logic.
XTAL2
RST
T2
T2EX
EA/V
PP
The 89C535/89C536/89C538 contain a non-volatile FLASH EPROM
program memory (8K bytes in 89C535, 16k bytes in the 89C536,
and 64k bytes in the 89C538). The devices have 512 bytes of RAM
data memory.
PSEN
ALE/PROG
RxD
TxD
INT0
INT1
T0
T1
ADDRESS BUS
FEATURES
WR
RD
• 80C51 Central Processing Unit
• 8k x 8 (89C535) 16k × 8 (89C536) or 64k × 8 (89C538), FLASH
SU00830
EPROM Program Memory
• 512 × 8 RAM, externally expandable to 64k × 8 Data Memory
• Three 16-bit counter/timers
• Up to 3 external interrupt request inputs
• 6 interrupt sources with 2 priority levels
• Four 8-bit I/O ports
• Full-duplex UART
• Power control modes
– Idle mode
– Power down mode, with wakeup from power down using
external interrupt
• 44-pin PLCC and QFP packages
ORDERING INFORMATION
FREQ.
(MHz)
DRAWING
NUMBER
PART NUMBER
MEMORY SIZE
TEMPERATURE RANGE (°C) AND PACKAGE
P89C535NBA A
P89C536NBA A
P89C536NBB B
P89C538NBA A
P89C538NBB B
8k bytes
16k bytes
16k bytes
64k bytes
64k bytes
0 to +70, 44-pin Plastic Leaded Chip Carrier
0 to +70, 44-pin Plastic Leaded Chip Carrier
0 to +70, 44-pin Plastic Quad Flat Package
0 to +70, 44-pin Plastic Leaded Chip Carrier
0 to +70, 44-pin Plastic Quad Flat Package
33
33
33
33
33
SOT187-2
SOT187-2
SOT307-2
SOT187-2
SOT307-2
2
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
BLOCK DIAGRAM
P0.0–P0.7
P2.0–P2.7
PORT 0
DRIVERS
PORT 2
DRIVERS
V
CC
V
SS
RAM ADDR
REGISTER
PORT 0
LATCH
PORT 2
LATCH
ROF/EPROM
RAM
8
B
STACK
POINTER
ACC
REGISTER
PROGRAM
ADDRESS
REGISTER
TMP1
TMP2
BUFFER
ALU
SFRs
PC
INCRE-
MENTER
TIMERS
PSW
8
16
PROGRAM
COUNTER
PSEN
ALE/PROG
DPTR’S
MULTIPLE
TIMING
AND
CONTROL
EAV
PP
RST
PORT 1
LATCH
PORT 3
LATCH
PD
OSCILLATOR
PORT 1
DRIVERS
PORT 3
DRIVERS
XTAL1
XTAL2
P1.0–P1.7
P3.0–P3.7
SU00854
3
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
CERAMIC AND PLASTIC LEADED CHIP CARRIER
PIN FUNCTIONS
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
6
1
40
44
34
7
39
1
33
LCC
PQFP
17
29
11
23
18
28
12
Pin Function
22
Pin Function
Pin Function
Pin Function
Pin Function
Pin Function
1
2
3
4
5
V
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P2.7/A15
PSEN
ALE/PROG
NIC*
SS
1
2
P1.5
P1.6
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
V
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
SS
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3
CC
3
P1.7
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
4
RST
EA/V
PP
5
6
P3.0/RxD
NIC*
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
6
P1.4
XTAL1
7
P1.5
V
V
SS
7
8
9
10
11
12
13
14
15
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
8
P1.6
CC
V
CC
9
P1.7
P2.0/A8
P2.1/A9
V
SS
10
11
12
13
14
15
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
ALE/PROG
NIC*
EA/V
V
CC
PP
P0.7/AD7
* NO INTERNAL CONNECTION
SU00852A
SU00853A
* NO INTERNAL CONNECTION
4
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC LCC
QFP
TYPE NAME AND FUNCTION
V
V
1, 22
16, 39
I
I
Ground: 0V reference.
SS
CC
23, 44 17, 38
43–36 37–30
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
P0.0–0.7
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float
and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and data memory. In this application, it uses strong
internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and
received code bytes during EEPROM programming. External pull-ups are required during program
verification.
P1.0–P1.7
2–9
40–44,
1–3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that
are externally pulled low will source current because of the internal pull-ups. (See DC Electrical
Characteristics: I ). Port 1 also receives the low-order address byte during program memory
IL
verification.
Alternate functions for Port 1 include:
2
3
40
41
I/O
I
T2 (P1.0): Timer/Counter 2 external count input
T2EX (P1.1): Timer/Counter 2 Reload/Capture
P2.0–P2.7
P3.0–P3.7
24–31 18–25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that
are externally being pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: I ). Port 2 emits the high-order address byte during fetches from external
IL
program memory and during accesses to external data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. Some Port 2 pins
receive the high order address bits during EEPROM programming and verification.
11,
5,
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that
are externally being pulled low will source current because of the pull-ups. (See DC Electrical
13–19
7–13
Characteristics: I ). Port 3 also serves the special features of the 80C51 family, as listed below:
IL
11
13
14
15
16
17
18
19
5
7
8
I
O
I
I
I
I
O
O
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
9
10
11
12
13
RST
10
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An
internal diffused resistor to V permits a power-on reset using only an external capacitor to V
.
SS
CC
ALE/PROG
33
27
O
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory. This pin is also the program pulse input
(PROG) during EEPROM programming.
PSEN
32
35
26
29
O
I
Program Store Enable: The read strobe to external program memory. When the processor is
executing code from the external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data memory. PSEN is
not activated during fetches from internal program memory.
EA/V
External Access Enable/Programming Supply Voltage: EA must be externally held low to enable
PP
the device to fetch code from external program memory. If EA is held high, the device executes from
internal program memory. This pin also receives the 12V programming supply voltage (V ) during
PP
EPROM programming. EA is internally latched on Reset.
XTAL1
XTAL2
NOTE:
21
20
15
14
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
Crystal 2: Output from the inverting oscillator amplifier.
O
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V + 0.5V or V – 0.5V, respectively.
CC
SS
5
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
Table 1. Special Function Registers
DIRECT
ADDRESS MSB
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
RESET
VALUE
SYMBOL
DESCRIPTION
Accumulator
LSB
ACC*
B*
E0H
F0H
E7
F7
E6
F6
E5
F5
E4
F4
E3
F3
E2
F2
E1
F1
E0
00H
B register
F0
00H
DPTR:
DPH
DPL
Data Pointer (2 bytes)
Data Pointer High
Data Pointer Low
83H
82H
00H
00H
AF
EA
BF
–
AE
–
AD
ET2
BD
PT2
85
AC
ES
BC
PS
84
AB
ET1
BB
AA
EX1
BA
A9
ET0
B9
A8
EX0
B8
IE*
Interrupt Enable
Interrupt Priority
Port 0
A8H
B8H
80H
90H
A0H
00H
BE
–
IP*
PT1
83
PX1
82
PT0
81
PX0
80
x0000000B
FFH
87
86
P0*
P1*
P2*
AD7
97
AD6
96
AD5
95
AD4
94
AD3
93
AD2
92
AD1
91
AD0
90
Port 1
–
–
–
–
–
–
T2EX
A1
T2
FFH
A7
A6
AD14
B6
WR
A5
A4
A3
A2
A0
Port 2
AD15
B7
AD13
B5
AD12
B4
AD11
B3
AD10
B2
AD9
B1
AD8
B0
FFH
P3*
Port 3
B0H
87H
RD
T1
T0
INT1
INT0
TxD
RxD
FFH
PCON#
Power Control
SMOD
D7
–
–
–
GF1
D3
GF0
D2
PD
D1
–
IDL
D0
P
0xxxx000B
D6
AC
D5
F0
D4
PSW*
Program Status Word
D0H
CY
RS1
RS0
OV
00H
RACAP2H# Timer 2 Capture High
CBH
CAH
00H
00H
RACAP2L#
Timer 2 Capture Low
SBUF
Serial Data Buffer
99H
xxxxxxxxB
9F
9E
9D
9C
9B
9A
99
TI
98
RI
SCON*
SP
Serial Control
Stack Pointer
98H
81H
SM0
SM1
SM2
REN
TB8
RB8
00H
07H
8F
TF1
CF
8E
TR1
CE
8D
TF0
8C
TR0
CC
8B
IE1
8A
IT1
CA
89
IE0
C9
88
IT0
C8
TCON*
Timer Control
88H
00H
CD
CB
T2CON*
TH0
TH1
TH2#
TL0
TL1
Timer 2 Control
Timer High 0
Timer High 1
Timer High 2
Timer Low 0
Timer Low 1
Timer Low 2
C8H
8CH
8DH
CDH
8AH
8BH
CCH
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2 00H
00H
00H
00H
00H
00H
00H
TL2#
TMOD
Timer Mode
89H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
*
SFRs are bit addressable.
#
–
SFRs are modified from or added to the 80C51 SFRs.
Reserved bits.
6
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
the instruction that invoked Power Down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator.
their values down to 2.0V and care must be taken to return V to
CC
the minimum specified operating voltages before the Power Down
Mode is terminated.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
Either a hardware reset or external interrupt can be used to exit from
Power Down. Reset redefines all the SFRs but does not change the
on-chip RAM. An external interrupt allows both the SFRs and the
on-chip RAM to retain their values.
To properly terminate Power Down the reset or external interrupt
should not be executed before V is restored to its normal
CC
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10ms).
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the
oscillator but bringing the pin back high completes the exit. Once the
interrupt is serviced, the next instruction to be executed after RETI
will be the one following the instruction that put the device into
Power Down.
V
CC
and RST must come up at the same time for a proper start-up.
Ports 1, 2, and 3 will asynchronously be driven to their reset
condition when a voltage above V
(min.) is applied to RESET.
IH1
Design Consideration
• To eliminate the possibility of an unexpected write when Idle is
terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or to memory.
LOW POWER MODES
Idle Mode
In the idle mode (see Table 2), the CPU puts itself to sleep while all
of the on-chip peripherals stay active. The instruction to invoke the
idle mode is the last instruction executed in the normal operating
mode before the idle mode is activated. The CPU contents, the
on-chip RAM, and all of the special function registers remain intact
during this mode. The idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up at the
interrupt service routine and continued), or by a hardware reset
which starts the processor in the same manner as a power-on reset.
ONCE Mode
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked by:
1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the 8XC51FA/FB is
in this mode, an emulator or test CPU can be used to drive the
circuit. Normal operation is restored when a normal reset is applied.
Power-Down Mode
To save even more power, a Power Down mode (see Table 2) can
be invoked by software. In this mode, the oscillator is stopped and
Table 2. External Pin Status During Idle and Power-Down Mode
MODE
PROGRAM MEMORY
Internal
ALE
PSEN
PORT 0
Data
PORT 1
Data
PORT 2
Data
PORT 3
Data
Idle
Idle
1
1
0
0
1
1
0
0
External
Float
Data
Address
Data
Data
Power-down
Power-down
Internal
Data
Data
Data
External
Float
Data
Data
Data
7
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
illustrated in Figure 2 (There is no reload value for TL2 and TH2 in
this mode. Even when a capture event occurs from T2EX, the
counter keeps on counting T2EX pin transitions or osc/12 pulses.).
TIMER 2 OPERATION
Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an
event timer or an event counter, as selected by C/T2* in the special
function register T2CON (see Figure 1). Timer 2 has three operating
modes:Capture, Auto-reload, and Baud Rate Generator, which are
selected by bits in the T2CON as shown in Table 3.
Auto-Reload Mode
In the 16-bit auto-reload mode, Timer 2 can be configured as either
a timer or counter (C/T2* in T2CON).
Figure 3 shows the auto–reload mode of Timer 2. In this mode there
are two options selected by bit EXEN2 in T2CON register. If
EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2
(Overflow Flag) bit upon overflow. This causes the Timer 2 registers
to be reloaded with the 16-bit value in RCAP2L and RCAP2H.
Capture Mode
In the capture mode there are two options which are selected by bit
EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or
counter (as selected by C/T2* in T2CON) which, upon overflowing
sets bit TF2, the timer 2 overflow bit. This bit can be used to
generate an interrupt (by enabling the Timer 2 interrupt bit in the
IE register/SFR table). If EXEN2= 1, Timer 2 operates as described
above, but with the added feature that a 1- to -0 transition at external
input T2EX causes the current value in the Timer 2 registers, TL2
and TH2, to be captured into registers RCAP2L and RCAP2H,
respectively. In addition, the transition at T2EX causes bit EXF2 in
T2CON to be set, and EXF2 like TF2 can generate an interrupt
(which vectors to the same location as Timer 2 overflow interrupt.
The Timer 2 interrupt service routine can interrogate TF2 and EXF2
to determine which event caused the interrupt). The capture mode is
The values in RCAP2L and RCAP2H are preset by software. If
EXEN2=1, then a 16-bit reload can be triggered either by an
overflow or by a 1-to-0 transition at input T2EX. This transition also
sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be
generated when either TF2 or EXF2 are 1.
The external flag EXF2 toggles when Timer 2 underflows or
overflows. This EXF2 bit can be used as a 17th bit of resolution if
needed. The EXF2 flag does not generate an interrupt in this mode
of operation.
(MSB)
(LSB)
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Symbol
Position
Name and Significance
TF2
T2CON.7
T2CON.6
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set
when either RCLK or TCLK = 1.
EXF2
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2
interrupt routine. EXF2 must be cleared by software.
RCLK
TCLK
T2CON.5
T2CON.4
T2CON.3
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock
in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock
in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.
TR2
T2CON.2
T2CON.1
Start/stop control for Timer 2. A logic 1 starts the timer.
C/T2
Timer or counter select. (Timer 2)
0 = Internal timer (OSC/12)
1 = External event counter (falling edge triggered).
CP/RL2
T2CON.0
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When
cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when
EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload
on Timer 2 overflow.
SU00866
Figure 1.
Timer/Counter 2 (T2CON) Control Register
Table 3. Timer 2 Operating Modes
RCLK + TCLK
CP/RL2
TR2
MODE
0
0
1
X
0
1
1
1
1
0
16-bit Auto-reload
16-bit Capture
Baud rate generator
(off)
X
X
8
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
OSC
÷ 12
C/T2 = 0
C/T2 = 1
TL2
(8-bits)
TH2
(8-bits)
TF2
T2 Pin
Control
TR2
Capture
Transition
Detector
Timer 2
Interrupt
RCAP2L
RCAP2H
T2EX Pin
EXF2
Control
EXEN2
SU00066
Figure 2.
Timer 2 in Capture Mode
OSC
÷ 12
C/T2 = 0
C/T2 = 1
TL2
(8-BITS)
TH2
(8-BITS)
T2 PIN
CONTROL
TR2
RELOAD
TRANSITION
DETECTOR
RCAP2L
RCAP2H
TF2
TIMER 2
INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
SU00067
Figure 3.
Timer 2 in Auto-Reload Mode
9
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
Timer 1
Overflow
÷ 2
NOTE: OSC. Freq. is divided by 2, not 12.
“0”
“0”
“1”
OSC
÷ 2
C/T2 = 0
C/T2 = 1
SMOD
RCLK
“1”
TL2
(8-bits)
TH2
(8-bits)
T2 Pin
Control
÷ 16
RX Clock
“1”
“0”
TR2
Reload
TCLK
Transition
Detector
RCAP2L
RCAP2H
÷ 16
TX Clock
Timer 2
Interrupt
T2EX Pin
EXF2
Control
EXEN2
Note availability of additional external interrupt.
SU00068
Figure 4.
Timer 2 in Baud Rate Generator Mode
The baud rates in modes 1 and 3 are determined by Timer 2’s
overflow rate given below:
Table 4. Timer 2 Generated Commonly Used
Baud Rates
Timer 2 Overflow Rate
Modes 1 and 3 Baud Rates +
Timer 2
16
Baud Rate
Osc Freq
RCAP2H
RCAP2L
The timer can be configured for either “timer” or “counter” operation.
In many applications, it is configured for “timer” operation (C/T2*=0).
Timer operation is different for Timer 2 when it is being used as a
baud rate generator.
375K
9.6K
2.8K
2.4K
1.2K
300
110
300
110
12MHz
12MHz
12MHz
12MHz
12MHz
12MHz
12MHz
6MHz
FF
FF
FF
FF
FE
FB
F2
FD
F9
FF
D9
B2
64
C8
1E
AF
8F
57
Usually, as a timer it would increment every machine cycle (i.e., 1/12
the oscillator frequency). As a baud rate generator, it increments
every state time (i.e., 1/2 the oscillator frequency). Thus the baud
rate formula is as follows:
Modes 1 and 3 Baud Rates =
6MHz
Oscillator Frequency
[32 [65536 * (RCAP2H, RCAP2L)]]
Baud Rate Generator Mode
Where: (RCAP2H, RCAP2L)= The content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.
Bits TCLK and/or RCLK in T2CON (Table 3) allow the serial port
transmit and receive baud rates to be derived from either Timer 1 or
Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit
baud rate generator. When TCLK= 1, Timer 2 is used as the serial
port transmit baud rate generator. RCLK has the same effect for the
serial port receive baud rate. With these two bits, the serial port can
have different receive and transmit baud rates – one generated by
Timer 1, the other by Timer 2.
The Timer 2 as a baud rate generator mode shown in Figure 4, is
valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a
rollover in TH2 does not set TF2, and will not generate an interrupt.
Thus, the Timer 2 interrupt does not have to be disabled when
Timer 2 is in the baud rate generator mode. Also if the EXEN2
(T2 external enable flag) is set, a 1-to-0 transition in T2EX
(Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but
will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2).
Therefore when Timer 2 is in use as a baud rate generator, T2EX
can be used as an additional external interrupt, if needed.
Figure 4 shows the Timer 2 in baud rate generation mode. The baud
rate generation mode is like the auto-reload mode,in that a rollover
in TH2 causes the Timer 2 registers to be reloaded with the 16-bit
value in registers RCAP2H and RCAP2L, which are preset by
software.
10
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
When Timer 2 is in the baud rate generator mode, one should not try
to read or write TH2 and TL2. As a baud rate generator, Timer 2 is
incremented every state time (osc/2) or asynchronously from pin T2;
under these conditions, a read or write of TH2 or TL2 may not be
accurate. The RCAP2 registers may be read, but should not be
written to, because a write might overlap a reload and cause write
and/or reload errors. The timer should be turned off (clear TR2)
before accessing the Timer 2 or RCAP2 registers.
If Timer 2 is being clocked internally , the baud rate is:
fOSC
Baud Rate +
[32 [65536 * (RCAP2H, RCAP2L)]]
Where f
= Oscillator Frequency
OSC
To obtain the reload value for RCAP2H and RCAP2L, the above
equation can be rewritten as:
fOSC
Table 4 shows commonly used baud rates and how they can be
obtained from Timer 2.
RCAP2H, RCAP2L + 65536 * ǒ
Ǔ
32 Baud Rate
Summary Of Baud Rate Equations
Timer 2 is in baud rate generating mode. If Timer 2 is being clocked
through pin T2(P1.0) the baud rate is:
Timer/Counter 2 Set-up
Except for the baud rate generator mode, the values given for
T2CON do not include the setting of the TR2 bit. Therefore, bit TR2
must be set, separately, to turn the timer on. see Table 5 for set-up
of Timer 2 as a timer. Also see Table 6 for set-up of Timer 2 as a
counter.
Timer 2 Overflow Rate
Baud Rate +
16
Table 5. Timer 2 as a Timer
T2CON
MODE
INTERNAL CONTROL
(Note 1)
EXTERNAL CONTROL
(Note 2)
16-bit Auto-Reload
00H
01H
34H
24H
14H
08H
09H
36H
26H
16H
16-bit Capture
Baud rate generator receive and transmit same baud rate
Receive only
Transmit only
Table 6. Timer 2 as a Counter
TMOD
MODE
INTERNAL CONTROL
(Note 1)
EXTERNAL CONTROL
(Note 2)
16-bit
02H
03H
0AH
0BH
Auto-Reload
NOTES:
1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate
generator mode.
11
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
Mode 3: 11 bits are transmitted (through TxD) or received (through
jRxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data
bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all
respects except baud rate. The baud rate in Mode 3 is variable.
Serial Interface
The 89C538/536 has a standard 80C51 serial port. This serial port
can operate in 4 modes:
Mode 0: Serial data enters and exits through RxD. TxD outputs the
shift clock. 8 bits are transmitted/received (LSB first). The baud rate
is fixed at 1/12 the oscillator frequency.
In all four modes, transmission is initiated by any instruction that
uses SBUF as a destination register. Reception is initiated in Mode 0
by the condition RI = 0 and REN = 1. Reception is initiated in the
other modes by the incoming start bit if REN = 1.
Mode 1: 10 bits are transmitted (through TxD) or received (through
RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On
receive, the stop bit goes into RB8 in Special Function Register
SCON. The baud rate is variable.
Serial Port Control Register
The serial port control and status register is the Special
FunctionRegister SCON, shown in Figure 5. This register contains
not only the mode selection bits, but also the 9th data bit for transmit
and receive (TB8 and RB8), and the serial port interrupt bits (TI and
RI).
Mode 2: 11 bits are transmitted (throughTxD) or received (through
RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data
bit, and a stop bit (1). On Transmit, the 9th data bit (TB8 in SCON)
can be assigned the value of 0 or 1, Or, for example, the parity bit
(P, in the PSW) could be moved into TB8. On receive, the 9th data
bit goes into RB8 in Special Function Register SCON, while the stop
bit is ignored. The baud rate is programmable to either 1/32 or 1/64
the oscillator frequency.
Additional details of serial port operation may be found in the 80C51
Family Hardware Description found in the Philips 80C51–Based
8–Bit Microcontroller Data Handbook, IC20.
SCON Address = 98H
Reset Value = 0000 0000B
Bit Addressable
SM0
SM1
SM2
REN
TB8
RB8
Tl
Rl
Bit:
7
6
5
4
3
2
1
0
Symbol
Function
SM0
SM1
Serial Port Mode Bit 0
Serial Port Mode Bit 1
SM0
SM1
Mode
Description
Baud Rate**
0
0
1
1
0
1
0
1
0
1
2
3
shift register
8-bit UART
9-bit UART
9-bit UART
f
/12
OSC
variable
/64 or f
f
/32
OSC
OSC
variable
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
REN
TB8
RB8
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Tl
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Rl
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
NOTE:
**f
= oscillator frequency
OSC
SU00867
Figure 5.
SCON: Serial Port Control Register
12
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
Interrupt Priority Structure
The 89C535/536/538 has a 6-source two-level interrupt structure
(see Table 7). There are 2 SFRs associated with the interrupts on
the 89C535/536/538. They are the IE and IP. (See Figures 6 and 7.)
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IP.x
0
1
Level 0 (lowest priority)
Level 1 (highest priority)
Table 7.
Interrupt Table
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR?
VECTOR ADDRESS
1
2
X0
T0
X1
T1
SP
T2
1
2
3
4
5
6
IE0
TP0
N (L) Y (T)
03H
0BH
13H
1BH
23H
2BH
Y
IE1
N (L) Y (T)
TF1
Y
N
N
R1, TI
TF2, EXF2
NOTES:
1. L = Level activated
2. T = Transition activated
13
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
7
6
5
4
3
2
1
0
IE (0A8H)
EA
—
ET2
ES
ET1
EX1
ET0
EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
SYMBOL FUNCTION
IE.7
EA
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
Not implemented.
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
—
ET2
ES
ET1
EX1
ET0
EX0
SU00571
Figure 6.
IE Registers
3
7
6
5
4
2
1
0
IP (0B8H)
—
—
PT2
PS
PT1
PX1
PT0
PX0
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
SYMBOL FUNCTION
—
—
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit.
Serial Port interrupt priority bit.
Timer 1 interrupt priority bit.
PT2
PS
PT1
PX1
PT0
PX0
External interrupt 1 priority bit.
Timer 0 interrupt priority bit.
External interrupt 0 priority bit.
SU00572
Figure 7.
IP Registers
14
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
For example:
MOV @R0,#data
Expanded Data RAM Addressing
The 89C535/536/538 has internal data memory that is mapped into
four separate segments: the lower 128 bytes of RAM, upper 128
bytes of RAM, 128 bytes Special Function Register (SFR), and 256
bytes expanded RAM (ERAM).
where R0 contains 0A0H, accesses the data byte at address 0A0H,
rather than P2 (whose address is 0A0H).
The ERAM can be accessed by indirect addressing and MOVX
instructions. This part of memory is physically located on-chip,
logically occupies the first 256-bytes of external data memory.
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are
directly and indirectly addressable.
The ERAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or
DPTR. An access to ERAM will not affect ports P0, P3.6 (WR#) and
P3.7 (RD#). P2 SFR is output during external addressing.
For example,
2. The Upper 128 bytes of RAM (addresses 80H to FFH) are
indirectly addressable only.
3. The Special Function Registers, SFRs, (addresses 80H to FFH)
are directly addressable only.
MOVX @R0,#data
4. The 256-bytes expanded RAM (ERAM, 00H – FFH) are indirectly
accessed by move external instruction, MOVX.
where R0 contains 0A0H, accesses the ERAM at address 0A0H
rather than external memory. An access to external data memory
locations higher than FFH (i.e., 0100H to FFFFH) will be performed
with the MOVX DPTR instructions in the same way as in the
standard 80C51, so with P0 and P2 as data/address bus, and P3.6
and P3.7 as write and read timing signals. Refer to Figure 8.
The Lower 128 bytes can be accessed by either direct or indirect
addressing. The Upper 128 bytes can be accessed by indirect
addressing only. The Upper 128 bytes occupy the same address
space as the SFRs. That means they have the same address, but
are physically separate from SFR space.
External data memory cannot be accessed using the MOVX with R0
or R1. This will always access the ERAM.
When an instruction accesses an internal location above address
7FH, the CPU knows whether the access is to the upper 128 bytes
of data RAM or to SFR space by the addressing mode used in the
instruction. Instructions that use direct addressing access SFR
space. For example:
The stack pointer (SP) may be located anywhere in the 256 bytes
RAM (lower and upper RAM) internal data memory. The stack may
not be located in the ERAM.
MOV 0A0H,#data
accesses the SFR at location 0A0H (which is P2). Instructions that
use indirect addressing access the Upper 128 bytes of data RAM.
FF
FF
FF
FFFF
UPPER
128 BYTES
INTERNAL RAM
SPECIAL
FUNCTION
REGISTER
EXTERNAL
DATA
MEMORY
80
80
ERAM
256 BYTES
LOWER
128 BYTES
INTERNAL RAM
0100
0000
00
00
00
SU00868
Figure 8.
Internal and External Data Memory Address Space
15
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Operating temperature under bias
RATING
0 to +70
–65 to +150
0 to +13.0
–0.5 to +6.5
15
UNIT
°C
°C
V
Storage temperature range
Voltage on EA/V pin to V
PP
SS
Voltage on any other pin to V
V
SS
Maximum I per I/O pin
mA
W
OL
Power dissipation (based on package heat transfer limitations, not device power consumption)
NOTES:
1
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise
SS
noted.
16
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C; 5V ±10%; V = 0V
SS
LIMITS
UNIT
TEST
CONDITIONS
SYMBOL
PARAMETER
MIN
MAX
V
V
V
Input low voltage
4.5V < V < 5.5V
–0.5
0.2V –0.1
V
V
V
IL
CC
CC
Input high voltage (ports 0, 1, 2, 3, EA)
Input high voltage, XTAL1, RST
0.2V +0.9
V
CC
V
CC
+0.5
+0.5
IH
CC
0.7V
IH1
CC
V
OL
= 4.5V
= 1.6mA
CC
6
V
V
V
V
Output low voltage, ports 1, 2, 3
0.4
V
V
V
OL
1
I
I
V
CC
= 4.5V
5, 6
Output low voltage, port 0, ALE, PSEN
0.4
OL1
OH
1
= 3.2mA
OL
V
CC
= 4.5V
= –30µA
2
Output high voltage, ports 1, 2, 3
V
V
– 0.7
– 0.7
CC
I
OH
7
Output high voltage (port 0 in external bus mode), ALE ,
V
CC
= 4.5V
= –800µA
V
OH1
CC
2
PSEN
I
OH
I
I
Logical 0 input current, ports 1, 2, 3
Logical 1-to-0 transition current, ports 1, 2, 3
Input leakage current, port 0
V
V
= 0.4V
= 2.0V
–1
–50
–650
±10
µA
µA
µA
IL
IN
IN
TL
See note 3
I
I
0.45 < V < V – 0.3
LI
IN
CC
Power supply current (see Figure 16):
Active mode
Idle mode
Power-down mode or clock stopped
(see Figure 20 for conditions)
See note 4
= 5.5V
CC
V
CC
60
25
100
mA
mA
µA
FREQ = 24 MHz
= 0°C to 70°C
T
amb
R
Internal reset pull-down resistor
40
225
kΩ
RST
NOTES:
1. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due
OL
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no
OL
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
2. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the V –0.7 specification when the
OH
CC
address bits are stabilizing.
3. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V is approximately 2V.
IN
4. See Figures 17 through 20 for I test conditions.
CC
Active mode:
Idle mode:
I
I
= 0.9 × FREQ. + 1.1mA
= 0.18 × FREQ. +1.0mA; See Figure 16.
CC(MAX)
CC(MAX)
5. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
6. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin:
15mA
26mA
71mA
OL
Maximum I per 8-bit port:
OL
Maximum total I for all outputs:
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
7. ALE is tested to V
, except when ALE is off then V is the voltage specification.
OH
OH1
8. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF
(except EA is 25pF).
17
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
AC ELECTRICAL CHARACTERISTICS
1, 2, 3
T
amb
= 0°C to +70°C, V = 5V ±10%, V = 0V
CC SS
VARIABLE CLOCK
33MHz CLOCK
SYMBOL FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/t
CLCL
9
Oscillator frequency
3.5
33
Speed versions : N (33MHz)
MHz
3.5
21
5
33
t
t
t
t
t
t
t
t
t
t
t
9
9
9
9
9
9
9
9
9
9
9
ALE pulse width
2t
–40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
t
–25
AVLL
LLAX
LLIV
CLCL
CLCL
–25
5
4t
3t
–65
55
30
CLCL
t
–25
5
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
PSEN pulse width
3t
CLCL
–45
45
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–60
CLCL
0
0
t
–25
5
CLCL
5t
CLCL
–80
70
10
10
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
11
RD pulse width
6t
–100
–100
82
82
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
5t
2t
–90
–28
60
CLCL
0
0
Data float after RD
32
90
CLCL
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
8t
–150
–165
CLCL
CLCL
9t
105
140
AVDV
LLWL
3t
–50
–75
3t
CLCL
+50
40
45
0
CLCL
4t
AVWL
QVWX
WHQX
QVWH
RLAZ
WHLH
CLCL
t
t
–30
CLCL
CLCL
CLCL
–25
5
Data valid to WR high
RD low to address float
RD or WR high to ALE high
7t
–130
80
10, 11
10, 11
0
0
t
–25
t
+25
5
55
CLCL
CLCL
External Clock
t
t
t
t
13
13
13
13
High time
Low time
Rise time
Fall time
17
17
t
–t
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
CLCL CLCX
t
–t
CLCL CHCX
5
5
Shift Register
t
t
t
t
t
12
12
12
12
12
Serial port clock cycle time
12t
360
167
50
ns
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10t –133
CLCL
QVXH
XHQX
XHDX
XHDV
2t
CLCL
–80
0
0
10t
–133
167
CLCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
18
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
P – PSEN
Q – Output data
R – RD signal
t – Time
A – Address
V – Valid
C – Clock
W– WR signal
D – Input data
H – Logic level high
X – No longer a valid logic level
Z – Float
I – Instruction (program memory contents)
L – Logic level low, or ALE
Examples: t
= Time for address valid to ALE low.
=Time for ALE low to PSEN low.
AVLL
t
LLPL
t
LHLL
ALE
t
t
LLPL
AVLL
t
PLPH
t
LLIV
t
PLIV
PSEN
t
LLAX
t
PXIZ
t
PLAZ
t
PXIX
A0–A7
INSTR IN
A0–A7
PORT 0
PORT 2
t
AVIV
A0–A15
A8–A15
SU00006
Figure 9.
External Program Memory Read Cycle
ALE
PSEN
RD
t
WHLH
t
LLDV
t
t
LLWL
RLRH
t
RHDZ
t
LLAX
t
t
RLDV
AVLL
t
RLAZ
t
RHDX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA IN
A0–A7 FROM PCL
INSTR IN
t
AVWL
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00025
Figure 10.
External Data Memory Read Cycle
19
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
ALE
t
WHLH
PSEN
t
t
WLWH
LLWL
WR
t
LLAX
t
t
WHQX
t
AVLL
QVWX
t
QVWH
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA OUT
A0–A7 FROM PCL
INSTR IN
t
AVWL
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00026
Figure 11. External Data Memory Write Cycle
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
t
XLXL
CLOCK
t
XHQX
t
QVXH
OUTPUT DATA
0
1
2
3
4
5
6
7
WRITE TO SBUF
t
XHDX
t
SET TI
VALID
XHDV
INPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
SU00027
Figure 12.
Shift Register Mode Timing
V
–0.5
CC
0.7V
CC
CC
0.45V
0.2V
–0.1
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
SU00009
Figure 13.
External Clock Drive
20
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
V
–0.5
CC
V
V
+0.1V
LOAD
V
V
–0.1V
TIMING
REFERENCE
POINTS
OH
0.2V
0.2V
+0.9
–0.1
CC
V
LOAD
CC
–0.1V
LOAD
+0.1V
OL
0.45V
NOTE:
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from
load voltage occurs, and begins to float when a 100mV change from the loaded
AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.
CC
IH
IL
V
/V level occurs. I /I ≥ ±20mA.
OH OL
OH OL
SU00717
SU00718
Figure 14.
AC Testing Input/Output
Figure 15.
Float Waveform
90.00
80.00
MAX ACTIVE MODE
70.00
60.00
50.00
TYP ACTIVE MODE
40.00
30.00
20.00
MAX IDLE MODE
10.00
0.00
TYP IDLE MODE
24 28 32
FREQ AT XTAL1 (MHz)
0
4
8
12
16
20
36
SU00886
Figure 16.
I
vs. FREQ Valid only within frequency specifications of the device under test
CC
21
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
V
V
CC
CC
I
I
CC
CC
V
V
CC
CC
V
RST
V
V
CC
CC
CC
P0
EA
P0
EA
RST
(NC)
XTAL2
XTAL1
(NC)
XTAL2
XTAL1
CLOCK SIGNAL
CLOCK SIGNAL
V
V
SS
SS
SU00719
SU00720
Figure 17.
I
Test Condition, Active Mode
Figure 18.
I
Test Condition, Idle Mode
CC
CC
All other pins are disconnected
All other pins are disconnected
V
–0.5
CC
0.7V
CC
CC
0.45V
0.2V
–0.1
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
SU00009
Figure 19.
Clock Signal Waveform for I Tests in Active and Idle Modes
CC
t
= t
= 5ns
CHCL
CLCH
V
CC
CC
I
CC
V
CC
V
RST
P0
EA
(NC)
XTAL2
XTAL1
V
SS
SU00016
Figure 20.
I
Test Condition, Power Down Mode
CC
All other pins are disconnected. V = 2V to 5.5V
CC
22
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
does not require the system to time out or verify the data
programmed. The typical room temperature chip programming time
of the 89C535/536/538 is less than 5 seconds.
FLASH EPROM PROGRAM MEMORY
FEATURES
Automatic Chip Erase
• 8K (89C535), 16K (89C536), 64K (89C538) or electrically
The device may be erased using the automatic Erase algorithm. The
automatic Erase algorithm automatically programs the entire array
prior to electrical erase. The timing and verification of electrical
erase are controlled internal to the device.
erasable internal program.
• Up to 64 Kilobyte external program memory if the internal program
memory is switched off (EA = 0)..
Automatic Programming Algorithm
• Programming and erasing voltage 12V "5%
• Command register architecture
– Byte Programming (10 us typical)
The 89C535/536/538 automatic Programming algorithm requires the
user to only write a program set–up command and a program
command (program data and address). The device automatically
times the programming pulse width, provides the program verify, and
counts the number of sequences. A status bit similar to DATA
polling and a status bit toggling between consecutive read cycles,
provide feedback to the user as to the status of the programming
operation.
– Auto chip erase 5 seconds typical (including preprogramming
time)
• Auto Erase and auto program
– DATA polling
– Toggle bit
• 100 minimum erase/program cycles
AUTOMATIC ERASE ALGORITHM
The 89C535/536/538 Automatic Erase algorithm requires the user to
only write an erase set–up command and erase command. The
device will automatically pre–program and verify the entire array.
Then the device automatically times the erase pulse width, provides
the erase verify, and counts the number of sequences. A status bit
similar to DATA polling and a status bit toggling between
consecutive read cycles, provide feedback to the user as to the
status of the erase operation.
• Advanced CMOS FLASH EPROM memory technology
GENERAL DESCRIPTION
The 89C535/536/538 FLASH EPROM memory augments EPROM
functionality with In–circuit electrical erasure and programming. The
89C535/536/538 uses a command register to manage this
functionality.
Commands are written to the command register. Register contents
serve as inputs to an internal state–machine which controls the
erase and programming circuitry. During write cycles, the command
register internally latches address and data needed for the
programming and erase operations. For system design
simplification, the 89C535/536/538 is designed to support either WE
or CE controlled writes. During a system write cycle, addresses are
latched on the falling edge of WE or CE, whichever occurs last. Data
is latched on the rising edge of WE or CE, whichever occurs first. To
simplify the following discussion, the WE pin is used as the write
cycle control pin through the rest of this text. All setup and hold
times are with respect to the WE signal.
The FLASH EPROM reliably stores memory contents even after 100
erase and program cycles. The cell is designed to optimize the
erase and programming mechanisms. In addition, the combination
of advanced tunnel oxide processing and low internal electric fields
for erase and programming operations produces reliable cycling.
The 89C535/536/538 uses a 12.0V "5%V supply to perform the
PP
Auto Program/Erase algorithms.
Automatic Programming
The 89C535/536/538 is byte programmable using the Automatic
Programming algorithm. The Automatic Programming algorithm
23
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
+5V
VDD
P0
A0–A7
1
P1
PGM COMMAND/DATA
EA
V
PP
RST
P3.3
XTAL2
ALE/WE
PSEN
LOW PULSE
CE
0
89C535/536/538
OE
P2.7
P3.5
A15
4–6 MHz
A8–A13
P2.0–P2.5
XTAL1
VSS
P3.4
A14
0000b
P2.6, P3.7, P3.1, P3.0
su00876
Figure 21.
Erase/Programming/Verification
SYMBOL
Table 8. Pin Description
PIN NAME
FUNCTION
P1.0–P1.7
A0–A7
Input Low Order Address Bits
P2.0–P2.5, P3.4, P3.5
A8–A13, A14–A15
Input High Order Address Bits
Data Input/Output
P0.0–P0.7
Q0–Q7
CE
P3.3
Chip Enable Input
P2.7
OE
Output Enable Input
Write Enable Pin
ALE/WE
WE
EA
V
Program Supply Voltage
Flash Test Mode Selection
Power Supply Voltage (+5V)
Ground Pin
PP
P2.6, P3.7, P3.1, P3.0
FTEST3–FTEST0
V
CC
V
CC
GND
GND
Table 9. Command Definitions
FIRST BUS CYCLE
OPERATION ADDRESS DATA
SECOND BUS CYCLE
COMMAND
BUS CYCLES
OPERATION ADDRESS DATA
Setup auto erase/auto erase (chip)
Setup auto program/program
Reset
2
2
2
Write
Write
Write
X
X
X
30H
40H
FFH
Write
Write
Write
X
30H
PD
PA
X
FFH
Note:
Command Definitions
When low voltage is applied to the V pin, the contents of the
command register default to 00H. Placing high voltage on the V
pin enables read/write operations. Device operations are selected
by writing specific data patterns into the command register. Table 2
defines these 89C535/536/538 register commands. Table 3 defines
the bus operations of 89C535/536/538.
• PA = Address of memory location to be programmed
• PD = Data to be programmed at location
PP
PP
24
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
Table 10.
OPERATION
V
PP
(1)
CE
OE
WE
D00–D07
READ/WRITE
Read(2)
Standby(4)
Write
V
PPH
V
PPH
V
PPH
V
IL
V
IH
V
IL
V
X
V
VI
X
DATA OUT(3)
Tri–State
IL
H
V
IL
Data In(5)
IH
NOTES:
1. V
is the programming voltage specified for the device.
PPH
2. Read operation withVPP = V
may access array data (if write command is preceded) or silicon ID codes.
PPH
3. With V at high voltage, the standby current equals I +I (standby).
PP
CC PP
4. Refer to Table 38 for valid Data–In during a write operation.
5. X can be V or V
.
IH
IL
Set–Up Automatic Chip Erase/Erase Commands
The automatic chip erase does not require the device to be entirely
pre–programmed prior to executing the Automatic set–up erase
command and automatic chip erase command. Upon executing the
Automatic chip erase command, the device automatically will
program and verify the entire memory for an all–zero data pattern.
When the device is automatically verified to contain an all–zero
pattern, a self–timed chip erase and verify begins. The erase and
verify operations are complete when the data on DQ7 is”1” at which
time the device returns to the standby mode. The system is not
required to provide any control or timing during these operations.
Reset Command
A reset command is provided as a means to safely abort the erase–
or program–command sequences. Following either set–up
command (erase or program) with two consecutive writes of FFH
will safely abort the operation. Memory contents will not be altered.
Should program–fail or erase–fail happen, two consecutive writes of
FFH will reset the device to abort the operation. A valid command
must then be written to place the device in the desired state.
Write Operation Status
Toggle Bit–DQ6
When using the Automatic Chip Erase algorithm, note that the erase
automatically terminates when adequate erase margin has been
achieved for the memory array (no erase verify command is
required). The margin voltages are internally generated in the same
manner as when the standard erase verify command is used.
The 89C535/536/538 features a “Toggle Bit” as a method to indicate
to the host system that the Auto Program/Erase algorithms are
either in progress or completed.
While the Automatic Program or Erase algorithm is in progress,
successive attempts to read data from the device will result in DQ6
toggling between one and zero. Once the Automatic Program or
Erase algorithm is completed, DQ6 will stop toggling and valid data
will be read. The toggle bit is valid after the rising edge of the
second WE pulse of the two write pulse sequences.
The Automatic set–up erase command is a command only operation
that stages the device for automatic electrical erasure of all bytes in
the array. Automatic set–up erase is performed by writing 30H to the
command register.
To command automatic chip erase, the command 30H must be
written again to the command register. The automatic chip erase
begins on the rising edge of the WE and terminates when the data
on DQ7 is ”1 “ and the data on DQ6 stops toggling for two
consecutive read cycles, at which time the device returns to the
standby mode.
Data Polling–D07
The 89C535/536/538 also features DATA Polling as a method to
indicate to the host system that the Automatic Program or Erase
algorithms are either in progress or completed.
While the Automatic Programming algorithm is in operation an
attempt to read the device will produce the complement data of the
data last written to DQ7. Upon completion of the Automatic Program
algorithm an attempt to read the device will produce the true data
last written to DQ7. The Data Polling feature is valid after the rising
edge of the second WE pulse of the two write pulse sequences.
Set–Up Automatic Program/Program Commands
The Automatic Set–up Program is a command–only operation that
stages the devices for automatic programming. Automatic Set–up
Program is performed by writing 40H to the command register.
Once the Automatic Set–up Program operation is performed, the
next WE pulse causes a transition to an active programming
operation. Addresses are internally latched on the falling edge of the
WE pulse. Data is internally latched on the rising edge of the WE
pulse. The rising edge of WE also begins the programming
operation. The system is not required to provide further controls or
timings. The device will automatically provide an adequate internally
generated program pulse and verify margin. The automatic
programming operation is completed when the data read on DQ6
stops toggling for two consecutive read cycles and the data on DQ7
and DQ6 are equivalent to data written to these two bits at which
time the device returns to the Read mode (no program verify
command is required; but data can be read out if OE is active low).
While the Automatic Erase algorithm is in operation, DQ7 will read
“0” until the erase operation is completed. Upon completion of the
erase operation, the data on DQ7 will read “1”. The DATA Polling
feature is valid after the rising edge of the second WE pulse of two
writes pulse sequences.
The DATA Polling feature is active during Automatic Program/Erase
algorithms.
Write Operation
The data to be programmed into Flash should be inverted when
programming. In other words to program the value ‘00’, ‘FF’ should
be applied to port P0.
25
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
dependent on the output capacitance loading of the device. At a
minimum, a 0.1uF ceramic capacitor (high frequency, low inherent
System Considerations
During the switch between active and standby conditions, transient
current peaks are produced on the rising and falling edges of Chip
Enable. The magnitude of these transient current peaks is
inductance) should be used on each device between V and GND,
CC
and between V and GND to minimize transient effects.
PP
SYMBOL
PARAMETER
MIN
TYP
MAX
14
UNIT
PF
CONDITION
VI = 0V
C
V
PPH
V
PPH
IN
N
C
16
pF
V
OUT
= 0V
OUT
Command programming/Data programming/Erase Operation
DC CHARACTERISTICS
T
amb
= 0°C to 70°C, V = 5V ± 10%, V = 12.0V ± 5%
CC PP
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
I
I
Input Leakage Current
Output Leakage Current
V
V
= GND to V
CC
10
µA
µA
mA
µA
mA
mA
mA
mA
mA
mA
µA
mA
mA
mA
mA
V
LI
IN
= GND to V
CC
10
1
LO
OUT
CE = VI
I
I
Standby V Current
H
SB1
CC
SB2
CE = V ± 0.3 V
1
100
30
50
50
50
50
50
100
50
50
50
50
CC
I
I
I
I
I
I
I
I
I
I
I
(Read)
Operating V Current
I
= 0 mA, f=1 MHz
= 0 mA, F=11MHz
CC1
CC2
CC3
CC4
CC5
CC6
PP1
PP2
PP3
PP4
PP5
CC
OUT
OUT
I
(Program)
(Erase)
In Programming
In Erase
(Program Verify)
(Erase Verify)
(Read)
In Program Verify
In erase Verify
V
PP
Current
V
PP
=12.6 V
(Program)
In Programming
In Erase
(Erase)
(Program Verify)
(Erase Verify)
In Program Verify
In Erase Verify
V
V
Input Voltage
–0.5 (Note 5)
2.4
0.2V – 0.3
PP
IL
V
CC
+0.3V
V
IH
(Note 6)
0.45
V
V
Output Voltage Low
Output Voltage High
I
I
=2.1mA
V
V
OL
OL
=400uA
2.4
OH
OH
NOTES:
1. V must be applied before V and removed after V .
PP
CC
PP
2. V must not exceed 14V including overshoot.
PP
3. An influence may be had upon device reliability if the device is installed or removed while V =12V.
PP
4. Do not alter V from V to 12V or 12V to V when CE=V
PP
IL
IL
IL
5. V min. = –0.5V for pulse width ≤ 20ns.
IL
6. If V is over the specified maximum value, programming operation cannot be guaranteed.
IH
7. All currents are in RMS unless otherwise noted. (Sampled, not 100% tested.).
26
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
AC CHARACTERISTICS
T
= 0°C to 70°C, V = 5V " 10%, V = 12V " 5%
amb
CC
PP
SYMBOL
PARAMETER
CONDITION
MIN
100
100
150
60
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
τ
τ
τ
τ
τ
τ
τ
τ
τ
τ
τ
τ
τ
τ
τ
τ
τ
τ
V
setup time
VPS
OES
CWC
CEP
EPH1
CEPH2
AS
PP
OE setup time
Command programming cycles
WE programming pulse width
WE programming pulse width High
WE programming pulse width High
Address setup time
20
100
0
Address hold time for DATA Polling
DATA setup time
0
AH1
DS
50
DATA hold time
10
DH
CE setup time before DATA polling/toggle bit
CE setup time
100
0
CESP
CES
CESC
VPH
DF
CE setup time before command write
100
100
V
PP
hold time
Output disable time (Note 2)
35
150
DATA polling/toggle bit access time
Total erase time in auto chip erase
Total programming time in auto verify
DPA
AETC
AVT
5(TYP)
300
15
ms
NOTES:
1. CE and OE must be fixed high during V transition from 5V to 12V or from 12V to 5V.
PP
2. τ is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
DF
circuit. Programming completion can be verified by DATA polling and
toggle bit checking after automatic verify starts. Device outputs
DATA during programming and DATA after programming on Q7. Q0
to Q5(Q6 is for toggle bit; see toggle bit, DATA polling, timing
waveform) are in high impedance.
Timing Waveform
Automatic Programming
One byte of data is programmed. Verifying in fast algorithm and
additional programming by external control are not required because
these operations are executed automatically by an internal control
27
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
SETUP AUTO PROGRAM/
PROGRAM COMMAND
AUTO PROGRAM & DATA POLLING
V
5V
CC
12V
OV
V
PP
τ
VPH
τ
VPS
ADDRESS
VALID
A0–A15
WE
τ
AS
τ
AH1
τ
AVT
τcwc
CE
OE
τ
τ
CESC
τ
CEPH1
τ
τ
τ
CEP
CEP
CESP
CES
τ
QES
τ
τ
τ
τ
DS
DH
DS
DH
t
τ
DF
DPA
DATA IN
DATA
Q7
DATA
COMMAND IN
DATA POLLING
COMMAND IN
DATA IN
Q0–Q5
DATA
COMMAD #40H
su00877
Figure 22.
Automatic Programming Timing Waveform
AUTOMATIC CHIP ERASE
0 during erasure and 1 after erasure on Q7, Q0 to Q5 (Q6 is for
toggle bit; see toggle bit, DATA polling, timing waveform) are in high
impedance.
All data in the FLASH memory is erased. External erase verification
is not required. Erasure completion can be verified by DATA polling
and toggle bit checking after automatic erase starts. Device outputs
28
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
RESET
SETUP AUTO CHIP ERASE/
ERASE COMMAND
AUTO CHIP ERASE & DATA POLLING
V
5V
CC
12V
OV
τ
V
VPH
PP
τ
VPS
A0–A15
WE
τ
AETC
τ
CWC
CE
OE
τ
CESC
τ
τCES
τ
CEP
τ
CEP
τ
CESP
CEPH1
τ
QES
τ
τ
τ
τ
τ
DS
DS
DPA
DH
DH
τ
DF
COMMAND IN
COMMAND IN
COMMAND IN
Q7
DATA POLLING
COMMAND IN
Q0–Q5
su00878
Figure 23.
Automatic Chip Erase Timing Waveform
29
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
V
CC
5V
12V
0V
V
PP
τ
VPS
A0–A15
t
CWC
WE
CE
τ
QES
τ
τ
τ
CEP
CEP
CEPH1
OE
τ
τ
DH
τ
τ
DS
DS
DH
Q0–Q7
COMMAND IN
FFH
COMMAND IN
FFH
su00879
Figure 24.
Reset Timing Waveform
Toggle Bit, Data Polling
Toggle bit appears in Q6, when program/erase is operating. DATA
polling appears in Q7 during programming or erase.
30
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
HIGH
WE
12V
CE
V
PP
OE
OE
TOGGLE BIT
HIGH–Z
DATA
DURING P/E
DATA POLLING
DATA
HIGH–Z
HIGH–Z
HIGH–Z
O7
DATA
DATA
DATA
DATA
DURING P
PROGRAM/ERASE COMPLETE
DATA POLLING
O7
DURING P
O0–O5
su00880
Figure 25.
Toggle Bit, Data Polling Timing Waveform
31
1997 Jun 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
32
1997 June 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
33
1997 June 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
NOTES
34
1997 June 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
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Telephone 800-234-7381
Philips
Semiconductors
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