P89C54BA [NXP]
80C51 8-bit microcontroller family 4K/8K/16K/32K Flash; 80C51的8位单片机系列4K / 8K / 16K / 32K闪存
| 型号： | P89C54BA |
| 厂家： | 
NXP |
| 描述： | 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash |
| 文件： | 总39页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
89C51/89C52/89C54/89C58
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
Product data
2002 Jan 15
Supersedes data of 1999 Oct 27
IC28 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
DESCRIPTION
The 89C51/89C52/89C54/89C58 contain a non-volatile FLASH
program memory that is parallel programmable. For devices that are
serial programmable (In-System Programmable (ISP) and
In-Application Programmable (IAP) with a boot loader), see the
89C51Rx2 or 89C66x datasheets.
All three families are Single-Chip 8-bit Microcontrollers
manufactured in advanced CMOS process and are derivatives of
the 80C51 microcontroller family. All the devices have the same
instruction set as the 80C51.
SELECTION TABLE FOR FLASH DEVICES
MTP devices
(this data sheet)
ISP/IAP devices
(see separate data sheets)
89C51
4K
89C52/54/58
89C51Rx2
89C66x
16K–64K
512–8K
yes
ROM/EPROM memory size
RAM size (byte)
8K/16K/32K
16K–64K
512–1K
yes
128
yes
no
256
yes
no
Parallel programming
In-System Programming (ISP)
In-Application Programming (IAP)
PWM
yes
yes
no
no
yes
yes
no
no
yes
yes
Programmable Timer/Counter (PCA)
Hardware Watchdog Timer
Serial Channels
no
no
yes
yes
no
no
yes
yes
2
UART
UART
UART
UART + I C
MTP = Multi-Time Programming (via parallel programmer)
ISP = In-System Programming (via serial interface)
IAP = In-Application Programming
Please note that the FLASH programming algorithm for these parts has been modified. Please see the Device Comparison table for details.
DEVICE COMPARISON TABLE
Item
Old devices
New devices
Reason for change
Type description
P89C5xUBxx / P89C5xUFxx
P89C5xBx
Letter U dropped for shorter type
descriptions (formerly designated
speed (0–33 MHz))
Programming algorithm
When using parallel programmer, When using a parallel program-
Programming algorithm modifica-
be sure to select P89C5xUxxx
devices
mer, be sure to select P89C5xBx tion required by process change!
devices (no more letter U). IF
DEVICES ARE NOT YET SE-
LECTABLE, ASK YOUR VEN-
DOR FOR A SOFTWARE UP-
DATE.
Quad Flat Package type
Package identifiers
PQFP package (P89C5xUxBB)
PQFP package replaced by
LQFP package (P89C5xBBD).
SEE NEW DIMENSIONS AT
THE END OF THIS DATA
SHEET.
Reduction in package height
Shorter type descriptions
PLCC = AA
PQFP = BB
PDIP = PN
PLCC = A
LQFP = BD
PDIP = P
Flash memory program and
erase cycles
100 program and erase cycles
10,000 program and erase
cycles
Process change allows more pro-
gram and erase cycles
Power consumption
Active mode: I
=
Active mode: I
=
CC(MAX)
Process change allows lower
power consumption
CC(MAX)
(0.9 FREQ. + 20)mA
(0.55 FREQ. + 8.0)mA
Idle mode: I
=
Idle mode: I
=
CC(MAX)
CC(MAX)
(0.37 FREQ. + 1.0)mA
(0.3 FREQ. + 2.0)mA
2
2002 Jan 15
853–2148 27548
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
FEATURES
• 80C51 Central Processing Unit
• Three 16-bit timers/counters T0, T1 (standard 80C51) and
additional T2 (capture and compare)
• On-chip FLASH Program Memory
• Speed up to 33 MHz
• Power control modes
– Clock can be stopped and resumed
– Idle mode
• Fully static operation
– Power down mode
• RAM expandable externally up to 64 kbytes
• 4 interrupt priority levels
• 6 interrupt sources
• Programmable clock out
• Second DPTR register
• Asynchronous port reset
• Four 8-bit I/O ports
• Low EMI (inhibit ALE)
• Full-duplex enhanced UART
– Framing error detection
• Wake up from power down by an external interrupt
– Automatic address recognition
ORDERING INFORMATION
Temperature
Range (°C)
Voltage
Range (V) (MHz)
Frequency
Type number
Package
16K Flash 32K Flash Name
3
4K Flash
version
8K Flash
version
Description
Version
SOT187-2
SOT129-1
version
version
P89C51BA
P89C52BA
P89C54BA
P89C58BA
PLCC44 plastic leaded chip
carrier; 44 leads
0 to +70
0 to +70
5
5
0 to 33
0 to 33
1
1
1
1
P89C51BP
P89C52BP
P89C54BP
P89C58BP
DIP40
plastic dual in-line
package; 40 leads
2
2
2
2
P89C51BN
P89C52BN
P89C54BN
P89C58BN
P89C51BBD P89C52BBD P89C54BBD P89C58BBD LQFP44 plastic low profile quad SOT389-1
0 to +70
5
0 to 33
flat package; 44 leads;
body 10 x 10 x 1.4 mm
NOTES:
1. Philips (except North America) Part Order Number
2. Philips North America Part Order Number. Note that parts will be marked “P89C5xBP”, respectively (x = 1, 2, 4, 8)
3. Industrial temperatures will be released with P89C5xX2 devices (see separate data sheet)
PART NUMBER DERIVATION
Device number (P89C5x)
Temperature range
Package
P89C51
P89C52
P89C54
P89C58
B = 0 _C to 70 _C
BD = LQFP
A = PLCC
P = PDIP
3
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
BLOCK DIAGRAM 1
Standard 80C51+
CPU
4K – 32K Byte
Code Flash
Full-duplex enhanced
UART
128 / 256 Byte
Data RAM
Timer 0
Timer 1
Port 3
Configurable I/Os
Timer 2
Port 2
Configurable I/Os
Port 1
Configurable I/Os
Port 0
Configurable I/Os
Crystal or
Resonator
Oscillator
su01554
4
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
BLOCK DIAGRAM 2 (CPU ORIENTED)
P0.0–P0.7
P2.0–P2.7
PORT 0
DRIVERS
PORT 2
DRIVERS
V
V
CC
SS
RAM ADDR
REGISTER
PORT 0
LATCH
PORT 2
LATCH
FLASH
RAM
8
B
STACK
POINTER
ACC
REGISTER
PROGRAM
ADDRESS
REGISTER
TMP1
TMP2
BUFFER
ALU
SFRs
PC
INCRE-
MENTER
TIMERS
PSW
8
16
PROGRAM
COUNTER
PSEN
ALE
DPTR’S
MULTIPLE
TIMING
AND
CONTROL
EAV
PP
RST
PORT 1
LATCH
PORT 3
LATCH
PD
OSCILLATOR
PORT 1
DRIVERS
PORT 3
DRIVERS
XTAL1
XTAL2
P1.0–P1.7
P3.0–P3.7
SU01066
5
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
LOGIC SYMBOL
Ceramic and Plastic Leaded Chip Carrier
Pin Functions
V
V
SS
CC
6
1
40
XTAL1
ADDRESS AND
DATA BUS
7
39
PLCC
XTAL2
RST
T2
T2EX
17
29
EA/V
PP
18
28
PSEN
ALE/PROG
Pin Function
Pin Function
Pin Function
RxD
1
2
3
NIC*
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
V
SS
NIC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P2.7/A15
PSEN
ALE
NIC*
EA/V
PP
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
TxD
INT0
P1.0/T2
P1.1/T2EX
P1.2
INT1
T0
T1
WR
RD
4
ADDRESS BUS
SU00830
5
P1.3
6
P1.4
7
P1.5
8
P1.6
9
P1.7
10
11
12
13
14
15
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
V
CC
PIN CONFIGURATIONS
Dual In-Line Package Pin Functions
* NO INTERNAL CONNECTION
SU01062
T2/P1.0
40
39
V
1
2
3
CC
T2EX/P1.1
P0.0/AD0
Low Profile Quad Flat Pack Pin Functions
P1.2
P1.3
P1.4
38 P0.1/AD1
37
44
34
4
5
P0.2/AD2
36 P0.3/AD3
35
1
33
P1.5
P1.6
P1.7
RST
6
7
8
9
P0.4/AD4
34 P0.5/AD5
33
LQFP
P0.6/AD6
11
23
32 P0.7/AD7
DUAL
IN-LINE
PACKAGE
31 EA/V
PP
RxD/P3.0 10
TxD/P3.1 11
INT0/P3.2 12
12
Pin Function
22
30 ALE
Pin Function
Pin Function
29
PSEN
28 P2.7/A15
27
1
2
3
P1.5
P1.6
P1.7
RST
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
NIC*
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
SS
13
INT1/P3.3
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
NIC*
EA/V
PP
P0.7/AD7
4
P2.6/A14
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
XTAL1 19
5
6
P3.0/RxD
NIC*
26 P2.5/A13
25 P2.4/A12
7
8
9
10
11
12
13
14
15
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
V
CC
NIC*
24
P2.3/A11
23 P2.2/A10
22
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
P2.1/A9
21 P2.0/A8
V
20
SS
XTAL1
* NO INTERNAL CONNECTION
SU01494
SU01063
6
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC DIP
LCC
22
QFP
16
TYPE NAME AND FUNCTION
V
SS
V
CC
20
40
I
I
Ground: 0 V reference.
44
38
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
P0.0–0.7
39–32 43–36 37–30
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s.
P1.0–P1.7
1–8
2–9
40–44,
1–3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 1 pins that are externally pulled low will source current because of the internal pull-ups.
(See DC Electrical Characteristics: I ). Alternate function for Port 1:
IL
1
2
2
3
40
41
I/O
I
T2 (P1.0): Timer/Counter2 external count input/clockout (see Programmable Clock-Out).
T2EX (P1.1): Timer/Counter2 reload/capture/direction control.
P2.0–P2.7
P3.0–P3.7
21–28 24–31 18–25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I ). Port 2 emits the high-order address byte
IL
during fetches from external program memory and during accesses to external data memory
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses
(MOV @Ri), port 2 emits the contents of the P2 special function register.
10–17
11,
5,
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low will source current because of the pull-ups.
13–19 7–13
(See DC Electrical Characteristics: I ). Port 3 also serves the special features of the
IL
89C51/89C52/89C54/89C58, as listed below:
RxD (P3.0): Serial input port
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
I
O
I
I
I
I
O
O
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
9
10
11
12
13
RST
ALE
9
10
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V permits a power-on reset using only an external
SS
capacitor to V
.
CC
30
33
27
O
Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or clocking. Note that one ALE
pulse is skipped during each access to external data memory. ALE can be disabled by
setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.
PSEN
29
31
32
35
26
29
O
I
Program Store Enable: The read strobe to external program memory. When executing
code from the external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data memory.
PSEN is not activated during fetches from internal program memory.
EA/V
External Access Enable/Programming Supply Voltage: EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H to the
maximum internal memory boundary. If EA is held high, the device executes from internal
program memory unless the program counter contains an address greater than 0FFFH for
4 k devices, 1FFFH for 8 k devices, 3FFFH for 16 k devices, and 7FFFH for 32 k devices.
The value on the EA pin is latched when RST is released and any subsequent changes
PP
have no effect. This pin also receives the 5V/12V (±10%) programming supply voltage (V
)
PP
during FLASH programming.
XTAL1
XTAL2
19
18
21
20
15
14
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
O
Crystal 2: Output from the inverting oscillator amplifier.
NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin (other than V ) at any time must not be higher than V + 0.5 V or
PP
CC
V
– 0.5 V, respectively.
SS
7
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Table 1. 89C51/89C52/89C54/89C58 Special Function Registers
DIRECT
ADDRESS MSB
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
RESET
VALUE
SYMBOL
DESCRIPTION
LSB
ACC*
AUXR#
AUXR1#
B*
Accumulator
E0H
8EH
A2H
F0H
E7
–
E6
–
E5
–
E4
–
E3
–
E2
–
E1
–
E0
00H
Auxiliary
AO
DPS
F0
xxxxxxx0B
xxxx00x0B
00H
Auxiliary 1
B register
–
–
–
–
GF2
F3
0
–
F7
F6
F5
F4
F2
F1
DPTR:
DPH
DPL
Data Pointer (2 bytes)
Data Pointer High
Data Pointer Low
83H
82H
00H
00H
AF
EA
BF
–
AE
–
AD
ET2
BD
AC
ES
BC
PS
B4
AB
ET1
BB
AA
EX1
BA
A9
ET0
B9
A8
EX0
B8
IE*
Interrupt Enable
Interrupt Priority
Interrupt Priority High
Port 0
A8H
B8H
B7H
80H
90H
A0H
0x000000B
xx000000B
xx000000B
FFH
BE
–
IP*
PT2
B5
PT1
B3
PX1
B2
PT0
B1
PX0
B0
B7
–
B6
–
IPH#
P0*
P1*
P2*
P3*
PT2H
85
PSH
84
PT1H
83
PX1H PT0H
PX0H
80
87
86
82
AD2
92
81
AD1
91
AD7
97
AD6
96
AD5
95
AD4
94
AD3
93
AD0
90
Port 1
–
–
–
–
–
–
T2EX
A1
T2
FFH
A7
AD15
B7
RD
A6
AD14
B6
WR
A5
A4
A3
A2
A0
Port 2
AD13
B5
AD12
B4
AD11
B3
AD10
B2
AD9
B1
AD8
B0
FFH
Port 3
B0H
87H
T1
T0
INT1
INT0
TxD
RxD
FFH
1
2
PCON#
Power Control
SMOD1 SMOD0
–
POF
GF1
D3
GF0
D2
PD
D1
–
IDL
D0
P
00xxx000B
D7
CY
D6
AC
D5
F0
D4
PSW*
Program Status Word
D0H
RS1
RS0
OV
000000x0B
RACAP2H# Timer 2 Capture High
RACAP2L# Timer 2 Capture Low
CBH
CAH
00H
00H
SADDR#
SADEN#
Slave Address
Slave Address Mask
A9H
B9H
00H
00H
SBUF
Serial Data Buffer
99H
xxxxxxxxB
9F
9E
9D
9C
9B
9A
99
TI
98
RI
SM0/FE
SCON*
SP
Serial Control
Stack Pointer
98H
81H
SM1
SM2
REN
TB8
RB8
00H
07H
8F
TF1
CF
TF2
–
8E
TR1
CE
8D
TF0
CD
8C
TR0
CC
8B
IE1
8A
IT1
CA
TR2
–
89
IE0
88
IT0
C8
TCON*
Timer Control
88H
C8H
00H
CB
C9
T2CON*
Timer 2 Control
EXF2
–
RCLK
–
TCLK
–
EXEN2
–
C/T2
T2OE
CP/RL2 00H
T2MOD#
TH0
TH1
TH2#
TL0
TL1
Timer 2 Mode Control
Timer High 0
Timer High 1
Timer High 2
Timer Low 0
C9H
8CH
8DH
CDH
8AH
8BH
CCH
DCEN xxxxxx00B
00H
00H
00H
00H
00H
00H
Timer Low 1
Timer Low 2
TL2#
TMOD
Timer Mode
89H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
*
SFRs are bit addressable.
#
–
SFRs are modified from or added to the 80C51 SFRs.
Reserved bits.
1. Reset value depends on reset source.
2. Bit will not be affected by reset.
8
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
FLASH EPROM MEMORY
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an
on-chip oscillator.
General Description
The 89C51/89C52/89C54/89C58 FLASH reliably stores memory
contents even after 10,000 erase and program cycles. The cell is
designed to optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide processing and
low internal electric fields for erase and programming operations
produces reliable cycling.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
Features
• FLASH EPROM internal program memory with Chip Erase
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
• Up to 64 k byte external program memory if the internal program
memory is disabled (EA = 0)
• Programmable security bits
• 10,000 minimum erase/program cycles for each byte
• 10 year minimum data retention
V
CC
and RST must come up at the same time for a proper start-up.
Ports 1, 2, and 3 will asynchronously be driven to their reset
condition when a voltage above V (min.) is applied to RST.
IH1
• Programming support available from many popular vendors
The value on the EA pin is latched when RST is deasserted and has
no further effect.
9
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
two machine cycles before the internal reset algorithm takes control.
On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of
an unexpected write when Idle is terminated by reset, the instruction
following the one that invokes Idle should not be one that writes to a
port pin or to external memory.
LOW POWER MODES
Stop Clock Mode
The static design enables the clock speed to be reduced down to
0 MHz (stopped). When the oscillator is stopped, the RAM and
Special Function Registers retain their values. This mode allows
step-by-step utilization and permits reduced system power
consumption by lowering the clock frequency down to any value. For
lowest power consumption the Power Down mode is suggested.
ONCE Mode
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked by:
Idle Mode
In the idle mode (see Table 2), the CPU puts itself to sleep while all
of the on-chip peripherals stay active. The instruction to invoke the
idle mode is the last instruction executed in the normal operating
mode before the idle mode is activated. The CPU contents, the
on-chip RAM, and all of the special function registers remain intact
during this mode. The idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up at the
interrupt service routine and continued), or by a hardware reset
which starts the processor in the same manner as a power-on reset.
1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the device is in this
mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
Programmable Clock-Out
Power-Down Mode
A 50% duty cycle clock can be programmed to come out on P1.0.
This pin, besides being a regular I/O pin, has two alternate
functions. It can be programmed:
To save even more power, a Power Down mode (see Table 2) can
be invoked by software. In this mode, the oscillator is stopped and
the instruction that invoked Power Down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
1. to input the external clock for Timer/Counter 2, or
2. to output a 50% duty cycle clock ranging from 61Hz to 4MHz at a
16MHz operating frequency.
their values down to 2.0 V and care must be taken to return V to
CC
the minimum specified operating voltages before the Power Down
Mode is terminated.
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit
TR2 (T2CON.2) also must be set to start the timer.
Either a hardware reset or external interrupt can be used to exit from
Power Down. Reset redefines all the SFRs but does not change the
on-chip RAM. An external interrupt allows both the SFRs and the
on-chip RAM to retain their values.
The Clock-Out frequency depends on the oscillator frequency and
the reload value of Timer 2 capture registers (RCAP2H, RCAP2L)
as shown in this equation:
To properly terminate Power Down the reset or external interrupt
should not be executed before V is restored to its normal
Oscillator Frequency
CC
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10ms).
4 (65536 * RCAP2H, RCAP2L)
Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L
taken as a 16-bit unsigned integer.
With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the oscillator
but bringing the pin back high completes the exit. Once the interrupt
is serviced, the next instruction to be executed after RETI will be the
one following the instruction that put the device into Power Down.
In the Clock-Out mode Timer 2 roll-overs will not generate an
interrupt. This is similar to when it is used as a baud-rate generator.
It is possible to use Timer 2 as a baud-rate generator and a clock
generator simultaneously. Note, however, that the baud-rate and the
Clock-Out frequency will be the same.
Design Consideration
When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
Table 2. External Pin Status During Idle and Power-Down Mode
MODE
PROGRAM MEMORY
ALE
PSEN
PORT 0
PORT 1
Data
PORT 2
Data
PORT 3
Data
Idle
Idle
Internal
1
1
0
0
1
1
0
0
Data
External
Float
Data
Address
Data
Data
Power-down
Power-down
Internal
Data
Data
Data
External
Float
Data
Data
Data
10
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Mode 1
TIMER 0 AND TIMER 1 OPERATION
Mode 1 is the same as Mode 0, except that the Timer register is
being run with all 16 bits.
Timer 0 and Timer 1
The “Timer” or “Counter” function is selected by control bits C/T in
the Special Function Register TMOD. These two Timer/Counters
have four operating modes, which are selected by bit-pairs (M1, M0)
in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters.
Mode 3 is different. The four operating modes are described in the
following text.
Mode 2
Mode 2 configures the Timer register as an 8-bit Counter (TL1) with
automatic reload, as shown in Figure 4. Overflow from TL1 not only
sets TF1, but also reloads TL1 with the contents of TH1, which is
preset by software. The reload leaves TH1 unchanged.
Mode 2 operation is the same for Timer/Counter 0.
Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer,
which is an 8-bit Counter with a divide-by-32 prescaler. Figure 2
shows the Mode 0 operation as it applies to Timer 1.
Mode 3
Timer 1 in Mode 3 simply holds its count. The effect is the same as
setting TR1 = 0.
In this mode, the Timer register is configured as a 13-bit register. As
the count rolls over from all 1s to all 0s, it sets the Timer interrupt
flag TF1. The counted input is enabled to the Timer when TR1 = 1
and either GATE = 0 or INT1 = 1. (Setting GATE = 1 allows the
Timer to be controlled by external input INT1, to facilitate pulse width
measurements). TR1 is a control bit in the Special Function Register
TCON (Figure 3). GATE is in TMOD.
Timer 0 in Mode 3 establishes TL0 and TH0 as two separate
counters. The logic for Mode 3 on Timer 0 is shown in Figure 5. TL0
uses the Timer 0 control bits: C/T, GATE, TR0, and TF0, as well as
the INT0 pin. TH0 is locked into a timer function (counting machine
cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus,
TH0 now controls the “Timer 1” interrupt.
Mode 3 is provided for applications requiring an extra 8-bit timer on
the counter. With Timer 0 in Mode 3, an 80C51 can look like it has
three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be
turned on and off by switching it out of and into its own Mode 3, or
can still be used by the serial port as a baud rate generator, or in
fact, in any application not requiring an interrupt.
The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits
of TL1. The upper 3 bits of TL1 are indeterminate and should be
ignored. Setting the run flag (TR1) does not clear the registers.
Mode 0 operation is the same for the Timer 0 as for Timer 1.
Substitute TR0, TF0, and INT0 for the corresponding Timer 1
signals in Figure 2. There are two different GATE bits, one for Timer
1 (TMOD.7) and one for Timer 0 (TMOD.3).
TMOD
Address = 89H
Reset Value = 00H
Not Bit Addressable
7
6
5
4
3
2
1
0
GATE C/T
M1
M0 GATE
C/T
M1
M0
TIMER 1
TIMER 0
GATE
C/T
Gating control when set. Timer/Counter “x” is enabled only while “INTx” pin is high and
“TRx” control pin is set. when cleared Timer “x” is enabled whenever “TRx” control bit is set.
Timer or Counter Selector cleared for Timer operation (input from in=ternal system clock.)
Set for Counter operation (input from “Tx” input pin).
M1
0
0
M0
0
1
OPERATING
8048 Timer “TLx” serves as 5-bit prescaler.
16-bit Timer/Counter “THx” and “TLx” are cascaded; there is no prescaler.
1
0
8-bit auto-reload Timer/Counter “THx” holds a value which is to be reloaded
into “TLx” each time it overflows.
1
1
1
1
(Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits.
TH0 is an 8-bit timer only controlled by Timer 1 control bits.
(Timer 1) Timer/Counter 1 stopped.
SU01514
Figure 1. Timer/Counter 0/1 Mode Control (TMOD) Register
11
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
OSC
÷ 12
C/T = 0
C/T = 1
TL1
(5 Bits)
TH1
(8 Bits)
TF1
Interrupt
Control
T1 Pin
TR1
Gate
INT1 Pin
SU01555
Figure 2. Timer/Counter 0/1 Mode 0: 13-Bit Counter (Timer 1 shown)
TCON
Address = 88H
Bit Addressable
Reset Value = 00H
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
BIT
SYMBOL FUNCTION
TCON.7
TF1
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow.
Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software.
TCON.6
TCON.5
TR1
TF0
Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter on/off.
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow.
Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software.
TCON.4
TCON.3
TR0
IE1
Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter on/off.
Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected.
Cleared when interrupt processed.
TCON.2
TCON.1
TCON.0
IT1
IE0
IT0
Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered
external interrupts.
Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected.
Cleared when interrupt processed.
Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level
triggered external interrupts.
SU01516
Figure 3. Timer/Counter 0/1 Control (TCON) Register
12
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
OSC
÷ 12
C/T = 0
C/T = 1
TL1
(8 Bits)
TF1
Interrupt
Control
T1 Pin
Reload
TR1
Gate
TH1
(8 Bits)
INT1 Pin
SU01556
Figure 4. Timer/Counter 0/1 Mode 2: 8-Bit Auto-Load (Timer 1 shown)
OSC
÷ 12
C/T = 0
C/T = 1
TL0
(8 Bits)
TF0
Interrupt
Control
T1 Pin
TR0
Gate
INT0 Pin
OSC
÷ 12
÷ 6
X2 = 0
X2 = 1
TH0
TF1
Interrupt
(8 Bits)
Control
TR1
SU01557
Figure 5. Timer/Counter 0 Mode 3: Two 8-Bit Counters
13
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Figure 3). When reset is applied the DCEN=0 which means Timer 2
will default to counting up. If DCEN bit is set, Timer 2 can count up
or down depending on the value of the T2EX pin.
TIMER 2 OPERATION
Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an
event timer or an event counter, as selected by C/T2 in the special
function register T2CON (see Figure 1). Timer 2 has three operating
modes: Capture, Auto-reload (up or down counting), and Baud Rate
Generator, which are selected by bits in the T2CON as shown in
Table 3.
Figure 4 shows Timer 2 which will count up automatically since
DCEN=0. In this mode there are two options selected by bit EXEN2
in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH
and sets the TF2 (Overflow Flag) bit upon overflow. This causes the
Timer 2 registers to be reloaded with the 16-bit value in RCAP2L
and RCAP2H. The values in RCAP2L and RCAP2H are preset by
software means.
Capture Mode
In the capture mode there are two options which are selected by bit
EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or
counter (as selected by C/T2 in T2CON) which, upon overflowing
sets bit TF2, the timer 2 overflow bit. This bit can be used to
generate an interrupt (by enabling the Timer 2 interrupt bit in the
IE register). If EXEN2= 1, Timer 2 operates as described above, but
with the added feature that a 1- to -0 transition at external input
T2EX causes the current value in the Timer 2 registers, TL2 and
TH2, to be captured into registers RCAP2L and RCAP2H,
respectively. In addition, the transition at T2EX causes bit EXF2 in
T2CON to be set, and EXF2 like TF2 can generate an interrupt
(which vectors to the same location as Timer 2 overflow interrupt.
The Timer 2 interrupt service routine can interrogate TF2 and EXF2
to determine which event caused the interrupt). The capture mode is
illustrated in Figure 2 (There is no reload value for TL2 and TH2 in
this mode. Even when a capture event occurs from T2EX, the
counter keeps on counting T2EX pin transitions or osc/12 pulses.).
If EXEN2=1, then a 16-bit reload can be triggered either by an
overflow or by a 1-to-0 transition at input T2EX. This transition also
sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be
generated when either TF2 or EXF2 are 1.
In Figure 5 DCEN=1 which enables Timer 2 to count up or down.
This mode allows pin T2EX to control the direction of count. When a
logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will
overflow at 0FFFFH and set the TF2 flag, which can then generate
an interrupt, if the interrupt is enabled. This timer overflow also
causes the 16–bit value in RCAP2L and RCAP2H to be reloaded
into the timer registers TL2 and TH2.
When a logic 0 is applied at pin T2EX this causes Timer 2 to count
down. The timer will underflow when TL2 and TH2 become equal to
the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets
the TF2 flag and causes 0FFFFH to be reloaded into the timer
registers TL2 and TH2.
Auto-Reload Mode (Up or Down Counter)
The external flag EXF2 toggles when Timer 2 underflows or
overflows. This EXF2 bit can be used as a 17th bit of resolution if
needed. The EXF2 flag does not generate an interrupt in this mode
of operation.
In the 16-bit auto-reload mode, Timer 2 can be configured (as either
a timer or counter [C/T2 in T2CON]) then programmed to count up
or down. The counting direction is determined by bit DCEN (Down
Counter Enable) which is located in the T2MOD register (see
T2CON Address = C8H
Reset Value = 00H
Bit Addressable
7
6
5
4
3
2
1
0
(MSB)
(LSB)
TF2
EXF2
RCLK
TCLK EXEN2
TR2
C/T2 CP/RL2
Symbol
Position
Name and Significance
TF2
T2CON.7
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set
when either RCLK or TCLK = 1.
EXF2
T2CON.6
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2
interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down
counter mode (DCEN = 1).
RCLK
TCLK
T2CON.5
T2CON.4
T2CON.3
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock
in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock
in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.
EXEN2
TR2
C/T2
T2CON.2
T2CON.1
Start/stop control for Timer 2. A logic 1 starts the timer.
Timer or counter select. (Timer 2)
0 = Internal timer (OSC/12)
1 = External event counter (falling edge triggered).
CP/RL2
T2CON.0
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When
cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when
EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload
on Timer 2 overflow.
SU01558
Figure 1. Timer/Counter 2 (T2CON) Control Register
14
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Table 3. Timer 2 Operating Modes
RCLK + TCLK
CP/RL2
TR2
1
MODE
0
0
1
X
0
1
16-bit Auto-reload
1
16-bit Capture
Baud rate generator
(off)
X
X
1
0
OSC
÷ 12
C/T2 = 0
TL2
(8-bits)
TH2
(8-bits)
TF2
C/T2 = 1
T2 Pin
Control
TR2
Capture
Transition
Detector
Timer 2
Interrupt
RCAP2L
RCAP2H
T2EX Pin
EXF2
Control
EXEN2
SU00066
Figure 2. Timer 2 in Capture Mode
T2MOD Address = 0C9H
Reset Value = XXXX XX00B
Not Bit Addressable
7
6
5
4
3
2
1
0
—
—
—
—
—
—
T2OE
DCEN
Symbol
Function
1
—
Not implemented, reserved for future use .
T2OE
DCEN
Timer 2 Output Enable bit.
Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.
SU01559
1. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that
case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
Figure 3. Timer 2 Mode (T2MOD) Control Register
15
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
OSC
÷ 12
C/T2 = 0
C/T2 = 1
TL2
(8-BITS)
TH2
(8-BITS)
T2 PIN
CONTROL
TR2
RELOAD
TRANSITION
DETECTOR
RCAP2L
RCAP2H
TF2
TIMER 2
INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
SU00067
Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)
(DOWN COUNTING RELOAD VALUE)
FFH
FFH
TOGGLE
EXF2
OSC
÷12
C/T2 = 0
OVERFLOW
TL2
TH2
TF2
INTERRUPT
C/T2 = 1
T2 PIN
CONTROL
TR2
COUNT
DIRECTION
1 = UP
0 = DOWN
RCAP2L
RCAP2H
(UP COUNTING RELOAD VALUE)
T2EX PIN
SU00730
Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)
16
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Timer 1
Overflow
÷ 2
NOTE: OSC. Freq. is divided by 2, not 12.
“0”
“0”
“1”
OSC
÷ 2
C/T2 = 0
C/T2 = 1
SMOD
RCLK
“1”
TL2
(8-bits)
TH2
(8-bits)
T2 Pin
Control
÷ 16
RX Clock
“1”
“0”
TR2
Reload
TCLK
Transition
Detector
RCAP2L
RCAP2H
÷ 16
TX Clock
Timer 2
Interrupt
T2EX Pin
EXF2
Control
EXEN2
Note availability of additional external interrupt.
SU00068
Figure 6. Timer 2 in Baud Rate Generator Mode
The baud rates in modes 1 and 3 are determined by Timer 2’s
overflow rate given below:
Table 4. Timer 2 Generated Commonly Used
Baud Rates
Timer 2 Overflow Rate
Modes 1 and 3 Baud Rates +
Timer 2
16
Baud Rate
Osc Freq
RCAP2H
RCAP2L
The timer can be configured for either “timer” or “counter” operation.
In many applications, it is configured for “timer” operation (C/T2*=0).
Timer operation is different for Timer 2 when it is being used as a
baud rate generator.
375 k
9.6 k
2.8 k
2.4 k
1.2 k
300
110
300
110
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
6 MHz
FF
FF
FF
FF
FE
FB
F2
FD
F9
FF
D9
B2
64
C8
1E
AF
8F
57
Usually, as a timer it would increment every machine cycle (i.e., 1/12
the oscillator frequency). As a baud rate generator, it increments
every state time (i.e., 1/2 the oscillator frequency). Thus the baud
rate formula is as follows:
Modes 1 and 3 Baud Rates =
6 MHz
Oscillator Frequency
[32 [65536 * (RCAP2H, RCAP2L)]]
Baud Rate Generator Mode
Where: (RCAP2H, RCAP2L) = The content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.
Bits TCLK and/or RCLK in T2CON (Table 4) allow the serial port
transmit and receive baud rates to be derived from either Timer 1 or
Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit
baud rate generator. When TCLK= 1, Timer 2 is used as the serial
port transmit baud rate generator. RCLK has the same effect for the
serial port receive baud rate. With these two bits, the serial port can
have different receive and transmit baud rates – one generated by
Timer 1, the other by Timer 2.
The Timer 2 as a baud rate generator mode shown in Figure 6, is
valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a
rollover in TH2 does not set TF2, and will not generate an interrupt.
Thus, the Timer 2 interrupt does not have to be disabled when
Timer 2 is in the baud rate generator mode. Also if the EXEN2
(T2 external enable flag) is set, a 1-to-0 transition in T2EX
(Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but
will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2).
Therefore when Timer 2 is in use as a baud rate generator, T2EX
can be used as an additional external interrupt, if needed.
Figure 6 shows the Timer 2 in baud rate generation mode. The baud
rate generation mode is like the auto-reload mode, in that a rollover in
TH2 causes the Timer 2 registers to be reloaded with the 16-bit value
in registers RCAP2H and RCAP2L, which are preset by software.
17
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
When Timer 2 is in the baud rate generator mode, one should not try
to read or write TH2 and TL2. As a baud rate generator, Timer 2 is
incremented every state time (osc/2) or asynchronously from pin T2;
under these conditions, a read or write of TH2 or TL2 may not be
accurate. The RCAP2 registers may be read, but should not be
written to, because a write might overlap a reload and cause write
and/or reload errors. The timer should be turned off (clear TR2)
before accessing the Timer 2 or RCAP2 registers.
If Timer 2 is being clocked internally , the baud rate is:
fOSC
Baud Rate +
[32 [65536 * (RCAP2H, RCAP2L)]]
Where f
= Oscillator Frequency
OSC
To obtain the reload value for RCAP2H and RCAP2L, the above
equation can be rewritten as:
fOSC
Table 4 shows commonly used baud rates and how they can be
obtained from Timer 2.
RCAP2H, RCAP2L + 65536 * ǒ
Ǔ
32 Baud Rate
Summary Of Baud Rate Equations
Timer 2 is in baud rate generating mode. If Timer 2 is being clocked
through pin T2(P1.0) the baud rate is:
Timer/Counter 2 Set-up
Except for the baud rate generator mode, the values given for T2CON
do not include the setting of the TR2 bit. Therefore, bit TR2 must be
set, separately, to turn the timer on. see Table 5 for set-up of Timer 2
as a timer. Also see Table 6 for set-up of Timer 2 as a counter.
Timer 2 Overflow Rate
Baud Rate +
16
Table 5. Timer 2 as a Timer
T2CON
MODE
INTERNAL CONTROL
(Note 1)
EXTERNAL CONTROL
(Note 2)
16-bit Auto-Reload
00H
01H
34H
24H
14H
08H
09H
36H
26H
16H
16-bit Capture
Baud rate generator receive and transmit same baud rate
Receive only
Transmit only
Table 6. Timer 2 as a Counter
TMOD
MODE
INTERNAL CONTROL
(Note 1)
EXTERNAL CONTROL
(Note 2)
16-bit
02H
03H
0AH
0BH
Auto-Reload
NOTES:
1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate
generator mode.
18
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Slave 1
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1110
1100 000X
Enhanced UART operation
In addition to the standard operation modes, the UART can perform
framing error detect by looking for missing stop bits, and automatic
address recognition. The UART also fully supports multiprocessor
communication.
In the above example SADDR is the same and the SADEN data is
used to differentiate between the two slaves. Slave 0 requires a 0 in
bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is
ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be
selected at the same time by an address which has bit 0 = 0 (for
slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.
When used for framing error detect the UART looks for missing stop
bits in the communication. A missing bit will set the FE bit in the
SCON register. The FE bit shares the SCON.7 bit with SM0 and the
function of SCON.7 is determined by PCON.6 (SMOD0) (see
Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7
functions as SM0 when SMOD0 is cleared. When used as FE
SCON.7 can only be cleared by software. Refer to Figure 8.
In a more complex system the following could be used to select
slaves 1 and 2 while excluding slave 0:
Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART
to recognize certain addresses in the serial bit stream by using
hardware to make the comparisons. This feature saves a great deal
of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART
modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be
automatically set when the received byte contains either the “Given”
address or the “Broadcast” address. The 9 bit mode requires that
the 9th information bit is a 1 to indicate that the received information
is an address and not data. Automatic address recognition is shown
in Figure 9.
Slave 0
Slave 1
Slave 2
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1001
1100 0XX0
SADDR
SADEN
Given
=
=
=
1110 0000
1111 1010
1110 0X0X
SADDR
SADEN
Given
=
=
=
1110 0000
1111 1100
1110 00XX
In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary to make bit 2 = 1 to exclude slave 2.
The 8 bit mode is called Mode 1. In this mode the RI flag will be set
if SM2 is enabled and the information received has a valid stop bit
following the 8 address bits and the information is either a Given or
Broadcast address.
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to
selectively communicate with one or more slaves by invoking the
Given slave address or addresses. All of the slaves may be
contacted by using the Broadcast address. Two special Function
Registers are used to define the slave’s address, SADDR, and the
address mask, SADEN. SADEN is used to define which bits in the
SADDR are to be used and which bits are “don’t care”. The SADEN
mask can be logically ANDed with the SADDR to create the “Given”
address which the master will use for addressing each of the slaves.
Use of the Given address allows multiple slaves to be recognized
while excluding others. The following examples will help to show the
versatility of this scheme:
The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are trended
as don’t-cares. In most cases, interpreting the don’t-cares as ones,
the broadcast address will be FF hexadecimal.
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR
address 0B9H) are leaded with 0s. This produces a given address
of all “don’t cares” as well as a Broadcast address of all “don’t
cares”. This effectively disables the Automatic Addressing mode and
allows the microcontroller to use standard 80C51 type UART drivers
which do not make use of this feature.
Slave 0
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1101
1100 00X0
19
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
SCON Address = 98H
Reset Value = 0000 0000B
Bit Addressable
7
6
5
4
3
2
1
0
SM0/FE
SM1
SM2
REN
TB8
RB8
Tl
Rl
(SMOD0 = 0/1)*
Symbol
Position
Function
FE
SCON.7
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not
cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable
access to the FE bit.*
SM0
SM1
SCON.7
SCON.6
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
SM0
SM1
Mode
Description
Baud Rate**
0
0
1
1
0
1
0
1
0
1
2
3
shift register
8-bit UART
9-bit UART
9-bit UART
f
/12 or f
/6 depending on the mode
/32
OSC
OSC
variable
/64 or f
f
OSC
OSC
variable
SM2
SCON.5
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set
unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or
Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was
received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0.
REN
TB8
RB8
SCON.4
SCON.3
SCON.2
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that
was received.
In Mode 0, RB8 is not used.
Tl
SCON.1
SCON.0
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of
the stop bit in the other modes, in any serial transmission. Must be cleared by software.
Rl
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the
stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by
software.
NOTES:
*SMOD0 is located at PCON.6.
**f = oscillator frequency
OSC
SU01484
Figure 7. SCON: Serial Port Control Register
20
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
D0
D1
D2
D3
D4
D5
D6
D7
D8
START
BIT
DATA BYTE
ONLY IN
MODE 2, 3
STOP
BIT
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)
SM0 TO UART MODE CONTROL
SCON
(98H)
SM0 / FE
SMOD1
SM1
SM2
REN
POF
TB8
GF1
RB8
GF0
TI
RI
PCON
(87H)
SMOD0
–
PD
IDL
0 : SCON.7 = SM0
1 : SCON.7 = FE
SU01191
Figure 8. UART Framing Error Detection
D0
D1
D2
D3
D4
D5
D6
D7
D8
SCON
(98H)
SM0
SM1
SM2
REN
1
TB8
X
RB8
TI
RI
1
1
1
0
1
RECEIVED ADDRESS D0 TO D7
PROGRAMMED ADDRESS
COMPARATOR
IN UART MODE 2 OR MODE 3 AND SM2 = 1:
INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”
– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES
– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
SU00045
Figure 9. UART Multiprocessor Communication, Automatic Address Recognition
21
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Priority Level Structure
Interrupt Priority Structure
Each interrupt source can also be individually programmed to one of
four priority levels by setting or clearing bits in Special Function
Registers IP (Figure 12) and IPH (Figure 13). A lower-priority
interrupt can itself be interrupted by a higher-priority interrupt, but
not by another interrupt of the same level. A high-priority level 3
interrupt can’t be interrupted by any other interrupt source.
0
INT0
TF0
IT0
IE0
1
If two request of different priority levels are received simultaneously,
the request of higher priority level is serviced. If requests of the
same priority level are received simultaneously, an internal polling
sequence determines which request is serviced. Thus within each
priority level there is a second priority structure determined by the
polling sequence as follows:
Interrupt
Sources
0
1
IE1
INT1
TF1
IT1
Source
Priority Within Level
1. IE0 (External Int 0)
2. TF0 (Timer 0)
3. IE1 (External Int 1)
4. TF1 (Timer 1)
5. RI+TI (UART)
6. TF2, EXF2 (Timer 2)
(highest)
TI
RI
TF2, EXF2
(lowest)
SU01521
Note that the “priority within level” structure is only used to resolve
simultaneous requests of the same priority level.
Figure 10. 80C51 Interrupt Sources
The IP and IPH registers contain a number of unimplemented bits.
User software should not write 1s to these positions, since they may
be used in other 80C51 Family products.
Interrupts
The devices described in this data sheet provide six interrupt
sources. These are shown in Figure 10. The External Interrupts
INT0 and INT1 can each be either level-activated or
How Interrupts Are Handled
The interrupt flags are sampled at S5P2 of every machine cycle.
The samples are polled during the following machine cycle. If one of
the flags was in a set condition at S5P2 of the preceding cycle, the
polling cycle will find it and the interrupt system will generate an
LCALL to the appropriate service routine, provided this
hardware-generated LCALL is not blocked by any of the following
conditions:
1. An interrupt of equal or higher priority level is already in
progress.
2. The current (polling) cycle is not the final cycle in the execution
of the instruction in progress.
transition-activated, depending on bits IT0 and IT1 in Register
TCON. The flags that actually generate these interrupts are bits IE0
and IE1 in TCON. When an external interrupt is generated, the flag
that generated it is cleared by the hardware when the service routine
is vectored to only if the interrupt was transition-activated. If the
interrupt was level-activated, then the external requesting source is
what controls the request flag, rather than the on-chip hardware.
The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1,
which are set by a rollover in their respective Timer/Counter
registers (except see Timer 0 in Mode 3). When a timer interrupt is
generated, the flag that generated it is cleared by the on-chip
hardware when the service routine is vectored to.
3. The instruction in progress is RETI or any write to the IE or IP
registers.
Any of these three conditions will block the generation of the LCALL
to the interrupt service routine. Condition 2 ensures that the
instruction in progress will be completed before vectoring to any
service routine. Condition 3 ensures that if the instruction in
progress is RETI or any access to IE or IP, then at least one more
instruction will be executed before any interrupt is vectored to.
The Serial Port Interrupt is generated by the logical OR of RI and TI.
Neither of these flags is cleared by hardware when the service
routine is vectored to. In fact, the service routine will normally have
to determine whether it was RI or TI that generated the interrupt,
and the bit will have to be cleared in software.
All of the bits that generate interrupts can be set or cleared by
software, with the same result as though it had been set or cleared
by hardware. That is, interrupts can be generated or pending
interrupts can be canceled in software.
The polling cycle is repeated with each machine cycle, and the
values polled are the values that were present at S5P2 of the
previous machine cycle. Note that if an interrupt flag is active but not
being responded to for one of the above conditions, if the flag is not
still active when the blocking condition is removed, the denied
interrupt will not be serviced. In other words, the fact that the
interrupt flag was once active but not serviced is not remembered.
Every polling cycle is new.
Each of these interrupt sources can be individually enabled or
disabled by setting or clearing a bit in Special Function Register IE
(Figure 11). IE also contains a global disable bit, EA, which disables
all interrupts at once.
22
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
IE
Address = 0A8H
Bit Addressable
Reset Value = 0X000000B
7
6
5
4
3
2
1
0
EA
—
ET2
ES
ET1
EX1
ET0
EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
SYMBOL FUNCTION
IE.7
EA
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
Not implemented. Reserved for future use.
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
—
ET2
ES
ET1
EX1
ET0
EX0
SU01522
Figure 11. Interrupt Enable (IE) Register
IP
Address = 0B8H
Bit Addressable
Reset Value = xx000000B
7
6
5
4
3
2
1
0
—
—
PT2
PS
PT1
PX1
PT0
PX0
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
SYMBOL FUNCTION
—
—
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit.
Serial Port interrupt priority bit.
Timer 1 interrupt priority bit.
PT2
PS
PT1
PX1
PT0
PX0
External interrupt 1 priority bit.
Timer 0 interrupt priority bit.
External interrupt 0 priority bit.
SU01523
Figure 12. Interrupt Priority (IP) Register
IPH
Address = B7H
Bit Addressable
Reset Value = xx000000B
7
6
5
4
3
2
1
0
—
—
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT
SYMBOL FUNCTION
IPH.7
IPH.6
IPH.5
IPH.4
IPH.3
IPH.2
IPH.1
IPH.0
—
—
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit high.
Serial Port interrupt priority bit high.
Timer 1 interrupt priority bit high.
External interrupt 1 priority bit high.
Timer 0 interrupt priority bit high.
External interrupt 0 priority bit high.
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
SU01524
Figure 13. Interrupt Priority HIGH (IPH) Register
23
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
. . . . . . . . .
. . . .
C1
C2
C3
C4
C5
S5P2
S6
. . . . . . . . .
. . . .
. . . .
ε
Interrupts
Are Polled
Long Call to
Interrupt
Interrupt Routine
Vector Address
Interrupt
Goes
Interrupt
Latched
Active
This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP.
SU00546
Figure 14. Interrupt Response Timing Diagram
The polling cycle/LCALL sequence is illustrated in Figure 14.
service routine is completed, or else another interrupt will be
generated.
Note that if an interrupt of higher priority level goes active prior to
S5P2 of the machine cycle labeled C3 in Figure 14, then in
accordance with the above rules it will be vectored to during C5 and
C6, without any instruction of the lower priority routine having been
executed.
Response Time
The INT0 and INT1 levels are inverted and latched into IE0 and IE1
at S5P2 of every machine cycle. The values are not actually polled
by the circuitry until the next machine cycle. If a request is active
and conditions are right for it to be acknowledged, a hardware
subroutine call to the requested service routine will be the next
instruction to be executed. The call itself takes two cycles. Thus, a
minimum of three complete machine cycles elapse between
activation of an external interrupt request and the beginning of
execution of the first instruction of the service routine. Figure 14
shows interrupt response timings.
Thus the processor acknowledges an interrupt request by executing
a hardware-generated LCALL to the appropriate servicing routine. In
some cases it also clears the flag that generated the interrupt, and in
other cases it doesn’t. It never clears the Serial Port flag. This has to
be done in the user’s software. It clears an external interrupt flag
(IE0 or IE1) only if it was transition-activated. The
hardware-generated LCALL pushes the contents of the Program
Counter on to the stack (but it does not save the PSW) and reloads
the PC with an address that depends on the source of the interrupt
being vectored to, as shown in Table 7.
A longer response time would result if the request is blocked by one
of the 3 previously listed conditions. If an interrupt of equal or higher
priority level is already in progress, the additional wait time obviously
depends on the nature of the other interrupt’s service routine. If the
instruction in progress is not in its final cycle, the additional wait time
cannot be more the 3 cycles, since the longest instructions (MUL
and DIV) are only 4 cycles long, and if the instruction in progress is
RETI or an access to IE or IP, the additional wait time cannot be
more than 5 cycles (a maximum of one more cycle to complete the
instruction in progress, plus 4 cycles to complete the next instruction
if the instruction is MUL or DIV).
Execution proceeds from that location until the RETI instruction is
encountered. The RETI instruction informs the processor that this
interrupt routine is no longer in progress, then pops the top two
bytes from the stack and reloads the Program Counter. Execution of
the interrupted program continues from where it left off.
Note that a simple RET instruction would also have returned
execution to the interrupted program, but it would have left the
interrupt control system thinking an interrupt was still in progress,
making future interrupts impossible.
Thus, in a single-interrupt system, the response time is always more
than 3 cycles and less than 9 cycles.
External Interrupts
The external sources can be programmed to be level-activated or
transition-activated by setting or clearing bit IT1 or IT0 in Register
TCON. If ITx = 0, external interrupt x is triggered by a detected low
at the INTx pin. If ITx = 1, external interrupt x is edge triggered. In
this mode if successive samples of the INTx pin show a high in one
cycle and a low in the next cycle, interrupt request flag IEx in TCON
is set. Flag bit IEx then requests the interrupt.
As previously mentioned, the derivatives described in this data
sheet have a four-level interrupt structure. The corresponding
registers are IE, IP and IPH. (See Figures 11, 12, and 13.) The IPH
(Interrupt Priority High) register makes the four-level interrupt
structure possible.
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
Since the external interrupt pins are sampled once each machine
cycle, an input high or low should hold for at least 12 oscillator
periods to ensure sampling. If the external interrupt is
transition-activated, the external source has to hold the request pin
high for at least one cycle, and then hold it low for at least one cycle.
This is done to ensure that the transition is seen so that interrupt
request flag IEx will be set. IEx will be automatically cleared by the
CPU when the service routine is called.
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPH.x
IP.x
0
0
0
1
1
Level 0 (lowest priority)
Level 1
1
If the external interrupt is level-activated, the external source has to
hold the request active until the requested interrupt is actually
generated. Then it has to deactivate the request before the interrupt
0
Level 2
1
Level 3 (highest priority)
24
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
Table 7.
Interrupt Table
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR?
VECTOR ADDRESS
1
2
External interrupt 0
Timer 0
1
2
3
4
5
6
IE0
TF0
N (L) Y (T)
03H
0BH
13H
1BH
23H
2BH
Y
External interrupt 1
Timer 1
IE1
N (L) Y (T)
TF1
Y
N
N
UART
RI, TI
TF2, EXF2
Timer 2
NOTES:
1. L = Level activated
2. T = Transition activated
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the ALE output, unless the CPU needs to perform an off-chip memory access.
AUXR
Address = 8EH
Reset Value = xxxx xxx0B
Not Bit Addressable
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
AO
Symbol
Function
AO
Disable/Enable ALE
AO
0
Operating Mode
1
1
ALE is emitted at a constant rate of / the oscillator frequency (6 clock mode; / f
in 12 clock mode)
3
6
OSC
1
ALE is active only during off-chip memory accesses.
1
—
Not implemented, reserved for future use .
SU01560
1. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that
case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
Figure 15. AUXR: Auxiliary Register
25
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Dual DPTR
• New Register Name: AUXR1#
• SFR Address: A2H
• Reset Value: xxxx00x0B
The dual DPTR structure (see Figure 17) is a way by which the chip
will specify the address of an external data memory location. There
are two 16-bit DPTR registers that address the external memory,
and a single bit called DPS = AUXR1/bit0 that allows the program
code to switch between them.
AUXR1
Address = A2H
Reset Value = xxxx 00x0B
Not Bit Addressable
7
6
5
4
3
2
0
1
0
—
—
—
—
GF2
—
DPS
Symbol
Function
GF2
The GF2 bit is a general purpose user-defined flag. Note that bit 2 is not writable and is always read as a zero. This
allows the DPS bit to be quickly toggled simply by executing an INC AUXR1 instruction without affecting the GF2 bit.
DPS
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
Select Reg
DPTR0
DPTR1
DPS
0
1
SU01561
1
—
Not implemented, reserved for future use .
1. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that
case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
Figure 16. AUXR1: Auxiliary 1 Register
INC DPTR
Increments the data pointer by 1
DPS
MOV DPTR, #data16 Loads the DPTR with a 16-bit constant
BIT0
AUXR1
MOV A, @ A+DPTR
MOVX A, @ DPTR
Move code byte relative to DPTR to ACC
DPTR1
DPTR0
Move external RAM (16-bit address) to
ACC
DPH
DPL
(83H)
(82H)
EXTERNAL
DATA
MEMORY
MOVX @ DPTR , A
JMP @ A + DPTR
Move ACC to external RAM (16-bit
address)
SU00745A
Jump indirect relative to DPTR
Figure 17.
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
26
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Operating temperature under bias
RATING
0 to +70 or –40 to +85
–65 to +150
0 to +13.0
–0.5 to +6.5
15
UNIT
°C
°C
V
Storage temperature range
Voltage on EA/V pin to V
PP
SS
Voltage on any other pin to V
V
SS
Maximum I per I/O pin
mA
W
OL
Power dissipation (based on package heat transfer limitations, not device power consumption)
1.5
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise noted.
SS
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C or –40°C to +85°C
CLOCK FREQUENCY
RANGE –f
SYMBOL
PARAMETER
UNIT
MIN
MAX
1/t
CLCL
Oscillator frequency
0
33
MHz
27
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C or –40°C to +85°C; 5 V ±10%; V = 0 V
SS
LIMITS
TEST
CONDITIONS
SYMBOL
PARAMETER
UNIT
1
MIN
TYP
MAX
0.2 V –0.1
V
V
V
Input low voltage
4.5 V < V < 5.5 V
–0.5
V
V
V
IL
CC
CC
Input high voltage (ports 0, 1, 2, 3, EA)
Input high voltage, XTAL1, RST
0.2 V +0.9
V
CC
V
CC
+0.5
+0.5
IH
CC
0.7 V
IH1
CC
V
OL
= 4.5 V
= 1.6 mA
CC
8
V
V
V
V
Output low voltage, ports 1, 2, 3
0.4
V
V
V
OL
2
I
I
V
CC
= 4.5 V
7, 8
Output low voltage, port 0, ALE, PSEN
0.4
OL1
OH
2
= 3.2 mA
OL
V
CC
= 4.5 V
= –30 µA
3
Output high voltage, ports 1, 2, 3
V
V
– 0.7
– 0.7
CC
I
OH
Output high voltage (port 0 in external bus mode),
V
CC
= 4.5 V
= –3.2 mA
V
OH1
CC
9
3
ALE , PSEN
I
OH
I
I
Logical 0 input current, ports 1, 2, 3
Logical 1-to-0 transition current, ports 1, 2, 3
Input leakage current, port 0
V
V
= 0.4 V
= 2.0 V
–1
–75
–650
±10
µA
µA
µA
IL
IN
IN
6
TL
See Note 4
I
I
0.45 < V < V – 0.3
LI
IN
CC
Power supply current (see Figure 25):
Active mode (see Note 5)
See Note 5
CC
Idle mode (see Note 5)
Power-down mode or clock stopped (see Figure 29
for conditions)
T
= 0°C to 70°C
= –40°C to +85°C
3
100
125
µA
µA
amb
T
amb
R
C
Internal reset pull-down resistor
40
225
15
kΩ
RST
IO
10
Pin capacitance (except EA)
pF
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due
OL
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no
OL
single output sinks more than 5 mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the V –0.7 specification when the
OH
CC
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V is approximately 2 V.
IN
5. See Figures 26 through 29 for I test conditions and Figure 25 for I vs Freq.
CC
CC
Active mode:
Idle mode:
I
I
= (0.56 × FREQ. + 8.0)mA
= (0.30 × FREQ. +2.0)mA
CC(MAX)
CC(MAX)
6. This value applies to T
= 0°C to +70°C.
amb
7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin:
15 mA (*NOTE: This is 85°C specification.)
OL
Maximum I per 8-bit port:
26 mA
OL
Maximum total I for all outputs:
71 mA
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
9. ALE is tested to V
, except when ALE is off then V is the voltage specification.
OH
OH1
10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF
(except EA is 25 pF).
28
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
AC ELECTRICAL CHARACTERISTICS
1, 2, 3
T
amb
= 0°C to +70°C or –40°C to +85°C, V = 5 V ±10%, V = 0V
CC SS
4
VARIABLE CLOCK
33MHz CLOCK
SYMBOL
1/t
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
18
Oscillator frequency
3.5
33
CLCL
MHz
Speed versions
3.5
21
5
33
t
t
t
t
t
t
t
t
t
t
t
18
18
18
18
18
18
18
18
18
18
18
ALE pulse width
2t
–40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
t
–25
AVLL
LLAX
LLIV
CLCL
CLCL
t
–25
5
4t
3t
–65
55
30
CLCL
t
–25
5
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
3t
–45
45
CLCL
PSEN low to valid instruction in
–60
CLCL
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
0
0
t
–25
5
CLCL
5t
–80
70
10
CLCL
10
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
19, 20
19, 20
19, 20
19, 20
19, 20
19, 20
19, 20
19, 20
19, 20
19, 20
19, 20
20
RD pulse width
6t
–100
–100
82
82
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
5t
2t
–90
–28
60
CLCL
0
0
Data float after RD
32
90
CLCL
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
8t
–150
–165
CLCL
CLCL
9t
105
140
AVDV
LLWL
3t
–50
–75
3t
CLCL
+50
40
45
0
CLCL
4t
AVWL
QVWX
WHQX
QVWH
RLAZ
WHLH
CLCL
t
t
–30
CLCL
CLCL
CLCL
–25
5
Data valid to WR high
RD low to address float
RD or WR high to ALE high
7t
–130
80
19, 20
19, 20
0
0
t
–25
t
+25
5
55
CLCL
CLCL
External Clock
t
t
t
t
22
22
22
22
High time
Low time
Rise time
Fall time
17
17
t
–t
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
CLCL CLCX
t
–t
CLCL CHCX
5
5
Shift Register
t
t
t
t
t
21
21
21
21
21
Serial port clock cycle time
12t
360
167
50
ns
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10t –133
CLCL
QVXH
XHQX
XHDX
XHDV
2t
CLCL
0
–80
0
10t
–133
167
CLCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.
4. Parts are guaranteed to operate down to 0 Hz.
29
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
P – PSEN
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
Q – Output data
R – RD signal
designations are:
A – Address
t – Time
V – Valid
C – Clock
W– WR signal
D – Input data
H – Logic level high
X – No longer a valid logic level
Z – Float
I
– Instruction (program memory contents)
Examples: t
= Time for address valid to ALE low.
=Time for ALE low to PSEN low.
AVLL
L – Logic level low, or ALE
t
LLPL
t
LHLL
ALE
t
t
AVLL
LLPL
t
PLPH
t
LLIV
t
PLIV
PSEN
t
LLAX
t
PXIZ
t
PLAZ
t
PXIX
A0–A7
INSTR IN
A0–A7
PORT 0
PORT 2
t
AVIV
A0–A15
A8–A15
SU00006
Figure 18. External Program Memory Read Cycle
ALE
PSEN
RD
t
WHLH
t
LLDV
t
t
LLWL
RLRH
t
RHDZ
t
LLAX
t
t
RLDV
AVLL
t
RLAZ
t
RHDX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA IN
A0–A7 FROM PCL
INSTR IN
t
AVWL
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00025
Figure 19. External Data Memory Read Cycle
30
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
ALE
t
WHLH
PSEN
t
t
WLWH
LLWL
WR
t
LLAX
t
t
WHQX
t
AVLL
QVWX
t
QVWH
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA OUT
A0–A7 FROM PCL
INSTR IN
t
AVWL
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00026
Figure 20. External Data Memory Write Cycle
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
t
XLXL
CLOCK
t
XHQX
t
QVXH
OUTPUT DATA
0
1
2
3
4
5
6
7
WRITE TO SBUF
t
XHDX
t
SET TI
VALID
XHDV
INPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
SU00027
Figure 21. Shift Register Mode Timing
V
–0.5
CC
0.7V
CC
CC
0.45V
0.2V
–0.1
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
SU00009
Figure 22. External Clock Drive
31
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
V
–0.5
CC
V
V
+0.1V
LOAD
V
V
–0.1V
TIMING
REFERENCE
POINTS
OH
0.2V
0.2V
+0.9
–0.1
CC
V
LOAD
CC
–0.1V
LOAD
+0.1V
OL
0.45V
NOTE:
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from
load voltage occurs, and begins to float when a 100mV change from the loaded
AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.
CC
IH
IL
V
/V level occurs. I /I ≥ ±20mA.
OH OL
OH OL
SU00717
SU00718
Figure 23. AC Testing Input/Output
Figure 24. Float Waveform
60
55
50
45
40
35
I
(mA)
CC
30
Icc MAX. ACTIVE MODE
25
20
15
Icc MAX ACTIVE MODE (TYP.)
Icc MAX. IDLE MODE
Icc IDLE MODE (TYP.)
10
5
0
4
8
12
16
20
24
28
32
36
Frequency at XTAL1 (MHz)
SU01495
Figure 25. I vs. FREQ
CC
Valid only within frequency specifications of the device under test
32
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
V
V
CC
CC
I
I
CC
CC
V
V
CC
CC
V
RST
V
V
CC
CC
CC
P0
EA
P0
EA
RST
(NC)
XTAL2
XTAL1
(NC)
XTAL2
XTAL1
CLOCK SIGNAL
CLOCK SIGNAL
V
V
SS
SS
SU00719
SU00720
Figure 26. I Test Condition, Active Mode
CC
Figure 27. I Test Condition, Idle Mode
CC
All other pins are disconnected
All other pins are disconnected
V
–0.5
CC
0.7V
CC
–0.1
0.45V
0.2V
CC
t
CHCX
t
t
t
CLCH
CHCL
CLCX
t
CLCL
SU00009
Figure 28. Clock Signal Waveform for I Tests in Active and Idle Modes
CC
t
= t
= 5ns
CHCL
CLCH
V
CC
CC
I
CC
V
CC
V
RST
P0
EA
(NC)
XTAL2
XTAL1
V
SS
SU00016
Figure 29. I Test Condition, Power Down Mode
CC
All other pins are disconnected. V = 2V to 5.5V
CC
33
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Security
The security feature protects against software piracy and prevents the contents of the FLASH from being read. The Security Lock bits are
located in FLASH. The 89C51/89C52/89C54/89C58 has 3 programmable security lock bits that will provide different levels of protection for the
on-chip code and data (see Table 8). Unlike the ROM and OTP versions, the security lock bits are independent. LB3 includes the security
protection of LB1.
Table 8.
1
SECURITY LOCK BITS
PROTECTION DESCRIPTION
Level
MOVC instructions executed from external program memory are disabled from fetching code bytes from
internal memory.
LB1
LB2
LB3
Program verification is disabled
External execution is disabled.
NOTE:
1. The security lock bits are independent.
34
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
35
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
36
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm
SOT389-1
37
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
REVISION HISTORY
Release date
CPCN
Modifications to previous release
2002 Jan 15
9397 750 09302
PROGRAMMING ALGORITHM MODIFIED due to process change (see device comparison table).
PQFP package replaced by LQFP package (dimensions see end of data sheet).
Lower power consumption due to process change.
DEVICE COMPARISON TABLE inserted (beginning of data sheet).
Selection Table for Flash devices updated and extended.
Ordering information table updated.
Erase and program cycles increased from 100 to 10,000.
1999 Oct 27
9397 750 06613
Combined data sheet for all four parts (89C51/52/54/58).
38
2002 Jan 15
Philips Semiconductors
Product data
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
Data sheet status
Product
status
Definitions
[1]
Data sheet status
[2]
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Koninklijke Philips Electronics N.V. 2002
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 01-02
9397 750 09302
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
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