P89C739ABB [NXP]
8-bit Flash microcontrollers; 8位闪存微控制器
| 型号： | P89C739ABB |
| 厂家： | 
NXP |
| 描述： | 8-bit Flash microcontrollers |
| 文件： | 总64页 (文件大小：363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
P89C738; P89C739
8-bit Flash microcontrollers
1998 Apr 07
Product specification
Supersedes data of 1997 Dec 15
File under Integrated Circuits, IC20
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
CONTENTS
15
RESET
15.1
16
Power-on reset
1
2
3
4
5
6
FEATURES
MULTIPLE PROGRAMMING ROM
(MTP-ROM)
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
16.1
16.2
16.3
Features
General description
Automatic programming and Automatic chip
erase
Command definitions
Silicon-ID-Read command
Set-up of Automatic chip erase and Automatic
erase commands
FUNCTIONAL DIAGRAM
PINNING INFORMATION
16.4
16.5
16.6
6.1
6.2
Pin configuration
Pin description
7
FUNCTIONAL DESCRIPTION
16.7
Set-up of the Automatic program and Program
commands
Reset command
Write operation status
Write operation
System considerations
Command programming/data programming
and erase operation
7.1
7.2
General
Instruction set execution
16.8
16.9
16.10
16.11
16.12
8
MEMORY ORGANIZATION
8.1
8.2
8.3
Program memory
Internal data memory
Addressing
9
INTERRUPT SYSTEM
17
SPECIAL FUNCTION REGISTERS
OVERVIEW
9.1
9.2
Interrupt Enable Register (IE)
Interrupt Priority Register (IP)
18
19
20
21
INSTRUCTION SET
10
TIMERS/COUNTERS
LIMITING VALUES
10.1
10.2
10.3
Timer 0 and Timer 1
Timer 2
Watchdog Timer (T3)
DC CHARACTERISTICS
AC CHARACTERISTICS
11
12
I/O FACILITIES
21.1
21.2
21.3
Serial Port characteristics
Timing waveforms
Timing symbol naming conventions
FULL DUPLEX SERIAL PORT (UART)
12.1
12.2
The Serial Port operating modes
Serial Port Control Register (SCON)
22
23
PACKAGE OUTLINES
SOLDERING
13
REDUCED POWER MODES
13.1
13.2
13.3
13.4
13.5
Idle mode
Power-down mode
Wake-up from Power-down mode
Status of external pins
Power Control Register (PCON)
23.1
23.2
23.3
Introduction
DIP
PLCC and QFP
24
25
DEFINITIONS
LIFE SUPPORT APPLICATIONS
14
OSCILLATOR CIRCUIT
1998 Apr 07
2
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
• Frequency range: 3.5 to 40 MHz
• ROM code protection.
1
FEATURES
• 80C51 CPU
• 64-kbyte on-chip Multiple Programming ROM
(MTP-ROM), expandable externally to 64 kbytes
program memory address space
2
GENERAL DESCRIPTION
The P89C738 and P89C739 (hereafter generally referred
to as P89C738 unless the P89C739 is specifically
mentioned) are 8 8-bit Flash microcontrollers
• 512-byte on-chip RAM, expandable externally to
64 kbytes data memory address space
manufactured in an advanced CMOS process and is a
derivative of the PCB80C51 microcontroller family. This
device provides architectural enhancements that make it
applicable in a variety of applications in general control
systems, especially in those systems which need a large
on-chip ROM and RAM capacity.
• P89C738 pin outs fully compatible to the standard
8051/8052
• 8-bit I/O ports for P89C738: 4 and P89C739: 6
• Full-duplex UART compatible with the standard 80C51
and the 8052
• Two standard 16-bit timers/event counters
The P89C738 contains a non-volatile 64-kbyte Multiple
Programming ROM (MTP-ROM) program memory, a
volatile 512 bytes read/write data memory, four 8-bit I/O
ports (six for the P89C739), two 16-bit timer/event
counters (identical to the timers of the 80C51), a 16-bit
timer (identical to the Timer 2 of the 8052), a multi-source
two-priority-level nested interrupt structure, one serial
interface (UART), a Watchdog Timer (T3), an on-chip
oscillator and timing circuits. For systems that require
extra capability, the P89C738 can be expanded using
standard TTL compatible memories and logic.
• An additional 16-bit timer (functionally equivalent to the
Timer 2 of the 8052)
• On-chip Watchdog Timer (T3)
• 6-source and 6-vector interrupt structure with 2 priority
levels
• Up to 3 external interrupt request inputs
• Two programmable power reduction modes: Idle and
Power-down
• Termination of Idle mode by any interrupt, external or
Watchdog Timer reset
The device also functions as an arithmetic processor
having facilities for both binary and BCD arithmetic plus
bit-handling capabilities. The P89C738 has the same
instruction set as the PCB80C51 which consists of over
100 instructions: 49 one-byte, 46 two-byte and
16 three-byte. With a 16 MHz crystal, 58% of the
instructions are executed in 750 ns and 40% in 1.5 µs.
Multiply and divide instructions require 3 µs.
• Wake-up from Power-down by external interrupt,
external or Watchdog Timer reset
• Packages,
– P89C738: DIP40, PLCC44 and QFP44
– P89C739: PLCC68 and QFP64
• Improved Electromagnetic Compatibility (EMC)
3
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER(1)
NAME
DESCRIPTION
plastic leaded chip carrier; 44 leads
VERSION
note 2
P89C738ABA
PLCC44
DIP40
P89C738ABP
P89C738ABB
P89C739ABA
P89C739ABB
plastic dual in-line package; 40 leads (600 mil)
plastic quad flat package; 44 leads
SOT129-1
note 2
QFP44
PLCC68
QFP64
plastic leaded chip carrier; 68 leads
note 2
plastic quad flat package; 64 leads (lead length 1.95 mm);
SOT319-1
body 14 × 20 × 2.7 mm; high stand-off height
Notes
1. Temperature and frequency range for all types: 0 to 70 °C and 3.5 to 40 MHz.
2. For more information on the package outline of this version, please contact the Philips Semiconductors Sales office.
1998 Apr 07
3
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g
(2)
(2)
(2)
(2)
V
V
SS
T0
T1
INT0
internal
INT1
DD
(2)
(2)
RXD
TXD
interrupts
PROGRAMMABLE
SERIAL PORT
FULL DUPLEX
UART
SYNCHRONOUS
SHIFT
XTAL1
XTAL2
TWO 16-BIT
TIMERS/
EVENT
COUNTERS
(T0, T1)
DATA
MEMORY
DATA
MEMORY
PROGRAM
MEMORY
CPU
256-byte
RAM
256-byte
AUX-RAM
64-kbyte
MTP-ROM
80C51 core
excluding
ROM/RAM
P89C738
P89C739
8-bit
internal bus
16-BIT
PARALLEL I/O PORTS
AND
EXTERNAL BUS
TIMER/
EVENT
COUNTER
(T2)
WATCHDOG
TIMER
16 kbytes BUS
EXPANSION CONTROL
(T3)
internal
reset
8
8
8
8
8
8
(2)
(1)
(1)
PSEN
ALE/WE
RD
WR
T2EX
T2
RST
(3)
(3)
P0 P1 P2 P3 P4
P5
(2)
EA
MGK189
(1) Alternative function for Port 1.
(2) Alternative function for Port 3.
(3) P4 and P5 are only available on the P89C738ABA and P89C739ABB (PLCC68 and QFP64).
Fig.1 Block diagram.
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
5
FUNCTIONAL DIAGRAM
XTAL1
XTAL2
ADDRESS
AND
DATA BUS
PORT 0
PORT 1
PORT 2
PORT 3
T2
T2EX
RST
EA
PSEN
ALE
P89C738
P89C739
ADDRESS
BUS
PORT 5
RXD
TXD
INT0
INT1
T0
secondary
functions
PORT 4
T1
WR
RD
V
V
SS
DD
MGK191
Fig.2 Functional diagram.
5
1998 Apr 07
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
6
PINNING INFORMATION
Pin configuration
6.1
7
8
39
38
37
36
P1.5
P1.6
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
9
P1.7
10
11
12
RST
P3.0/RXD/data
n.c.
35 EA/V
34 n.c.
PP
P89C738ABA
P3.1/TXD/clock 13
P3.2/INT0 14
P3.3/INT1 15
P3.4/T0 16
33 ALE/WE
32 PSEN
31 P2.7/A15
30 P2.6/A14
29 P2.5/A13
P3.5/T1 17
MGK185
Fig.3 Pin configuration for PLCC44 package; for more information on the version see Chapter 3.
1998 Apr 07
6
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
handbook, halfpage
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P1.0/T2
V
DD
P1.1/T2EX
P1.2
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
3
4
P1.3
5
P1.4
6
P1.5
7
P1.6
8
P1.7
9
RST
10
11
12
13
14
15
16
17
18
19
20
P3.0/RXD/data
P3.1/TXD/clock
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
EA/V
PP
P89C738ABP
ALE/WE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
XTAL1
V
SS
MGK184
Fig.4 Pin configuration for DIP40 package (SOT129-1).
7
1998 Apr 07
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
1
2
3
4
5
6
7
8
9
33 P0.4/AD4
P0.5/AD5
P1.5
P1.6
32
P1.7
31 P0.6/AD6
30 P0.7/AD7
RST
P3.0/RXD/data
n.c.
29 EA/V
PP
28 n.c.
P89C738ABB
P3.1/TXD/clock
P3.2/INT0
P3.3/INT1
27 ALE/WE
26 PSEN
25 P2.7/A15
24 P2.6/A14
23 P2.5/A13
P3.4/T0 10
P3.5/T1 11
MGK186
Fig.5 Pin configuration for QFP44 package; for more information on the version see Chapter 3.
1998 Apr 07
8
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
P5.5 10
P0.3/AD3 11
P0.2/AD2 12
P5.6 13
60 P5.0
59 P2.4/AD12
58 P2.3/AD11
57 P4.7
P0.1/AD1 14
P0.0/AD0 15
P5.7 16
56 P2.2/AD10
55 P2.1/AD9
54 P2.0/AD8
53 P4.6
V
17
18
DD
n.c.
n.c.
V
52
51
P89C739ABA
P1.0/T2 19
P4.0 20
SS
50 P4.5
P1.1/T2EX 21
P1.2 22
49 XTAL1
48 XTAL2
47 P3.7/RD
46 P4.4
P1.3 23
P4.1 24
P1.4 25
45 P3.6/WR
44 P4.3
P4.2 26
MGK187
Fig.6 Pin configuration for PLCC68 package; for more information on the version see Chapter 3.
1998 Apr 07
9
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
P0.4/AD4
P5.5
1
2
51 P2.5/AD13
50 P5.0
P0.3/AD3
P0.2/AD2
P5.6
3
49 P2.4/AD12
48 P2.3/AD11
47 P4.7
4
5
P0.1/AD1
P0.0/AD0
P5.7
6
46 P2.2/AD10
45 P2.1/AD9
44 P2.0/AD8
7
8
V
P4.6
n.c.
9
43
42
41
DD
V
P89C739ABB
10
SS
V
P1.0/T2 11
P4.0 12
SS
40 P4.5
P1.1/T2EX 13
P1.2 14
39 XTAL1
38 XTAL2
37 P3.7/RD
36 P4.4
P1.3 15
P4.1 16
P1.4 17
35 P3.6/WR
34 P4.3
P4.2 18
P1.5 19
33 P3.5/T1
MGK188
Fig.7 Pin configuration for QFP64 package (SOT319-1).
10
1998 Apr 07
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Table 1 Pin description for DIP40; QFP44; PLC44; QFP64 and PLCC68.
PIN(1)
SYMBOL
P1.0/T2
DESCRIPTION
PLCC68
19
QFP64
11
PLCC44
16
QFP44
DIP40
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Port 1: P1.0 to P1.7; 8-bit quasi-bidirectional I/O port. Port 1 can
sink/source one TTL (= 4 LSTTL) input. It can drive CMOS inputs
without external pull-ups.
P1.1/T2EX
P1.2
21
22
23
25
27
28
29
30
13
14
15
17
19
20
21
22
15
14
13
12
1
Port 1 alternative functions are: T2; Timer/event counter 2 external
event counter input (falling edge triggered). T2EX; Timer/event
counter 2 capture/reload trigger or external interrupt 2 input (falling
edge triggered).
P1.3
P1.4
P1.5
P1.6
2
P1.7
3
RST
4
10
Reset; a HIGH level on this pin for two machine cycles while the
oscillator is running, resets the device. An internal pull-down resistor
permits power-on reset using only a capacitor connected to VDD
.
After a Watchdog Timer overflow this pin is pulled HIGH while the
internal reset signal is active.
P3.0/RXD/data 34
P3.1/TXD/clock 39
26
29
30
31
32
33
35
37
5
11
13
14
15
16
17
18
19
10
11
12
13
14
15
16
17
Port 3: P3.0 to P3.7; 8-bit quasi-bidirectional I/O Port with internal
pull-ups. Port 3 can sink/source one TTL (= 4 LSTTL) input. It can
drive CMOS inputs without external pull-ups.
7
P3.2/INT0
P3.3/INT1
P3.4/T0
40
41
42
43
45
47
8
Port 3 alternative functions are: RXD/data; Serial Port data input
(asynchronous) or data input/output (synchronous).
9
10
11
44
43
TXD/clock; Serial Port data output (asynchronous) or clock output
(synchronous). INT0; External interrupt 0 or gate control input for
Timer/event counter 0. INT1; External interrupt 1 or gate control
input for Timer/event counter 1. T0; external input for Timer/event
counter 0. T1; external input for Timer/event counter 1.
WR; external data memory write strobe. RD; external data memory
read strobe.
P3.5/T1
P3.6WR
P3.7/RD
XTAL2
XTAL1
48
49
38
39
42
41
20
21
18
19
Crystal input 2: output of the inverting amplifier that forms the
oscillator. This pin left open-circuit when an external oscillator clock
is used (see Figs 18 and 20).
Crystal input 1: input to the inverting amplifier that forms the
oscillator, and input to the internal clock generator. Receives the
external oscillator clock signal when an external oscillator is used
(see Figs 18 and 20).
VSS
51
41
40
22
20
Ground: circuit ground potential.
PIN(1)
SYMBOL
DESCRIPTION
PLCC68
QFP64
PLCC44
QFP44
DIP40
P2.0/A8 to
P2.2/A10
54 to 56
44 to 46
38 to 34
24 to 31
21 to 28
Port 2: P2.0 to P2.7; 8-bit quasi-bidirectional I/O Port with internal
pull-ups. Port 2 can sink/source one TTL (= 4 LSTTL) input. It can
drive CMOS inputs without external pull-ups.
P2.3/A11 to
P2.4/A12
58 to 59
48 to 49
Port 2 alternative functions are: A8 to A15; during access to
external memories (RAM/ROM) that use 16-bit addresses (MOVX
@DPTR) Port 2 emits the high-order address byte (A8 to A15).
P2.5/A13 to
P2.7/A15
61, 64
and 65
51, 54
and 55
23 to 25
26
PSEN
67
56
32
29
Program Store Enable output: read strobe to the external program
memory via Port 0 and Port 2. It is activated twice each machine
cycle during fetches from external program memory.
When executing out of external program memory two activations of
PSEN are skipped during each access to external data memory.
PSEN is not activated (remains HIGH) during no fetches from
external program memory. PSEN can sink/source 8 LSTTL inputs. It
can drive CMOS inputs without external pull-ups.
ALE/WE(2)
68
57
59
27
29
33
30
Address Latch Enable output: latches the lower byte of the
address during access to external memory in normal operation. It is
activated every six oscillator periods except during an external data
memory access. ALE can sink/source 8 LSTTL inputs. It can drive
CMOS inputs without an external pull-up.
WE: Write Enable.
EA/VPP
2
35
31
External Access input: when during reset, EA is held at a TTL
HIGH level, the CPU executes from the internal program ROM.
When EA is held at a TTL LOW level during reset, the CPU executes
out of external program memory via Port 0 and Port 2. EA is not
allowed to float. EA is latched during reset and don’t care after reset.
VPP: programming supply voltage.
P0.7/AD7 to
P0.4/AD4
3, 5, 6
and 9
60, 61, 62 30 to 33
and 1
36 to 43
32 to 39
Port 0: P0.7 to P0.0; 8-bit open-drain bidirectional I/O port. It is also
the multiplexed low-order address and data bus during accesses to
external memory: AD0 to AD7. During these accesses internal
pull-ups are activated. Port 0 can sink/source 8 LSTTL inputs.
P0.3/AD3 to
P0.2/AD2
11 to 12
14 to 15
17
3 to 4
6 to 7
9
22 to 21
20 to 19
18
P0.1/AD1 to
P0.0/AD0
VDD
44
40
Power supply (+5 V) pin for normal operation, Idle mode and
Power-down mode.
PIN(1)
SYMBOL
DESCRIPTION
PLCC68
QFP64
PLCC44
QFP44
n.a.
DIP40
n.a.
P4.0 to P4.7
20, 24,
26, 44,
46, 50, 53 36, 40, 43
12, 16,
18, 34,
n.a.(3)
Port 4: P4.0 to P4.7; 8-bit quasi-bidirectional I/O port with internal
pull-ups. Port 4 can sink/source 4 LSTTL inputs. It can drive CMOS
inputs without external pull-ups.
and 57
and 47
P5.0 to P5.7
n.c.
60, 62,
63, 7, 8,
10, 13
50, 52,
53, 63,
64, 2, 5
and 8
n.a.
n.a.
n.a.
Port 5: P5.0 to P5.7; 8-bit quasi-bidirectional I/O port with internal
pull-ups. Port 5 can sink/source 4 LSTTL inputs. It can drive CMOS
inputs without external pull-ups.
and 16
1, 4, 18,
31, 32,
33, 35,
23, 24,
25, 27,
28, 42
6, 17, 28 1, 12, 23 n.a.
and 39 and 34
Not connected.
36, 37, 38 and 58
52 and 66
Notes
1. To avoid a ‘latch-up’ effect at power-on, the voltage on any pin (at any time) must not be higher than VDD + 0.5 V or lower than VSS − 0.5 V
respectively.
2. To prohibit the toggling of the ALE/WE pin (RFI noise reduction) the bit RFI in the PCON register (PCON.5) must be set by software. This bit is
cleared on reset and can be cleared by software. When set, ALE/WE pin will be pulled down internally, switching an external address latch to a
quiet state. The MOVX instruction will still toggle ALE/WE as a normal MOVX. ALE/WE will retain its normal HIGH value during Idle mode and a
LOW value during Power-down mode while in the ‘RFI’ mode. Additionally during internal access (EA = 1) ALE/WE will toggle normally when the
address exceeds the internal program memory size. During external access (EA = 0) ALE/WE will always toggle normally, whether the flag ‘RFI’ is
set or not.
3. n.a. = not applicable.
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
The P89C738 has two software selectable modes of
reduced activity for further power reduction: Idle and
Power-down. The Idle mode freezes the CPU while
allowing the RAM, timers, serial ports and interrupt system
to continue functioning. The Power-down mode saves the
RAM contents but freezes the oscillator causing all other
chip functions to be inoperative except the Watchdog
Timer if it is enabled. The Power-down mode can be
terminated by an external reset, a Watchdog Timer
overflow and in addition, by either of the two external
interrupts.
7
FUNCTIONAL DESCRIPTION
This chapter gives a brief overview of the device.
Detailed functional descriptions are given in the following
chapters:
Chapter 8 “Memory organization”
Chapter 9 “Interrupt system”
Chapter 10 “Timers/counters”
Chapter 11 “I/O facilities”
Chapter 12 “Full duplex Serial Port (UART)”
Chapter 13 “Reduced power modes”
Chapter 14 “Oscillator circuit”
7.2
Instruction set execution
The P89C738 uses the powerful instruction set of the
80C51. Additional Special Function Registers (SFRs) are
incorporated to control the on-chip peripherals.
Chapter 15 “Reset”
Chapter 16 “Multiple Programming ROM (MTP-ROM)”.
The instruction set consists of 49 single-byte, 46 two-byte
and 16 three-byte instructions. When using a 16 MHz
oscillator, 64 instructions execute in 750 ns and
45 instructions execute in 1.5 µs. Multiply and divide
instructions execute in 3 µs (see Chapter 18).
7.1
General
The P89C738 is a stand-alone high-performance
microcontroller designed for use in real time applications
such as instrumentation, industrial control and medium to
high-end consumer applications.
In addition to the 80C51 standard functions, the device
provides a number of dedicated hardware functions for
these applications. The P89C738 is a control-oriented
CPU with on-chip Program and data memory. It can
execute programs with internal or external program
memory up to 64 kbytes. It can also access up to
64 kbytes of external data memory. For systems requiring
extra capability, the P89C738 can be expanded using
standard memories and peripherals.
1998 Apr 07
14
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
8
MEMORY ORGANIZATION
8.2
Internal data memory
The Central Processing Unit (CPU) manipulates operands
in three memory spaces; these are the 64 kbytes external
data memory (of which the lower 256 bytes reside in the
internal AUX-RAM), 512 bytes internal data memory
(consisting of 256 bytes standard RAM and 256 bytes
AUX-RAM) and the 64 kbytes internal and external
program memory.
The internal data memory is divided into three physically
separated parts: 256 bytes of RAM, 256 bytes of
AUX-RAM, and a 128 bytes Special Function Registers
(SFRs) area. These parts can be addressed as follows
(see Fig.9 and Table 3):
• RAM locations 0 to 127 can be addressed directly and
indirectly as in the 80C51. Address pointers are R0 and
R1 of the selected register bank.
8.1
Program memory
• RAM locations 128 to 255 can only be addressed
indirectly. Address pointers are R0 and R1 of the
selected register bank.
The program memory address space of the P89C738
comprises an internal and an external memory portion.
The P89C738 has 64 kbytes of program memory on-chip.
The program memory can also be externally addressed up
to 64 kbytes. If the EA pin is held HIGH, the P89C738
executes out of the internal program memory. If EA pin is
held LOW, the P89C738 fetches all instructions from the
external program memory. Figure 8 illustrates the program
memory address space.
• AUX-RAM locations 0 to 255 are indirectly addressable
as the external data memory locations 0 to 255 with the
MOVX instructions. Address pointers are R0 and R1 of
the selected register bank and DPTR. When executing
from internal program memory, an access to AUX-RAM
0 to 255 will not affect the ports Port 0, Port 2,
P3.6 and P3.7.
The security bit is always set in the P89C738 and
P89C739 to protect the ROM code. Table 2 lists the
access to the internal and external program memory by the
MOVC instructions when the security bit has been set to a
logic 1. If the security bit has been set to a logic 0 there are
no restrictions for the MOVC instructions.
• The SFRs can only be addressed directly in the address
range from 128 to 255.
An access to external data memory locations higher than
255 will be performed with the MOVX DPTR instructions in
the same way as in the 80C51 structure, i.e. with Port 0
and Port 2 as data/address bus and P3.6 and P3.7 as write
and read timing signals. Note that the external data
memory cannot be accessed with R0 and R1 as address
pointer.
Table 2 Internal and external program memory access
PROGRAM MEMORY ACCESS
MOVC
INSTRUCTION
Figure 9 shows the internal and external data memory
address space. Chapter 17 shows the Special Function
Registers overview. Four 8-bit register banks occupy
locations 0 through 31 in the lower RAM area. Only one of
these banks may be enabled at a time. The next 16 bytes,
locations 32 through 47, contain 128 directly addressable
bit locations.
INTERNAL
EXTERNAL
MOVC in internal
program memory
YES
YES
MOVC in external
program memory
NO
YES
The stack can be located anywhere in the internal
256-byte RAM. The stack depth is only limited by the
available internal RAM space of 256 bytes. All registers
except the Program Counter and the four 8-bit register
banks reside in the SFR address space.
handbook, halfp6a5g5e35
INTERNAL
(EA = 1)
EXTERNAL
(EA = 0)
Table 3 Internal data memory access
0
MEMORY
LOCATION
ADDRESS MODE
MGK190
RAM
0 to 127
128 to 255
128 to 255
0 to 255
direct and indirect
indirect only
PROGRAM MEMORY
SFR
direct only
Fig.8 Program memory address space.
AUX-RAM
indirect only with MOVX
1998 Apr 07
15
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
64kbytes
64 kbytes
64 kbytes
INTERNAL
(EA = 1)
EXTERNAL
(EA = 0)
OVERLAPPED SPACE
256
255
127
0
SFRs
AUXILIARY
RAM
INDIRECT ONLY
DIRECT AND
INDIRECT
0
MAIN RAM
EXTERNAL
DATA MEMORY
PROGRAM MEMORY
INTERNAL DATA MEMORY
MBK524
Fig.9 Internal and external data memory address space.
• 512 bytes of internal RAM through Direct or
Register-Indirect addressing. Bytes 0 to 127 of internal
RAM may be addressed directly/indirectly. Bytes
128 to 255 of internal RAM share their address location
with the SFRs and so may only be addressed indirectly
as data RAM. Bytes 0 to 255 of AUX-RAM can only be
addressed indirectly via MOVX.
8.3
Addressing
The P89C738 has five modes for addressing:
• Register
• Direct
• Register-Indirect
• Immediate
• SFR through Direct addressing at address locations
128 to 255
• Base-Register plus Index-Register-Indirect.
The first three methods can be used for addressing
destination operands. Most instructions have a
‘destination/source’ field that specifies the data type,
addressing methods and operands involved.
For operations other than MOVs, the destination operand
is also a source operand.
• External data memory through Register-Indirect
addressing
• Program memory look-up tables through Base-Register
plus Index-Register-Indirect addressing.
Access to memory addresses is as follows:
• Register in one of the four 8-bit register banks through
Register, Direct or Register-Indirect addressing
1998 Apr 07
16
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
9
INTERRUPT SYSTEM
Table 4 Interrupt vectors
The P89C738 contains the same interrupt structure as the
PCB80C51BH, but with a six-source interrupt structure
with two priority levels (see Fig.10).
PRIORITY
WITHIN LEVEL
VECTOR
ADDRESS
SOURCE
IE0
1 (highest)
0003H
000BH
0013H
001BH
0023H
002BH
The external interrupts INT0 and INT1 can each be either
level-activated or transition-activated, depending on bits
IT0 and IT1 in SFR TCON. The flags that actually generate
these interrupts are bits IE0 and IE1 in TCON. When an
external interrupt is generated, the corresponding request
flag is cleared by the hardware when the service routine is
vectored to, only if the interrupt was transition-activated.
If the interrupt was level-activated the external source has
to hold the request active until the requested interrupt is
actually generated. Then it has to deactivate the request
before the interrupt service routine is completed, or else
another interrupt will be generated.
TF0
2
IE1
3
TF1
4
5
RI + TI
TF2 + EXF2
6 (lowest)
The Timer 0 and Timer 1 interrupts are generated by TF0
and TF1, which are set by a roll-over in their respective
timer/counter register (except for Timer 0 in Mode 3 of the
serial interface). When a timer interrupt is generated, the
flag that generated it is cleared by the on-chip hardware
when the service routine is vectored to.
handbook, halfpage
INT0
0
1
IT0
IE0
The Serial Port interrupt is generated by the logical ‘OR’ of
RI and TI. Neither of these flags is cleared by hardware.
The service routine will normally have to determine
whether it was RI or TI that generated the interrupt, and the
bit will have to be cleared by software.
TF0
0
1
interrupt
sources
INT1
IT1
IE1
The Timer 2 interrupt is generated by the logical OR of TF2
and EXF2. Neither of these flags is cleared by hardware.
In fact the service routine may have to determine whether
it was TF2 or EXF2 that generated the interrupt, and the bit
will have to be cleared by software.
TF1
TI
RI
TF2
An additional (third) external interrupt is available, if
Timer 2 is not used as timer/counter or if Timer 2 is used
in the baud rate generator mode. That external interrupt 2
is falling-edge triggered. It shares the Timer 2 interrupt
vector, interrupt enable and interrupt priority bits. If bit
EXEN2 = 1 (T2CON.3), a HIGH-to-LOW transition at pin
P1.1/T2EX sets the interrupt request flag EXF2
(T2CON.6) and can be used to generate an external
interrupt.
EXF2
MGK193
Fig.10 P89C738/P89C739 interrupt sources.
The interrupt vectors are listed in Table 4.
1998 Apr 07
17
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
9.1
Interrupt Enable Register (IE)
Table 5 Interrupt Enable Register (SFR address A8H)
7
6
5
4
3
2
1
0
EA
−
ET2
ES
ET1
EX1
ET0
EX0
Table 6 Description of IE bits
BIT
SYMBOL
DESCRIPTION
7
EA
General enable/disable control. If EA = 0, no interrupt is enabled. If EA = 1, any
individually enabled interrupt will be accepted.
6
5
4
3
2
1
0
−
reserved
ET2
ES
enable Timer 2 interrupt
enable Serial Port interrupt
enable Timer 1 interrupt
enable external interrupt 1
enable Timer 0 interrupt
enable external interrupt 0
ET1
EX1
ET0
EX0
9.2
Interrupt Priority Register (IP)
Table 7 Interrupt Priority Register (SFR address B8H)
7
6
5
4
3
2
1
0
−
−
PT2
PS
PT1
PX1
PT0
PX0
Table 8 Description of IP bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
−
reserved
reserved
−
PT2
PS
Timer 2 interrupt priority level
Serial Port interrupt priority level
Timer 1 interrupt priority level
external interrupt 1 priority level
Timer 0 interrupt priority level
external interrupt 0 priority level
PT1
PX1
PT0
PX0
1998 Apr 07
18
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
Timer 0 and Timer 1 can be programmed independently to
operate in one of four modes:
10 TIMERS/COUNTERS
The P89C738 contains three 16-bit timer/counters:
Timer 0, Timer 1 and Timer 2; and one 8-bit timer, the
Watchdog Timer (T3). Timer 0, Timer 1 and Timer 2 may
be programmed to carry out the following functions:
Mode 0 8-bit timer/counter with divide-by-32 prescaler
Mode 1 16-bit timer/counter
Mode 2 8-bit timer/counter with automatic reload
• Measure time intervals and pulse durations
• Count events
Mode 3 Timer 0: one 8-bit timer/counter and one 8-bit
timer. Timer 1: stopped.
• Generate interrupt requests.
When Timer 0 is in Mode 3, Timer 1 can be programmed
to operate in Modes 0, 1 or 2 but cannot set an interrupt
request flag and generate an interrupt. However, the
overflow from Timer 1 can be used to pulse the Serial Port
transmission-rate generator. With a 16 MHz crystal, the
counting frequency of these timer/counters is as follows:
10.1 Timer 0 and Timer 1
Timers 0 and 1 each have a control bit in SFR TMOD that
selects the timer or counter function of the corresponding
timer. In the timer function, the register is incremented
every machine cycle. Thus, one can think of it as counting
machine cycles. Since a machine cycle consists
of 12 oscillator periods, the count rate is 1⁄12 of the
oscillator frequency.
• In the timer function, the timer is incremented at a
frequency of 1.33 MHz (1⁄12 × oscillator frequency)
• In the counter function, the frequency handling range for
external inputs is 0 to 0.66 MHz.
In the counter function, the register is incremented in
response to a HIGH-to-LOW transition at the
Both internal and external inputs can be gated to the timer
by a second external source for directly measuring pulse
duration.
corresponding external input pin, T0 or T1. In this function,
the external input is sampled during S5P2 of every
machine cycle. When the samples show a HIGH in one
cycle and a LOW in the next cycle, the counter is
incremented. Thus, it takes two machine cycles
(24 oscillator periods) to recognize a HIGH-to-LOW
transition. There are no restrictions on the duty cycle of the
external input signal, but to ensure that a given level is
sampled at least once before it changes, it should be held
for at least one full machine cycle.
The timers are started and stopped under software control.
Each one sets its interrupt request flag when it overflows
from all logic 1's to all logic 0's (respectively, the automatic
reload value), with the exception of Mode 3 as previously
described.
10.1.1 Timer/Counter Mode Control Register (TMOD)
Table 9 Timer/Counter Mode Control Register (SFR address 89H)
7
6
5
4
3
2
1
0
GATE
C/T
M1
M0
GATE
C/T
M1
M0
Table 10 Description of TMOD bits for Timer 1 and Timer 0
Timer 0: bit TMOD.0 to TMOD.3; Timer 1: bit TMOD.4 to TMOD.7; n = 0, 1.
BIT
SYMBOL
DESCRIPTION
7 and 3
GATE
Gating control. When set Timer/counter ‘n’ is enabled only when INTn pin is HIGH and
control bit TRn (TR1 or TR0) is set. When cleared Timer n is enabled whenever TRn
control bit is set.
6 and 2
C/T
Timer or Counter Selector. Cleared for Timer operation; input from internal system
clock. Set for Counter operation; input from pin Tn (T1 or T0).
5 and 1
4 and 0
M1
M0
Timer 0, Timer 1 mode select; see Table 11.
1998 Apr 07
19
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
Table 11 Timer 0; Timer 1 mode select
M1
M0
OPERATING
Timer TL0; TL1 serves as 5-bit prescaler.
0
0
1
0
1
0
16-bit Timer/Counter TH0; TH1 and TL0; TL1 are cascaded; there is no prescaler.
8-bit auto-reload Timer/Counter TH0; TH1 holds a value which is to be reloaded into
TL0; TL1 each time it overflows.
1
1
1
1
Timer 0: TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits.
TH0 is an 8-bit timer only controlled by Timer 1 control bits.
Timer 1: Timer/Counter 1 stopped.
10.1.2 Timer/Counter Control Register (TCON)
Table 12 Timer/Counter Control Register (SFR address 88H)
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Table 13 Description of TCON bits
BIT
SYMBOL
DESCRIPTION
7 and 5
TF1 and TF0 Timer 1 and Timer 0 overflow flags. Set by hardware on Timer/Counter overflow.
Cleared by hardware when processor vectors to interrupt routine.
6 and 4
3 and 1
2 and 0
TR1 and TR0 Timer 1 and Timer 0 run control bits. Set/cleared by software to turn Timer/Counter
on/off.
IE1 and IE0 Interrupt 1 and Interrupt 0 edge flags. Set by hardware when external interrupt edge
detected. Cleared when interrupt processed.
IT1 and IT0 Interrupt 1 and Interrupt 0 type control bits. Set/cleared by software to specify falling
edge/LOW level triggered external interrupts.
1998 Apr 07
20
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
10.2 Timer 2
Timer 2 is functionally similar to the Timer 2 of the 8052AH. Timer 2 is a 16-bit timer/counter which is formed by two
SFRs, TL2 and TH2. Another pair of SFRs, RCAP2L and RCAP2H, form a 16-bit capture register or a 16-bit reload
register.
Like Timer 0 and Timer 1, Timer 2 can operate either as timer or as event counter. This is selected by bit C/T2 in SFR
T2CON. The timer has three operating modes: ‘capture’, ‘autoload’ and ‘baud rate generator’, which are selected by bits
in SFR T2CON (see Tables 14 and 15).
10.2.1 TIMER/COUNTER 2 CONTROL REGISTER (T2CON)
Table 14 Timer/Counter 2 Control Register (SFR address C8H)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Table 15 Description of T2CON bits
BIT
SYMBOL
DESCRIPTION
7
TF2
Timer 2 overflow flag. Set by a Timer 2 overflow and must be cleared by software. TF2
will not be set when either RCLK = 1 or TCLK = 1. When Timer 2 interrupt is enabled,
TF2 = 1 will cause the CPU to vector to Timer 2 interrupt routine.
6
5
4
3
EXF2
RCLK
TCLK
Timer 2 external flag. Set when either a capture or reload is caused by a negative
transition on T2EX and when EXEN2 = 1. When Timer T2 interrupt is enabled,
EXF2 = 1 will cause the CPU to vector to Timer 2 interrupt routine.
Receive clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses
for its receive clock in Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used
for the receive clock.
Transmit clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses
for its transmit clock in Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used
for the transmit clock.
EXEN2
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result
of a negative transition on T2EX, if Timer 2 is not being used to clock the Serial Port.
EXEN2 = 0, causes Timer 2 to ignore events at T2EX.
2
1
TR2
Timer 2 start/stop control. TR2 = 1 starts Timer 2; TR2 = 0 stops Timer 2.
C/T2
Timer 2 timer or counter select. C/T2 = 0 selects the internal timer with a clock
frequency of 1⁄12fclk. C/T2 = 1 selects the external event counter; falling edge triggered.
0
CP/RL2
Capture/reload flag. When set, capture will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, reloads will occur upon either Timer 2 overflows or negative
transitions at T2EX if EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored
and the timer is forced to reload upon overflow.
Table 16 Timer 2 operating modes
X = don’t care.
RCLK
TCLK
CP/RL2
TR2
1
MODE
0
0
1
X
0
0
1
X
0
1
16-bit automatic reload
16-bit capture
baud rate generator
off
1
X
X
1
0
1998 Apr 07
21
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
10.2.2 CAPTURE MODE
The baud rate generation by Timer 1 and/or Timer 2 is
used for the Serial Port in Mode 1 and Mode 3. The baud
rate generation mode is similar to the automatic reload
mode, in that a roll-over in TH2 causes the Timer 2
registers to be reloaded with the 16-bit value in registers
RCAP2L and RCAP2H, which are preset by software.
The baud rates for the Serial Port in Modes 1 and 3 are
determined by Timer 2 overflow rate as follows:
In the capture mode (see Fig.11) there are two options
which are selected by bit EXEN2 in T2CON. If EXEN2 = 0,
then Timer 2 is a 16-bit timer/counter which on overflow
sets bit TF2 (Timer 2 overflow bit). TF2 can be used to
generate an interrupt. If EXEN2 = 1, Timer 2 operates as
above, with the added feature that a HIGH-to-LOW
transition at the external input T2EX causes the current
value in Timer 2 registers (TL2 and TH2) to be captured
into registers RCAP2L and RCAP2H, respectively. The
HIGH-to-LOW transition of T2EX also causes bit EXF2 in
T2CON to be set. EXF2 can be used to generate an
interrupt.
Timer 2 overflow rate
Baud rate =
-------------------------------------------------------
16
Timer 2 can be configured for either ‘timer’ or ‘counter’
operation. Normally, as a timer it would increment every
machine cycle (thus at 1⁄12fclk). As a baud rate generator,
however it increments every state time (thus at 1⁄2fclk).
10.2.3 AUTOMATIC RELOAD MODE
The baud rate is given by the formula:
fclk
In the automatic reload mode (see Fig.12) there are two
options which are selected by bit EXEN2 in SFR T2CON.
If EXEN2 = 0, then a Timer 2 overflow sets TF2 and
causes the Timer 2 registers to be reloaded with the 16-bit
value in registers RCAP2L and RCAP2H, which are preset
by software.
Baud rate =
----------------------------------------------------------------------------------------------------
32 × [65536 – (RCAP2H, RCAP2L) ]
In this mode an overflow of Timer 2 does not set TF2.
If EXEN2 = 1, a HIGH-to-LOW transition at pin T2EX sets
EXF2 and can be used to generate an interrupt.
If EXEN2 = 1, Timer 2 operates as above, with the added
feature that a HIGH-to-LOW transition at the external input
T2EX triggers the 16-bit reload and sets EXF2.
10.2.4 BAUD RATE GENERATOR MODE
The baud rate generator mode (see Fig.13) is selected by
RCLK = 1 and/or TCLK = 1 in SFR T2CON. Overflows of
either Timer 2 or Timer 1 can be used independently for
generating baud rates for transmit and receive.
OSC
12
C/T2 = 0
C/T2 = 1
TL2
(8 BITS)
TH2
(8 BITS)
TF2
control
TR2
T2 PIN
Timer 2
interrupt
capture
transition
detector
RCAP2L
RCAP2H
T2EX PIN
EXF2
MLA608
control
EXEN2
Fig.11 Timer 2 in capture mode.
1998 Apr 07
22
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
OSC
12
C/T2 = 0
C/T2 = 1
TL2
(8 BITS)
TH2
(8 BITS)
TF2
control
TR2
T2 PIN
Timer 2
interrupt
reload
RCAP2L
RCAP2H
transition
detector
T2EX PIN
EXF2
MLA609
control
EXEN2
Fig.12 Timer 2 in automatic reload mode.
timer 1
overflow
÷2
(note: oscillator frequency
is divided by 2 not by 12)
0
1
SMOD
OSC
÷2
C/T2 = 0
1
1
0
0
TL2
(8 BITS)
TH2
(8 BITS)
RCLK
÷16
C/T2 = 1
T2 pin
control
TR2
RX clock
reload
RCAP2L
EXF2
RCAP2H
transition
detector
TCLK
÷16
timer 2
interrupt
T2EX pin
TX clock
control
EXEN2
MGK192
Fig.13 Timer 2 in baud rate generator mode.
23
1998 Apr 07
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
10.3 Watchdog Timer (T3)
This time interval is determined by the 8-bit reload value
that is written into register T3:
The Watchdog Timer (see Fig.14), consists of an 11-bit
prescaler and an 8-bit timer formed by SFR T3. The timer
is incremented every 1.5 ms, which is derived from the
system clock frequency of 16 MHz by the following
[T3] × 12 × 2048
Watchdog time interval =
----------------------------------------------
fclk
The Watchdog Timer can only be reloaded if the condition
flag WLE (PCON.4) has been previously set HIGH by
software. At the moment the counter is loaded WLE is
automatically cleared.
fclk
formula: ftimer
=
--------------------------------
(12 × 2048)
The 8-bit timer increments every 12 × 2048 cycles of the
on-chip oscillator. When a timer overflow occurs, the
microcontroller is reset. The internal reset signal is not
inhibited when the external RST pin is kept LOW, e.g. by
an external reset circuit. The reset signal drives Ports 1, 2,
3, 4 and 5 outputs into the HIGH state and Port 0 into
high-impedance, no matter whether the clock oscillator is
running or not.
In the Idle mode the Watchdog Timer and reset circuitry
remain active.
The Watchdog Timer is controlled by the Watchdog enable
signal EW (EBTCON.1). A HIGH level enables the
Watchdog Timer and disables the Power-down mode.
A LOW level disables the Watchdog Timer and enables
the Power-down mode.
To prevent a system reset the timer must be reloaded in
time by the application software. If the processor suffers a
hardware/software malfunction, the software will fail to
reload the timer. This failure will result in a reset upon
overflow thus preventing the processor running out of
control.
INTERNAL BUS
(1)
to reset circuitry
PRESCALER
11-BIT
1/12 f
clk
TIMER T3 (8-BIT)
CLEAR
LOAD
LOADEN
CLEAR
write
T3
WLE
PD
LOADEN
PCON.4
PCON.1
EW
INTERNAL BUS
MBH081
(1) See Fig.21.
Fig.14 Watchdog Timer block diagram.
1998 Apr 07
24
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
Port 2 Provides the high-order address bus when
expanding the P89C738 with external program
memory and/or external data memory.
11 I/O FACILITIES
The P89C738 has 4 and P89C739 has 6 8-bit ports.
Ports 0 to 3 are the same as in the 80C51, with the
exception of the additional function of Port 1. Port lines
P1.0 and P1.1 may be used as inputs for Timer 2, P1.1
may also be used as an additional (third) external interrupt
request input.
Port 3 Pins can be configured individually to provide:
external interrupt request inputs (external
interrupt 0/1); external inputs for Timer/counter 0
and Timer/counter 1; Serial Port receiver input and
transmitter output control signals to read and write
external data memory.
Ports 0, 1, 2, and 3 perform the following alternative
functions:
Bits which are not used for the alternative functions may be
used as normal bidirectional I/O pins. The generation or
use of a Port 1 or Port 3 pin as an alternative function is
carried out automatically by the P89C738 provided the
associated SFR bit is HIGH. Otherwise the port pin is held
at a logical LOW level.
Port 0 Provides the multiplexed low-order address and
data bus used for expanding the P89C738 with
standard memories and peripherals.
Port 1 Pins can be configured individually to provide:
external interrupt request input (external
interrupt 2); external inputs for Timer/counter 2.
strong pull-up
V
DD
2 oscillator
periods
p2
p3
p1
n
I/O PIN
Q
from port latch
I1
input data
INPUT
BUFFER
MGG025
read port pin
Fig.15 I/O buffers in the P89C738; P89C739 (Ports 1, 2, 3, 4 and 5).
1998 Apr 07
25
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
Mode 2 11 bits are transmitted (through TXD) or received
(through RXD): start bit (logic 0), 8 data bits (LSB
first), a programmable 9th data bit, and a stop bit
(logic 1). On transmit, the 9th data bit (TB8 in
SFR SCON) can be assigned the value of a
logic 0 or logic 1. For example, the parity bit (P in
the PSW) could be moved into TB8. On receive,
the 9th data bit goes into RB8 in SFR SCON,
while the stop bit is ignored. The baud rate is
programmable to either 1⁄32 or 1⁄64fclk.
12 FULL DUPLEX SERIAL PORT (UART)
The serial port is functionally similar to the implementation
in the 8052AH, with the possibility of two different baud
rates for receive and transmit with Timer 1 and Timer 2 as
baud rate generators. It is full duplex, meaning it can
receive and transmit simultaneously. It is also
receive-buffered, meaning it can commence reception of a
second byte before a previously received byte has been
read from the receive register. However, if the first byte still
has not been read by the time the reception of the second
byte is complete, one of the bytes will be lost. The Serial
Port receive and transmit registers are both accessed as
SFR SBUF. Writing to SBUF loads the transmit register,
and reading SBUF accesses the physically separate
receive register.
Mode 3 11 bits are transmitted (through TXD) or received
(through RXD): a start bit (logic 0), 8 data bits
(LSB first), a programmable 9th data bit and a
stop bit (logic 1). In fact, Mode 3 is the same as
Mode 2 in all respects except the baud rate.
The baud rate in Mode 3 is variable.
12.1 The Serial Port operating modes
In all four modes, transmission is initiated by any
instruction that uses SFR SBUF as a destination register.
In Mode 0, reception is initiated by the condition RI = 0 and
REN = 1. Reception is initiated by incoming start bit if
REN = 1 in the other modes.
The serial port can operate in one of 4 modes:
Mode 0 Serial data enters and exits through RXD.
TXD outputs the shift clock. Eight bits are
transmitted/received (LSB first). The baud rate is
fixed at 1⁄12fclk.
Mode 1 10 bits are transmitted (through TXD) or received
(through RXD): a start bit (logic 0), 8 data bits
(LSB first), and a stop bit (logic 1). On receive,
the stop bit goes into RB8 in SFR SCON.
The baud rate is variable.
1998 Apr 07
26
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
12.2 Serial Port Control Register (SCON)
Table 17 Serial Port Control Register (SFR address 98H)
7
6
5
4
3
2
1
0
SMO
SM1
SM2
REN
TB8
RB8
TI
RI
Table 18 Description of SCON bits
BIT
SYMBOL
DESCRIPTION
These bits are used to select the Serial Port mode; see Table 19.
7
6
5
SM0
SM1
SM2
Enables the multiprocessor communication feature in Modes 2 and 3. In these
modes, if SM2 = 1, then RI will not be activated if the received 9th data bit (RB8) is a
logic 0. In Mode 1, if SM2 = 1, then RI will not be activated unless a valid stop bit was
received. In Mode 0, SM2 should be a logic 0.
4
3
REN
TB8
Enables serial reception. Set and cleared by software as required.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or cleared by software
as required.
2
1
RB8
TI
In Modes 2 and 3, RB8 is the 9th data bit received. In Mode 1, if SM2 = 0 then RB8 is
the stop bit that was received. In Mode 0, RB8 is not used.
Transmit Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at
the beginning of the stop bit time in the other modes, in any serial transmission. TI must
be cleared by software.
0
RI
Receive Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or
halfway through the stop bit time in the other modes, in any serial transmission (except:
see SM2). RI must be cleared by software.
Table 19 Selection of the Serial Port modes
SMO
SM1
MODE
DESCRIPTION
BAUD RATE
0
0
1
1
0
1
0
1
Mode 0
Mode 1
Mode 2
Mode 3
shift register
8-bit UART
9-bit UART
9-bit UART
1⁄12fclk
variable
32 or 1⁄64fclk
1
⁄
variable
1998 Apr 07
27
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
13 REDUCED POWER MODES
13.2 Power-down mode
Two software selectable modes of reduced power
consumption are implemented: Idle and Power-down
mode.
The instruction that sets PD (PCON.1) is the last executed
prior to going into the Power-down mode. The oscillator is
stopped. Note that the Power-down mode also can be
entered when the watchdog has been disabled.
The Power-down mode can be terminated by an external
reset in the same way as in the 80C51 or in addition by any
one of the two external interrupts, IE0 or IE1
Idle mode operation permits the interrupt, serial ports and
timer blocks to function while the CPU is halted. The
following functions remain active during Idle mode:
• Timer 0, Timer 1, Timer 2, Watchdog Timer
• UART
(see Section 9.1).
The status of the external pins during Power-down mode
is shown in Table 20. If the Power-down mode is activated
while in external program memory, the port data that is
held in the SFR P2 is restored to Port 2. If the data is a
logic 1, the port pin is held HIGH during the Power-down
mode by the strong pull-up transistor ‘p1’ (see Fig.15).
• External interrupt.
These functions may generate an interrupt or reset and
thus end the Idle mode.
The Power-down mode operation freezes the oscillator.
and can only be activated by setting the PD bit in the SFR
PCON (see Fig.17).
13.3 Wake-up from Power-down mode
The Power-down mode of the P89C738 can also be
terminated by any one of the two external interrupts, IE0 or
IE1. A termination with an external interrupt does not affect
the internal data memory and does not affect the Special
Function Registers (SFRs). This gives the possibility to
exit Power-down without changing the port output levels.
To terminate the Power-down mode with an external
interrupt, IE0 or IE1 must be switched to be level-sensitive
and must be enabled. The external interrupt input signal
INT0 and INT1 must be kept LOW until the oscillator has
restarted and stabilized (see Fig.16).
13.1 Idle mode
The instruction that sets IDL (PCON.0) is the last
instruction executed in the normal operating mode before
Idle mode is activated. Once in the Idle mode, the CPU
status is preserved in its entirety: the Stack Pointer,
Program Counter, Program Status Word, Accumulator,
RAM and all other registers maintain their data during Idle
mode. The status of external pins during Idle mode is
shown in Table 20.
There are three ways to terminate the Idle mode:
In order to prevent any interrupt priority problems during
wake-up, the priority of the desired wake-up interrupt
should be higher than the priorities of all other enabled
interrupt sources. The instruction following the one that put
the device into the Power-down mode will be the first one
which will be executed after an interrupt has been
serviced.
• Activation of any enabled interrupt will cause IDL
(PCON.0) to be cleared by hardware terminating Idle
mode. The interrupt is serviced, and following return
from interrupt instruction RETI, the next instruction to be
executed will be the one which follows the instruction
that wrote a logic 1 to PCON.0.
The flag bits GF0 (PCON.2) and GF1 (PCON.3) may be
used to determine whether the interrupt was received
during normal execution or during the Idle mode.
For example, the instruction that writes to PCON.0 can
also set or clear one or both flag bits. When Idle mode is
terminated by an interrupt, the service routine can
examine the status of the flag bits.
• The second way of terminating the Idle mode is with an
external hardware reset. Since the oscillator is still
running, the hardware reset is required to be active for
two machine cycles (24 oscillator periods) to complete
the reset operation.
• The third way of terminating the Idle mode is by internal
watchdog reset.
1998 Apr 07
28
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
internal timing stopped
C1
C1
C1
C2
LCALL
Idle mode
Power−down mode
>
oscillator start_up 10 ms
interrupts are polled
interrupt routine
XTAL1, 2 oscillator stopped
INT0: 2 cycles
INT1: 1 cycle
>
560 ms
32 kHz oscillator stopped
32 kHz oscillator running
>
10 ms
INT0
INT1
MGK195
set external interrupt latch
Fig.16 Wake-up by external interrupt input.
h
XTAL2
XTAL1
interrupts,
serial port,
timer blocks
OSCILLATOR
CLOCK
GENERATOR
CPU
MGK194
IDL
PD
Fig.17 Internal Idle and Power-down clock configuration.
29
1998 Apr 07
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
13.4 Status of external pins
Table 20 Status of the external pins during Idle and Power-down modes
MODE
Idle
MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
internal
external
internal
external
HIGH
HIGH
LOW
LOW
HIGH port data port data port data port data port data port data
HIGH
LOW
LOW
floating
port data port data port data port data port data port data
floating port data port data port data port data port data
port data address port data port data port data
Power-down
13.5 Power Control Register (PCON)
Special modes are activated by software via the SFR PCON. PCON is not bit addressable. The reset value of PCON is
00H.
Table 21 Power Control Register (SFR address 87H)
7
6
5
4
3
2
1
0
SMOD
ARE
RFI
WLE
GF1
GF0
PD
IDL
Table 22 Description of PCON bits
BIT
SYMBOL
DESCRIPTION
7
SMOD
Double baud rate bit. When set to a logic 1 the baud rate is doubled when Timer 1 is
used to generate baud rate, and the Serial Port is used in Modes 1, 2 or 3.
6
5
ARE
RFI
AUX-RAM enable bit. When set to a logic 1 the AUX-RAM is disabled, so that all
MOVX-instructions access the external data memory.
Reduced Radio Frequency Interference bit. When set to a logic 1 the toggling of the
ALE pin is prohibited. This bit is cleared on reset. See also Chapters 1 “Features”: on
EMC and 6 “Pinning information”: note 2.
4
WLE
Watchdog Load Enable. This flag must be set by software prior to loading the
Watchdog Timer (T3). It is cleared when timer T3 is loaded.
3
2
1
0
GF1
GF0
PD(1)
IDL(1)
General-purpose flag bit.
Power-down select. Setting this bit activates the Power-down mode.
Idle mode select. Setting this bit activates the Idle mode.
Note
1. If logic 1s are written to PD and IDL at the same time, PD takes precedence.
1998 Apr 07
30
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
Both are operated in parallel resonance. XTAL 1 is the
high gain amplifier input, and XTAL 2 is the output (see
Fig.18).
14 OSCILLATOR CIRCUIT
The oscillator circuit of the P89C738 is a single-stage
inverting amplifier in a Pierce oscillator configuration.
The circuitry between the XTAL 1 and XTAL 2 is basically
an inverter biased to the transfer point. Either a crystal or
ceramic resonator can be used as the feedback element to
complete the oscillator circuitry (see Fig.19).
To drive the P89C738 externally, XTAL 1 is driven from an
external source and XTAL 2 left open-circuit (see Fig.20).
to internal
timing circuits
V
DD
Q2
D1
400 Ω
R1
XTAL1
XTAL2
Q1
Q3
D2
Q4
V
PO
SS
MGK196
Fig.18 P89C738/P89C739 oscillator internal circuit.
handbook, halfpage
handbook, halfpage
C1
XTAL1
20 pF
NC
XTAL2
XTAL1
external
oscillator
signal
C2
V
XTAL2
SS
20 pF
CMOS gate
MBK775
MGK197
Fig.19 P89C738/P89C739 oscillator circuit
with crystal/ceramic resonator.
Fig.20 Driving the P89C738/P89C739 from an
external source.
1998 Apr 07
31
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
The internal reset is executed during the second cycle in
which RST is pulled HIGH and is repeated every cycle until
RST goes LOW. It leaves the internal registers as shown
in Chapter 17.
15 RESET
The reset circuitry for the P89C738 is connected to the
reset pin RST. A Schmitt trigger is used at the input for
noise rejection. The output of the Schmitt trigger is
sampled by the reset circuitry every machine cycle.
15.1 Power-on reset
A reset is accomplished by holding the RST pin HIGH for
at least two machine cycles (24 oscillator periods).
The CPU responds by executing an internal reset. During
reset ALE and PSEN output are at a HIGH level. In order
to perform a correct reset, this level must not be affected
by external elements.
Figure 21 shows the on-chip reset configuration.
When VDD is turned on, and provided its rise time does not
exceed 10 ms, an automatic reset can be obtained by
connecting the RST pin to VDD via a 2.2 µF capacitor.
When the power is switched on, the voltage on the RST pin
is equal to VDD minus the capacitor voltage, and
In the P89C738 the internal reset can also be activated by
the Watchdog Timer (T3). If the Watchdog Timer is also
used to reset external devices, the usual capacitor
arrangement should not be connected to RST pin. Instead,
an extra circuit should be used to perform the power-on
reset operation. It should be remembered that a timer T3
overflow, if enabled, will force a reset condition to the
P89C738 by an internal connection, whether the output
RST is tied to LOW or not (see Fig.21).
decreases from VDD as the capacitor charges through the
internal resistor (RRST) to ground. The larger the capacitor,
the more slowly VRST decreases. VRST must remain above
the lower threshold of the Schmitt trigger long enough to
effect a complete reset. The time required is the oscillator
start-up time, plus 2 machine cycles.
V
DD
SCHMITT
TRIGGER
+
10 µF
RSTOUT
RESET
CIRCUITRY
RST
8 kΩ
R
RST
GND
overflow timer T3
POC
on-chip circuit
MGK198
Fig.21 On-chip reset configuration.
1998 Apr 07
32
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
16 MULTIPLE PROGRAMMING ROM (MTP-ROM)
16.1 Features
16.3.1 AUTOMATIC PROGRAMMING ALGORITHM
The P89C738 Automatic programming algorithm requires
the user to only write a program set-up command and a
program command (program data and address).
The device automatically times the programming pulse
width, provides the program verification, and counts the
number of sequences. A status bit similar to DATA polling
and a status bit toggling between consecutive read cycles,
provide feedback to the user as to the status of the
programming operation.
• 64 kbytes electrically erasable internal program memory
• Up to 64 kbytes external program memory if the internal
program memory is switched off (EA = 0)
• Programming and erasing voltage 12 V ±5%
• Command register architecture
– Byte Programming (10 µs typical)
– Auto chip erase: 5 seconds (typical; including
pre-programming time)
16.3.2 AUTOMATIC ERASE ALGORITHM
• Auto-erase and auto-program
– DATA polling
The P89C738 Automatic erase algorithm requires the user
to only write an erase set-up command and erase
command. The device will automatically pre-program and
verify the entire array. Then the device automatically times
the erase pulse width, provides the erase verify, and
counts the number of sequences. A status bit similar to
DATA polling and a status bit toggling between
– Toggle bit
• Minimum 100 erase/program cycles
• Advanced CMOS MTP memory technology.
consecutive read cycles, provide feedback to the user as
to the status of the erase operation.
16.2 General description
The P89C738’s MTP memories augment EPROM
functionality with in-circuit electrical erasure and
programming. The P89C738 uses a command register to
manage this functionality.
Commands are written to the command register. Register
contents serve as inputs to an internal state-machine
which controls the erase and programming circuitry.
During write cycles, the command register internally
latches address and data needed for the programming and
erase operations. For system design simplification, the
P89C738 is designed to support either WE or CE
controlled writes. During a system write cycle, addresses
are latched on the falling edge of WE or CE whichever
occurs last. Data is latched on the rising edge of WE or CE
whichever occur first. To simplify the following discussion,
the WE pin is used as the write cycle control pin throughout
the rest of this text. All set-up and hold times are with
respect to the WE signal.
P89C738’s MTP reliably stores memory contents even
after 100 erase and program cycles. The cell is designed
to optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide
processing and low internal electric fields for erase and
programming operations produces reliable cycling.
The P89C738 uses a VPP = 12.0 V ±5% supply to perform
the auto-erase and auto-program algorithms.
16.3 Automatic programming and Automatic chip
erase
16.4 Command definitions
The P89C738 is byte programmable using the Automatic
programming algorithm. The Automatic programming
algorithm does not require the system to time out or verify
the data programmed. At typical room temperature the
chip programming time of the P89C738 is less than
5 seconds.
When a low voltage is applied to the VPP pin, the contents
of the command register is set to a default value: 00H.
Applying high voltage to the VPP pin enables read/write
operations. Device operations are selected by writing
specific data patterns into the command register.
The device may be erased using the Automatic erase
algorithm. The Automatic erase algorithm automatically
programs the entire array prior to electrical erase.
The timing and verification of the electrical erase are
controlled internally by the device.
Table 23 defines these P89C738 register commands.
Table 24 defines the bus operations of the P89C738.
1998 Apr 07
33
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
Table 23 Command definitions
FIRST BUS CYCLE
SECOND BUS CYCLE
BUS
COMMAND
CYCLES
OPERATION ADDRESS DATA OPERATION ADDRESS DATA
Read identified codes
Set-up auto erase/auto chip erase
Set-up auto program/program
Reset
2
2
2
2
write
write
write
write
X(1)
X
90H
30H
40H
FFH
read
write
write
write
IA(2)
ID(3)
X
30H
X
PA(4)
X
PD(5)
FFH
X
Notes
1. X = don’t care.
2. IA = identifier address.
3. ID = data read from location IA during device identification.
4. PA = address of memory location to be programmed.
5. PD = data to be programmed at location.
Table 24 P89C738 bus operations
(1)
READ/WRITE OPERATION
Read(2)
Standby(5)
VPP
CE
OE
WE
D00 TO D07
VPPH
VPPH
VPPH
VIL
VIH
VIL
VIL
X(6)
VIH
VIH
X
data out(3)(4)
3-state
data in(3)
Write
VIL
Notes
1. VPPH is the programming voltage specified for the device.
2. Manufacturer and device codes are accessed via a command register write sequence. Refer to Table 23. All other
addresses are LOW.
3. Data out means that the data is read out from the microcontroller. Data in means that the data is send into the
microcontroller from outside.
4. Read operation with VPP = VPPH may access array data (if write command is preceded) or Silicon-ID codes.
5. With VPP at high voltage, the standby current equals IDD + IPP (standby).
6. X can be VIL or VIH.
1998 Apr 07
34
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
The set-up of Automatic program is performed by writing
40H to the command register.
16.5 Silicon-ID-Read command
MTP memories are intended for use in applications where
the local CPU alters memory contents. As such,
manufacturer and device-codes must be accessible while
the device resides in the target system.
Once the set-up of the Automatic program operation is
performed, the next WE pulse causes a transition to an
active programming operation. Addresses are internally
latched on the falling edge of the WE pulse. Data is
internally latched on the rising edge of the WE pulse.
The rising edge of WE also starts the programming
operation. The system is not required to provide further
controls or timings. The device will automatically provide
an adequate internally generated program pulse and verify
margin. The automatic programming operation is
completed when the data read on DQ6 stops toggling for
two consecutive read cycles and the data on DQ7 and
DQ6 are equivalent to data written to these two bits at
which time the device returns to the read mode (no
program verify command is required; but data can be read
out if OE is active LOW).
P89C738 contains a Silicon-ID-Read operation.
The operation is initiated by writing 90H into the command
register. Following the command write, a read cycle from
address 0000H retrieves the manufacturer code: C2H.
A read cycle from address 0001H returns the device
code: 1AH.
16.6 Set-up of Automatic chip erase and Automatic
erase commands
The Automatic chip erase does not require the device to be
entirely pre-programmed prior to executing the set-up of
Automatic erase command and Automatic chip erase
commands. Upon executing the Automatic chip erase
command, the device automatically will program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The erase
and verify operations are complete when the data on DQ7
is a logic 1 at which time the device returns to the standby
mode. The system is not required to provide any control or
timing during these operations.
16.8 Reset command
A reset command is provided as a means to safely abort
the erase or program command sequences.
Following either set-up command (erase or program) with
two consecutive writes of FFH will safely abort the
operation. Memory contents will not be altered. Should
program-fail or erase-fail happen, two consecutive writes
of FFH will reset the device to abort the operation. A valid
command must then be written to place the device in the
desired state.
When using the Automatic chip erase algorithm, note that
the erase automatically terminates when adequate erase
margin has been achieved for the memory array (no erase
verify command is required). The margin voltages are
internally generated in the same manner as when the
standard erase verify command is used.
16.9 Write operation status
16.9.1 Toggle bit DQ6
The P89C738 features a ‘toggle bit’ as a method to
indicate to the host system that the Automatic program or
erase algorithms are either in progress or completed.
The set-up of the Automatic erase command is a
command only operation that stages the device for
automatic electrical erasure of all bytes in the array.
The set-up Automatic erase is performed by writing 30H to
the command register.
While the Automatic program or erase algorithm is in
progress, successive attempts to read data from the
device will result in DQ6 toggling between a logic 1and a
logic 0. Once the Automatic program or erase algorithm is
completed, DQ6 will stop toggling and valid data will be
read. The toggle bit is valid after the rising edge of the
second WE pulse of the two write pulse sequences.
To execute the Automatic chip erase, 30H must be written
again to the command register. The automatic chip erase
begins on the rising edge of the WE and terminates when
the data on DQ7 is a logic 1 and the data on DQ6 stops
toggling for two consecutive read cycles, at which time the
device returns to the standby mode.
Toggle bit appears in Q6, when program or erase is
operating.
16.7 Set-up of the Automatic program and Program
commands
The set-up of the Automatic program is a command only
operation that stages the devices for automatic
programming.
1998 Apr 07
35
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
16.9.2 DATA polling DQ7
16.11 System considerations
The P89C738 also features DATA polling as a method to
indicate to the host system that the Automatic program or
erase algorithms are either in progress or completed.
During the switch between active and standby conditions,
transient current peaks are produced on the rising and
falling edges of CE. The magnitude of these transient
current peaks is dependent on the output capacitance
loading of the device.
While the Automatic programming algorithm is in operation
an attempt to read the device will produce the complement
data of the data last written to DQ7. Upon completion of
the Automatic programming algorithm an attempt to read
the device will produce the true data last written to DQ7.
The DATA polling feature is valid after the rising edge of
the second WE pulse of the two write pulse sequences.
A ceramic capacitor of minimum 0.1 µF (high frequency,
low inherent inductance) should be used on each device
between VDD and VSS, and between VPP and VSS to
minimize transient effects.
Table 25 Capacitance of pin VPP
Tamb = 25 °C; fclk = 1.0 MHz
While the Automatic erase algorithm is in operation, DQ7
will read a logic 0 until the erase operation is completed.
Upon completion of the erase operation, the data on DQ7
will read a logic 1. The DATA polling feature is valid after
the rising edge of the second WE pulse of two write pulse
sequences.
SYMBOL
PARAMETER
CONDITION VALUE
CIN
input capacitance
VIN = 0 V
14 pF
16 pF
COUT
output capacitance VOUT = 0 V
The DATA polling feature is active during Automatic
program or erase algorithms.
DATA polling appears in Q7 during programming or erase.
16.10 Write operation
Because of the electronic features of the Flash cell, the
data to be programmed into Flash should be reversed
when programming. In other words, to program 00H the
value FFH must be sent to Port 0.
1998 Apr 07
36
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
16.12 Command programming/data programming and erase operation
+5 V
V
DD
A0 to A7
HIGH
CE
P1
P0
EA
PGM command/data
RSTIN
P3.3
V
PP
LOW pulse
ALE/WE
PSEN
P2.7
LOW
OE
P89C738
XTAL2
A15
P3.5
4 to 6 MHz
P2.0 to P2.5
P3.4
A8 to A13
A14
XTAL1
V
P2.6, P3.7, P3.1 and P3.0
0000B
SS
MGK199
Fig.22 Automatic programming/erase timing and verification.
Table 26 Pin connections during Automatic programming/erase timing and verification
PIN NAME SIGNAL FUNCTION
A0 to A7 input low-order address bits
P1.0 to P1.7
P2.0 to P2.5
P3.4 to P3.5
P0.0 to P0.7
P3.3
A8 to A13
input high-order address bits
A14 to A15
Q0 to Q7
data input/output
CE
Chip Enable input
P2.7
OE
Output Enable input
Write Enable pin
ALE/WE
EA/VPP
WE
VPP
programming supply voltage
Flash Test mode selection
power supply voltage (+5 V)
ground pin
P2.6, P3.7, P3.1 and P3.0
FTEST3 to FTEST0
VDD
VSS
VDD
VSS
Table 27 DC characteristics during Command programming/data programming and erase operation
Tamb = 0 to 70 °C; VDD = 5 V ±10% (note 1); VPP = 12.0 V ±5%; all currents are in RMS unless otherwise noted
(sampled, not 100% tested).
SYMBOL
PARAMETER
input leakage current
CONDITIONS
VIN = VSS to VDD
MIN.
MAX.
UNIT
ILI
−
−
−
−
−
−
−
10
10
1
µA
ILO
output leakage current
VOUT = VSS to VDD
CE = VIH
µA
IDD(stb)
supply current standby mode
mA
µA
CE = VDD ±0.3 V
IO = 0 mA; fclk = 1 MHz
IO = 0 mA; fclk = 11 MHz
100
30
IDD(read)
supply current read mode
mA
mA
mA
50
IDD(prog)
supply current program mode
50
1998 Apr 07
37
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
SYMBOL
IDD(erase)
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
mA
mA
mA
µA
supply current erase mode
−
−
−
50
50
50
IDD(prog-verify)
IDD(erase-verify)
IPP(read)
supply current program/verify mode
supply current erase/verify mode
programming supply current read
mode
VPP = 12.6 V; note 2 and 3 −
100
50
50
50
50
IPP(prog)
programming supply current
program mode
−
−
−
−
mA
mA
mA
mA
IPP(erase)
programming supply current erase
mode
IPP(prog-verify)
IPP(erase-verify)
programming supply current
programming/erase mode
programming supply current
erase/verify mode
VIL
LOW-level input voltage
HIGH-level input voltage
LOW-level output voltage
HIGH-level output voltage
note 4
−0.5(5)
0.2VPP − 0.3 V
VIH
VOL
VOH
2.4
−
VDD + 0.3(6)
V
V
V
IOL = 2.1 mA
0.45
IOH = 400 µA
2.4
−
Notes
1. VDD must be applied before VPP and removed after VPP
2. VPP must not exceed 14 V including overshoot.
.
3. The device reliability can be affected when the device is installed or removed while VPP = 12 V.
4. Do not alter VPP either ‘VIL to 12 V’ or ‘12 V to VIL’ when CE = VIL.
5. VIL(min) = −0.5 V for pulse width < 20 ns.
6. If VIH is over the specified maximum value, programming operation cannot be guaranteed.
Table 28 AC characteristics during command programming, data programming and erase operation
T
amb = 0 to 70 °C; VDD = 5 V + 10%; VPP = 12 V + 5%; refer to Figs 23 to 27.
SYMBOL PARAMETER MIN.
tsu(Vpp) 100
TYP.
MAX.
UNIT
VPP set-up time
OE set-up time
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu(OE)
100
150
60
20
100
0
Tcy(P)
command programming cycles
WE programming pulse width
WE programming pulse width HIGH
WE programming pulse width HIGH
address set-up time
tWP(WE)
tWP(WE)H1
tWP(WE)H2
tsu(A)
th(A-DATA)
tsu(D)
address hold time for DATA polling
DATA set-up time
0
50
10
100
0
th(D)
DATA hold time
tsu(DATA-CE)
tsu(CE)
CE set-up time before DATA polling/toggle bit
CE set-up time
tsu(CE-W)
CE set-up time before command write
100
1998 Apr 07
38
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
SYMBOL
th(Vpp)
PARAMETER
MIN.
100
TYP.
MAX.
UNIT
VPP hold time
−
−
−
−
−
ns
ns
ns
s
to(dis)
output disable time; note 2
−
35
tACC(DATA)
tE(tot)
DATA polling/toggle bit access time
total erase time in auto-chip-erase
total programming time in auto-verify
−
150
5
−
tP(tot)
15
−
300
us
Notes
1. CE and OE must be fixed HIGH during VPP transition from ‘5 to 12 V’ or from ‘12 to 5 V’.
2. to(dis) defined as the time at which the output achieves the open circuit condition and data is no longer driven.
16.12.1 AUTOMATIC PROGRAMMING
16.12.2 AUTOMATIC ERASE
One byte data is programmed. Verifying in fast algorithm
and additional programming by external control are not
required because these operations are executed
automatically by the internal control circuit. Programming
completion can be verified by DATA polling (see
Section 16.9.2) and toggle bit (see Section 16.9.1)
checking after automatic verify starts. Device outputs
DATA during programming and DATA after programming
on Q7. Q0 to Q5 are in high-impedance state; Q6 is the
toggle bit (see Section 16.9.1).
All the data on the chip is erased. External erase verifying
is not required because data is erased automatically by
internal control circuit. Erasure completion can be verified
by DATA polling and toggle bit checking after automatic
erase starts.
Device outputs a logic 0 during erasure and a logic 1 after
erasure on Q7. Q0 to Q5 are in high-impedance state; Q6
is the toggle bit (see Section 16.9.1).
Figure 24 shows the timing waveform.
Figure 23 shows the timing waveform.
1998 Apr 07
39
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
16.12.3 TIMING WAVEFORMS
set-up auto program/
program command
auto program and DATA polling
V
V
5 V
12 V
0 V
DD
PP
t
t
h(Vpp)
su(Vpp)
A0 to A15
address valid
t
su(A)
WE
CE
t
t
h(A-DATA)
P(tot)
T
cy(P)
t
t
su(OE)
su(CE)
t
t
t
su(CE-W)
WP(WE)
WP(WE)
t
t
WP(WE)H1
su(DATA-CE)
OE
t
t
t
t
su(D)
h(D)
su(D)
h(D)
t
t
ACC(DATA)
o(dis)
Q7
command in
data in
data in
DATA
DATA polling
DATA
DATA
Q0 to Q5
command in
MGK200
command #40H
Fig.23 Automatic programming timing waveform.
1998 Apr 07
40
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
set-up auto chip erase/
erase command
auto chip erase and DATA polling
V
V
5 V
12 V
0 V
DD
PP
t
t
h(Vpp)
su(Vpp)
A0 to A15
WE
CE
t
E(tot)
T
cy(P)
t
su(OE)
t
su(CE)
t
t
t
WP(WE)
WP(WE)
su(CE-W)
t
t
WP(WE)H1
su(DATA-CE)
OE
t
t
t
t
su(D)
su(D)
h(D)
h(D)
t
t
o(dis)
ACC(DATA)
Q7
command in
command in
command in
command in
DATA polling
Q0 to Q5
MGK201
Fig.24 Automatic chip erase timing waveform.
V
5 V
DD
12 V
V
PP
0 V
t
su(Vpp)
A0 to A15
T
cy(P)
WE
CE
t
t
su(OE)
WP(WE)
t
t
WP(WE)H1
WP(WE)
OE
t
t
t
t
h(D)
su(D)
h(D)
su(D)
Q0 to Q7
command in
FFH
command in
FFH
MGK203
Fig.25 Reset timing waveform.
41
1998 Apr 07
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
V
5 V
DD
12 V
V
PP
0 V
A0
t
t
h(Vpp)
su(Vpp)
address valid 0 or 1
A1 to A15
t
ACC
T
cy(P)
WE
t
su(CE-W)
CE
t
t
t
su(OE)
CE
su(OE)
t
t
WP(WE)
WP(WE)H2
OE
t
o(dis)
t
t
t
t
h(D)
su(D)
h(D)
OE
data out valid
C2H or 1AH
Q0 to Q7
command in
C0H
MGK202
Fig.26 VPP = VPPH (high voltage) identification code read timing waveform.
HIGH
WE
V
12 V
CE
PP
OE
toggle bit
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
Q6
during P/E
DATA
DATA polling
DATA
Q7
during P
DATA
DATA
DATA
program/erase complete
Q7
during E
Q0 to Q5
DATA polling
DATA
MGK204
Fig.27 Toggle bit, DATA polling timing waveform.
42
1998 Apr 07
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
17 SPECIAL FUNCTION REGISTERS OVERVIEW
The P89C738; P89C739 have 30 SFRs available to the user.
ADDRESS
(HEX)
RESET VALUE
(B)(1)
NAME
FUNCTION
FF
F0
EB
E0
D0
CD
CC
CB
CA
C8
C7
C0
B8
B0
A8
A0
99
T3
B(2)
0000 0000
0000 0000
XXXX XX00
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
X000 0000
1111 1111
0000 0000
1111 1111
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0111
1111 1111
Watchdog Timer
B Register
EBTCON
ACC(2)
PSW(2)
TH2
Watchdog Timer Control Register
Accumulator
Program Status Word
Timer 2 High byte Register
Timer 2 Low byte Register
TL2
RCAP2H
RCAP2L
T2CON(2)
P5
P4(2)
IP0(2)
P3(2)
Timer 2 Reload/Capture Register High byte
Timer 2 Reload/Capture Register Low byte
Timer/Counter 2 Control Register
I/O Port Register 5
I/O Port Register 4
Interrupt Priority Register 0
I/O Port Register 3
IEN0(2)
Interrupt Enable Register 0
I/O Port Register 2
P2
S0BUF
S0CON(2)
P1(2)
Serial Data Buffer Register 0
Serial Port Control Register 0
I/O Port Register 2
98
90
8D
8C
8B
8A
89
TH1
Timer 1 High byte Register
Timer 0 High byte Register
Timer 1 Low byte Register
Timer 0 Low byte Register
Timer/Counter Mode Control Register
Timer/Counter Control Register
Power Control Register
TH0
TL1
TL0
TMOD
TCON(2)
PCON
DPH
88
87
83
Data Pointer High byte Register
Data Pointer Low byte Register
Stack Pointer
82
DPL
81
SP
P0(2)
80
I/O Port Register 0
Notes
1. X = undefined.
2. Bit addressable register.
1998 Apr 07
43
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
18 INSTRUCTION SET
The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 12 MHz
oscillator, 64 instructions execute in 1 µs and 45 instructions execute in 2 µs. Multiply and divide instructions execute in
4 µs.
For the description of the Data Addressing modes and Hexadecimal opcode cross-reference see Table 33.
Table 29 Instruction set description: Arithmetic operations
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES CYCLES
Arithmetic operations
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
INC
A,Rr
Add register to A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
2*
A,direct
A,@Ri
A,#data
A,Rr
Add direct byte to A
25
Add indirect RAM to A
26, 27
24
Add immediate data to A
Add register to A with carry flag
Add direct byte to A with carry flag
Add indirect RAM to A with carry flag
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment A
3*
A,direct
A,@Ri
A,#data
A,Rr
35
36, 37
34
9*
A,direct
A,@Ri
A,#data
A
95
96, 97
94
04
INC
Rr
Increment register
0*
INC
direct
@Ri
Increment direct byte
05
INC
Increment indirect RAM
Decrement A
06, 07
14
DEC
DEC
DEC
DEC
INC
A
Rr
Decrement register
1*
direct
@Ri
Decrement direct byte
15
Decrement indirect RAM
Increment data pointer
16, 17
A3
DPTR
AB
MUL
DIV
Multiply A and B
A4
AB
Divide A by B
84
DA
A
Decimal adjust A
D4
1998 Apr 07
44
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
Table 30 Instruction set description: Logic operations
OPCODE
BYTES CYCLES
(HEX)
MNEMONIC
DESCRIPTION
Logic operations
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
A,Rr
AND register to A
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
5*
A,direct
A,@Ri
A,#data
direct,A
AND direct byte to A
AND indirect RAM to A
AND immediate data to A
AND A to direct byte
55
56, 57
54
52
direct,#data AND immediate data to direct byte
53
A,Rr
OR register to A
4*
A,direct
A,@Ri
A,#data
direct,A
OR direct byte to A
OR indirect RAM to A
OR immediate data to A
OR A to direct byte
45
46, 47
44
42
direct,#data OR immediate data to direct byte
43
A,Rr
Exclusive-OR register to A
6*
A,direct
A,@Ri
A,#data
direct,A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate data to A
Exclusive-OR A to direct byte
65
66, 67
64
62
direct,#data Exclusive-OR immediate data to direct byte
63
A
A
A
A
A
A
A
Clear A
E4
F4
Complement A
Rotate A left
23
RLC
RR
Rotate A left through the carry flag
Rotate A right
33
03
RRC
SWAP
Rotate A right through the carry flag
Swap nibbles within A
13
C4
1998 Apr 07
45
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
Table 31 Instruction set description: Data transfer
OPCODE
BYTES CYCLES
(HEX)
MNEMONIC
DESCRIPTION
Data transfer
A,Rr
A,direct (note 1) Move direct byte to A
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVC
MOVC
MOVX
MOVX
MOVX
MOVX
PUSH
POP
Move register to A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
E*
E5
A,@Ri
Move indirect RAM to A
E6, E7
74
A,#data
Move immediate data to A
Move A to register
Rr,A
F*
Rr,direct
Rr,#data
direct,A
Move direct byte to register
Move immediate data to register
Move A to direct byte
A*
7*
F5
direct,Rr
direct,direct
direct,@Ri
direct,#data
@Ri,A
Move register to direct byte
Move direct byte to direct
8*
85
Move indirect RAM to direct byte
Move immediate data to direct byte
Move A to indirect RAM
86, 87
75
F6, F7
A6, A7
76, 77
90
@Ri,direct
@Ri,#data
Move direct byte to indirect RAM
Move immediate data to indirect RAM
DPTR,#data 16 Load data pointer with a 16-bit constant
A,@A+DPTR
A,@A+PC
A,@Ri
Move code byte relative to DPTR to A
Move code byte relative to PC to A
Move external RAM (8-bit address) to A
Move external RAM (16-bit address) to A
Move A to external RAM (8-bit address)
Move A to external RAM (16-bit address)
Push direct byte onto stack
93
83
E2, E3
E0
A,@DPTR
@Ri,A
F2, F3
F0
@DPTR,A
direct
C0
direct
Pop direct byte from stack
D0
XCH
A,Rr
Exchange register with A
C*
XCH
A,direct
A,@Ri
Exchange direct byte with A
C5
XCH
Exchange indirect RAM with A
C6, C7
D6, D7
XCHD
A,@Ri
Exchange LOW-order digit indirect RAM with A
Note
1. MOV A,ACC is not permitted.
1998 Apr 07
46
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
Table 32 Instruction set description: Boolean variable manipulation, Program and machine control
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES CYCLES
Boolean variable manipulation
CLR
CLR
SETB
SETB
CPL
CPL
ANL
ANL
ORL
ORL
MOV
MOV
C
Clear carry flag
Clear direct bit
Set carry flag
Set direct bit
1
2
1
2
1
2
2
2
2
2
2
2
1
1
1
1
1
1
2
2
2
2
1
2
C3
bit
C2
D3
D2
B3
B2
82
B0
72
A0
A2
92
C
bit
C
Complement carry flag
bit
Complement direct bit
C,bit
C,/bit
C,bit
C,/bit
C,bit
bit,C
AND direct bit to carry flag
AND complement of direct bit to carry flag
OR direct bit to carry flag
OR complement of direct bit to carry flag
Move direct bit to carry flag
Move carry flag to direct bit
Program and machine control
ACALL
LCALL
RET
addr11
addr16
Absolute subroutine call
2
3
1
1
2
3
2
1
2
2
2
2
3
3
3
3
3
3
3
2
3
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
•1addr
12
Long subroutine call
Return from subroutine
22
RETI
AJMP
LJMP
SJMP
JMP
Return from interrupt
32
addr11
addr16
rel
Absolute jump
♦ 1addr
02
Long jump
Short jump (relative address)
Jump indirect relative to the DPTR
Jump if A is zero
80
@A+DPTR
rel
73
JZ
60
JNZ
rel
Jump if A is not zero
70
JC
rel
Jump if carry flag is set
40
JNC
rel
Jump if carry flag is not set
Jump if direct bit is set
50
JB
bit,rel
20
JNB
bit,rel
Jump if direct bit is not set
Jump if direct bit is set and clear bit
Compare direct to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to register and jump if not equal
30
JBC
bit,rel
10
CJNE
CJNE
CJNE
CJNE
DJNZ
DJNZ
NOP
A,direct,rel
A,#data,rel
Rr,#data,rel
B5
B4
B*
@Ri,#data,rel Compare immediate to indirect and jump if not equal
B6, B7
D*
Rr,rel
Decrement register and jump if not zero
Decrement direct and jump if not zero
No operation
direct,rel
D5
00
1998 Apr 07
47
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
Table 33 Description of the mnemonics in the Instruction set
MNEMONIC
DESCRIPTION
Data addressing modes
Rr
Working registers R0 to R7.
128 internal RAM locations and any special function register (SFR).
direct
@Ri
Indirect internal RAM location addressed by register R0 or R1 of the actual register bank.
8-bit constant included in instruction.
#data
#data 16
bit
16-bit constant included as bytes 2 and 3 of instruction.
Direct addressed bit in internal RAM or SFR.
addr16
16-bit destination address. Used by LCALL and LJMP.
The branch will be anywhere within the 64 kbytes Program Memory address space.
addr11
rel
111-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes
page of Program Memory as the first byte of the following instruction.
Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps.
Range is −128 to +127 bytes relative to first byte of the following instruction.
Hexadecimal opcode cross-reference
*
•
8, 9, A, B, C, D, E, F.
1, 3, 5, 7, 9, B, D, F.
0, 2, 4, 6, 8, A, C, E.
♦
1998 Apr 07
48
Table 34 Instruction map
First hexadecimal character of opcode
← Second hexadecimal character of opcode →
↓
0
1
2
3
4
5
6
0
0
7
1
1
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
1
1
1
1
1
1
1
1
1
1
1
A B C D E
INC Rr
F
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
INC @Ri
DEC @Ri
AJMP
addr11
LJMP
addr16
RR
A
INC
A
INC
direct
0
NOP
2
3
4
5
6
6
6
6
6
6
6
6
6
6
6
DEC Rr
JBC
bit,rel
ACALL
addr11
LCALL
addr16
RRC
A
DEC
A
DEC
direct
1
2
2
3
4
5
ADD A,@Ri
ADD A,Rr
JB
bit,rel
AJMP
addr11
RL
A
ADD
A,#data
ADD
A,direct
RET
0
1
2
3
4
5
ADDC A,@Ri
ADDC A,Rr
JNB
bit,rel
ACALL
addr11
RLC
A
ADDC
A,#data
ADDC
A,direct
3
RETI
0
1
1
2
3
4
5
ORL A,@Ri
ORL A,Rr
JC
rel
AJMP
addr11
ORL
direct,A
ORL
direct,#data
ORL
A,#data
ORL
A,direct
4
0
2
2
2
3
4
5
5
5
ANL A,@Ri
ANL A,Rr
JNC
rel
ACALL
addr11
ANL
direct,A
ANL
direct,#data
ANL
A,#data
ANL
A,direct
5
0
1
1
3
4
XRL A,@Ri
XRL A,Rr
JZ
rel
AJMP
addr11
XRL
direct,A
XRL
direct,#data
XRL
A,#data
XRL
A,direct
6
0
3
4
MOV @Ri,#data
MOV Rr,#data
JNZ
rel
ACALL
addr11
ORL
C,bit
JMP
@A+DPTR
MOV
A,#data
MOV
direct,#data
7
0
1
2
3
4
5
MOV direct,@Ri
MOV direct,Rr
SJMP
rel
AJMP
addr11
ANL
C,bit
MOVC
A,@A+PC
DIV
AB
MOV
direct,direct
8
0
1
2
3
4
5
SUBB A,@Ri
SUB A,Rr
MOV
DTPR,#data16
ACALL
addr11
MOV
bit,C
MOVC
A,@A+DPTR
SUBB
A,#data
SUBB
A,direct
9
0
1
2
3
4
5
MOV @Ri,direct
MOV Rr,direct
ORL
C,/bit
AJMP
addr11
MOV
bit,C
INC
DPTR
MUL
AB
A
0
1
2
3
4
5
CJNE @Ri,#data,rel
CJNE Rr,#data,rel
ANL
C,/bit
ACALL
addr11
CPL
bit
CPL
C
CJNE
A,#data,rel
CJNE
A,direct,rel
B
0
1
1
1
1
1
1
2
3
4
5
6
6
6
6
6
XCH A,@Ri
XCH A,Rr
PUSH
direct
AJMP
addr11
CLR
bit
CLR
C
SWAP
A
XCH
A,direct
C
D
E
0
1
2
3
4
5
XCHD A,@Ri
DJNZ Rr,rel
POP
direct
ACALL
addr11
SETB
bit
SETB
C
DA
A
DJNZ
direct,rel
0
1
2
3
4
5
MOVX A,@Ri
MOV A,@Ri
MOV A,Rr
MOVX
A,@DTPR
AJMP
addr11
CLR
A
MOV
A,direct (1)
0
0
1
0
0
1
2
3
4
5
MOVX @Ri,A
MOV @Ri,A
MOV Rr,A
MOVX
@DTPR,A
ACALL
addr11
CPL
A
MOV
direct,A
F
1
1
2
3
4
5
Note
1. MOV A, ACC is not a valid instruction.
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
19 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
−0.5
MAX.
+6.5
UNIT
VDD
VI
supply voltage
V
input voltage on any pin with respect to ground (VSS
total power dissipation
)
−0.5
−
VDD + 0.5
V
Ptot
Tstg
Tamb
1
W
°C
°C
storage temperature
−65
0
+150
70
operating ambient temperature
20 DC CHARACTERISTICS
DD = 5 V ±10%; VSS = 0 V; Tamb = 0 to +70 °C; all voltages with respect to VSS unless otherwise specified.
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Supply
VDD
IDD
supply voltage
4.5
5.5
60
V
supply current operating
VDD = 6 V; fclk = 24 MHz;
notes 1 and 2
−
mA
IDD(id)
supply current Idle mode
VDD = 6.5 V ±10%; fclk = 24 MHz;
notes 2 and 3
−
−
25
mA
IDD(pd)
supply current Power-down
mode
2 V ≤ VPD ≤ VDD(max); note 4
100
µA
Inputs
VIL
LOW-level input voltage;
except EA
−0.5
−0.5
0.2VDD − 1
0.2VDD − 0.3
V
VIL1
VIH
LOW-level input voltage EA
V
V
HIGH-level input voltage
(except RST and XTAL1)
0.2VDD + 0.9 VDD + 0.5
VIH1
IIL
HIGH-level input voltage
RST and XTAL1
0.7VDD
VDD + 0.5
−50
V
input current logic 0
Ports 1, 2, 3, 4 and 5
VI = 0.45 V
VI = 2.0 V
−
−
µA
µA
IITL
input current HIGH-to-LOW
transition Ports 1, 2, 3,
4 and 5
−650
ILI1
input leakage current Port 0 0.45 < VI < VDD
and EA
−
±10
µA
Outputs
VOL
LOW-level output voltage
Ports 1, 2, 3, 4 and 5
IOL = 1.6 mA; notes 5 and 6
OL = 3.2 mA; notes 5 and 6
−
−
0.45
0.45
V
V
VOL1
VOH
LOW-level output voltage
Port 0, ALE and PSEN
I
HIGH-level output voltage
Ports 1, 2, 3, 4 and 5
IOH = −60 µA; VDD = 5 V ±10%
IOH = −25 µA
2.4
−
−
−
V
V
V
0.75VDD
0.9VDD
I
OH = −10 µA
1998 Apr 07
50
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VOH1
HIGH level output voltage
Port 0 in external bus mode,
ALE, PSEN and RST
IOH = −800 µA; VDD = 5 V ±10%
2.4
−
V
I
I
OH = −300 µA
0.75VDD
0.9VDD
40
−
V
OH = −80 µA; note 7
−
V
RRST
CI/O
RST pull−down resistor
100
10
kΩ
pF
capacitance of input buffer
test frequency = 1 MHz;
−
Tamb = 25 °C
Notes
1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5 ns;
VIL = VSS + 0.5 V; VIH = VDD − 0.5 V; XTAL2 not connected; EA = RST = Port 0 = VDD; the Watchdog Timer is
disabled (by the external reset).
2. IDD(max) at other frequencies can be derived from Fig.28.
3. The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5 ns;
VIL = VSS +0.5 V; VIH = VDD −0.5 V; XTAL2 not connected; the Watchdog Timer is disabled; EA = RST = VSS
Port 0 = P1.6 = P1.7 = VDD
4. The Power-down current is measured with all output pins disconnected; XTAL2 not connected; Watchdog Timer is
disabled; EA = RST = XTAL1 = VSS; Port 0 = P1.6 = P1.7 = VDD
;
.
.
5. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW-level
output voltage of ALE, Port 1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0
and Port 2 pins when these pins make a HIGH-to-LOW transition during bus operations. In the worst cases
(capacitive loading >100 pF) the noise pulse on the ALE line may exceed 0.8 V. In such cases it may be desirable
to provide ALE with a Schmitt trigger, or use an address latch with a Schmitt trigger STROBE input.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
a) Maximum IOL per port pin: 10 mA.
b) Maximum IOL per 8-bit port: Port 0 = 26 mA; Ports 1, 2, 3, 4 and 5 = 15 mA.
c) Maximum total IOL for all output pins: 71 mA.
d) If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current
greater than the listed test conditions.
7. Capacitive loading on Port 0 and Port 2 may cause the HIGH-level output voltage on ALE and PSEN to momentarily
fall below the 0.9VDD specification when the address bits are stabilizing.
1998 Apr 07
51
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
MGK205
30
handbook, halfpage
I
DD
(mA)
maximum active mode
20
typical active mode
10
maximum Idle mode
typical Idle mode
0
0
4
8
12
16
20
frequency (MHz)
Fig.28 IDD as function of frequency; valid only within frequency specifications of the device under test.
21 AC CHARACTERISTICS
DD = 5 V ±10%; VSS = 0 V; Tamb = 0 to +70 °C; tclk(min) = 63 ns; Cl = 100 pF for Port 0, ALE and PSEN; Cl = 80 pF for
all other outputs unless otherwise specified; tclk(min) = 1/fclk(max); fclk = clock frequency; tclk = clock period.
V
12 MHz 16 MHz 24 MHz 40 MHz
VARIABLE CLOCK(1)
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SYMBOL PARAMETER
External program memory
UNIT
MIN.
MAX.
tLHLL
tAVLL
tLLAX
tLLIV
ALE pulse
duration
127
28
48
−
−
85
8
−
43
23
21
−
−
35
10
10
−
−
2tclk − 40
−
−
−
ns
ns
ns
address set-up
time to ALE
−
−
−
−
t
clk − 55
clk − 35
address hold
time after ALE
−
28
−
−
−
−
t
time from ALE to
valid instruction
input
233
150
95
55
−
4tclk − 100 ns
tLLPL
time from ALE to 43
control pulse
PSEN
−
23
−
28
−
10
−
t
clk − 40
−
−
ns
ns
tPLPH
tPLIV
control pulse
205
−
143
−
90
−
60
−
3tclk − 45
duration PSEN
time from PSEN
to valid
−
145
−
83
−
55
−
25
−
3tclk − 105 ns
instruction input
1998 Apr 07
52
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
12 MHz
16 MHz
24 MHz
40 MHz
VARIABLE CLOCK(1)
UNIT
SYMBOL PARAMETER
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
MIN.
MAX.
tPXIX
input instruction
hold time after
PSEN
0
−
0
−
0
−
0
−
0
−
ns
ns
tPXIZ
input instruction
float delay after
PSEN
−
59
−
38
−
8
−
15
−
tclk − 25
tAVIV
address to valid
instruction input
−
−
312
10
−
−
208
10
−
−
125
10
−
65
−
−
5tclk − 105 ns
tPLAZ
PSEN to
address float
time
5
−
10
ns
External data memory
tLHLL
tAVLL
tLLAX
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
ALE pulse
duration
127
28
48
400
400
−
−
85
8
−
43
15
21
149
149
−
−
35
10
10
120
120
−
−
2tclk − 40
−
−
−
−
−
ns
ns
ns
ns
ns
address set-up
time to ALE
−
−
−
−
t
clk − 55
clk − 35
address hold
time after ALE
−
28
275
275
−
−
−
−
t
RD pulse
duration
−
−
−
−
6tclk − 100
WR pulse
duration
−
−
−
−
6tclk − 100
RD to valid data
input
252
−
148
−
118
−
30
−
−
0
−
−
−
5tclk − 165 ns
data hold time
after RD
0
0
0
0
−
ns
ns
data float delay
after RD
−
97
517
585
−
55
350
398
−
40
183
209
174
−
−
15
110
130
90
−
2tclk − 70
time from ALE to
valid data input
−
−
−
−
8tclk − 150 ns
9tclk − 165 ns
address to valid
data input
−
−
−
−
time from ALE to 200 300
RD or WR
138 238
74
91
60
70
3tclk − 50 3tclk + 50 ns
time from
address to RD or
WR
203
−
120
23
3
−
4tclk − 130
−
ns
ns
ns
tWHLH
time from RD or 43
WR HIGH to
ALE HIGH
123
−
103
−
21
21
66
10
5
40
t
clk − 40
clk − 60
tclk + 40
tQVWX
data valid to
23
−
−
t
−
WR transition
1998 Apr 07
53
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
12 MHz
16 MHz
24 MHz
40 MHz
VARIABLE CLOCK(1)
UNIT
SYMBOL PARAMETER
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
MIN.
MAX.
tQVWH
tWHQX
tRLAZ
data set-up time 433
before WR
−
−
0
288
13
−
−
−
0
200
21
−
−
−
0
125
−
−
0
7tclk − 150
−
−
0
ns
ns
ns
data hold time
after WR
33
5
tclk − 50
address float
−
−
−
delay after RD
Note
1. The operating frequency is limited to: 3.5 MHz ≤ fclk ≤ 40 MHz.
Table 35 External clock drive XTAL1
VARIABLE CLOCK
MIN. MAX.
SYMBOL
PARAMETER
clock frequency
UNIT
fclk
3.5
63
20
20
−
40
MHz
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
tCY
clock period
high time
833
ns
ns
ns
ns
ns
µs
t
clk − tCLCX
clk − tCHCX
low time
t
rise time
20
20
10
fall time
−
cycle time (tCY = 12tclk)
0.75
t
t
t
CHCL
CHCX
CLCH
V
V
V
V
IH1
IH1
IH1
IH1
0.8 V
0.8 V
0.8 V
0.8 V
t
CLCX
t
MLA856
CLCL
Fig.29 External clock drive XTAL1.
1998 Apr 07
54
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
V
− 0.5
DD
0.2V
0.2V
+ 0.9
− 0.1
DD
DD
0.45 V
MGK209
a. Output waveform.
V
V
+ 0.1 V
− 0.1 V
V
V
− 0.1 V
LOAD
LOAD
OH
OL
timing
reference points
V
LOAD
+ 0.1 V
MGK210
b. Float waveform
AC testing inputs are driven at 2.4 V for a logic 1 and 0.45 V for a logic 0.
Timing measurements are taken at 2.0 V for a logic 1 and 0.8 V for a logic 0, see Fig.30a.
The float state is defined as the point at which a Port 0 pin sinks 3.2 mA or sources 400 µA at
the voltage test levels, see Fig.30b.
Fig.30 AC testing input.
1998 Apr 07
55
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
one machine cycle
one machine cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
P1 P2
P1 P2
P1 P2 P1 P2 P1 P2
P1 P2 P1 P2 P1 P2
P1 P2 P1 P2 P1 P2
P1 P2
XTAL1
INPUT
ALE
PSEN
RD
dotted lines
are valid when
RD or WR are
active
only active
during a read
from external
data memory
only active
during a write
to external
WR
data memory
BUS
(PORT 0)
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
external
program
memory
fetch
PORT 2
address A8 - A15
address A8 - A15
address A8 - A15
address A8 - A15
BUS
(PORT 0)
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
address
A0 - A7
data output or data input
read or
write of
external data
memory
address A8 - A15
address A8 - A15 or Port 2 out
address A8 - A15
PORT 2
PORT
OUTPUT
old data
new data
PORT
INPUT
sampling time of I/O port pins during input (including INT0 and INT1)
SERIAL
PORT
CLOCK
MGA180
Fig.31 Instruction cycle timing.
56
1998 Apr 07
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
21.1 Serial Port characteristics
Table 36 Serial Port timing: Shift Register mode
VDD = 5 V ±10%; VSS = 0 V; Tamb = 0 to 70 °C; load capacitance = 80 pF.
12 MHz
OSCILLATOR
VARIABLE OSCILLATOR
UNIT
SYMBOL
PARAMETER
MIN.
MAX.
MIN.
12tclk
MAX.
tXLXL
Serial Port clock cycle time
1
−
−
−
−
−
−
−
−
µs
ns
ns
ns
ns
tQVXH
tXHQX
tXHDX
tXHDV
output data set-up to clock rising edge 700
output data hold after clock rising edge 50
10tclk − 133
2tclk − 117
input data hold after clock rising edge
clock rising edge to input data valid
0
0
−
700
−
10tclk − 133
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
t
XLXL
CLOCK
t
XHQX
t
QVXH
OUTPUT DATA
WRITE TO SBUF
INPUT DATA
t
XHDX
SET TI
t
XHDV
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CLEAR RI
SET RI
MGA179
Fig.32 Shift register mode timing.
1998 Apr 07
57
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
21.2 Timing waveforms
t
ALE
LHLL
t
t
t
PLPH
AVLL
LLPL
t
PLIV
PSEN
PORT 0
PORT 2
t
t
PXIZ
PLAZ
t
t
LLAX
PXIX
instr in
A0 to A7
A0 to A7
t
LLIV
t
AVIV
A0 to A15
A8 to A15
MGK206
Fig.33 External program memory read cycle.
ALE
t
WHLH
PSEN
RD
t
LLDV
t
t
LLWL
RLRH
t
t
t
RHDZ
RLAZ
RLDV
t
t
t
AVLL
LLAX
RHDX
data in
A0 to A7
from RI or DPL
PORT 0
PORT 2
A0 to A7 from PCL
instr in
t
AVWL
t
AVDV
P2.0 to P2.7 or A8 to A15 from DPH
A0 to A15 from PCH
MGK207
Fig.34 External data memory read cycle.
58
1998 Apr 07
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
ALE
t
WHLH
PSEN
t
AVWL
t
t
LLWL
WLWH
WR
t
t
WHQX
QVWX
t
t
AVLL
LLAX
A0 to A7
from RI or DPL
PORT 0
PORT 2
data output
A0 to A7 from PCL
instr in
P2.0 to P2.7 or A8 to A15 from DPF
A0 to A15 from PCH
MGK208
Fig.35 External data memory write cycle.
• P = PSEN
21.3 Timing symbol naming conventions
• Q = output data
• R = RD signal
• t = time
Each timing symbol has five characters. The first character
is always a ‘t’ (= time). The remaining four characters of
the symbol (typed in subscript), depending on their relative
positions, indicate the name of a signal or the logical status
of that signal. The designations are as follows:
• V = valid
• W = WR signal
• A = address
• X = no longer a valid logic level
• Z = float.
• C = clock
• D = input data
Examples:
• H = logic level HIGH
• I = instruction (program memory contents)
• L = Logic level LOW or ALE
tAVLL = time for address valid to ALE LOW
tLLPL = time for ALE LOW to PSEN LOW.
1998 Apr 07
59
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
22 PACKAGE OUTLINES
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
D
M
E
A
2
A
L
A
1
c
e
w M
Z
b
1
(e )
1
b
M
H
40
21
pin 1 index
E
1
20
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
w
UNIT
mm
b
b
c
D
E
e
e
L
M
M
1
1
E
H
max.
min.
max.
max.
1.70
1.14
0.53
0.38
0.36
0.23
52.50
51.50
14.1
13.7
3.60
3.05
15.80
15.24
17.42
15.90
4.7
0.51
4.0
2.54
0.10
15.24
0.60
0.254
0.01
2.25
0.067
0.045
0.021
0.015
0.014
0.009
2.067
2.028
0.56
0.54
0.14
0.12
0.62
0.60
0.69
0.63
inches
0.19
0.020
0.16
0.089
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-14
SOT129-1
051G08
MO-015AJ
1998 Apr 07
60
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
QFP64: plastic quad flat package;
64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
SOT319-1
y
X
A
51
33
52
32
Z
E
e
A
2
H
A
E
(A )
3
E
A
1
θ
w M
p
L
pin 1 index
p
b
L
20
64
detail X
1
19
w M
Z
v
M
M
D
A
b
p
e
D
B
H
v
B
D
0
5
scale
10 mm
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
D
E
p
D
max.
7o
0o
0.36 2.87
0.10 2.57
0.50 0.25 20.1 14.1
0.35 0.13 19.9 13.9
24.2 18.2
23.6 17.6
1.0
0.6
1.2
0.8
1.2
0.8
mm
3.3
0.25
1
1.95
0.2
0.2
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-08-01
SOT319-1
1998 Apr 07
61
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
“Data Handbook IC26; Integrated Circuit Packages;
Section: Packing Methods”.
23 SOLDERING
23.1 Introduction
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
23.3.2 WAVE SOLDERING
23.3.2.1 PLCC
23.2 DIP
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
23.2.1 SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
• The package footprint must incorporate solder thieves at
the downstream corners.
23.3.2.2 QFP
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
23.2.2 REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
CAUTION
Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.
If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
23.3 PLCC and QFP
23.3.1 REFLOW SOLDERING
Reflow soldering techniques are suitable for all PLCC and
QFP packages.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
The choice of heating method may be influenced by larger
plastic PLCC and QFP packages (44 leads, or more).
If infrared or vapour phase heating is used and the large
packages are not absolutely dry (less than 0.1% moisture
content by weight), vaporization of the small amount of
moisture in them can cause cracking of the plastic body.
For details, refer to the Drypack information in the
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
1998 Apr 07
62
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
23.3.2.3 Method (PLCC and QFP)
23.3.3 REPAIRING SOLDERED JOINTS
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
24 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
25 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Apr 07
63
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© Philips Electronics N.V. 1998
SCA59
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
455104/1200/02/pp64
Date of release: 1998 Apr 07
Document order number: 9397 750 03529
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