P89LPC917FDH,129 [NXP]

P89LPC915/916/917 - 8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converter TSSOP 16-Pin;


型号：	P89LPC917FDH,129
厂家：	NXP
描述：	P89LPC915/916/917 - 8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converter TSSOP 16-Pin 时钟 PC 微控制器光电二极管外围集成电路
文件：	总75页 (文件大小：336K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

2 kB 3 V ﬂash with 8-bit A/D converter

Rev. 05 — 15 December 2009

Product data sheet

1. General description

The P89LPC915/916/917 are single-chip microcontrollers, available in low-cost packages,

based on a high performance processor architecture that executes instructions in two to

four clocks, six times the rate of standard 80C51 devices. Many system-level functions

have been incorporated into the P89LPC915/916/917 in order to reduce component

count, board space, and system cost.

2. Features

2.1 Principal features

I 2 kB byte-erasable ﬂash code memory organized into 256-byte sectors and 16-byte

pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.

I 256-byte RAM data memory.

I Two 16-bit counter/timers. Timer 0 (and Timer 1 - P89LPC917) may be conﬁgured to

toggle a port output upon timer overﬂow or to become a PWM output.

I 23-bit system timer that can also be used as a Real-Time clock.

I 4-input multiplexed 8-bit A/D converter/single DAC output. Two analog comparators

with selectable reference.

I Enhanced UART with fractional baud rate generator, break detect, framing error

detection, automatic address detection and versatile interrupt capabilities.

I SPI communication port (P89LPC916).

I Internal RC oscillator option allows operation without external oscillator components.

The RC oscillator (factory calibrated to ±1 %) option is selectable and ﬁne tunable.

I 2.4 V to 3.6 V V_DDoperating range. I/O pins are 5 V tolerant (may be pulled up or

driven to 5.5 V).

I Up to 14 I/O pins when using internal oscillator and reset options (P89LPC916,

P89LPC917).

2.2 Additional features

I 14-pin (P89LPC915) and 16-pin (P89LPC916, P89LPC917) TSSOP packages.

I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns

for all instructions except multiply and divide when executing at 18 MHz. This is six

times the performance of the standard 80C51 running at the same clock frequency. A

lower clock frequency for the same performance results in power savings and reduced

EMI.

I In-Application Programming (IAP-Lite) and byte erase allows code memory to be used

for non-volatile data storage.

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

I Serial Flash In-Circuit Programming (ICP) allows simple production coding with

commercial EPROM programmers. Flash security bits prevent reading of sensitive

application programs.

I Watchdog timer with separate on-chip oscillator, requiring no external components.

The Watchdog prescaler is selectable from 8 values.

I Low voltage brownout detect allows a graceful system shutdown when power fails.

May optionally be conﬁgured as an interrupt.

I Idle and two different power-down reduced power modes. Improved wake-up from

Power-down mode (a LOW interrupt input starts execution). Typical power-down

current is 1 µA (total power-down with voltage comparators disabled).

I Active-LOW reset. On-chip power-on reset allows operation without external reset

components. A reset counter and reset glitch suppression circuitry prevent spurious

and incomplete resets. A software reset function is also available.

I Programmable port output conﬁguration options: quasi-bidirectional, open drain,

push-pull, input-only.

I Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of

the pins match or do not match a programmable pattern.

I LED drive capability (20 mA) on all port pins. A maximum limit is speciﬁed for the

entire chip.

I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns

minimum ramp times.

I Only power and ground connections are required to operate the P89LPC915/916/917

when internal reset option is selected.

I Four interrupt priority levels.

I Five (P89LPC916), six (P89LPC915), or seven (P89LPC917) keypad interrupt inputs.

I Second data pointer.

I Schmitt trigger port inputs.

I Emulation support.

3. Product comparison overview

Table 1 highlights the differences between these three devices. For a complete list of

device features, please see Section 2 “Features”.

Table 1.

Product comparison overview

Type number Comparator 2 SPI

output

T1 toggle/PWM CLKOUT INT1

KBI

P89LPC915

P89LPC916

P89LPC917

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

2 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

4. Ordering information

Table 2.

Ordering information

Type number

Package

Name

Description

Version

P89LPC915FDH

TSSOP14 plastic thin shrink small outline package;

14 leads; body width 4.4 mm

SOT402-1

P89LPC915FN

DIP14

plastic dual in-line package; 14 leads (300 mil)

SOT27-1

P89LPC915HDH

TSSOP14 plastic thin shrink small outline package;

14 leads; body width 4.4 mm

SOT402-1

P89LPC916FDH

P89LPC917FDH

TSSOP16 plastic thin shrink small outline package;

16 leads; body width 4.4 mm

SOT403-1

TSSOP16 plastic thin shrink small outline package;

16 leads; body width 4.4 mm

4.1 Ordering options

Table 3.

Ordering options^[1]

Type number

P89LPC915FDH

P89LPC915FN

P89LPC916FDH

P89LPC917FDH

P89LPC915HDH

Temperature range

Frequency

−40 °C to +85 °C

0 MHz to 18 MHz

−40 °C to +125 °C

[1] Please contact your local NXP sales ofﬁce for availability of extended temperature (−40 °C to +125 °C)

versions of the P89LPC916 and P89LPC917 devices.

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

3 of 75

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NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

5. Block diagram

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

P89LPC915

TXD

2 kB CODE FLASH

UART

RXD

internal bus

SCL

256 BYTE DATA RAM

I C

SDA

AD10

AD11

AD12

AD13

DAC1

PORT 1

CONFIGURABLE I/O

P1[5:0]

P0[5:0]

ADC1/DAC1

PORT 0

CONFIGURABLE I/O

REAL TIME CLOCK/

SYSTEM TIMER

TIMER 0

TIMER 1

KEYPAD INTERRUPT

CMP2

CIN2B

CIN2A

CIN1A

CIN1B

CMPREF

ANALOG

COMPARATORS

WATCHDOG TIMER

AND OSCILLATOR

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

PROGRAMMABLE

OSCILLATOR DIVIDER

CPU clock

external clock

input

ON-CHIP RC

OSCILLATOR

002aaa822

Fig 1. P89LPC915 block diagram

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

4 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

P89LPC916

TXD

2 kB CODE FLASH

UART

RXD

internal bus

SCL

256 BYTE DATA RAM

I C

SDA

AD10

AD11

AD12

AD13

DAC1

PORT 2

CONFIGURABLE I/O

ADC1/DAC1

SPI

P2[5:2]

P1.5, P1[3:0]

P0[5:1]

SPICLK

MOSI

MISO

PORT 1

CONFIGURABLE I/O

REAL TIME CLOCK/

SYSTEM TIMER

PORT 0

CONFIGURABLE I/O

TIMER 0

TIMER 1

KEYPAD INTERRUPT

CIN2B

CIN2A

CIN1A

CIN1B

CMPREF

ANALOG

COMPARATORS

WATCHDOG TIMER

AND OSCILLATOR

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

PROGRAMMABLE

OSCILLATOR DIVIDER

CPU clock

external clock

input

ON-CHIP RC

OSCILLATOR

002aaa823

Fig 2. P89LPC916 block diagram

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

5 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

P89LPC917

TXD

2 kB CODE FLASH

UART

RXD

internal bus

SCL

256 BYTE DATA RAM

I C

SDA

AD10

AD11

AD12

AD13

DAC1

PORT 2

CONFIGURABLE I/O

P2.2

P1[5:0]

ADC1/DAC1

PORT 1

CONFIGURABLE I/O

REAL TIME CLOCK/

SYSTEM TIMER

PORT 0

CONFIGURABLE I/O

TIMER 0

TIMER 1

P0.7, P[5:0]

CMP2

CIN2B

CIN2A

CIN1A

CIN1B

CMPREF

ANALOG

COMPARATORS

KEYPAD INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

PROGRAMMABLE

OSCILLATOR DIVIDER

CPU clock

external clock

input

ON-CHIP RC

OSCILLATOR

clkout

002aaa824

Fig 3. P89LPC917 block diagram

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

6 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

6. Functional diagram

KBI0

CMP2

CIN2B

TXD

RXD

AD10

AD11

AD12

AD13

CLKIN

KBI1

KBI2

KBI3

KBI4

KBI5

CIN2A

SCL

SDA

PORT 0

PORT 1

CIN1B

INT0

INT1

RST

P89LPC915

DAC1

CIN1A

CMPREF

002aaa828

Fig 4. P89LPC915 functional diagram

TXD

RXD

KBI1

KBI2

KBI3

KBI4

KBI5

CIN2B

CIN2A

AD10

AD11

AD12

AD13

CLKIN

SCL

SDA

PORT 1

CIN1B

INT0

PORT 0

DAC1

CIN1A

P89LPC916

CMPREF

RST

MOSI

MIS0

PORT 2

SPICLK

002aaa829

Fig 5. P89LPC916 functional diagram

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

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P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

KBI0

KBI1

KBI2

KBI3

KBI4

KBI5

KBI7

CMP2

CIN2B

CIN2A

CIN1B

CIN1A

CMPREF

TXD

RXD

AD10

AD11

AD12

SCL

SDA

PORT 1

PORT 2

INT0

INT1

RST

PORT 0

P89LPC917

AD13

DAC1

CLKIN

CLKOUT

002aaa830

Fig 6. P89LPC917 functional diagram

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

8 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

7. Pinning information

7.1 Pinning

P0.1/CIN2B/KBI1/AD10

P0.0/CMP2/KBI0

P1.5/RST

P0.2/CIN2A/KBI2/AD11

P0.3/CIN1B/KBI3/AD12

P0.4/CIN1A/KBI4/AD13/DAC1

P0.5/CMPREF/KBI5/CLKIN

P89LPC915

P1.4/INT1

P1.3/INT0/SDA

P1.2/T0/SCL

P1.0/TXD

P1.1/RXD

002aaa825

Fig 7. P89LPC915 TSSOP14 pin conﬁguration

P0.1/CIN2B/KBI1/AD10

P0.0/CMP2/KBI0

P1.5/RST

P0.2/CIN2A/KBI2/AD11

P0.3/CIN1B/KBI3/AD12

P0.4/CIN1A/KBI4/AD13/DAC1

P0.5/CMPREF/KBI5/CLKIN

P89LPC915

P1.4/INT1

P1.3/INT0/SDA

P1.2/T0/SCL

P1.0/TXD

P1.1/RXD

002aaf085

Fig 8. P89LPC915 DIP14 pin conﬁguration

P0.1/CIN2B/KBI1/AD10

P2.4/SS

P0.2/CIN2A/KBI2/AD11

P0.3/CIN1B/KBI3/AD12

P1.5/RST

P0.4/CIN1A/KBI4/AD13/DAC1

P0.5/CMPREF/KBI5/CLKIN

P89LPC916

P2.3/MISO

P2.2/MOSI

P2.5/SPICLK

P1.0/TXD

P1.3/INT0/SDA

P1.2/T0/SCL

P1.1/RXD

002aaa826

Fig 9. P89LPC916 TSSOP16 pin conﬁguration

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

9 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

P0.1/CIN2B/KBI1/AD10

P0.0/CMP2/KBI0

P1.5/RST

P0.2/CIN2A/KBI2/AD11

P0.3/CIN1B/KBI3/AD12

P0.4/CIN1A/KBI4/AD13/DAC1

P0.5/CMPREF/KBI5/CLKIN

P89LPC917

P2.2

P1.4/INT1

P0.7/T1/KBI7/CLKOUT

P1.0/TXD

P1.3/INT0/SDA

P1.2/T0/SCL

P1.1/RXD

002aaa827

Fig 10. P89LPC917 TSSOP16 pin conﬁguration

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

10 of 75

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NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

7.2 Pin description

Table 4.

Symbol

P89LPC915 pin description

Type Description

P0.0 to P0.5

I/O

Port 0: Port 0 is a 6-bit I/O port with a user-conﬁgurable output type.

During reset Port 0 latches are conﬁgured in the input only mode with the

internal pull-up disabled. The operation of Port 0 pins as inputs and

outputs depends upon the port conﬁguration selected. Each port pin is

conﬁgured independently. Refer to Section 8.13.1 “Port conﬁgurations”

and Table 15 “Static characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

P0.0 — Port 0 bit 0.

P0.0/CMP2/KBI0

I/O

CMP2 — Comparator 2 output.

KBI0 — Keyboard input 0.

P0.1/CIN2B/KBI1/AD10

I/O

P0.1 — Port 0 bit 1.

CIN2B — Comparator 2 positive input B.

KBI1 — Keyboard input 1.

AD10 — ADC1 channel 0 analog input.

P0.2 — Port 0 bit 2.

P0.2/CIN2A/KBI2/AD11

P0.3/CIN1B/KBI3/AD12

I/O

CIN2A — Comparator 2 positive input A.

KBI2 — Keyboard input 2.

AD11 — ADC1 channel 1 analog input.

P0.3 — Port 0 bit 3.

I/O

CIN1B — Comparator 1 positive input B.

KBI3 — Keyboard input 3.

AD12 — ADC1 channel 2 analog input.

P0.4 — Port 0 bit 4.

P0.4/CIN1A/KBI4/AD13/

DAC1

I/O

CIN1A — Comparator 1 positive input A.

KBI4 — Keyboard input 4.

AD13 — ADC1 channel 3 analog input.

DAC1 — DAC1 analog output.

P0.5 — Port 0 bit 5.

P0.5/CMPREF/KBI5/CLKIN 11

I/O

CMPREF — Comparator reference (negative) input.

KBI5 — Keyboard input 5.

CLKIN — External clock input.

P1.0 to P1.5

I/O, I Port 1: Port 1 is a 6-bit I/O port with a user-conﬁgurable output type,

[1]

except for three pins as noted below. During reset Port 1 latches are

conﬁgured in the input only mode with the internal pull-up disabled. The

operation of the conﬁgurable Port 1 pins as inputs and outputs depends

upon the port conﬁguration selected. Each of the conﬁgurable port pins

are programmed independently. Refer to Section 8.13.1 “Port

conﬁgurations” and Table 15 “Static characteristics” for details. P1.2 to

P1.3 are open drain when used as outputs. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

11 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

Table 4.

Symbol

P1.0/TXD

P89LPC915 pin description …continued

Type Description

I/O

P1.0 — Port 1 bit 0.

TXD — Transmitter output for serial port.

P1.1 — Port 1 bit 1.

P1.1/RXD

I/O

RXD — Receiver input for serial port.

P1.2 — Port 1 bit 2 (open-drain when used as output).

P1.2/T0/SCL

I/O

T0 — Timer/counter 0 external count input or overﬂow output (open-drain

when used as output).

I/O

SCL — I²C serial clock input/output.

P1.3 — Port 1 bit 3 (open-drain when used as output).

INT0 — External interrupt 0 input.

SDA — I²C serial data input/output.

P1.4 — Port 1 bit 4.

P1.3/INT0/SDA

I/O

P1.4/INT1

P1.5/RST

INT1 — External interrupt 1 input.

P1.5 — Port 1 bit 5 (input only).

RST — External Reset input during power-on or if selected via UCFG1.

When functioning as a reset input, a LOW on this pin resets the

microcontroller, causing I/O ports and peripherals to take on their default

states, and the processor begins execution at address 0. Also used

during a power-on sequence to force ISP mode. When using an

oscillator frequency above 12 MHz, the reset input function of P1.5

must be enabled. An external circuit is required to hold the device in

reset at power-up until V_DDhas reached its speciﬁed level. When

system power is removed V_DDwill fall below the minimum speciﬁed

operating voltage. When using an oscillator frequency above

12 MHz, in some applications, an external brownout detect circuit

may be required to hold the device in reset when V_DDfalls below the

minimum speciﬁed operating voltage.

V_SS

V_DD

Ground: 0 V reference.

Power supply: This is the power supply voltage for normal operation as

well as Idle and Power-down modes.

[1] Input/output for P1.0 to P1.4. Input for P1.5.

Table 5.

Symbol

P89LPC916 pin description

Type Description

I/O

P0.0 to P0.5

Port 0: Port 0 is an 6-bit I/O port with a user-conﬁgurable output type.

During reset Port 0 latches are conﬁgured in the input only mode with

the internal pull-up disabled. The operation of Port 0 pins as inputs and

outputs depends upon the port conﬁguration selected. Each port pin is

conﬁgured independently. Refer to Section 8.13.1 “Port conﬁgurations”

and Table 15 “Static characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

12 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

Table 5.

P89LPC916 pin description …continued

Symbol

Type Description

P0.1/CIN2B/KBI1/AD10

I/O

P0.1 — Port 0 bit 1.

CIN2B — Comparator 2 positive input B.

KBI1 — Keyboard input 1.

AD10 — ADC1 channel 0 analog input.

P0.2 — Port 0 bit 2.

P0.2/CIN2A/KBI2/AD11

P0.3/CIN1B/KBI3/AD12

I/O

CIN2A — Comparator 2 positive input A.

KBI2 — Keyboard input 2.

AD11 — ADC1 channel 1 analog input.

P0.3 — Port 0 bit 3.

I/O

CIN1B — Comparator 1 positive input B.

KBI3 — Keyboard input 3.

AD12 — ADC1 channel 2 analog input.

P0.4 — Port 0 bit 4.

P0.4/CIN1A/KBI4/AD13/DAC1 14

I/O

CIN1A — Comparator 1 positive input A.

KBI4 — Keyboard input 4.

AD13 — ADC1 channel 3 analog input.

DAC1 — DAC1 analog output.

P0.5 — Port 0 bit 5.

P0.5/CMPREF/KBI5/CLKIN

P1.0 to P1.5

I/O

CMPREF — Comparator reference (negative) input.

KBI5 — Keyboard input 5.

CLKIN — External clock input.

I/O, I Port 1: Port 1 is an 6-bit I/O port with a user-conﬁgurable output type,

[1]

except for three pins as noted below. During reset Port 1 latches are

conﬁgured in the input only mode with the internal pull-up disabled. The

operation of the conﬁgurable Port 1 pins as inputs and outputs depends

upon the port conﬁguration selected. Each of the conﬁgurable port pins

are programmed independently. Refer to Section 8.13.1 “Port

conﬁgurations” and Table 15 “Static characteristics” for details. P1.2 to

P1.3 are open drain when used as outputs. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

P1.0/TXD

I/O

P1.0 — Port 1 bit 0.

TXD — Transmitter output for serial port.

P1.1 — Port 1 bit 1.

P1.1/RXD

P1.2/T0/SCL

I/O

RXD — Receiver input for serial port.

P1.2 — Port 1 bit 2 (open-drain when used as output).

I/O

T0 — Timer/counter 0 external count input or overﬂow output

(open-drain when used as output).

I/O

SCL — I²C serial clock input/output.

P1.3 — Port 1 bit 3 (open-drain when used as output).

INT0 — External interrupt 0 input.

P1.3/INT0/SDA

P1.5/RST

I/O

SDA — I²C serial data input/output.

P1.5 — Port 1 bit 5 (input only).

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

13 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

Table 5.

Symbol

P89LPC916 pin description …continued

Type Description

RST — External Reset input during power-on or if selected via UCFG1.

When functioning as a reset input, a LOW on this pin resets the

microcontroller, causing I/O ports and peripherals to take on their

default states, and the processor begins execution at address 0. Also

used during a power-on sequence to force ISP mode. When using an

oscillator frequency above 12 MHz, the reset input function of P1.5

must be enabled. An external circuit is required to hold the device

in reset at power-up until V_DDhas reached its speciﬁed level. When

system power is removed V_DDwill fall below the minimum

speciﬁed operating voltage. When using an oscillator frequency

above 12 MHz, in some applications, an external brownout detect

circuit may be required to hold the device in reset when V_DDfalls

below the minimum speciﬁed operating voltage.

P2.2 to P2.5

Port 2: Port 2 is a 4-bit I/O port with a user-conﬁgurable output type.

During reset Port 2 latches are conﬁgured in the input only mode with

the internal pull-up disabled. The operation of Port 2 pins as inputs and

outputs depends upon the port conﬁguration selected. Each port pin is

conﬁgured independently. Refer to Section 8.13.1 “Port conﬁgurations”

and Table 15 “Static characteristics” for details.

All pins have Schmitt triggered inputs.

Port 2 also provides various special functions as described below:

P2.2 — Port 2 bit 2.

P2.2/MOSI

P2.3/MISO

I/O

MOSI — SPI master out slave in. When conﬁgured as master, this pin is

output; when conﬁgured as slave, this pin is input.

I/O

P2.3 — Port 2 bit 3.

MISO — When conﬁgured as master, this pin is input, when conﬁgured

as slave, this pin is output.

P2.4/SS

I/O

P2.4 — Port 2 bit 4.

SS — SPI Slave select.

P2.5 — Port 2 bit 5.

P2.5/SPICLK

SPICLK — SPI clock. When conﬁgured as master, this pin is output;

when conﬁgured as slave, this pin is input.

V_SS

V_DD

Ground: 0 V reference.

Power supply: This is the power supply voltage for normal operation as

well as Idle and Power-down modes.

[1] Input/output for P1.0 to P1.3. Input for P1.5.

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

14 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

Table 6.

P89LPC917 pin description

Symbol

Type Description

P0.0 to P0.5, P0.7

I/O

Port 0: Port 0 is a 7-bit I/O port with a user-conﬁgurable output type.

During reset Port 0 latches are conﬁgured in the input only mode with the

internal pull-up disabled. The operation of Port 0 pins as inputs and

outputs depends upon the port conﬁguration selected. Each port pin is

conﬁgured independently. Refer to Section 8.13.1 “Port conﬁgurations”

and Table 15 “Static characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

P0.0 — Port 0 bit 0.

P0.0/CMP2/KBI0

I/O

CMP2 — Comparator 2 output.

KBI0 — Keyboard input 0.

P0.1/CIN2B/KBI1/AD10

I/O

P0.1 — Port 0 bit 1.

CIN2B — Comparator 2 positive input B.

KBI1 — Keyboard input 1.

AD10 — ADC1 channel 0 analog input.

P0.2 — Port 0 bit 2.

P0.2/CIN2A/KBI2/AD11

P0.3/CIN1B/KBI3/AD12

I/O

CIN2A — Comparator 2 positive input A.

KBI2 — Keyboard input 2.

AD11 — ADC1 channel 1 analog input.

P0.3 — Port 0 bit 3.

I/O

CIN1B — Comparator 1 positive input B.

KBI3 — Keyboard input 3.

AD12 — ADC1 channel 2 analog input.

P0.4 — Port 0 bit 4.

P0.4/CIN1A/KBI4/AD13/

DAC1

I/O

CIN1A — Comparator 1 positive input A.

KBI4 — Keyboard input 4.

AD13 — ADC1 channel 3 analog input.

DAC1 — DAC1 analog output.

P0.5 — Port 0 bit 5.

P0.5/CMPREF/KBI5

I/O

CMPREF — Comparator reference (negative) input.

KBI5 — Keyboard input 5.

CLKIN — External clock input.

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

15 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

Table 6.

P89LPC917 pin description …continued

Symbol

Type Description

P0.7/T1/KBI7/CLKOUT

I/O

P0.7 — Port 0 bit 7.

T1 — Timer/counter 1 external count input or overﬂow output.

KBI7 — Keyboard input 7.

CLKOUT — Clock output.

P1.0 to P1.5

I/O, I Port 1: Port 1 is a 6-bit I/O port with a user-conﬁgurable output type,

[1]

except for three pins as noted below. During reset Port 1 latches are

conﬁgured in the input only mode with the internal pull-up disabled. The

operation of the conﬁgurable Port 1 pins as inputs and outputs depends

upon the port conﬁguration selected. Each of the conﬁgurable port pins

are programmed independently. Refer to Section 8.13.1 “Port

conﬁgurations” and Table 15 “Static characteristics” for details. P1.2 to

P1.3 are open drain when used as outputs. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

P1.0/TXD

I/O

P1.0 — Port 1 bit 0.

TXD — Transmitter output for serial port.

P1.1 — Port 1 bit 1.

P1.1/RXD

P1.2/T0/SCL

I/O

RXD — Receiver input for serial port.

P1.2 — Port 1 bit 2 (open-drain when used as output).

I/O

T0 — Timer/counter 0 external count input or overﬂow output (open-drain

when used as output).

I/O

SCL — I²C serial clock input/output.

P1.3 — Port 1 bit 3 (open-drain when used as output).

INT0 — External interrupt 0 input.

SDA — I²C serial data input/output.

P1.4 — Port 1 bit 4.

P1.3/INT0/SDA

I/O

P1.4/INT1

P1.5/RST

INT1 — External interrupt 1 input.

P1.5 — Port 1 bit 5 (input only).

RST — External Reset input during power-on or if selected via UCFG1.

When functioning as a reset input, a LOW on this pin resets the

microcontroller, causing I/O ports and peripherals to take on their default

states, and the processor begins execution at address 0. Also used

during a power-on sequence to force ISP mode. When using an

oscillator frequency above 12 MHz, the reset input function of P1.5

must be enabled. An external circuit is required to hold the device in

reset at power-up until V_DDhas reached its speciﬁed level. When

system power is removed V_DDwill fall below the minimum speciﬁed

operating voltage. When using an oscillator frequency above

12 MHz, in some applications, an external brownout detect circuit

may be required to hold the device in reset when V_DDfalls below the

minimum speciﬁed operating voltage.

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

16 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

Table 6.

Symbol

P2.2

P89LPC917 pin description …continued

Type Description

Port 2: Port 2 is a single bit I/O port with a user-conﬁgurable output type.

During reset Port 2 latches are conﬁgured in the input only mode with the

internal pull-up disabled. The operation of this Port 2 pin as an input and

output depends upon the port conﬁguration selected. Refer to Section

8.13.1 “Port conﬁgurations” and Table 15 “Static characteristics” for

details.

This pin has a Schmitt triggered input.

V_SS

V_DD

Ground: 0 V reference.

Power supply: This is the power supply voltage for normal operation as

well as Idle and Power-down modes.

[1] Input/output for P1.0 to P1.4. Input for P1.5.

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

17 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

8. Functional description

8.1 Special function registers

Remark: SFR accesses are restricted in the following ways:

• User must not attempt to access any SFR locations not deﬁned.

• Accesses to any deﬁned SFR locations must be strictly for the functions for the SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise speciﬁed, must be written with ‘0’, but can return any value

when read (even if it was written with ‘0’). It is a reserved bit and may be used in

future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.

– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

18 of 75

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Table 7.

P89LPC915 special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex Binary

Bit address

E0H

ACC*

Accumulator

ADCI1 ENADC1 ADCS11 ADCS10 00

0000 0000

ADCON1

ADC control register 1

97H

ENBI1

ENADCI

TMM1

EDGE1

0000 0000

ADINS

ADC input select

A3H

C0H

A1H

ADI13

BNDI1

CLK2

ADI12

BURST1

CLK1

ADI11

SCC1

CLK0

ADI10

SCAN1

0000 0000

000x 0000

1111 1111

0000 0000

0000 00x0

ADMODA

ADMODB

AD1BH

ADC mode register A

ADC mode register B

ENDAC1

BSA1

A/D_1 boundary high register C4H

A/D_1 boundary low register BCH

AD1BL

AD1DAT0

AD1DAT1

AD1DAT2

AD1DAT3

AUXR1

A/D_1 data register 0

A/D_1 data register 1

A/D_1 data register 2

A/D_1 data register 3

Auxiliary function register

D5H

D6H

D7H

F5H

A2H CLKLP

EBRR

ENT0

SRST

DPS

Bit address

F0H

B register

0000 0000

BRGR0

BRGR1

BRGCON

CMP1

CMP2

DIVM

Baud rate generator rate low BEH

Baud rate generator rate high BFH

Baud rate generator control

BDH

SBRGS BRGEN 00^[2]xxxx xx00

Comparator 1 control register ACH

Comparator 2 control register ADH

CPU clock divide-by-M control 95H

Data pointer (2 bytes)

CE1

CE2

CP1

CP2

CN1

CN2

CO1

CO2

CMF1 00^[1]xx00 0000

CMF2 00^[1]xx00 0000

OE2

0000 0000

DPTR

DPH

Data pointer high

83H

82H

E7H

E6H

0000 0000

DPL

Data pointer low

FMADRH

FMADRL

Program ﬂash address high

Program ﬂash address low

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P89LPC915 special function registers …continued

Table 7.

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex Binary

FMCON

Program ﬂash control (Read) E4H

BUSY

HVA

HVE

0111 0000

Program ﬂash control (Write) E4H FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD.

FMDATA

I2ADR

Program ﬂash data

I²C slave address register

E5H

DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0

0000 0000

Bit address

I2CON*

I2DAT

I²C control register

I²C data register

D8H

DAH

DDH

I2EN

STA

STO

CRSEL 00

x000 00x0

I2SCLH

Serial clock generator/SCL

duty cycle register high

0000 0000

1111 1000

I2SCLL

I2STAT

Serial clock generator/SCL

duty cycle register low

I²C status register

DCH

D9H

STA.4

EAD

STA.3

STA.2

STA.1

STA.0

Bit address

A8H

IEN0*

IEN1*

Interrupt enable 0

Interrupt enable 1

EWDRT

EBO

ES/ESR

ET1

EX1

ET0

EX0

0000 0000

Bit address

E8H

EST

EKBI

EI2C

00^[1]00x0 0000

Bit address

B8H

IP0*

Interrupt priority 0

PWDRT

PBO

PBOH

PS/PSR

PT1

PT1H

PX1

PX1H

PT0

PT0H

PX0

PX0H

00^[1]x000 0000

IP0H

Interrupt priority 0 high

B7H

PWDRT

PSH/

PSRH

Bit address

F8H

PAD

PADH

PST

PSTH

PCH

IP1*

Interrupt priority 1

PKBI

PKBIH

PI2C

00^[1]00x0 0000

IP1H

Interrupt priority 1 high

Keypad control register

F7H

PI2CH 00^[1]00x0 0000

KBIF

00^[1]xxxx xx00

KBCON

94H

PATN

_SEL

KBMASK

KBPATN

Keypad interrupt mask

86H

0000 0000

1111 1111

Keypad pattern register

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P89LPC915 special function registers …continued

Table 7.

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex Binary

Bit address

[1]

P0*

P1*

Port 0

Port 1

80H

CMPREF CIN1A

CIN1B

/KB3

CIN2A

/KB2

CIN2B

/KB1

CMP2

/KB0

/KB5

/KB4

Bit address

90H

RST

INT1

INT0/

SDA

T0/SCL

RXD

TXD

Bit address

84H

P0M1

P0M2

P1M1

P1M2

PCON

PCONA

Port 0 output mode 1

Port 0 output mode 2

Port 1 output mode 1

Port 1 output mode 2

Power control register

Power control register A

(P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF^[1]1111 1111

(P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00^[1]0000 0000

85H

91H

(P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3^[1]11x1 xx11

(P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00^[1]00x0 xx00

92H

87H SMOD1 SMOD0

BOPD

VCPD

BOI

ADPD

GF1

I2PD

GF0

PMOD1 PMOD0 00

0000 0000

00^[1]0000 0000

B5H RTCPD

SPD

Bit address

PSW*

Program status word

Port 0 digital input disable

Reset source register

RTC control

D0H

F6H

DFH

D1H

RS1

RS0

0000 0000

xx00 000x

PT0AD

PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1

[3]

RSTSRC

RTCCON

BOF

POF

R_BK

R_WD

R_SF

ERTC

R_EX

RTCF

RTCS1

RTCS0

RTCEN 60^[1][011x xx00

RTCH

RTCL

RTC register high

D2H

D3H

A9H

B9H

00^[6]0000 0000

RTC register low

SADDR

SADEN

SBUF

Serial port address register

Serial port address enable

0000 0000

xxxx xxxx

Serial Port data buffer register 99H

Bit address

TB8

RB8

SCON*

SSTAT

Serial port control

98H SM0/FE

BAH DBMOD

SM1

SM2

CIDIS

REN

0000 0000

Serial port extended status

INTLO

DBISEL

STINT 00

Stack pointer

81H

0000 0111

xxx0 xxx0

TAMOD

Timer 0 and 1 auxiliary mode 8FH

T0M2

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P89LPC915 special function registers …continued

Table 7.

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex Binary

Bit address

88H

TCON*

TH0

Timer 0 and 1 control

Timer 0 high

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

0000 0000

8CH

0000 0000

TH1

Timer 1 high

8DH

TL0

Timer 0 low

8AH

TL1

Timer 1 low

8BH

TMOD

TRIM

Timer 0 and 1 mode

89H T1GATE

T1C/T

T1M1

TRIM.5

PRE0

T1M0

TRIM.4

T0GATE

TRIM.3

T0C/T

T0M1

T0M0

[5] [6]

Internal oscillator trim register 96H RCCLK

TRIM.2

TRIM.1

TRIM.0

[4] [6]

WDCON

WDL

Watchdog control register

Watchdog load

A7H

C1H

C2H

C3H

PRE2

PRE1

WDRUN WDTOF WDCLK

1111 1111

WFEED1

WFEED2

Watchdog feed 1

Watchdog feed 2

[1] All ports are in input only (high-impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reﬂects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset

value is xx11 0000.

[4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset source that affects these SFRs is power-on reset.

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Table 8.

P89LPC916 special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex Binary

Bit address

E0H

ACC*

Accumulator

ADCI1 ENADC1 ADCS11 ADCS10 00

0000 0000

ADCON1

ADC control register 1

97H

ENBI1

ENADCI

TMM1

EDGE1

0000 0000

ADINS

ADC input select

A3H

C0H

A1H

ADI13

BNDI1

CLK2

ADI12

BURST1

CLK1

ADI11

SCC1

CLK0

ADI10

SCAN1

0000 0000

000x 0000

1111 1111

0000 0000

0000 00x0

ADMODA

ADMODB

AD1BH

ADC mode register A

ADC mode register B

ENDAC1

BSA1

A/D_1 boundary high register C4H

A/D_1 boundary low register BCH

AD1BL

AD1DAT0

AD1DAT1

AD1DAT2

AD1DAT3

AUXR1

A/D_1 data register 0

A/D_1 data register 1

A/D_1 data register 2

A/D_1 data register 3

Auxiliary function register

D5H

D6H

D7H

F5H

A2H CLKLP

EBRR

ENT0

SRST

DPS

Bit address

F0H

B register

0000 0000

BRGR0

BRGR1

BRGCON

CMP1

CMP2

DIVM

Baud rate generator rate low BEH

Baud rate generator rate high BFH

Baud rate generator control

BDH

SBRGS BRGEN 00^[2]xxxx xx00

Comparator 1 control register ACH

Comparator 2 control register ADH

CPU clock divide-by-M control 95H

Data pointer (2 bytes)

CE1

CE2

CP1

CP2

CN1

CN2

CO1

CO2

CMF1 00^[1]xx00 0000

CMF2 00^[1]xx00 0000

OE2

0000 0000

DPTR

DPH

Data pointer high

83H

82H

E7H

E6H

0000 0000

DPL

Data pointer low

FMADRH

FMADRL

Program ﬂash address high

Program ﬂash address low

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P89LPC916 special function registers …continued

Table 8.

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex Binary

FMCON

Program ﬂash control (Read) E4H

BUSY

HVA

HVE

0111 0000

Program ﬂash control (Write) E4H FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD.

FMDATA

I2ADR

Program ﬂash data

I²C slave address register

E5H

DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0

0000 0000

Bit address

I2CON*

I2DAT

I²C control register

I²C data register

D8H

DAH

DDH

I2EN

STA

STO

CRSEL 00

x000 00x0

I2SCLH

Serial clock generator/SCL

duty cycle register high

0000 0000

1111 1000

I2SCLL

I2STAT

Serial clock generator/SCL

duty cycle register low

I²C status register

DCH

D9H

STA.4

EAD

STA.3

STA.2

STA.1

STA.0

Bit address

A8H

IEN0*

IEN1*

Interrupt enable 0

Interrupt enable 1

EWDRT

EBO

ES/ESR

ET1

ET0

EX0

0000 0000

Bit address

E8H

EST

ESPI

EKBI

EI2C

00^[1]00x0 0000

Bit address

B8H

IP0*

Interrupt priority 0

PWDRT

PBO

PBOH

PS/PSR

PT1

PT1H

PT0

PT0H

PX0

PX0H

00^[1]x000 0000

IP0H

Interrupt priority 0 high

B7H

PWDRT

PSH/

PSRH

Bit address

F8H

PAD

PADH

PST

PSTH

PSPI

PSPIH

PCH

IP1*

Interrupt priority 1

PKBI

PKBIH

PI2C

00^[1]00x0 0000

IP1H

Interrupt priority 1 high

Keypad control register

F7H

PI2CH 00^[1]00x0 0000

KBIF

00^[1]xxxx xx00

KBCON

94H

PATN

_SEL

KBMASK

KBPATN

Keypad interrupt mask

86H

0000 0000

1111 1111

Keypad pattern register

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P89LPC916 special function registers …continued

Table 8.

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex Binary

Bit address

[1]

P0*

P1*

Port 0

Port 1

80H

CMPREF CIN1A

/KB5

CIN1B

/KB3

CIN2A

/KB2

CIN2B

/KB1

/KB4

Bit address

90H

RST

INT0/

SDA

T0/SCL

RXD

TXD

Bit address

P2*

Port 2

A0H

SPICLK

MISO

MOSI

P0M1

P0M2

P1M1

P1M2

P2M1

P2M2

PCON

PCONA

Port 0 output mode 1

Port 0 output mode 2

Port 1 output mode 1

Port 1 output mode 2

Port 2 output mode 1

Port 2 output mode 2

Power control register

Power control register A

84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF^[1]1111 1111

85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00^[1]0000 0000

91H (P1M1.7) (P1M1.6)

92H (P1M2.7) (P1M2.6)

(P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3^[1]11x1 xx11

(P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00^[1]00x0 xx00

A4H

A5H

(P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2)

(P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2)

FF^[1]11x1 xx11

00^[1]00x0 xx00

87H SMOD1 SMOD0

BOPD

VCPD

BOI

ADPD

GF1

I2PD

GF0

SPPD

PMOD1 PMOD0 00

0000 0000

B5H RTCPD

SPD

00^[1]0000 0000

Bit address

PSW*

Program status word

Port 0 digital input disable

Reset source register

RTC control

D0H

F6H

DFH

D1H

RS1

RS0

0000 0000

xx00 000x

PT0AD

PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1

[3]

RSTSRC

RTCCON

BOF

POF

R_BK

R_WD

R_SF

ERTC

R_EX

RTCF

RTCS1

RTCS0

RTCEN 60^[1][011x xx00

RTCH

RTCL

RTC register high

D2H

D3H

A9H

B9H

00^[6]0000 0000

RTC register low

SADDR

SADEN

SBUF

Serial port address register

Serial port address enable

0000 0000

xxxx xxxx

Serial Port data buffer register 99H

Bit address

SCON*

Serial port control

98H SM0/FE

SM1

SM2

REN

TB8

RB8

0000 0000

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P89LPC916 special function registers …continued

Table 8.

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex Binary

SSTAT

Serial port extended status

BAH DBMOD

81H

INTLO

CIDIS

DBISEL

STINT 00

0000 0000

Stack pointer

0000 0111

0000 0100

00xx xxxx

0000 0000

xxx0 xxx0

SPCTL

SPSTAT

SPDAT

TAMOD

SPI control register

SPI status register

SPI data register

E2H

E1H

E3H

SSIG

SPIF

SPEN

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

WCOL

Timer 0 and 1 auxiliary mode 8FH

T0M2

Bit address

TF0

IE0

TCON*

TH0

Timer 0 and 1 control

Timer 0 high

88H

8CH

8DH

8AH

8BH

TF1

TR1

TR0

IT0

0000 0000

TH1

Timer 1 high

TL0

Timer 0 low

TL1

Timer 1 low

TMOD

TRIM

Timer 0 and 1 mode

89H T1GATE

T1C/T

T1M1

TRIM.5

PRE0

T1M0

TRIM.4

T0GATE

TRIM.3

T0C/T

T0M1

T0M0

[5] [6]

Internal oscillator trim register 96H RCCLK

TRIM.2

TRIM.1

TRIM.0

[4] [6]

WDCON

WDL

Watchdog control register

Watchdog load

A7H

C1H

C2H

C3H

PRE2

PRE1

WDRUN WDTOF WDCLK

1111 1111

WFEED1

WFEED2

Watchdog feed 1

Watchdog feed 2

[1] All ports are in input only (high-impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reﬂects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset

value is xx11 0000.

[4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset source that affects these SFRs is power-on reset.

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Table 9.

P89LPC917 special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex Binary

Bit address

E0H

ACC*

Accumulator

ADCI1 ENADC1 ADCS11 ADCS10 00

0000 0000

ADCON1

ADC control register 1

97H

ENBI1

ENADCI

TMM1

EDGE1

0000 0000

ADINS

ADC input select

A3H

C0H

A1H

ADI13

BNDI1

CLK2

ADI12

BURST1

CLK1

ADI11

SCC1

CLK0

ADI10

SCAN1

0000 0000

000x 0000

1111 1111

0000 0000

0000 00x0

ADMODA

ADMODB

AD1BH

ADC mode register A

ADC mode register B

ENDAC1

BSA1

A/D_1 boundary high register C4H

A/D_1 boundary low register BCH

AD1BL

AD1DAT0

AD1DAT1

AD1DAT2

AD1DAT3

AUXR1

A/D_1 data register 0

A/D_1 data register 1

A/D_1 data register 2

A/D_1 data register 3

Auxiliary function register

D5H

D6H

D7H

F5H

A2H CLKLP

EBRR

ENT1

ENT0

SRST

DPS

Bit address

F0H

B register

0000 0000

BRGR0

BRGR1

BRGCON

CMP1

CMP2

DIVM

Baud rate generator rate low BEH

Baud rate generator rate high BFH

Baud rate generator control

BDH

SBRGS BRGEN 00^[2]xxxx xx00

Comparator 1 control register ACH

Comparator 2 control register ADH

CPU clock divide-by-M control 95H

Data pointer (2 bytes)

CE1

CE2

CP1

CP2

CN1

CN2

CO1

CO2

CMF1 00^[1]xx00 0000

CMF2 00^[1]xx00 0000

OE2

0000 0000

DPTR

DPH

Data pointer high

83H

82H

E7H

E6H

0000 0000

DPL

Data pointer low

FMADRH

FMADRL

Program ﬂash address high

Program ﬂash address low

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P89LPC917 special function registers …continued

Table 9.

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex Binary

FMCON

Program ﬂash control (Read) E4H

BUSY

HVA

HVE

0111 0000

Program ﬂash control (Write) E4H FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD.

FMDATA

I2ADR

Program ﬂash data

I²C slave address register

E5H

DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0

0000 0000

Bit address

I2CON*

I2DAT

I²C control register

I²C data register

D8H

DAH

DDH

I2EN

STA

STO

CRSEL 00

x000 00x0

I2SCLH

Serial clock generator/SCL

duty cycle register high

0000 0000

1111 1000

I2SCLL

I2STAT

Serial clock generator/SCL

duty cycle register low

I²C status register

DCH

D9H

STA.4

EAD

STA.3

STA.2

STA.1

STA.0

Bit address

A8H

IEN0*

IEN1*

Interrupt enable 0

Interrupt enable 1

EWDRT

EBO

ES/ESR

ET1

EX1

ET0

EX0

0000 0000

Bit address

E8H

EST

EKBI

EI2C

00^[1]00x0 0000

Bit address

B8H

IP0*

Interrupt priority 0

PWDRT

PBO

PBOH

PS/PSR

PT1

PT1H

PX1

PX1H

PT0

PT0H

PX0

PX0H

00^[1]x000 0000

IP0H

Interrupt priority 0 high

B7H

PWDRT

PSH/

PSRH

Bit address

F8H

PAD

PADH

PST

PSTH

PCH

IP1*

Interrupt priority 1

PKBI

PKBIH

PI2C

00^[1]00x0 0000

IP1H

Interrupt priority 1 high

Keypad control register

F7H

PI2CH 00^[1]00x0 0000

KBIF

00^[1]xxxx xx00

KBCON

94H

PATN

_SEL

KBMASK

KBPATN

Keypad interrupt mask

86H

0000 0000

1111 1111

Keypad pattern register

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P89LPC917 special function registers …continued

Table 9.

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex Binary

Bit address

[1]

P0*

P1*

Port 0

Port 1

80H T1/KB7/

CLKOUT

CMPREF CIN1A

CIN1B

/KB3

CIN2A

/KB2

CIN2B

/KB1

CMP2

/KB0

/KB5

/KB4

Bit address

90H

RST

INT1

INT0/

SDA

T0/SCL

RXD

TXD

Bit address

P0M1

P0M2

P1M1

P1M2

PCON

PCONA

Port 0 output mode 1

Port 0 output mode 2

Port 1 output mode 1

Port 1 output mode 2

Power control register

Power control register A

84H (P0M1.7)

85H (P0M2.7)

(P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF^[1]1111 1111

(P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00^[1]0000 0000

91H

92H

(P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3^[1]11x1 xx11

(P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00^[1]00x0 xx00

87H SMOD1 SMOD0

BOPD

VCPD

BOI

ADPD

GF1

I2PD

GF0

PMOD1 PMOD0 00

0000 0000

B5H RTCPD

SPD

00^[1]0000 0000

Bit address

PSW*

Program status word

Port 0 digital input disable

Reset source register

RTC control

D0H

F6H

DFH

D1H

RS1

RS0

0000 0000

xx00 000x

PT0AD

PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1

[3]

RSTSRC

RTCCON

BOF

POF

R_BK

R_WD

R_SF

ERTC

R_EX

RTCF

RTCS1

RTCS0

RTCEN 60^[1][011x xx00

RTCH

RTCL

RTC register high

D2H

D3H

A9H

B9H

00^[6]0000 0000

RTC register low

SADDR

SADEN

SBUF

Serial port address register

Serial port address enable

0000 0000

xxxx xxxx

Serial Port data buffer register 99H

Bit address

TB8

RB8

SCON*

SSTAT

Serial port control

98H SM0/FE

BAH DBMOD

SM1

SM2

CIDIS

REN

0000 0000

Serial port extended status

INTLO

DBISEL

STINT 00

Stack pointer

81H

0000 0111

xxx0 xxx0

TAMOD

Timer 0 and 1 auxiliary mode 8FH

T1M2

T0M2

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P89LPC917 special function registers …continued

Table 9.

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex Binary

Bit address

88H

TCON*

TH0

Timer 0 and 1 control

Timer 0 high

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

0000 0000

8CH

0000 0000

TH1

Timer 1 high

8DH

TL0

Timer 0 low

8AH

TL1

Timer 1 low

8BH

TMOD

TRIM

Timer 0 and 1 mode

89H T1GATE

T1C/T

ENCLK

PRE1

T1M1

TRIM.5

PRE0

T1M0

TRIM.4

T0GATE

TRIM.3

T0C/T

T0M1

T0M0

[5] [6]

Internal oscillator trim register 96H RCCLK

TRIM.2

TRIM.1

TRIM.0

[4] [6]

WDCON

WDL

Watchdog control register

Watchdog load

A7H

C1H

C2H

C3H

PRE2

WDRUN WDTOF WDCLK

1111 1111

WFEED1

WFEED2

Watchdog feed 1

Watchdog feed 2

[1] All ports are in input only (high-impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reﬂects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset

value is xx11 0000.

[4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset source that affects these SFRs is power-on reset.

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

8.2 Enhanced CPU

The P89LPC915/916/917 uses an enhanced 80C51 CPU which runs at six times the

speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and

most instructions execute in one or two machine cycles.

8.3 Clocks

8.3.1 Clock deﬁnitions

The P89LPC915/916/917 device has several internal clocks as deﬁned below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock

sources (see Figure 11) and can also be optionally divided to a slower frequency (see

Section 8.8 “CCLK modiﬁcation: DIVM register”).

Note: f_oscis deﬁned as the OSCCLK frequency.

CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine

cycle, and most instructions are executed in one to two machine cycles (two or four CCLK

cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.

PCLK — Clock for the various peripheral devices and is ^CCLK⁄₂.

8.3.2 CPU clock (OSCCLK)

The P89LPC915/916/917 provides several user-selectable oscillator options in generating

the CPU clock. This allows optimization for a range of needs from high precision to lowest

possible cost. These options are conﬁgured when the ﬂash is programmed and include an

on-chip watchdog oscillator, an on-chip RC oscillator, and an external clock source.

8.3.3 Clock output (P89LPC917)

The P89LPC917 supports a user-selectable clock output function on the CLKOUT pin.

This allows external devices to synchronize to the P89LPC917. This output is enabled by

the ENCLK bit in the TRIM register.

The frequency of this clock output is ¹⁄₂that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering Idle, saving additional power.

8.4 On-chip RC oscillator option

The P89LPC915/916/917 has a 6-bit TRIM register that can be used to tune the

frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory

pre-programmed value to adjust the oscillator frequency to 7.373 MHz ± 1 % at room

temperature. End-user applications can write to the TRIM register to adjust the on-chip

RC oscillator to other frequencies. If CCLK is 8 MHz or slower, the CLKLP SFR bit

(AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0

allowing highest performance access. This bit can then be set in software if CCLK is

running at 8 MHz or slower.

8.5 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator

can be used to save power when a high clock frequency is not needed.

P89LPC915_916_917_5

Product data sheet

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31 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

8.6 External clock input option

In this conﬁguration, the processor clock is derived from an external source driving the

CLKIN pin. The rate may be from 0 Hz up to 18 MHz.

When using an external clock input frequency above 12 MHz, the reset input

function of P1.5 must be enabled. An external circuit is required to hold the device

in reset at power-up until V_DDhas reached its speciﬁed level. When system power is

removed V_DDwill fall below the minimum speciﬁed operating voltage. When using

an external clock input frequency above 12 MHz, in some applications, an external

brownout detect circuit may be required to hold the device in reset when V_DDfalls

below the minimum speciﬁed operating voltage.

RTCS1:0

XCLK

RTC

CLKOUT

RCCLK

OSCCLK

CLKIN

CCLK

DIVM

CPU

RCCLK

OSCILLATOR

ADC1/DAC1

(7.3728 MHz)

÷2

PCLK

WDT

WATCHDOG

OSCILLATOR

(400 kHz)

peripheral clock

BAUD RATE

GENERATOR

SPI

(P89LPC916)

TIMERS 1 AND 0

I C

UART

002aaa831

Fig 11. Block diagram of oscillator control

8.7 CCLK wake-up delay

The P89LPC915/916/917 has an internal wake-up timer that delays the clock until it

stabilizes. The delay is 224 OSCCLK cycles plus 60 µs to 100 µs.

8.8 CCLK modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing

CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can

retain the ability to respond to events that would not exit Idle mode by executing its normal

program at a lower rate. This can also allow bypassing the oscillator start-up time in cases

where Power-down mode would otherwise be used. The value of DIVM may be changed

by the program at any time without interrupting code execution.

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

32 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

8.9 Low power select

The P89LPC915/916/917 is designed to run at 18 MHz (CCLK) maximum. However, if

CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the

power consumption further. On any reset, CLKLP is ‘0’ allowing highest performance

access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

8.10 Memory organization

The various P89LPC915/916/917 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect

addressing, using instructions other than MOVX and MOVC. All or part of the Stack

may be in this area.

• IDATA

Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via

indirect addressing using instructions other than MOVX and MOVC. All or part of the

Stack may be in this area. This area includes the DATA area and the 128 bytes

immediately above it.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and status

registers, accessible only via direct addressing.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC915/916/917 devices have 2 kB of on-chip Code

memory.

8.11 Data RAM arrangement

The 256 bytes of on-chip RAM are organized as shown in Table 10.

Table 10. On-chip data memory usages

Type

DATA

IDATA

Data RAM

Size (bytes)

128

Memory that can be addressed directly and indirectly

Memory that can be addressed indirectly

256

8.12 Interrupts

The P89LPC915/916/917 uses a four priority level interrupt structure. This allows great

ﬂexibility in controlling the handling of the many interrupt sources.

The P89LPC915 and P89LPC917 support 13 interrupt sources: external interrupts 0 and

1, timers 0 and 1, serial port TX, serial port RX, combined serial port RX/TX, brownout

detect, watchdog/RTC, I²C-bus, keyboard, comparators 1 and 2, and ADC completion.

The P89LPC916 supports 14 interrupt sources: external interrupts 0 and 1, timers 0 and

1, serial port TX, serial port RX, combined serial port RX/TX, brownout detect,

watchdog/RTC, I²C-bus, keyboard, comparators 1 and 2, SPI, and ADC completion.

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

33 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in

the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global

disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An

interrupt service routine in progress can be interrupted by a higher priority interrupt, but

not by another interrupt of the same or lower priority. The highest priority interrupt service

cannot be interrupted by any other interrupt source. If two requests of different priority

levels are pending at the start of an instruction, the request of higher priority level is

serviced.

If requests of the same priority level are pending at the start of an instruction, an internal

polling sequence determines which request is serviced. This is called the arbitration

ranking. Note that the arbitration ranking is only used to resolve pending requests of the

same priority level.

8.12.1 External interrupt inputs

The P89LPC915 and P89LPC917 have two external interrupt inputs. The P89LPC916 has

one external interrupt input. These external interrupt inputs are identical to those present

on the standard 80C51 microcontrollers. All three devices also have the Keypad Interrupt

function.

These external interrupts can be programmed to be level-triggered or edge-triggered by

setting or clearing bit IT1 or IT0 in Register TCON.

In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle

and a LOW in the next cycle, the interrupt request ﬂag IEn in TCON is set, causing an

interrupt request.

If an external interrupt is enabled when the P89LPC915/916/917 is put into Power-down

or Idle mode, the interrupt will cause the processor to wake-up and resume operation.

Refer to Section 8.15 “Power reduction modes” for details.

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

34 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

IE0

EX0

IE1

EX1

BOF

EBO

wake-up

(if in power-down)

RTCF

KBIF

EKBI

ERTC

(RTCCON.1)

WDOVF

EWDRT

CMF2

CMF1

EA (IE0.7)

TF0

ET0

TF1

ET1

TI_0 and RI_0/RI_0

ES/ESR

TI_0

EST

interrupt

to CPU

EI2C

SPIF

ESPI

TI_1 and RI_1/RI_1

ES1/ESR1

TI_1

EST1

ENADCI0

ADCI0

ENBI0

BNDI0

EADC

002aab408

Fig 12. Interrupt sources, interrupt enables, and power-down wake-up sources

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

35 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

8.13 I/O ports

The P89LPC916 and P89LPC917 devices have three I/O ports: Port 0, Port 1, and Port 2.

The exact number of I/O pins available depends upon the clock and reset options chosen,

as shown in Table 11.

Table 11. Number of I/O pins available (P89LPC916 and P89LPC917)

Clock source

Reset option

Number of I/O

pins (16-pin

package)

RC oscillator or watchdog

oscillator

No external reset (except during

power-up)

External RST pin supported

External clock input

No external reset (except during

power-up)

External RST pin supported^[1]

[1] Required for operation above 12 MHz.

The P89LPC915 has two I/O ports: Port 0 and Port 1. The exact number of I/O pins

available depends upon the clock and reset options chosen, as shown in Table 12.

Table 12. Number of I/O pins available (P89LPC915)

Clock source

Reset option

Number of I/O

pins (14-pin

package)

RC oscillator or watchdog

oscillator

No external reset (except during

power-up)

External RST pin supported

External clock input

No external reset (except during

power-up)

External RST pin supported^[1]

[1] Required for operation above 12 MHz.

8.13.1 Port conﬁgurations

All but three I/O port pins on the P89LPC915/916/917 may be conﬁgured by software to

one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port

outputs), push-pull, open drain, and input-only. Two conﬁguration registers for each port

select the output type for each port pin.

1. P1.5 (RST) can only be an input and cannot be conﬁgured.

2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be conﬁgured to be either input-only or

open-drain.

8.13.1.1 Quasi-bidirectional output conﬁguration

Quasi-bidirectional output type can be used as both an input and output without the need

to reconﬁgure the port. This is possible because when the port outputs a logic HIGH, it is

weakly driven, allowing an external device to pull the pin LOW. When the pin is driven

LOW, it is driven strongly and able to sink a fairly large current. These features are

somewhat similar to an open-drain output except that there are three pull-up transistors in

the quasi-bidirectional output that serve different purposes.

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The P89LPC915/916/917 is a 3 V device, but the pins are 5 V tolerant. In

quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current ﬂowing

from the pin to V_DD, causing extra power consumption. Therefore, applying 5 V in

quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch

suppression circuit.

8.13.1.2 Open-drain output conﬁguration

The open-drain output conﬁguration turns off all pull-ups and only drives the pull-down

transistor of the port driver when the port latch contains a logic 0. To be used as a logic

output, a port conﬁgured in this manner must have an external pull-up, typically a resistor

tied to V_DD

An open-drain port pin has a Schmitt triggered input that also has a glitch suppression

circuit.

8.13.1.3 Input-only conﬁguration

The input-only port conﬁguration has no output drivers. It is a Schmitt triggered input that

also has a glitch suppression circuit.

8.13.1.4 Push-pull output conﬁguration

The push-pull output conﬁguration has the same pull-down structure as both the

open-drain and the quasi-bidirectional output modes, but provides a continuous strong

pull-up when the port latch contains a logic 1. The push-pull mode may be used when

more source current is needed from a port output. A push-pull port pin has a

Schmitt triggered input that also has a glitch suppression circuit.

8.13.2 Port 0 analog functions

The P89LPC915/916/917 incorporates two Analog Comparators. In order to give the best

analog function performance and to minimize power consumption, pins that are being

used for analog functions must have the digital outputs and digital inputs disabled.

Digital outputs are disabled by putting the port output into the Input-Only

(high-impedance) mode.

Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On any

reset, PT0AD bits default to ‘0’s to enable digital functions.

8.13.3 Additional port features

After power-up, all pins are in Input-Only mode. After power-up, all I/O pins except P1.5,

may be conﬁgured by software.

• Pin P1.5 is input only.

• Pins P1.2 and P1.3 are conﬁgurable for either input-only or open-drain.

Every output on the P89LPC915/916/917 has been designed to sink typical LED drive

current. However, there is a maximum total output current for all ports which must not be

exceeded. Please refer to Table 15 “Static characteristics” for detailed speciﬁcations.

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All ports pins that can function as an output have slew rate controlled outputs to limit noise

generated by quickly switching output signals. The slew rate is factory-set to

approximately 10 ns rise and fall times.

8.14 Power monitoring functions

The P89LPC915/916/917 incorporates power monitoring functions designed to prevent

incorrect operation during initial power-up and power loss or reduction during operation.

This is accomplished with two hardware functions: Power-on detect and brownout detect.

8.14.1 Brownout detection

The brownout detect function determines if the power supply voltage drops below a

certain level. The default operation is for a brownout detection to cause a processor reset,

however it may alternatively be conﬁgured to generate an interrupt.

Brownout detection may be enabled or disabled in software.

If brownout detection is enabled the brownout condition occurs when V_DDfalls below the

brownout trip voltage, V_bo(see Table 15 “Static characteristics”), and is negated when V_DD

rises above V_bo. If the P89LPC915/916/917 device is to operate with a power supply that

can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can

operate at 2.4 V, otherwise continuous brownout reset may prevent the device from

operating.

For correct activation of brownout detect, the V_DDrise and fall times must be observed.

Please see Table 15 “Static characteristics” for speciﬁcations.

8.14.2 Power-on detection

The Power-on detect has a function similar to the brownout detect, but is designed to work

as power comes up initially, before the power supply voltage reaches a level where

brownout detect can work. The POF ﬂag in the RSTSRC register is set to indicate an

initial power-up condition. The POF ﬂag will remain set until cleared by software.

8.15 Power reduction modes

The P89LPC915/916/917 supports three different power reduction modes: Idle mode,

Power-down mode, and total Power-down mode.

8.15.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor

when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle

mode.

8.15.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption. The

P89LPC915/916/917 exits Power-down mode via any reset, or certain interrupts. In

Power-down mode, the power supply voltage may be reduced to the data retention

voltage V_DDR. This retains the RAM contents at the point where Power-down mode was

entered. SFR contents are not guaranteed after V_DDhas been lowered to V_DDR, therefore

it is highly recommended to wake-up the processor via reset in this case. V_DDmust be

raised to within the operating range before the Power-down mode is exited.

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Some chip functions continue to operate and draw power during Power-down mode,

increasing the total power used during power-down. These include: Brownout detect,

watchdog timer, comparators (note that comparators can be powered down separately),

and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator

has been selected as the system clock and the RTC is enabled.

8.15.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry and

the voltage comparators are also disabled to conserve additional power. The internal RC

oscillator is disabled unless both the RC oscillator has been selected as the system clock

and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during

power-down, there will be high power consumption. Please use an external low frequency

clock to achieve low power with the RTC running during power-down.

8.16 Reset

The P1.5/RST pin can function as either an active-LOW reset input or as a digital input,

P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the external

reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin

always functions as a reset input. An external circuit connected to this pin should not

hold this pin LOW during a power-on sequence as this will keep the device in reset.

After power-up this input will function either as an external reset input or as a digital input

as deﬁned by the RPE bit. Only a power-up reset will temporarily override the selection

deﬁned by RPE bit. Other sources of reset will not override the RPE bit.

Reset can be triggered from the following sources:

• External reset pin (during power-up or if user conﬁgured via UCFG1);

• Power-on detect;

• Brownout detect;

• Watchdog timer;

• Software reset;

• UART break character detect reset.

For every reset source, there is a ﬂag in the Reset Register, RSTSRC. The user can read

this register to determine the most recent reset source. These ﬂag bits can be cleared in

software by writing a ‘0’ to the corresponding bit. More than one ﬂag bit may be set:

• During a power-on reset, both POF and BOF are set but the other ﬂag bits are

cleared.

• For any other reset, previously set ﬂag bits that have not been cleared will remain set.

8.17 Timers/counters 0 and 1

The P89LPC915/916/917 have two general purpose counter/timers which are upward

compatible with the standard 80C51 Timer 0 and Timer 1. Both can be conﬁgured to

operate either as timers or event counters. An option to automatically toggle the T0 and/or

T1 pins upon timer overﬂow has been added.

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In the ‘Timer’ function, the register is incremented every machine cycle.

In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its

corresponding external input pin, T0 or T1. In this function, the external input is sampled

once during every machine cycle.

Timer 0 has ﬁve operating modes (Modes 0, 1, 2, 3 and 6).

Timer 1 has four operating modes (Modes 0, 1, 2, and 3), except on the P89LPC917

where Timer 1 also has Mode 6. Modes 0, 1, 2 and 6 are the same for both

Timers/Counters. Mode 3 is different.

8.17.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit

Counter with a divide-by-32 prescaler. In this mode, the Timer register is conﬁgured as a

13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

8.17.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

8.17.3 Mode 2

Mode 2 conﬁgures the Timer register as an 8-bit Counter with automatic reload. Mode 2

operation is the same for Timer 0 and Timer 1.

8.17.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit

counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is

in Mode 3 it can still be used by the serial port as a baud rate generator.

8.17.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of

256 timer clocks.

8.17.6 Timer overﬂow toggle output

Timer 0 (and Timer 1 on the P89LPC917) can be conﬁgured to automatically toggle a port

output whenever a timer overﬂow occurs. The same device pins that are used for the T0

and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a

logic 1 prior to the ﬁrst timer overﬂow when this mode is turned on.

8.18 RTC/system timer

The P89LPC915/916/917 have a simple RTC that allows a user to continue running an

accurate timer while the rest of the device is powered down. The RTC can be a wake-up

or an interrupt source. The RTC is a 23-bit down-counter comprised of a 7-bit prescaler

and a 16-bit loadable down-counter. When it reaches all ‘0’s, the counter will be reloaded

again and the RTCF ﬂag will be set.

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The clock source for this counter can be either the CPU clock (CCLK) or the external clock

input, provided that the external clock input is not being used as the CPU clock. If the

external clock input is used as the CPU clock, then the RTC will use CCLK as its clock

source. Only power-on reset will reset the RTC and its associated SFRs to the default

state.

8.19 UART

The P89LPC915/916/917 has an enhanced UART that is compatible with the conventional

80C51 UART except that Timer 2 overﬂow cannot be used as a baud rate source. The

P89LPC915/916/917 does include an independent Baud Rate Generator. The baud rate

can be selected from the oscillator (divided by a constant), Timer 1 overﬂow, or the

independent Baud Rate Generator. In addition to the baud rate generation, enhancements

over the standard 80C51 UART include Framing Error detection, automatic address

recognition, selectable double buffering and several interrupt options. The UART can be

operated in 4 modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU

clock/16.

8.19.1 Mode 0

Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are

transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at ¹⁄₁₆of the CPU clock

frequency.

8.19.2 Mode 1

10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),

8 data bits (LSB ﬁrst), and a stop bit (logic 1). When data is received, the stop bit is stored

in RB8_n in Special Function Register SnCON. The baud rate is variable and is

determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in Section

8.19.5 “Baud rate generator and selection”).

8.19.3 Mode 2

11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data

bits (LSB ﬁrst), a programmable 9^thdata bit, and a stop bit (logic 1). When data is

transmitted, the 9^thdata bit (TB8 in SCON) can be assigned the value of ‘0’ or ‘1’. Or, for

example, the parity bit (P, in the PSW) could be moved into TB8. When data is received,

the 9^thdata bit goes into RB8 in Special Function Register SCON, while the stop bit is not

saved. The baud rate is programmable to either ¹⁄₁₆or ¹⁄₃₂of the CPU clock frequency, as

determined by the SMOD1 bit in PCON. The SMOD1 bit controls the Timer 1 output rate

available to the UART.

8.19.4 Mode 3

11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8

data bits (LSB ﬁrst), a programmable 9^thdata bit, and a stop bit (logic 1). In fact, Mode 3 is

the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable

and is determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in

Section 8.19.5 “Baud rate generator and selection”).

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8.19.5 Baud rate generator and selection

Each enhanced UART has an independent Baud Rate Generator. The baud rate is

determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which

together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1

but is much more accurate. If the baud rate generator is used, Timer 1 can be used for

other timing functions.

The UART can use either Timer 1 or its baud rate generator output (see Figure 13). Note

that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The

independent Baud Rate Generator uses OSCCLK.

timer 1 overflow

SMOD1 = 1

(PCLK-based)

SBRGS = 0

SBRGS = 1

÷2

baud rate modes 1 and 3

002aaa897

SMOD1 = 0

baud rate generator

(CCLK-based)

Fig 13. Baud rate sources for UART (Modes 1, 3)

8.19.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)

is ‘1’, framing errors can be made available in SCON.7 respectively. If SMOD0 is ‘0’,

SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON [7:6]) are set up when

SMOD0 is ‘0’.

8.19.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the device

and force the device into ISP mode.

8.19.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be

written to SnBUF while the ﬁrst character is being transmitted. Double buffering allows

transmission of a string of characters with only one stop bit between any two characters,

as long as the next character is written between the start bit and the stop bit of the

previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is

compatible with the conventional 80C51 UART. If enabled, the UART allows writing to

SBUF while the previous data is being shifted out. Double buffering is only allowed in

Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled

(DBMOD = 0).

8.19.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the TI interrupt is generated

when the double buffer is ready to receive new data.

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8.19.10 The 9^thbit (bit 8) in double buffering (Modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as long

as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until

the bit is shifted out, as indicated by the TI interrupt.

If double buffering is enabled, TB must be updated before SBUF is written, as TB8 will be

double-buffered together with SBUF data.

8.20 I²C-bus serial interface

I²C-bus uses two wires (SDA and SCL) to transfer information between devices connected

to the bus, and it has the following features:

• Bidirectional data transfer between masters and slaves

• Multi master bus (no central master)

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer

• The I²C-bus may be used for test and diagnostic purposes.

A typical I²C-bus conﬁguration is shown in Figure 14. The P89LPC915/916/917 device

provides a byte-oriented I²C-bus interface that supports data transfers up to 400 kHz.

SDA

SCL

I C-bus

OTHER DEVICE

WITH I C-BUS

INTERFACE

OTHER DEVICE

WITH I C-BUS

INTERFACE

P1.3/SDA

P1.2/SCL

I C MCU

002aab410

Fig 14. I²C-bus conﬁguration

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I2ADR

ADDRESS REGISTER

COMPARATOR

P1.3

INPUT

FILTER

P1.3/SDA

SHIFT REGISTER

ACK

I2DAT

OUTPUT

STAGE

BIT COUNTER /

ARBITRATION

AND SYNC LOGIC

CCLK

INPUT

FILTER

TIMING

AND

CONTROL

LOGIC

P1.2/SCL

SERIAL CLOCK

GENERATOR

OUTPUT

STAGE

interrupt

timer 1

overflow

P1.2

I2CON

I2SCLH

I2SCLL

CONTROL REGISTERS AND

SCL DUTY CYCLE REGISTERS

STATUS

DECODER

status bus

I2STAT

STATUS REGISTER

002aaa899

Fig 15. I²C-bus serial interface block diagram

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8.21 SPI

8-bit microcontrollers with accelerated two-clock 80C51 core

The P89LPC916 provides another high-speed serial communication interface—the SPI

interface. SPI is a full-duplex, high-speed, synchronous communication bus with two

operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in

Master mode or up to 3 Mbit/s in Slave mode. It has a Transfer Completion Flag and Write

Collision Flag Protection.

MISO

P2.3

CPU clock

8-BIT SHIFT REGISTER

READ DATA BUFFER

MOSI

P2.2

CONTROL

LOGIC

DIVIDER

BY 4, 16, 64, 128

SPICLK

P2.5

clock

SPI clock (master)

SELECT

P2.4

CLOCK LOGIC

MSTR

SPEN

SPI CONTROL

SPI CONTROL REGISTER

SPI STATUS REGISTER

SPI

interrupt

request

internal

data

bus

002aaa900

Fig 16. SPI block diagram

The SPI interface has four pins: SPICLK, MOSI, MISO and SS:

• SPICLK, MOSI and MISO are typically tied together between two or more SPI

devices. Data ﬂows from master to slave on MOSI (Master Out Slave In) pin and ﬂows

from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output

in the master mode and is input in the slave mode. If the SPI system is disabled, i.e.,

SPEN (SPCTL.6) = 0 (reset value), these pins are conﬁgured for port functions.

• SS is the optional slave select pin. In a typical conﬁguration, an SPI master asserts

one of its port pins to select one SPI device as the current slave. An SPI slave device

uses its SS pin to determine whether it is selected.

Typical connections are shown in Figure 17 through Figure 19.

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8.21.1 Typical SPI conﬁgurations

master

slave

MISO

MOSI

MISO

MOSI

8-BIT SHIFT

SPICLK

PORT

SPICLK

SPI CLOCK

GENERATOR

002aaa901

Fig 17. SPI single master single slave conﬁguration

master

slave

MISO

MOSI

8-BIT SHIFT

MOSI

SPICLK

SPI CLOCK

GENERATOR

SPI CLOCK

GENERATOR

002aaa902

Fig 18. SPI dual device conﬁguration, where either can be a master or a slave

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master

slave

MISO

MOSI

MISO

MOSI

8-BIT SHIFT

SPICLK

port

SPICLK

SPI CLOCK

GENERATOR

slave

MISO

MOSI

8-BIT SHIFT

SPICLK

port

002aaa903

Fig 19. SPI single master multiple slaves conﬁguration

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8.22 Analog comparators

Two analog comparators are provided on the P89LPC915/916/917. Input and output

options allow use of the comparators in a number of different conﬁgurations. Comparator

operation is such that the output is a logical one when the positive input is greater than the

negative input (selectable from a pin or an internal reference voltage). Otherwise the

output is a zero. Each comparator may be conﬁgured to cause an interrupt when the

output value changes. Comparator 1 may be output to a port pin.

The overall connections to both comparators are shown in Figure 20. The comparators

function to V_DD= 2.4 V.

When each comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are not

guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt

should not be enabled during that time, and the comparator interrupt ﬂag must be cleared

before the interrupt is enabled in order to prevent an immediate interrupt service.

CP1

OE1

comparator 1

CO1

(P0.4) CIN1A

(P0.3) CIN1B

CMP1 (P0.6)

(P0.5) CMPREF

change detect

ref(bg)

CMF1

CMF2

CN1

CP2

interrupt

change detect

comparator 2

(P0.2) CIN2A

(P0.1) CIN2B

CMP2 (P0.0)

CO2

OE2

002aaa904

CN2

Fig 20. Comparator input and output connections

8.22.1 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single

comparator input pin is used. The value of the internal reference voltage, referred to as

V_ref(bg), is 1.23 V ± 10 %.

8.22.2 Comparator interrupt

Each comparator has an interrupt ﬂag contained in its conﬁguration register. This ﬂag is

set whenever the comparator output changes state. The ﬂag may be polled by software or

may be used to generate an interrupt. The two comparators use one common interrupt

vector. If both comparators enable interrupts, after entering the interrupt service routine,

the user needs to read the ﬂags to determine which comparator caused the interrupt.

8.22.3 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is

activated, but both comparators are disabled automatically in Total Power-down mode.

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If a comparator interrupt is enabled (except in Total Power-down mode), a change of the

comparator output state will generate an interrupt and wake-up the processor. If the

comparator output to a pin is enabled, the pin should be conﬁgured in the push-pull mode

in order to obtain fast switching times while in Power-down mode. The reason is that with

the oscillator stopped, the temporary strong pull-up that normally occurs during switching

on a quasi-bidirectional port pin does not take place.

Comparators consume power in Power-down and Idle modes, as well as in the normal

operating mode. This fact should be taken into account when system power consumption

is an issue. To minimize power consumption, the user can disable the comparators via

PCONA.5, or put the device in Total Power-down mode.

8.23 KBI

The Keypad Interrupt function is intended primarily to allow a single interrupt to be

generated when Port 0 is equal to or not equal to a certain pattern. This function can be

used for bus address recognition or keypad recognition. The user can conﬁgure the port

via SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to deﬁne which input pins

connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is

used to deﬁne a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag

(KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is

matched while the Keypad Interrupt function is active. An interrupt will be generated if

enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to

deﬁne equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series,

the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key

connected to Port 0 which is enabled by the KBMASK register will cause the hardware to

set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to

wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in

handheld, battery-powered systems that need to carefully manage power consumption

yet also need to be convenient to use.

In order to set the ﬂag and cause an interrupt, the pattern on Port 0 must be held longer

than six CCLKs.

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8.24 Watchdog timer

The watchdog timer causes a system reset when it underﬂows as a result of a failure to

feed the timer prior to the timer reaching its terminal count. It consists of a programmable

12-bit prescaler, and an 8-bit down-counter. The down-counter is decremented by a tap

taken from the prescaler. The clock source for the prescaler is either the PCLK or the

nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a

power-on reset. When the watchdog feature is disabled, it can be used as an interval timer

and may generate an interrupt. Figure 21 shows the watchdog timer in Watchdog mode.

Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog

clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a

time-out period that ranges from a few µs to a few seconds. Please refer to the

P89LPC915/916/917 User’s Manual for more details.

WDL (C1H)

MOV WFEED1, #0A5H

MOV WFEED2, #05AH

watchdog

oscillator

8-BIT DOWN

COUNTER

(1)

PRESCALER

reset

÷32

PCLK

SHADOW REGISTER

PRE2

PRE1

PRE0

WDRUN WDTOF WDCLK

WDCON (A7H)

002aaa905

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed

sequence.

Fig 21. Watchdog timer in Watchdog mode (WDTE = 1)

8.25 Additional features

8.25.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,

as if an external reset or watchdog reset had occurred. Care should be taken when writing

to AUXR1 to avoid accidental software resets.

8.25.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address

used with certain instructions. The DPS bit in the AUXR1 register selects one of the two

Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may

be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,

without the possibility of inadvertently altering other bits in the register.

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8.26 Flash program memory

8.26.1 General description

The P89LPC915/916/917 ﬂash memory provides in-circuit electrical erasure and

programming. The ﬂash can be erased, read, and written as bytes. The Sector and Page

Erase functions can erase any ﬂash sector (256 bytes) or page (16 bytes). The Chip

Erase operation will erase the entire program memory. ICP using standard commercial

programmers is available. In addition, IAP and byte-erase allows code memory to be used

for non-volatile data storage. On-chip erase and write timing generation contribute to a

user-friendly programming interface. The P89LPC915/916/917 ﬂash reliably stores

memory contents even after 100,000 erase and program cycles. The cell is designed to

optimize the erase and programming mechanisms. The P89LPC915/916/917 uses V_DDas

the supply voltage to perform the Program/Erase algorithms.

8.26.2 Features

• Programming and erase over the full operating voltage range.

• Byte erase allows code memory to be used for data storage.

• Read/Programming/Erase using ICP.

• Boot vector allows user-provided ﬂash loader code to reside anywhere in the ﬂash

memory space, providing ﬂexibility to the user.

• Any ﬂash program/erase operation in 2 ms.

• Programming with industry-standard commercial programmers.

• Programmable security for the code in the ﬂash for each sector.

• 100,000 typical erase/program cycles for each byte.

• 10 year minimum data retention.

8.26.3 Flash organization

The program memory consists of eight 256-byte sectors on the P89LPC915/916/917

devices. Each sector can be further divided into 16-byte pages. In addition to sector

erase, page erase, and byte erase, a 16-byte page register is included which allows from

1 to 16 bytes of a given page to be programmed at the same time, substantially reducing

overall programming time.

8.26.4 Using ﬂash as data storage

The ﬂash code memory array of this device supports individual byte erasing and

programming. Any byte in the code memory array may be read using the MOVC

instruction, provided that the sector containing the byte has not been secured (a MOVC

instruction is not allowed to read code memory contents of a secured sector). Thus any

byte in a non-secured sector may be used for non-volatile data storage.

8.26.5 Flash programming and erasing

Two different methods of erasing or programming of the ﬂash are available. The ﬂash may

be programmed or erased in the end-user application (IAP-Lite) under control of the

application’s ﬁrmware. Another option is to use the ICP mechanism. This ICP system

provides for programming through a serial clock/serial data interface. This device does not

provide for direct veriﬁcation of code memory contents. Instead, this device provides a

32-bit CRC result on either a sector or the entire user code space.

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8.26.6 ICP

8-bit microcontrollers with accelerated two-clock 80C51 core

ICP is performed without removing the microcontroller from the system. The ICP facility

consists of internal hardware resources to facilitate remote programming of the

P89LPC915/916/917 through a two-wire serial interface. The NXP ICP facility has made

in-circuit programming in an embedded application—using commercially available

programmers—possible with a minimum of additional expense in components and circuit

board area. The ICP function uses ﬁve pins. Only a small connector needs to be available

to interface your application to a commercial programmer in order to use this feature.

Additional details may be found in the P89LPC915/916/917 User’s Manual.

8.26.7 IAP-Lite

IAP-Lite is performed in the application under the control of the microcontroller’s ﬁrmware.

The IAP facility consists of internal hardware resources to facilitate programming and

erasing. The IAP-Lite operations are accomplished through the use of four SFRs

consisting of a control/status register, a data register, and two address registers.

Additional details may be found in the P89LPC915/916/917 User’s Manual.

8.26.8 Power-on reset code execution

The P89LPC915/916/917 contains two special ﬂash elements: the Boot Vector and the

Boot Status bit. Following reset, the P89LPC915/916/917 examines the contents of the

Boot Status bit. If the Boot Status bit is set to zero, power-up execution starts at location

0000H, which is the normal start address of the user’s application code. When the Boot

Status bit is set to a value other than zero, the contents of the Boot Vector are used as the

high byte of the execution address and the low byte is set to 00H.

Table 13 shows the factory default Boot Vector setting for this device. While these devices

do not contain a factory bootloader, the Boot Vector and Status bit do provide a

mechanism for an alternate code execution at reset.

Table 13. Default boot vector and Status bit values

Device

Default boot vector

Default Status bit

P89LPC915

P89LPC916

P89LPC917

00H

8.26.9 Hardware activation of the alternate code

The alternate code execution address can be forced during a power-on sequence (see the

P89LPC915/916/917 User’s Manual for speciﬁc information). This has the same effect as

having a non-zero status byte. This allows an application to be built that will normally

execute user code starting at address 0000H but can be manually forced into executing

from an alternated address using the Boot Vector. After programming the ﬂash, the status

byte should be programmed to zero in order to allow execution of the user’s application

code beginning at address 0000H.

8.27 User conﬁguration bytes

Some user-conﬁgurable features of the P89LPC915/916/917 must be deﬁned at power-up

and therefore cannot be set by the program after start of execution. These features are

conﬁgured through the use of the ﬂash byte UCFG1. Please see the P89LPC915/916/917

User’s Manual for additional details.

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8.28 User sector security bytes

There are eight User Sector Security Bytes on the P89LPC915/916/917. Each byte

corresponds to one sector. Please see the P89LPC915/916/917 User’s Manual for

additional details.

9. A/D converter

9.1 General description

The P89LPC915/916/917 devices have a single 8-bit, 4-channel multiplexed

analog-to-digital converter with a DAC module. A block diagram of the A/D converter is

shown in Figure 22. The A/D consists of a 4-input multiplexer which feeds a

sample-and-hold circuit providing an input signal to one of two comparator inputs. The

control logic in combination with the SAR drives a digital-to-analog converter which

provides the other input to the comparator. The output of the comparator is fed to the

SAR.

9.2 Features

I Single 8-bit, 4-channel multiplexed input, successive approximation A/D converter.

I Four A/D result registers.

I Six operating modes:

N Fixed channel, single conversion mode.

N Fixed channel, continuous conversion mode.

N Auto scan, single conversion mode.

N Auto scan, continuous conversion mode.

N Dual channel, continuous conversion mode.

N Single step mode.

I Three conversion start modes:

N Timer triggered start.

N Start immediately.

N Edge triggered.

I 8-bit conversion time of ≥3.9 µs at an A/D clock of 3.3 MHz.

I Interrupt or polled operation.

I Boundary limits interrupt.

I DAC output to a port pin with high output impedance.

I Clock divider.

I Power-down mode.

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9.3 Block diagram

comp

INPUT

SAR

MUX

–

DAC1

CONTROL

LOGIC

comp

INPUT

MUX

SAR

–

DAC0

CCLK

002aab080

Fig 22. ADC block diagram

9.4 A/D operating modes

9.4.1 Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will be

performed and the result placed in the result register which corresponds to the selected

input channel. An interrupt, if enabled, will be generated after the conversion completes.

9.4.2 Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of the

conversions will be sequentially placed in the four result registers. An interrupt, if enabled,

will be generated after every four conversions. Additional conversion results will again

cycle through the four result registers, overwriting the previous results. Continuous

conversions continue until terminated by the user.

9.4.3 Auto scan, single conversion mode

Any combination of the four input channels can be selected for conversion. A single

conversion of each selected input will be performed and the result placed in the result

generated after all selected channels have been converted. If only a single channel is

selected this is equivalent to single channel, single conversion mode.

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9.4.4 Auto scan, continuous conversion mode

Any combination of the four input channels can be selected for conversion. A conversion

of each selected input will be performed and the result placed in the result register which

corresponds to the selected input channel. An interrupt, if enabled, will be generated after

all selected channels have been converted. The process will repeat starting with the ﬁrst

selected channel. Additional conversion results will again cycle through the four result

registers, overwriting the previous results.Continous conversions continue until terminated

by the user.

9.4.5 Dual channel, continuous conversion mode

This is a variation of the auto scan continuous conversion mode where conversion occurs

on two user-selectable inputs. The result of the conversion of the ﬁrst channel is placed in

result register, AD1DAT0. The result of the conversion of the second channel is placed in

result register, AD1DAT1. The ﬁrst channel is again converted and its result stored in

AD1DAT2. The second channel is again converted and its result placed in AD1DAT3. An

interrupt is generated, if enabled, after every set of four conversions (two conversions per

channel).

9.4.6 Single step mode

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any

combination of the four input channels can be selected for conversion. After each channel

is converted, an interrupt is generated, if enabled, and the A/D waits for the next start

condition. May be used with any of the start modes.

9.5 Conversion start modes

9.5.1 Timer triggered start

An A/D conversion is started by the overﬂow of Timer 0. Once a conversion has started,

additional Timer 0 triggers are ignored until the conversion has completed. The Timer

triggered start mode is available in all A/D operating modes.

9.5.2 Start immediately

Programming this mode immediately starts a conversion.This start mode is available in all

A/D operating modes.

9.5.3 Edge triggered

An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has

started, additional edge triggers are ignored until the conversion has completed. The edge

triggered start mode is available in all A/D operating modes.

9.6 Boundary limits interrupt

The A/D converter has both a high and low boundary limit register. After the four MSBs

have been converted, these four bits are compared with the four MSBs of the boundary

high and low registers. If the four MSBs of the conversion are outside the limit an interrupt

will be generated, if enabled. If the conversion result is within the limits, the boundary

limits will again be compared after all 8 bits have been converted. An interrupt will be

generated, if enabled, if the result is outside the boundary limits. The boundary limit may

be disabled by clearing the boundary limit interrupt enable.

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9.7 DAC output to a port pin with high output impedance

The A/D converter’s DAC block can be output to a port pin. In this mode, the AD1DAT3

(written to AD1DAT3), the DAC output will appear on the channel 3 pin.

9.8 Clock divider

The A/D converter requires that its internal clock source be in the range of 500 kHz to

3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock

from 1 to 8 is provided for this purpose.

9.9 Power-down and Idle mode

In Idle mode the A/C converter, if enabled, will continue to function and can cause the

device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled.

In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is

enabled, it will consume power. Power can be reduced by disabling the A/D.

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10. Limiting values

Table 14. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

T_amb(bias)

T_stg

Parameter

Conditions

Min

Max

+125

+150

Unit

°C

operating bias ambient temperature

storage temperature range

HIGH-level output current per I/O pin

LOW-level output current per I/O pin

−55

−65

°C

I_OH(I/O)

I_OL(I/O)

I_{I/O(tot)(max)}maximum total I/O current

120

3.5

V_n

voltage on any pin (except V_SS

)

with respect to V_DD

P_tot(pack)

total power dissipation per package

based on package heat

transfer, not device power

consumption

1.5

[1] The following applies to Table 14:

a) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over ambient temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

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8-bit microcontrollers with accelerated two-clock 80C51 core

11. Static characteristics

Table 15. Static characteristics

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

µA

[2]

I_DD(oper)

I_DD(idle)

I_DD(pd)

operating supply current

V_DD= 3.6 V; f_osc= 12 MHz

V_DD= 3.6 V; f_osc= 18 MHz

V_DD= 3.6 V; f_osc= 12 MHz

V_DD= 3.6 V; f_osc= 18 MHz

V_DD= 3.6 V, industrial

V_DD= 3.6 V, extended

3.6

Idle mode supply current

4.8

power supply current,

power-down mode, voltage

comparators powered-down

150

µA

[3]

I_DD(tpd)

total Power-down mode

supply current

V_DD= 3.6 V, industrial

V_DD= 3.6 V, extended

of V_DD

<0.1

µA

(dV/dt)_r

(dV/dt)_f

V_POR

rise rate

mV/µs

fall rate

of V_DD

0.2

power-on reset voltage

data retention voltage

V_DDR

1.5

V_th(HL)

HIGH-LOW threshold

voltage

except SCL, SDA

0.22V_DD

0.4V_DD

V_IL

LOW-level input voltage

SCL, SDA only

−0.5

0.3V_DD

0.7V_DD

V_th(LH)

LOW-HIGH threshold

voltage

except SCL, SDA

0.6V_DD

V_IH

HIGH-level input voltage

hysteresis voltage

SCL, SDA only

port 1

0.7V_DD

5.5

V_hys

V_OL

0.2V_DD

0.6

[4]

LOW-level output voltage

I_OL= 20 mA; all ports

except SCL, SDA

1.0

I_OL= 10 mA; all ports

except SCL, SDA

0.2

0.3

I_OL= 3.2 mA; all ports

except SCL, SDA

V_OH

HIGH-level output voltage

I_OH= −8 mA;

push-pull mode; all ports

except SCL, SDA

_DD− 1

I_OH= −3.2 mA;

_DD− 0.7

_DD− 0.3

_DD− 0.4

_DD− 0.2

push-pull mode; all ports

except SCL, SDA

I_OH= −20 µA;

quasi-bidirectional mode;

all ports except SCL, SDA

V_xtal

V_n

crystal voltage

voltage on XTAL1, XTAL2

pins with respect to V_SS

−0.5

+4.0

+5.5

[5]

voltage on any pin (except

with respect to V_SS

XTAL1, XTAL2, V_DD

)

[6]

[7]

C_iss

I_IL

input capacitance

logical 0 input current

V_I= 0.4 V

−80

µA

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Table 15. Static characteristics …continued

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

±10

Unit

µA

[8]

[9]

I_LI

input leakage current

V_I= V_IL, V_IHor V_th(HL)

V_I= 1.5 V at V_DD= 3.6 V

I_TL

logical 1-to-0 transition

current, all ports

−30

−450

µA

R_RST(int)

V_bo

internal pull-up resistance

on pin RST

kΩ

brownout trip voltage

2.4 V < V_DD< 3.6 V; with

BOV = 1, BOPD = 0

2.40

2.70

V_ref(bg)

TC_bg

band gap reference voltage

1.11

1.23

1.34

band gap temperature

coefﬁcient

ppm/°C

[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.

[2] The I_DD(oper), I_DD(idle), and I_DD(pd)speciﬁcations are measured using an external clock with the following functions disabled: comparators,

real-time clock, and watchdog timer.

[3] The I_DD(tpd)speciﬁcation is measured using an external clock with the following functions disabled: comparators, real-time clock,

brownout detect, and watchdog timer.

[4] See Section 10 “Limiting values” for steady state (non-transient) limits on I_OLor I_OH. If I_OL/I_OHexceeds the test condition, V_OL/V_OHmay

exceed the related speciﬁcation.

[5] This speciﬁcation can be applied to pins which have A/D input or analog comparator input functions when the pin is not being used for

those analog functions. When the pin is being used as an analog input pin, the maximum voltage on the pin must be limited to 4.0 V with

respect to V_SS

[6] Pin capacitance is characterized but not tested.

[7] Measured with port in quasi-bidirectional mode.

[8] Measured with port in high-impedance mode.

[9] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is

highest when V_Iis approximately 2 V.

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12. Dynamic characteristics

Table 16. Dynamic characteristics (12 MHz)

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise speciﬁed.^[1][2]

Symbol

Parameter

Conditions

Variable clock

f_osc= 12 MHz Unit

Min Max

Min

Max

7.557

7.741

520

f_osc(RC)

internal RC oscillator frequency industrial

extended

7.189

7.004

320

7.189 7.557 MHz

7.004 7.741 MHz

f_osc(WD)

f_CLKLP

internal watchdog oscillator

frequency

320

520 kHz

low power select clock

frequency

MHz

Glitch ﬁlter

t_gr

glitch rejection time

P1.5/RST pin

any pin except

P1.5/RST

t_sa

signal acceptance time

P1.5/RST pin

125

any pin except

P1.5/RST

External clock

f_osc

oscillator frequency

MHz

T_cy(clk)

t_CHCX

t_CLCX

t_CLCH

t_CHCL

clock cycle time

clock HIGH time

clock LOW time

clock rise time

clock fall time

see Figure 28

_cy(CLK)− t_CLCX

_cy(CLK)− t_CHCX

Shift register (UART mode 0)

T_XLXLserial port clock cycle time

t_QVXH

see Figure 27

16T_cy(CLK)

13T_cy(CLK)

1333

1083

output data set-up to clock rising see Figure 27

edge time

t_XHQX

t_XHDX

t_XHDV

output data hold after clock

rising edge time

see Figure 27

T_cy(CLK)+ 20

103 ns

input data hold after clock rising see Figure 27

edge time

input data valid to clock rising

edge time

see Figure 27

150

SPI interface

f_SPI

SPI operating frequency

CCLK

slave

master

⁄

2.0 MHz

3.0 MHz

CCLK

⁄

T_SPICYC

SPI cycle time

slave

see Figure 23, 24,

25, 26

⁄

500

333

CCLK

master

⁄

CCLK

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Table 16. Dynamic characteristics (12 MHz) …continued

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise speciﬁed.^[1][2]

Symbol

Parameter

Conditions

Variable clock

f_osc= 12 MHz Unit

Min

Max

Min

250

Max

t_SPILEAD

SPI enable lead time

slave

see Figure 25, 26

250

t_SPILAG

SPI enable lag time

slave

t_SPICLKH

SPICLK HIGH time

master

see Figure 23, 24,

25, 26

⁄

165

250

CCLK

slave

⁄

CCLK

t_SPICLKL

SPICLK LOW time

master

see Figure 23, 24,

25, 26

⁄

165

250

CCLK

slave

⁄

CCLK

t_SPIDSU

t_SPIDH

t_SPIA

SPI data set-up time

master or slave

SPI data hold time

master or slave

SPI access time

slave

see Figure 23, 24,

25, 26

100

see Figure 23, 24,

25, 26

see Figure 25, 26

120

240

120 ns

240 ns

t_SPIDIS

SPI disable time

slave

see Figure 25, 26

t_SPIDV

SPI enable to output data valid see Figure 23, 24,

time

25, 26

slave

240

167

240 ns

167 ns

master

t_SPIOH

t_SPIR

SPI output data hold time

see Figure 23, 24,

25, 26

SPI rise time

see Figure 23, 24,

25, 26

SPI outputs

100

100 ns

2000 ns

(SPICLK, MOSI, MISO)

SPI inputs

2000

(SPICLK, MOSI, MISO, SS)

t_SPIF

SPI fall time

see Figure 23, 24,

25, 26

SPI outputs

100

100 ns

2000 ns

(SPICLK, MOSI, MISO)

SPI inputs

2000

(SPICLK, MOSI, MISO, SS)

[1] Parameters are valid over ambient temperature range unless otherwise speciﬁed.

[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

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Table 17. Dynamic characteristics (18 MHz)

V_DD= 3.0 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise speciﬁed.^[1][2]

Symbol

Parameter

Conditions

Variable clock

f_osc= 18 MHz Unit

Min Max

Min

Max

7.557

7.741

520

f_osc(RC)

internal RC oscillator frequency industrial

extended

7.189

7.004

320

7.189 7.557 MHz

7.004 7.741 MHz

f_osc(WD)

f_CLKLP

internal watchdog oscillator

frequency

320

520 kHz

low power select clock

frequency

MHz

Glitch ﬁlter

t_gr

glitch rejection time

P1.5/RST pin

any pin except

P1.5/RST

t_sa

signal acceptance time

P1.5/RST pin

125

any pin except

P1.5/RST

External clock

f_osc

oscillator frequency

MHz

T_cy(clk)

t_CHCX

t_CLCX

t_CLCH

t_CHCL

clock cycle time

clock HIGH time

clock LOW time

clock rise time

clock fall time

see Figure 28

_cy(CLK)− t_CLCX

_cy(CLK)− t_CHCX

Shift register (UART mode 0)

T_XLXLserial port clock cycle time

t_QVXH

see Figure 27

16T_cy(CLK)

13T_cy(CLK)

888

722

output data set-up to clock

rising edge time

t_XHQX

t_XHDX

t_XHDV

output data hold after clock

rising edge time

see Figure 27

T_cy(CLK)+ 20

input data hold after clock rising see Figure 27

edge time

input data valid to clock rising

edge time

see Figure 27

150

SPI interface

f_SPI

SPI operating frequency

CCLK

slave

⁄

3.0 MHz

4.5 MHz

CCLK

master

⁄

T_SPICYC

SPI cycle time

slave

see Figure 23, 24,

25, 26

⁄

333

222

CCLK

master

⁄

CCLK

t_SPILEAD

SPI enable lead time

slave

see Figure 25, 26

250

t_SPILAG

SPI enable lag time

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Table 17. Dynamic characteristics (18 MHz) …continued

V_DD= 3.0 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise speciﬁed.^[1][2]

Symbol

Parameter

Conditions

Variable clock

f_osc= 18 MHz Unit

Min

Max

Min

Max

t_SPICLKH

SPICLK HIGH time

master

see Figure 23, 24,

25, 26

⁄

111

167

CCLK

slave

t_SPICLKL

SPICLK LOW time

master

see Figure 23, 24,

25, 26

⁄

111

167

CCLK

slave

t_SPIDSU

t_SPIDH

t_SPIA

SPI data set-up time

master or slave

SPI data hold time

master or slave

SPI access time

slave

see Figure 23, 24,

25, 26

100

see Figure 23, 24,

25, 26

see Figure 25, 26

160

t_SPIDIS

SPI disable time

slave

see Figure 25, 26

160 ns

t_SPIDV

SPI enable to output data valid see Figure 23, 24,

time

25, 26

slave

160

111

160 ns

111 ns

master

t_SPIOH

t_SPIR

SPI output data hold time

see Figure 23, 24,

25, 26

SPI rise time

see Figure 23, 24,

25, 26

SPI outputs

100

100 ns

2000 ns

(SPICLK, MOSI, MISO)

SPI inputs

2000

(SPICLK, MOSI, MISO, SS)

t_SPIF

SPI fall time

see Figure 23, 24,

25, 26

SPI outputs

100

100 ns

2000 ns

(SPICLK, MOSI, MISO)

SPI inputs

2000

(SPICLK, MOSI, MISO, SS)

[1] Parameters are valid over ambient temperature range unless otherwise speciﬁed.

[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

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12.1 Waveforms

SPICYC

SPIR

SPIF

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(output)

SPIF

SPIR

SPICLKL

SPICLKH

SPICLK

(CPOL = 1)

(output)

SPIDH

SPIDSU

MISO

(input)

LSB/MSB in

MSB/LSB in

SPIDV

SPIOH

SPIR

MOSI

SPIF

(output)

master MSB/LSB out

master LSB/MSB out

002aaa908

Fig 23. SPI master timing (CPHA = 0)

SPICYC

SPIR

SPIF

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(output)

SPIR

SPIF

SPICLKL

SPICLK

(CPOL = 1)

(output)

SPICLKH

SPIDH

SPIDSU

MISO

(input)

LSB/MSB in

MSB/LSB in

SPIDV

SPIOH

SPIR

SPIF

MOSI

(output)

master MSB/LSB out

master LSB/MSB out

002aaa909

Fig 24. SPI master timing (CPHA = 1)

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SPIR

SPIF

SPICYC

SPIR

SPIF

SPILEAD

SPILAG

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(input)

SPIR

SPIF

SPICLKL

SPICLK

(CPOL = 1)

(input)

SPICLKH

SPIOH

SPIDIS

SPIOH

SPIA

SPIDV

MISO

(output)

slave MSB/LSB out

slave LSB/MSB out

not defined

SPIDH

SPIDSU

SPIDH

SPIDSU

MOSI

(input)

MSB/LSB in

LSB/MSB in

002aaa910

Fig 25. SPI slave timing (CPHA = 0)

SPIF

SPIR

SPICYC

SPIR

SPIF

SPILAG

SPILEAD

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(input)

SPIR

SPIF

SPICLKL

SPICLK

(CPOL = 1)

(input)

SPICLKH

SPIOH

SPIDIS

SPIDV

SPIA

MISO

(output)

slave LSB/MSB out

slave MSB/LSB out

not defined

SPIDH

SPIDSU

SPIDH

SPIDSU

MOSI

(input)

MSB/LSB in

LSB/MSB in

002aaa911

Fig 26. SPI slave timing (CPHA = 1)

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XLXL

clock

XHQX

QVXH

output data

write to SBUF

input data

XHDX

set TI

valid

XHDV

valid

clear RI

set RI

002aaa906

Fig 27. Shift register mode timing

CHCX

CHCL

CLCX

CLCH

cy(clk)

002aaa907

Fig 28. External clock timing

12.2 ISP entry mode

Table 18. Dynamic characteristics, ISP entry mode

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

_amb= −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

µs

t_VR

t_RH

t_RL

V_DDactive to RST active delay time

RST HIGH time

µs

RST LOW time

µs

RST

002aaa912

Fig 29. ISP entry timing

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13. Other characteristics

13.1 Comparator electrical characteristics

Table 19. Comparator electrical characteristics

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

_amb= −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IO

input offset voltage

±20

V_IC

common mode input voltage

common mode rejection ratio

total response time

V_DD− 0.3

[1]

CMRR

t_res(tot)

t_(CE-OV)

I_LI

−50

500

250

chip enable to output valid time

input leakage current

µs

0 < V_I< V_DD

±10

µA

[1] This parameter is characterized, but not tested in production.

13.2 ADC electrical characteristics

Table 20. ADC electrical characteristics

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

_amb= −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise speciﬁed.

All limits valid for an external source impedance of less than 10 kΩ.

Symbol

V_IA

Parameter

Conditions

Min

Typ

Max

V_SS+ 0.2

Unit

analog input voltage

analog input capacitance

differential linearity error

integral non-linearity

offset error

V_SS− 0.2

C_ia

E_D

±1

LSB

E_L(adj)

E_O

±1

±2

E_G

gain error

±1

E_u(tot)

M_CTC

α_ct(port)

SR_in

T_cy(ADC)

t_ADC

total unadjusted error

channel-to-channel matching

crosstalk between port inputs

input slew rate

±2

LSB

±1

0 kHz to 100 kHz

A/D enabled

−60

100

2000

V/ms

ADC clock cycle

111

conversion time

13T_cy(ADC)ns

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14. Package outline

DIP14: plastic dual in-line package; 14 leads (300 mil)

SOT27-1

w M

(e )

pin 1 index

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

UNIT

max.

min.

max.

1.73

1.13

0.53

0.38

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05

8.25

7.80

10.0

8.3

4.2

0.51

3.2

2.54

0.1

7.62

0.3

0.254

0.01

2.2

0.068

0.044

0.021

0.015

0.014

0.009

0.77

0.73

0.26

0.24

0.14

0.12

0.32

0.31

0.39

0.33

inches

0.17

0.02

0.13

0.087

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-13

SOT27-1

050G04

MO-001

SC-501-14

Fig 30. Package outline SOT27-1 (DIP14)

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TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

(2)

(1)

UNIT

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.72

0.38

1.1

0.65

0.25

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT402-1

MO-153

Fig 31. Package outline SOT402-1 (TSSOP14)

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Product data sheet

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8-bit microcontrollers with accelerated two-clock 80C51 core

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

(2)

(1)

UNIT

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

1.1

0.65

0.25

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig 32. Package outline SOT403-1 (TSSOP16)

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Product data sheet

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15. Abbreviations

Table 21. Acronym list

Acronym

ADC

Description

Analog to Digital Converter

Central Processing Unit

CPU

CCU

Capture/Compare Unit

DAC

Digital to Analog Converter

Erasable Programmable Read-Only Memory

Electrically Erasable Programmable Read-Only Memory

ElectroMagnetic Interference

Phase-Locked Loop

EPROM

EEPROM

EMI

PLL

PWM

RAM

Pulse Width Modulator

Random Access Memory

Resistance-Capacitance

RTC

Real-Time Clock

SAR

Successive Approximation Register

Special Function Register

SFR

SPI

Serial Peripheral Interface

UART

Universal Asynchronous Receiver/Transmitter

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16. Revision history

Table 22. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

P89LPC915_916_917_5 20091215

Product data sheet

P89LPC915_916_917-04

Modiﬁcations:

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Added ADC electrical characteristics, Table 20.

• Added P89LPC915FN.

P89LPC915_916_917-04 20041217

P89LPC915_916_917-03 20040701

P89LPC915_916_917-02 20040512

P89LPC915_916_917-01 20040408

Product data

P89LPC915_916_917-03

P89LPC915_916_917-02

P89LPC915_916_917-01

Preliminary data

P89LPC915_916_917_5

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17. Legal information

17.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

17.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

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19. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

8.17.1

8.17.2

8.17.3

8.17.4

8.17.5

8.17.6

8.18

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Timer overﬂow toggle output . . . . . . . . . . . . . 40

RTC/system timer. . . . . . . . . . . . . . . . . . . . . . 40

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Baud rate generator and selection. . . . . . . . . 42

Framing error . . . . . . . . . . . . . . . . . . . . . . . . . 42

Break detect. . . . . . . . . . . . . . . . . . . . . . . . . . 42

Double buffering. . . . . . . . . . . . . . . . . . . . . . . 42

Transmit interrupts with double buffering

2.1

2.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Principal features . . . . . . . . . . . . . . . . . . . . . . . 1

Additional features . . . . . . . . . . . . . . . . . . . . . . 1

Product comparison overview . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 7

4.1

8.19

8.19.1

8.19.2

8.19.3

8.19.4

8.19.5

8.19.6

8.19.7

8.19.8

8.19.9

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 9

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin description . . . . . . . . . . . . . . . . . . . . . . . . 11

8.1

8.2

8.3

8.3.1

8.3.2

8.3.3

8.4

8.5

8.6

8.7

8.8

8.9

8.10

8.11

8.12

8.12.1

8.13

8.13.1

Functional description . . . . . . . . . . . . . . . . . . 18

Special function registers . . . . . . . . . . . . . . . . 18

Enhanced CPU. . . . . . . . . . . . . . . . . . . . . . . . 31

Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Clock deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . 31

CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 31

Clock output (P89LPC917). . . . . . . . . . . . . . . 31

On-chip RC oscillator option. . . . . . . . . . . . . . 31

Watchdog oscillator option . . . . . . . . . . . . . . . 31

External clock input option . . . . . . . . . . . . . . . 32

CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 32

CCLK modiﬁcation: DIVM register . . . . . . . . . 32

Low power select . . . . . . . . . . . . . . . . . . . . . . 33

Memory organization . . . . . . . . . . . . . . . . . . . 33

Data RAM arrangement . . . . . . . . . . . . . . . . . 33

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

External interrupt inputs . . . . . . . . . . . . . . . . . 34

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Port conﬁgurations . . . . . . . . . . . . . . . . . . . . . 36

enabled (Modes 1, 2 and 3) . . . . . . . . . . . . . . 42

8.19.10 The 9^thbit (bit 8) in double buffering

(Modes 1, 2 and 3). . . . . . . . . . . . . . . . . . . . . 43

8.20

8.21

8.21.1

8.22

8.22.1

8.22.2

8.22.3

8.23

8.24

8.25

I²C-bus serial interface. . . . . . . . . . . . . . . . . . 43

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Typical SPI conﬁgurations . . . . . . . . . . . . . . . 46

Analog comparators. . . . . . . . . . . . . . . . . . . . 48

Internal reference voltage. . . . . . . . . . . . . . . . 48

Comparator interrupt . . . . . . . . . . . . . . . . . . . 48

Comparators and power reduction modes . . . 48

KBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 50

Additional features . . . . . . . . . . . . . . . . . . . . . 50

Software reset . . . . . . . . . . . . . . . . . . . . . . . . 50

Dual data pointers . . . . . . . . . . . . . . . . . . . . . 50

Flash program memory . . . . . . . . . . . . . . . . . 51

General description . . . . . . . . . . . . . . . . . . . . 51

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Flash organization . . . . . . . . . . . . . . . . . . . . . 51

Using ﬂash as data storage . . . . . . . . . . . . . . 51

Flash programming and erasing. . . . . . . . . . . 51

ICP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

IAP-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Power-on reset code execution . . . . . . . . . . . 52

Hardware activation of the alternate code . . . 52

User conﬁguration bytes. . . . . . . . . . . . . . . . . 52

User sector security bytes . . . . . . . . . . . . . . . 53

8.25.1

8.25.2

8.26

8.13.1.1 Quasi-bidirectional output conﬁguration . . . . . 36

8.13.1.2 Open-drain output conﬁguration . . . . . . . . . . . 37

8.13.1.3 Input-only conﬁguration . . . . . . . . . . . . . . . . . 37

8.13.1.4 Push-pull output conﬁguration . . . . . . . . . . . . 37

8.13.2

8.13.3

8.14

8.14.1

8.14.2

8.15

8.15.1

8.15.2

8.15.3

8.16

8.26.1

8.26.2

8.26.3

8.26.4

8.26.5

8.26.6

8.26.7

8.26.8

8.26.9

8.27

Port 0 analog functions. . . . . . . . . . . . . . . . . . 37

Additional port features. . . . . . . . . . . . . . . . . . 37

Power monitoring functions. . . . . . . . . . . . . . . 38

Brownout detection. . . . . . . . . . . . . . . . . . . . . 38

Power-on detection. . . . . . . . . . . . . . . . . . . . . 38

Power reduction modes . . . . . . . . . . . . . . . . . 38

Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Power-down mode . . . . . . . . . . . . . . . . . . . . . 38

Total Power-down mode . . . . . . . . . . . . . . . . . 39

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Timers/counters 0 and 1. . . . . . . . . . . . . . . . . 39

8.28

A/D converter. . . . . . . . . . . . . . . . . . . . . . . . . . 53

General description . . . . . . . . . . . . . . . . . . . . 53

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 54

9.1

9.2

9.3

8.17

continued >>

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

74 of 75

P89LPC915/916/917

NXP Semiconductors

8-bit microcontrollers with accelerated two-clock 80C51 core

9.4

A/D operating modes . . . . . . . . . . . . . . . . . . . 54

Fixed channel, single conversion mode . . . . . 54

9.4.1

9.4.2

9.4.3

9.4.4

9.4.5

9.4.6

9.5

9.5.1

9.5.2

9.5.3

9.6

Fixed channel, continuous conversion mode . 54

Auto scan, single conversion mode . . . . . . . . 54

Auto scan, continuous conversion mode . . . . 55

Dual channel, continuous conversion mode . . 55

Single step mode . . . . . . . . . . . . . . . . . . . . . . 55

Conversion start modes . . . . . . . . . . . . . . . . . 55

Timer triggered start . . . . . . . . . . . . . . . . . . . . 55

Start immediately . . . . . . . . . . . . . . . . . . . . . . 55

Edge triggered . . . . . . . . . . . . . . . . . . . . . . . . 55

Boundary limits interrupt. . . . . . . . . . . . . . . . . 55

DAC output to a port pin with high output

9.7

impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Power-down and Idle mode . . . . . . . . . . . . . . 56

9.8

9.9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 57

Static characteristics. . . . . . . . . . . . . . . . . . . . 58

12.1

12.2

Dynamic characteristics . . . . . . . . . . . . . . . . . 60

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

ISP entry mode. . . . . . . . . . . . . . . . . . . . . . . . 66

13.1

13.2

Other characteristics. . . . . . . . . . . . . . . . . . . . 67

Comparator electrical characteristics . . . . . . . 67

ADC electrical characteristics. . . . . . . . . . . . . 67

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 68

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 71

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 72

Legal information. . . . . . . . . . . . . . . . . . . . . . . 73

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 73

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 73

17.1

17.2

17.3

17.4

Contact information. . . . . . . . . . . . . . . . . . . . . 73

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 December 2009

Document identifier: P89LPC915_916_917_5

P89LPC917FDH,129 [NXP]

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