P89LPC9301FDH [NXP]

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable flash; 8位微控制器，带有加速双时钟80C51核心4 KB / 8 KB 3 V字节可擦除闪存


型号：	P89LPC9301FDH
厂家：	NXP
描述：	8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable flash 8位微控制器，带有加速双时钟80C51核心4 KB / 8 KB 3 V字节可擦除闪存闪存微控制器和处理器外围集成电路光电二极管时钟
文件：	总65页 (文件大小：297K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

P89LPC9301/931A1

8-bit microcontroller with accelerated two-clock 80C51 core

4 kB/8 kB 3 V byte-erasable ﬂash

Rev. 01 — 9 April 2009

Preliminary data sheet

1. General description

The P89LPC9301/931A1 is a single-chip microcontroller, available in low cost packages,

based on a high performance processor architecture that executes instructions in two to

four clocks, six times the rate of standard 80C51 devices. Many system-level functions

have been incorporated into the P89LPC9301/931A1 in order to reduce component count,

board space, and system cost.

2. Features

2.1 Principal features

I 4 kB/8 kB byte-erasable ﬂash code memory organized into 1 kB sectors and 64-byte

pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.

I 256-byte RAM data memory.

I Two analog comparators with selectable inputs and reference source.

I Two 16-bit counter/timers (each may be conﬁgured to toggle a port output upon timer

overﬂow or to become a PWM output).

I A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit

prescaler and a programmable and readable 16-bit timer.

I Enhanced UART with a fractional baud rate generator, break detect, framing error

detection, and automatic address detection; 400 kHz byte-wide I²C-bus

communication port and SPI communication port.

I 2.4 V to 3.6 V V_DDoperating range. I/O pins are 5 V tolerant (may be pulled up or

driven to 5.5 V).

I Enhanced low voltage (brownout) detect allows a graceful system shutdown when

power fails.

I 28-pin TSSOP and PLCC packages with 23 I/O pins minimum and up to 26 I/O pins

while using on-chip oscillator and reset options.

2.2 Additional features

I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns

for all instructions except multiply and divide when executing at 18 MHz. This is six

times the performance of the standard 80C51 running at the same clock frequency. A

lower clock frequency for the same performance results in power savings and reduced

EMI.

I Serial ﬂash In-Circuit Programming (ICP) allows simple production coding with

commercial EPROM programmers. Flash security bits prevent reading of sensitive

application programs.

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

I Serial ﬂash In-System Programming (ISP) allows coding while the device is mounted

in the end application.

I In-Application Programming (IAP) of the ﬂash code memory. This allows changing the

code in a running application.

I Watchdog timer with separate on-chip oscillator, nominal 400 kHz, calibrated to ±5 %,

requiring no external components. The watchdog prescaler is selectable from

eight values.

I High-accuracy internal RC oscillator option, with clock doubler option, allows operation

without external oscillator components. The RC oscillator option is selectable and ﬁne

tunable.

I Switching on the ﬂy among internal RC oscillator, watchdog oscillator, external clock

source provides optimal support of minimal power active mode with fast switching to

maximum performance.

I Idle and two different power-down reduced power modes. Improved wake-up from

Power-down mode (a LOW interrupt input starts execution). Typical power-down

current is 1 µA (total power-down with voltage comparators disabled).

I Active-LOW reset. On-chip power-on reset allows operation without external reset

components. A software reset function is also available.

I Conﬁgurable on-chip oscillator with frequency range options selected by user

programmed ﬂash conﬁguration bits. Oscillator options support frequencies from

20 kHz to the maximum operating frequency of 18 MHz.

I Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator

allowing it to perform an oscillator fail detect function.

I Programmable port output conﬁguration options: quasi-bidirectional, open drain,

push-pull, input-only.

I High current sourcing/sinking (20 mA) on eight I/O pins (P0.3 to P0.7, P1.4, P1.6,

P1.7). All other port pins have high sinking capability (20 mA). A maximum limit is

speciﬁed for the entire chip.

I Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of

the pins match or do not match a programmable pattern.

I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns

minimum ramp times.

I Only power and ground connections are required to operate the P89LPC9301/931A1

when internal reset option is selected.

I Four interrupt priority levels.

I Eight keypad interrupt inputs, plus two additional external interrupt inputs.

I Schmitt trigger port inputs.

I Second data pointer.

I Emulation support.

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

2 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

P89LPC9301FDH

TSSOP28 plastic thin shrink small outline package; 28

leads; body width 4.4 mm

SOT361-1

P89LPC931A1FDH TSSOP28 plastic thin shrink small outline package; 28

leads; body width 4.4 mm

SOT361-1

3.1 Ordering options

Table 2.

Ordering options

Type number

Flash memory

4 kB

Temperature range

−40 °C to +85 °C

Frequency

P89LPC9301FDH

P89LPC931A1FDH

0 MHz to 18 MHz

8 kB

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

3 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

4. Block diagram

P89LPC9301/931A1

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

4 kB/8 kB

CODE FLASH

TXD

UART

RXD

internal

bus

256-BYTE

DATA RAM

REAL-TIME CLOCK/

SYSTEM TIMER

PORT 3

CONFIGURABLE I/Os

SCL

SDA

P3[1:0]

I C-BUS

PORT 2

CONFIGURABLE I/Os

WATCHDOG TIMER

AND OSCILLATOR

P2[7:0]

P1[7:0]

PORT 1

CONFIGURABLE I/Os

TIMER 0

TIMER 1

CMP2

CIN2A

CIN1A

CIN2B

CMP1

CIN1B

PORT 0

CONFIGURABLE I/Os

ANALOG

COMPARATORS

P0[7:0]

KEYPAD

INTERRUPT

SPICLK

MOSI

MISO

SPI

PROGRAMMABLE

OSCILLATOR DIVIDER

CPU

clock

XTAL1

CRYSTAL

RESONATOR

ON-CHIP RC

OSCILLATOR WITH

CLOCK DOUBLER

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

CONFIGURABLE

OSCILLATOR

XTAL2

002aae447

Fig 1. Block diagram

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

4 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

5. Functional diagram

TXD

RXD

INT0

INT1

KBI0

KBI1

KBI2

KBI3

KBI4

KBI5

KBI6

KBI7

CMP2

CIN2B

CIN2A

CIN1B

CIN1A

CMPREF

CMP1

SCL

SDA

PORT 0

PORT 3

PORT 1

RST

P89LPC9301/

931A1

CLKOUT

XTAL2

XTAL1

MOSI

MISO

PORT 2

SPICLK

002aae448

Fig 2. Functional diagram

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

5 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

6. Pinning information

6.1 Pinning

P2.0

P2.1

P2.7

P2.6

P0.0/CMP2/KBI0

P1.7

P0.1/CIN2B/KBI1

P0.2/CIN2A/KBI2

P0.3/CIN1B/KBI3

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

P1.6

P1.5/RST

P89LPC9301FDH

P89LPC931A1FDH 21

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P1.0/TXD

P1.3/INT0/SDA

P1.2/T0/SCL

P1.1/RXD

P2.2/MOSI

P2.5/SPICLK

P2.4/SS

P2.3/MISO

002aae451

Fig 3. P89LPC9301/931A1 TSSOP28 pin conﬁguration

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

6 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

6.2 Pin description

Table 3.

Pin description

Symbol

Type Description

P0.0 to P0.7

I/O

Port 0: Port 0 is an 8-bit I/O port with a user-conﬁgurable output type. During reset

Port 0 latches are conﬁgured in the input only mode with the internal pull-up

disabled. The operation of Port 0 pins as inputs and outputs depends upon the

port conﬁguration selected. Each port pin is conﬁgured independently. Refer to

Section 7.16.1 “Port conﬁgurations” and Table 10 “Static characteristics” for

details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt trigger inputs.

Port 0 also provides various special functions as described below:

P0.0 — Port 0 bit 0.

P0.0/CMP2/

KBI0

I/O

CMP2 — Comparator 2 output

KBI0 — Keyboard input 0.

P0.1/CIN2B/

KBI1

I/O

P0.1 — Port 0 bit 1.

CIN2B — Comparator 2 positive input B.

KBI1 — Keyboard input 1.

P0.2/CIN2A/

KBI2

I/O

P0.2 — Port 0 bit 2.

CIN2A — Comparator 2 positive input A.

KBI2 — Keyboard input 2.

P0.3/CIN1B/

KBI3

I/O

P0.3 — Port 0 bit 3. High current source.

CIN1B — Comparator 1 positive input B.

KBI3 — Keyboard input 3.

P0.4/CIN1A/

KBI4

I/O

P0.4 — Port 0 bit 4. High current source.

CIN1A — Comparator 1 positive input A.

KBI4 — Keyboard input 4.

P0.5/CMPREF/

KBI5

I/O

P0.5 — Port 0 bit 5. High current source.

CMPREF — Comparator reference (negative) input.

KBI5 — Keyboard input 5.

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

7 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

Table 3.

Pin description …continued

Symbol

Type Description

P0.6/CMP1/KBI6

I/O

P0.6 — Port 0 bit 6. High current source.

CMP1 — Comparator 1 output.

KBI6 — Keyboard input 6.

P0.7/T1/KBI7

P1.0 to P1.7

I/O

P0.7 — Port 0 bit 7. High current source.

T1 — Timer/counter 1 external count input or overﬂow output.

KBI7 — Keyboard input 7.

I/O, I Port 1: Port 1 is an 8-bit I/O port with a user-conﬁgurable output type, except for

[1]

three pins as noted below. During reset Port 1 latches are conﬁgured in the input

only mode with the internal pull-up disabled. The operation of the conﬁgurable

Port 1 pins as inputs and outputs depends upon the port conﬁguration selected.

Each of the conﬁgurable port pins are programmed independently. Refer to

Section 7.16.1 “Port conﬁgurations” and Table 10 “Static characteristics” for

details. P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only.

All pins have Schmitt trigger inputs.

Port 1 also provides various special functions as described below:

P1.0/TXD

I/O

P1.0 — Port 1 bit 0.

TXD — Transmitter output for serial port.

P1.1 — Port 1 bit 1.

P1.1/RXD

P1.2/T0/SCL

I/O

RXD — Receiver input for serial port.

P1.2 — Port 1 bit 2 (open-drain when used as output).

I/O

T0 — Timer/counter 0 external count input or overﬂow output (open-drain when

used as output).

I/O

SCL — I²C-bus serial clock input/output.

P1.3 — Port 1 bit 3 (open-drain when used as output).

INT0 — External interrupt 0 input.

P1.3/INT0/SDA

I/O

SDA — I²C-bus serial data input/output.

P1.4 — Port 1 bit 4. High current source.

INT1 — External interrupt 1 input.

P1.4/INT1

P1.5/RST

I/O

P1.5 — Port 1 bit 5 (input only).

RST — External Reset input during power-on or if selected via UCFG1. When

functioning as a reset input, a LOW on this pin resets the microcontroller, causing

I/O ports and peripherals to take on their default states, and the processor begins

execution at address 0. Also used during a power-on sequence to force ISP mode.

P1.6

I/O

P1.6 — Port 1 bit 6. High current source.

P1.7 — Port 1 bit 7. High current source.

P1.7

P2.0 to P2.7

Port 2: Port 2 is an 8-bit I/O port with a user-conﬁgurable output type. During reset

Port 2 latches are conﬁgured in the input only mode with the internal pull-up

disabled. The operation of Port 2 pins as inputs and outputs depends upon the

port conﬁguration selected. Each port pin is conﬁgured independently. Refer to

Section 7.16.1 “Port conﬁgurations” and Table 10 “Static characteristics” for

details.

All pins have Schmitt trigger inputs.

Port 2 also provides various special functions as described below:

P2.0 — Port 2 bit 0.

P2.0

P2.1

I/O

P2.1 — Port 2 bit 1.

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

8 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

Table 3.

Pin description …continued

Symbol

Type Description

P2.2/MOSI

I/O

P2.2 — Port 2 bit 2.

MOSI — SPI master out slave in. When conﬁgured as master, this pin is output;

when conﬁgured as slave, this pin is input.

P2.3/MISO

I/O

P2.3 — Port 2 bit 3.

MISO — When conﬁgured as master, this pin is input, when conﬁgured as slave,

this pin is output.

P2.4/SS

I/O

P2.4 — Port 2 bit 4.

SS — SPI Slave select.

P2.5 — Port 2 bit 5.

P2.5/SPICLK

I/O

SPICLK — SPI clock. When conﬁgured as master, this pin is output; when

conﬁgured as slave, this pin is input.

P2.6

I/O

P2.6 — Port 2 bit 6.

P2.7 — Port 2 bit 7.

P2.7

P3.0 to P3.1

Port 3: Port 3 is a 2-bit I/O port with a user-conﬁgurable output type. During reset

Port 3 latches are conﬁgured in the input only mode with the internal pull-up

disabled. The operation of Port 3 pins as inputs and outputs depends upon the

port conﬁguration selected. Each port pin is conﬁgured independently. Refer to

Section 7.16.1 “Port conﬁgurations” and Table 10 “Static characteristics” for

details.

All pins have Schmitt trigger inputs.

Port 3 also provides various special functions as described below:

P3.0 — Port 3 bit 0.

P3.0/XTAL2/

CLKOUT

I/O

XTAL2 — Output from the oscillator ampliﬁer (when a crystal oscillator option is

selected via the ﬂash conﬁguration.

CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6).

It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or

external clock input, except when XTAL1/XTAL2 are used to generate clock source

for the RTC/system timer.

P3.1/XTAL1

I/O

P3.1 — Port 3 bit 1.

XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when

selected via the ﬂash conﬁguration). It can be a port pin if internal RC oscillator or

watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not

used to generate the clock for the RTC/system timer.

V_SS

V_DD

Ground: 0 V reference.

Power supply: This is the power supply voltage for normal operation as well as

Idle and Power-down modes.

[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

9 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

7. Functional description

Remark: Please refer to the P89LPC9301/931A1 User manual for a more detailed

functional description.

7.1 Special function registers

Remark: SFR accesses are restricted in the following ways:

• User must not attempt to access any SFR locations not deﬁned.

• Accesses to any deﬁned SFR locations must be strictly for the functions for the SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise speciﬁed, must be written with ‘0’, but can return any value

when read (even if it was written with ‘0’). It is a reserved bit and may be used in

future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.

– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

10 of 65

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Table 4.

Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

ACC*

Accumulator

E0H

A2H

0000 0000

0000 00x0

AUXR1

Auxiliary

function

CLKLP

EBRR

ENT1

ENT0

SRST

DPS

Bit address

F0H

B register

Baud rate

0000 0000

BRGR0^[2]

BEH

generator 0

rate low

BRGR1^[2]

BRGCON

Baud rate

generator 0

rate high

BFH

BDH

0000 0000

xxxx xx00

Baud rate

generator 0

control

SBRGS

BRGEN 00^[2]

CMP1

CMP2

DIVM

Comparator 1

control register

ACH

ADH

95H

CE1

CE2

CP1

CP2

CN1

CN2

OE1

OE2

CO1

CO2

CMF1

CMF2

00^[1]

xx00 0000

0000 0000

Comparator 2

control register

CPU clock

divide-by-M

control

DPTR

Data pointer

(2 bytes)

DPH

Data pointer

high

83H

82H

E7H

E6H

0000 0000

DPL

Data pointer

low

FMADRH

FMADRL

Program ﬂash

address high

Program ﬂash

address low

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Special function registers …continued

Table 4.

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

FMCON

Program ﬂash

control (Read)

E4H

BUSY

HVA

HVE

0111 0000

Program ﬂash

control (Write)

E4H FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 FMCMD.3 FMCMD.2 FMCMD.1 FMCMD.0

E5H

FMDATA

I2ADR

Program ﬂash

data

0000 0000

I²C-bus slave

address

DBH

I2ADR.6

I2ADR.5

I2ADR.4

I2ADR.3

I2ADR.2

I2ADR.1

I2ADR.0

Bit address

I2CON*

I2DAT

I²C-bus control D8H

I2EN

STA

STO

CRSEL 00

x000 00x0

I²C-bus data

DAH

I2SCLH

Serial clock

generator/SCL

duty cycle

DDH

0000 0000

I2SCLL

Serial clock

generator/SCL

duty cycle

I²C-bus status

DCH

D9H

I2STAT

IEN0*

IEN1*

IP0*

STA.4

STA.3

STA.2

STA.1

STA.0

1111 1000

0000 0000

00x0 0000

x000 0000

Bit address

Interrupt

enable 0

A8H

EWDRT

EBO

ES/ESR

ET1

EX1

ET0

EX0

Bit address

Interrupt

enable 1

E8H

EST

ESPI

EKBI

EI2C

00^[1]

Bit address

Interrupt

priority 0

B8H

PWDRT

PBO

PS/PSR

PT1

PX1

PT0

PX0

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Special function registers …continued

Table 4.

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

IP0H

Interrupt

B7H

PWDRTH

PBOH

PSH/

PT1H

PX1H

PT0H

PX0H

00^[1]

x000 0000

priority 0 high

PSRH

Bit address

IP1*

Interrupt

priority 1

F8H

PST

PSPI

PKBI

PI2C

00^[1]

00x0 0000

xxxx xx00

0000 0000

IP1H

Interrupt

priority 1 high

F7H

PSTH

PSPIH

PCH

PKBIH

PI2CH

KBIF

KBCON

KBMASK

Keypad control 94H

PATN

_SEL

Keypad

86H

interrupt mask

KBPATN

P0*

Keypad pattern 93H

1111 1111

Bit address

[1]

Port 0

80H

T1/KB7

CMP1

/KB6

CMPREF

/KB5

CIN1A

/KB4

CIN1B

/KB3

CIN2A

/KB2

CIN2B

/KB1

CMP2

/KB0

Bit address

90H

RST

INT1

INT0/SDA

T0/SCL

RXD

TXD

[1]

P1*

P2*

Port 1

Port 2

Port 3

Bit address

A0H

SPICLK

MISO

MOSI

Bit address

B0H

P3*

XTAL1

(P0M1.1)

XTAL2

P0M1

Port 0 output

mode 1

84H

85H

91H

92H

(P0M1.7)

(P0M1.6)

(P0M1.5)

(P0M1.4)

(P0M1.3)

(P0M1.2)

(P0M1.0) FF^[1]

(P0M2.0) 00^[1]

(P1M1.0) D3^[1]

(P1M2.0) 00^[1]

1111 1111

0000 0000

11x1 xx11

00x0 xx00

P0M2

P1M1

P1M2

Port 0 output

mode 2

(P0M2.7)

(P1M1.7)

(P1M2.7)

(P0M2.6)

(P1M1.6)

(P1M2.6)

(P0M2.5)

(P0M2.4)

(P1M1.4)

(P1M2.4)

(P0M2.3)

(P1M1.3)

(P1M2.3)

(P0M2.2)

(P1M1.2)

(P1M2.2)

(P0M2.1)

(P1M1.1)

(P1M2.1)

Port 1 output

mode 1

Port 1 output

mode 2

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Special function registers …continued

Table 4.

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

Hex Binary

addr.

MSB

LSB

P2M1

P2M2

P3M1

P3M2

PCON

PCONA

Port 2 output

mode 1

A4H (P2M1.7)

A5H (P2M2.7)

(P2M1.6)

(P2M1.5)

(P2M1.4)

(P2M1.3)

(P2M1.2)

(P2M1.1)

(P2M2.1)

(P3M1.1)

(P3M2.1)

PMOD1

SPD

(P2M1.0) FF^[1]

(P2M2.0) 00^[1]

(P3M1.0) 03^[1]

(P3M2.0) 00^[1]

PMOD0 00

1111 1111

0000 0000

xxxx xx11

xxxx xx00

0000 0000

Port 2 output

mode 2

(P2M2.6)

(P2M2.5)

(P2M2.4)

(P2M2.3)

(P2M2.2)

Port 3 output

mode 1

B1H

B2H

87H

B5H

Port 3 output

mode 2

BOI

Power control

SMOD1

RTCPD

SMOD0

GF1

I2PD

GF0

SPPD

Power control

VCPD

00^[1]

Bit address

PSW*

Program status D0H

word

RS1

RS0

0000 0000

xx00 000x

PT0AD

RSTSRC

Port 0 digital

input disable

F6H

PT0AD.5

BOF

PT0AD.4

PT0AD.3

PT0AD.2

R_WD

PT0AD.1

R_SF

[3]

Reset source

DFH

BOIF

RTCS1

POF

R_BK

R_EX

RTCCON

RTCH

RTC control

D1H

D2H

RTCF

RTCS0

ERTC

RTCEN 60^[1][6]011x xx00

RTC register

high

00^[6]

0000 0000

RTCL

RTC register

low

D3H

A9H

SADDR

Serial port

address

SADEN

SBUF

Serial port

address enable

B9H

99H

0000 0000

xxxx xxxx

Serial Port

data buffer

Bit address

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Special function registers …continued

Table 4.

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

SCON*

SSTAT

Serial port

control

98H

SM0/FE

DBMOD

SM1

SM2

REN

TB8

RB8

0000 0000

Serial port

extended

BAH

INTLO

CIDIS

DBISEL

STINT

0000 0000

status register

Stack pointer

81H

E2H

0000 0111

0000 0100

SPCTL

SPI control

SSIG

SPIF

SPEN

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

SPSTAT

SPDAT

TAMOD

SPI status

E1H

E3H

8FH

WCOL

00xx xxxx

0000 0000

xxx0 xxx0

SPI data

Timer 0 and 1

auxiliary mode

T1M2

T0M2

Bit address

TCON*

Timer 0 and 1

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

0000 0000

control

TH0

TH1

TL0

Timer 0 high

Timer 1 high

Timer 0 low

Timer 1 low

8CH

8DH

8AH

8BH

89H

0000 0000

TL1

TMOD

Timer 0 and 1

mode

T1GATE

RCCLK

T1C/T

T1M1

T1M0

T0GATE

TRIM.3

T0C/T

T0M1

T0M0

[5][6]

TRIM

Internal

oscillator trim

96H

A7H

ENCLK

TRIM.5

TRIM.4

TRIM.2

TRIM.1

TRIM.0

[4][6]

WDCON

Watchdog

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

control register

WDL

Watchdog load C1H

1111 1111

WFEED1

Watchdog

feed 1

C2H

WFEED2

Watchdog

feed 2

C3H

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

[1] All ports are in input only (high-impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reﬂects the cause of the P89LPC9301/931A1 reset except BOIF bit. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the

power-on reset value is x011 0000.

[4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

[5] On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset sources that affect these SFRs are power-on reset and watchdog reset.

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Table 5.

Name

Extended special function registers^[1]

Description

SFR

Bit functions and addresses

MSB

Reset value

addr.

LSB

Hex Binary

[2]

BODCFG

BOD

FFC8H

BOICFG1 BOICFG0

conﬁguration

[3]

CLKCON

CLOCK Control FFDEH CLKOK

XTALWD CLKDBL FOSC2

FOSC1

FOSC0

RTCDATH

Real-time clock FFBFH

data register

high

0000 0000

RTCDATL

Real-time clock FFBEH

data register low

0000 0000

[1] Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are

used to access these extended SFRs.

[2] The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset.

[3] CLKCON register reset value comes from UCFG1 and UCFG2. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit

comes from UCFG2.7.

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

7.2 Enhanced CPU

The P89LPC9301/931A1 uses an enhanced 80C51 CPU which runs at six times the

speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and

most instructions execute in one or two machine cycles.

7.3 Clocks

7.3.1 Clock deﬁnitions

The P89LPC9301/931A1 device has several internal clocks as deﬁned below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock

sources (see Figure 4) and can also be optionally divided to a slower frequency (see

Section 7.11 “CCLK modiﬁcation: DIVM register”).

Remark: f_oscis deﬁned as the OSCCLK frequency.

CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine

cycle, and most instructions are executed in one to two machine cycles (two or four CCLK

cycles).

RCCLK — The internal 7.373 MHz RC oscillator output. The clock doubler option, when

enabled, provides an output frequency of 14.746 MHz.

PCLK — Clock for the various peripheral devices and is ^CCLK⁄₂.

7.3.2 CPU clock (OSCCLK)

The P89LPC9301/931A1 provides several user-selectable oscillator options in generating

the CPU clock. This allows optimization for a range of needs from high precision to lowest

possible cost. These options are conﬁgured when the ﬂash is programmed and include an

on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external

crystal, or an external clock source.

7.4 Crystal oscillator option

The crystal oscillator can be optimized for low, medium, or high frequency crystals

covering a range from 20 kHz to 18 MHz. It can be the clock source of OSCCLK, RTC and

WDT.

7.4.1 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic

resonators are also supported in this conﬁguration.

7.4.2 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic

resonators are also supported in this conﬁguration.

7.4.3 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic

resonators are also supported in this conﬁguration.

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7.5 Clock output

The P89LPC9301/931A1 supports a user-selectable clock output function on the

P3.0/XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if

another clock source has been selected (on-chip RC oscillator, watchdog oscillator,

external clock input on XTAL1) and if the RTC and WDT are not using the crystal oscillator

as their clock source. This allows external devices to synchronize to the

P89LPC9301/931A1. This output is enabled by the ENCLK bit in the TRIM register.

The frequency of this clock output is ¹⁄₂that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering Idle, saving additional power.

7.6 On-chip RC oscillator option

The P89LPC9301/931A1 has a 6-bit TRIM register that can be used to tune the frequency

of the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed

value to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature.

End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to

other frequencies. When the clock doubler option is enabled (UCFG2.7 = 1), the output

frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can

be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing

highest performance access. This bit can then be set in software if CCLK is running at

8 MHz or slower. When clock doubler option is enabled, BOE1 bit (UCFG1.5) and BOE0

bit (UCFG1.3) are required to hold the device in reset at power-up until V_DDhas reached

its speciﬁed level.

7.7 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz, calibrated to

± 5 % at room temperature. This oscillator can be used to save power when a high clock

frequency is not needed.

7.8 External clock input option

In this conﬁguration, the processor clock is derived from an external source driving the

P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2/CLKOUT pin

may be used as a standard port pin or a clock output. When using an oscillator frequency

above 12 MHz, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the

device in reset at power-up until V_DDhas reached its speciﬁed level.

7.9 Clock sources switch on the ﬂy

P89LPC9301/931A1 can implement clock source switch in any sources of watchdog

oscillator, 7 MHz/14 MHz internal RC oscillator, external clock source (external crystal or

external clock input) during code is running. CLKOK bit in CLKCON register is used to

indicate the clock switch status. CLKOK is cleared when starting clock source switch and

set when completed. Notice that when CLKOK is ‘0’, writing to CLKCON register is not

allowed.

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8-bit microcontroller with accelerated two-clock 80C51 core

HIGH FREQUENCY

MEDIUM FREQUENCY

LOW FREQUENCY

XTAL1

XTAL2

RTC

OSCCLK

CCLK

DIVM

CPU

WDT

RC OSCILLATOR

RCCLK

WITH CLOCK DOUBLER

÷2

PCLK

(7.3728 MHz/14.7456 MHz ± 1 %)

WATCHDOG

OSCILLATOR

(400 kHz ± 5 %)

TIMER 0 AND

TIMER 1

I C-BUS

SPI

UART

002aae452

Fig 4. Block diagram of oscillator control

7.10 CCLK wake-up delay

The P89LPC9301/931A1 has an internal wake-up timer that delays the clock until it

stabilizes depending on the clock source used. If the clock source is any of the three

crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles

plus 60 µs to 100 µs. If the clock source is the internal RC oscillator, the delay is 200 µs to

300 µs. If the clock source is watchdog oscillator or external clock, the delay is

32 OSCCLK cycles.

7.11 CCLK modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing

CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can

retain the ability to respond to events that would not exit Idle mode by executing its normal

program at a lower rate. This can also allow bypassing the oscillator start-up time in cases

where Power-down mode would otherwise be used. The value of DIVM may be changed

by the program at any time without interrupting code execution.

7.12 Low power select

The P89LPC9301/931A1 is designed to run at 18 MHz (CCLK) maximum. However, if

CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the

power consumption further. On any reset, CLKLP is logic 0 allowing highest performance

access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

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7.13 Memory organization

The various P89LPC9301/931A1 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect

addressing, using instructions other than MOVX and MOVC. All or part of the Stack

may be in this area.

• IDATA

Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via

indirect addressing using instructions other than MOVX and MOVC. All or part of the

Stack may be in this area. This area includes the DATA area and the 128 bytes

immediately above it.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and status

registers, accessible only via direct addressing.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC9301/931A1 has 4 kB/8 kB of on-chip Code memory.

7.14 Data RAM arrangement

The 256 bytes of on-chip RAM are organized as shown in Table 6.

Table 6.

Type

On-chip data memory usages

Data RAM

Size (bytes)

128

DATA

Memory that can be addressed directly and indirectly

Memory that can be addressed indirectly

IDATA

256

7.15 Interrupts

The P89LPC9301/931A1 uses a four priority level interrupt structure. This allows great

ﬂexibility in controlling the handling of the many interrupt sources. The

P89LPC9301/931A1 supports 13 interrupt sources: external interrupts 0 and 1, timers 0

and 1, serial port TX, serial port RX, combined serial port RX/TX, brownout detect,

watchdog/RTC, I²C-bus, keyboard, comparators 1 and 2, SPI.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in

the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global

disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1 and IP1H. An

interrupt service routine in progress can be interrupted by a higher priority interrupt, but

not by another interrupt of the same or lower priority. The highest priority interrupt service

cannot be interrupted by any other interrupt source. If two requests of different priority

levels are pending at the start of an instruction, the request of higher priority level is

serviced.

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If requests of the same priority level are pending at the start of an instruction, an internal

polling sequence determines which request is serviced. This is called the arbitration

ranking. Note that the arbitration ranking is only used to resolve pending requests of the

same priority level.

7.15.1 External interrupt inputs

The P89LPC9301/931A1 has two external interrupt inputs as well as the Keypad Interrupt

function. The two interrupt inputs are identical to those present on the standard 80C51

microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by

setting or clearing bit IT1 or IT0 in Register TCON.

In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle

and a LOW in the next cycle, the interrupt request ﬂag IEn in TCON is set, causing an

interrupt request.

If an external interrupt is enabled when the P89LPC9301/931A1 is put into Power-down or

Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer

to Section 7.18 “Power reduction modes” for details.

IE0

EX0

IE1

EX1

BOIF

EBO

wake-up

(if in power-down)

RTCF

KBIF

EKBI

ERTC

(RTCCON.1)

WDOVF

EWDRT

CMF2

CMF1

EA (IE0.7)

TF0

ET0

TF1

ET1

TI and RI/RI

ES/ESR

interrupt

to CPU

EST

EI2C

SPIF

ESPI

002aae453

Fig 5. Interrupt sources, interrupt enables, and power-down wake-up sources

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8-bit microcontroller with accelerated two-clock 80C51 core

7.16 I/O ports

The P89LPC9301/931A1 has four I/O ports: Port 0, Port 1, Port 2 and Port 3. Ports 0, 1,

and 2 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available

depends upon the clock and reset options chosen, as shown in Table 7.

Table 7.

Number of I/O pins available

Clock source

Reset option

Number of I/O

pins (28-pin

package)

On-chip oscillator or watchdog

oscillator

No external reset (except during

power-up)

External RST pin supported

External clock input

No external reset (except during

power-up)

External RST pin supported

Low/medium/high speed

oscillator (external crystal or

resonator)

No external reset (except during

power-up)

External RST pin supported

7.16.1 Port conﬁgurations

All but three I/O port pins on the P89LPC9301/931A1 may be conﬁgured by software to

one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port

outputs), push-pull, open drain, and input-only. Two conﬁguration registers for each port

select the output type for each port pin.

1. P1.5 (RST) can only be an input and cannot be conﬁgured.

2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be conﬁgured to be either input-only or

open-drain.

7.16.1.1 Quasi-bidirectional output conﬁguration

Quasi-bidirectional output type can be used as both an input and output without the need

to reconﬁgure the port. This is possible because when the port outputs a logic HIGH, it is

weakly driven, allowing an external device to pull the pin LOW. When the pin is driven

LOW, it is driven strongly and able to sink a fairly large current. These features are

somewhat similar to an open-drain output except that there are three pull-up transistors in

the quasi-bidirectional output that serve different purposes.

The P89LPC9301/931A1 is a 3 V device, but the pins are 5 V-tolerant. In

quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current ﬂowing

from the pin to V_DD, causing extra power consumption. Therefore, applying 5 V in

quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression

circuit.

7.16.1.2 Open-drain output conﬁguration

The open-drain output conﬁguration turns off all pull-ups and only drives the pull-down

transistor of the port driver when the port latch contains a logic 0. To be used as a logic

output, a port conﬁgured in this manner must have an external pull-up, typically a resistor

tied to V_DD

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8-bit microcontroller with accelerated two-clock 80C51 core

An open-drain port pin has a Schmitt trigger input that also has a glitch suppression

circuit.

7.16.1.3 Input-only conﬁguration

The input-only port conﬁguration has no output drivers. It is a Schmitt trigger input that

also has a glitch suppression circuit.

7.16.1.4 Push-pull output conﬁguration

The push-pull output conﬁguration has the same pull-down structure as both the

open-drain and the quasi-bidirectional output modes, but provides a continuous strong

pull-up when the port latch contains a logic 1. The push-pull mode may be used when

more source current is needed from a port output. A push-pull port pin has a

Schmitt triggered input that also has a glitch suppression circuit. The P89LPC9301/931A1

device has high current source on eight pins in push-pull mode. See Table 9 “Limiting

values”.

7.16.2 Port 0 analog functions

The P89LPC9301/931A1 incorporates two Analog Comparators. In order to give the best

analog function performance and to minimize power consumption, pins that are being

used for analog functions must have the digital outputs and digital inputs disabled.

Digital outputs are disabled by putting the port output into the Input-Only

(high-impedance) mode.

Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5.

On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.

7.16.3 Additional port features

After power-up, all pins are in Input-Only mode. Please note that this is different from

the LPC76x series of devices.

• After power-up, all I/O pins except P1.5, may be conﬁgured by software.

• Pin P1.5 is input only. Pins P1.2 and P1.3 are conﬁgurable for either input-only or

open-drain.

Every output on the P89LPC9301/931A1 has been designed to sink typical LED drive

current. However, there is a maximum total output current for all ports which must not be

exceeded. Please refer to Table 10 “Static characteristics” for detailed speciﬁcations.

All ports pins that can function as an output have slew rate controlled outputs to limit noise

generated by quickly switching output signals. The slew rate is factory-set to

approximately 10 ns rise and fall times.

7.17 Power monitoring functions

The P89LPC9301/931A1 incorporates power monitoring functions designed to prevent

incorrect operation during initial power-up and power loss or reduction during operation.

This is accomplished with two hardware functions: Power-on detect and brownout detect.

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7.17.1 Brownout detection

The brownout detect function determines if the power supply voltage drops below a

certain level. Enhanced brownout detection has 3 independent functions: BOD reset,

BOD interrupt and BOD FLASH.

BOD reset is always on except in total Power-down mode. It could not be disabled in

software. BOD interrupt may be enabled or disabled in software. BOD FLASH is always

on, except in Power-down modes and could not be disabled in software.

BOD reset and BOD interrupt, each has four trip voltage levels. BOE1 bit (UCFG1.5) and

BOE0 bit (UCFG1.3) are used as trip point conﬁguration bits of BOD reset. BOICFG1 bit

and BOICFG0 bit in register BODCFG are used as trip point conﬁguration bits of BOD

interrupt. BOD reset voltage should be lower than BOD interrupt trip point. BOD FLASH is

used for ﬂash programming/erase protection and has only 1 trip voltage of 2.4 V. Please

refer to P89LPC9301/931A1 User manual for detail conﬁgurations.

If brownout detection is enabled the brownout condition occurs when V_DDfalls below the

brownout trip voltage and is negated when V_DDrises above the brownout trip voltage.

For correct activation of brownout detect, the V_DDrise and fall times must be observed.

Please see Table 10 “Static characteristics” for speciﬁcations.

7.17.2 Power-on detection

The Power-on detect has a function similar to the brownout detect, but is designed to work

as power comes up initially, before the power supply voltage reaches a level where

brownout detect can work. The POF ﬂag in the RSTSRC register is set to indicate an

initial power-up condition. The POF ﬂag will remain set until cleared by software.

7.18 Power reduction modes

The P89LPC9301/931A1 supports three different power reduction modes. These modes

are Idle mode, Power-down mode, and total Power-down mode.

7.18.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor

when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle

mode.

7.18.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption. The

P89LPC9301/931A1 exits Power-down mode via any reset, or certain interrupts. In

Power-down mode, the power supply voltage may be reduced to the data retention supply

voltage V_DDR. This retains the RAM contents at the point where Power-down mode was

entered. SFR contents are not guaranteed after V_DDhas been lowered to V_DDR, therefore

it is highly recommended to wake-up the processor via reset in this case. V_DDmust be

raised to within the operating range before the Power-down mode is exited.

Some chip functions continue to operate and draw power during Power-down mode,

increasing the total power used during power-down. These include: Brownout detect,

watchdog timer, comparators (note that comparators can be powered down separately),

and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator

has been selected as the system clock and the RTC is enabled.

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8-bit microcontroller with accelerated two-clock 80C51 core

7.18.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry and

the voltage comparators are also disabled to conserve additional power. The internal RC

oscillator is disabled unless both the RC oscillator has been selected as the system clock

and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during

power-down, there will be high power consumption. Please use an external low frequency

clock to achieve low power with the RTC running during power-down.

7.19 Reset

The P1.5/RST pin can function as either a LOW-active reset input or as a digital input,

P1.5. The Reset Pin Enable (RPE) bit in UCFG1, when set to logic 1, enables the external

reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin

always functions as a reset input. An external circuit connected to this pin should not

hold this pin LOW during a power-on sequence as this will keep the device in reset.

After power-up this pin will function as deﬁned by the RPE bit. Only a power-up reset will

temporarily override the selection deﬁned by RPE bit. Other sources of reset will not

override the RPE bit.

Note: During a power cycle, V_DDmust fall below V_PORbefore power is reapplied, in order

to ensure a power-on reset (see Table 10 “Static characteristics”).

Reset can be triggered from the following sources:

• External reset pin (during power-up or if user conﬁgured via UCFG1)

• Power-on detect

• Brownout detect

• Watchdog timer

• Software reset

• UART break character detect reset

For every reset source, there is a ﬂag in the Reset Register, RSTSRC. The user can read

this register to determine the most recent reset source. These ﬂag bits can be cleared in

software by writing a logic 0 to the corresponding bit. More than one ﬂag bit may be set:

• During a power-on reset, both POF and BOF are set but the other ﬂag bits are

cleared.

• A Watchdog reset is similar to a power-on reset, both POF and BOF are set but the

other ﬂag bits are cleared.

• For any other reset, previously set ﬂag bits that have not been cleared will remain set.

7.19.1 Reset vector

Following reset, the P89LPC9301/931A1 will fetch instructions from either address 0000H

or the Boot address. The Boot address is formed by using the boot vector as the high byte

of the address and the low byte of the address = 00H.

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The boot address will be used if a UART break reset occurs, or the non-volatile boot

status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see

P89LPC9301/931A1 User manual). Otherwise, instructions will be fetched from address

0000H.

7.20 Timers/counters 0 and 1

The P89LPC9301/931A1 has two general purpose counter/timers which are upward

compatible with the standard 80C51 Timer 0 and Timer 1. Both can be conﬁgured to

operate either as timers or event counters. An option to automatically toggle the T0 and/or

T1 pins upon timer overﬂow has been added.

In the ‘Timer’ function, the register is incremented every machine cycle.

In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its

corresponding external input pin, T0 or T1. In this function, the external input is sampled

once during every machine cycle.

Timer 0 and Timer 1 have ﬁve operating modes (Modes 0, 1, 2, 3 and 6). Modes 0, 1, 2

and 6 are the same for both Timers/Counters. Mode 3 is different.

7.20.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit

Counter with a divide-by-32 prescaler. In this mode, the Timer register is conﬁgured as a

13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

7.20.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

7.20.3 Mode 2

Mode 2 conﬁgures the Timer register as an 8-bit Counter with automatic reload. Mode 2

operation is the same for Timer 0 and Timer 1.

7.20.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit

counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is

in Mode 3 it can still be used by the serial port as a baud rate generator.

7.20.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of

256 timer clocks.

7.20.6 Timer overﬂow toggle output

Timers 0 and 1 can be conﬁgured to automatically toggle a port output whenever a timer

overﬂow occurs. The same device pins that are used for the T0 and T1 count inputs are

also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the ﬁrst

timer overﬂow when this mode is turned on.

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7.21 RTC/system timer

The P89LPC9301/931A1 has a simple RTC that allows a user to continue running an

accurate timer while the rest of the device is powered down. The RTC can be a wake-up

or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler

and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be

reloaded again and the RTCF ﬂag will be set. The clock source for this counter can be

either the CPU clock (CCLK) or the XTAL oscillator. Only power-on reset and watchdog

reset will reset the RTC and its associated SFRs to the default state.

The 16-bit loadable counter portion of the RTC is readable by reading the RTCDATL and

RTCDATH registers.

7.22 UART

The P89LPC9301/931A1 has an enhanced UART that is compatible with the conventional

80C51 UART except that Timer 2 overﬂow cannot be used as a baud rate source. The

P89LPC9301/931A1 does include an independent baud rate generator. The baud rate

can be selected from the oscillator (divided by a constant), Timer 1 overﬂow, or the

independent baud rate generator. In addition to the baud rate generation, enhancements

over the standard 80C51 UART include Framing Error detection, automatic address

recognition, selectable double buffering and several interrupt options. The UART can be

operated in four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU

clock/16.

7.22.1 Mode 0

Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are

transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at ¹⁄₁₆of the CPU clock

frequency.

7.22.2 Mode 1

10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),

8 data bits (LSB ﬁrst), and a stop bit (logic 1). When data is received, the stop bit is stored

in RB8 in special function register SCON. The baud rate is variable and is determined by

the Timer 1 overﬂow rate or the baud rate generator (described in Section 7.22.5 “Baud

rate generator and selection”).

7.22.3 Mode 2

11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data

bits (LSB ﬁrst), a programmable 9^thdata bit, and a stop bit (logic 1). When data is

transmitted, the 9^thdata bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.

Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is

received, the 9^thdata bit goes into RB8 in special function register SCON, while the stop

bit is not saved. The baud rate is programmable to either ¹⁄₁₆or ¹⁄₃₂of the CPU clock

frequency, as determined by the SMOD1 bit in PCON.

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7.22.4 Mode 3

8-bit microcontroller with accelerated two-clock 80C51 core

11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8

data bits (LSB ﬁrst), a programmable 9^thdata bit, and a stop bit (logic 1). In fact, Mode 3 is

the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable

and is determined by the Timer 1 overﬂow rate or the baud rate generator (described in

Section 7.22.5 “Baud rate generator and selection”).

7.22.5 Baud rate generator and selection

The P89LPC9301/931A1 enhanced UART has an independent baud rate generator. The

baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0

SFRs which together form a 16-bit baud rate divisor value that works in a similar manner

as Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be

used for other timing functions.

The UART can use either Timer 1 or the baud rate generator output (see Figure 6). Note

that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The

independent baud rate generators use OSCCLK.

timer 1 overflow

SMOD1 = 1

(PCLK-based)

SBRGS = 0

SBRGS = 1

÷2

baud rate modes 1 and 3

002aaa897

SMOD1 = 0

baud rate generator

(CCLK-based)

Fig 6. Baud rate sources for UART (Modes 1, 3)

7.22.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)

is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is

logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up

when SMOD0 is logic 0.

7.22.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the device

and force the device into ISP mode.

7.22.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be

written to SnBUF while the ﬁrst character is being transmitted. Double buffering allows

transmission of a string of characters with only one stop bit between any two characters,

as long as the next character is written between the start bit and the stop bit of the

previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is

compatible with the conventional 80C51 UART. If enabled, the UART allows writing to

SBUF while the previous data is being shifted out. Double buffering is only allowed in

Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled

(DBMOD = 0).

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7.22.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the TI interrupt is generated

when the double buffer is ready to receive new data.

7.22.10 The 9^thbit (bit 8) in double buffering (modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as long

as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until

the bit is shifted out, as indicated by the TI interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will

be double-buffered together with SBUF data.

7.23 I²C-bus serial interface

The I²C-bus uses two wires (SDA and SCL) to transfer information between devices

connected to the bus, and it has the following features:

• Bidirectional data transfer between masters and slaves

• Multi master bus (no central master)

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer

• The I²C-bus may be used for test and diagnostic purposes.

A typical I²C-bus conﬁguration is shown in Figure 7. The P89LPC9301/931A1 device

provides a byte-oriented I²C-bus interface that supports data transfers up to 400 kHz.

SDA

SCL

I C-bus

OTHER DEVICE

WITH I C-BUS

INTERFACE

OTHER DEVICE

WITH I C-BUS

INTERFACE

P1.3/SDA

P1.2/SCL

P89LPC9301/931A1

002aae455

Fig 7. I²C-bus conﬁguration

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8-bit microcontroller with accelerated two-clock 80C51 core

I2ADR

ADDRESS REGISTER

COMPARATOR

P1.3

INPUT

FILTER

P1.3/SDA

SHIFT REGISTER

ACK

I2DAT

OUTPUT

STAGE

BIT COUNTER /

ARBITRATION

AND SYNC LOGIC

CCLK

INPUT

FILTER

TIMING

AND

CONTROL

LOGIC

P1.2/SCL

SERIAL CLOCK

GENERATOR

OUTPUT

STAGE

interrupt

timer 1

overflow

P1.2

I2CON

I2SCLH

I2SCLL

CONTROL REGISTERS AND

SCL DUTY CYCLE REGISTERS

STATUS

DECODER

status bus

I2STAT

STATUS REGISTER

002aaa899

Fig 8. I²C-bus serial interface block diagram

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7.24 SPI

8-bit microcontroller with accelerated two-clock 80C51 core

The P89LPC9301/931A1 provides another high-speed serial communication interface:

the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with

two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in

either Master mode or Slave mode. It has a Transfer Completion Flag and Write Collision

Flag Protection.

MISO

P2.3

CPU clock

8-BIT SHIFT REGISTER

READ DATA BUFFER

MOSI

P2.2

CONTROL

LOGIC

DIVIDER

BY 4, 16, 64, 128

SPICLK

P2.5

clock

SPI clock (master)

SELECT

P2.4

CLOCK LOGIC

MSTR

SPEN

SPI CONTROL

SPI CONTROL REGISTER

SPI STATUS REGISTER

SPI

interrupt

request

internal

data

bus

002aaa900

Fig 9. SPI block diagram

The SPI interface has four pins: SPICLK, MOSI, MISO and SS:

• SPICLK, MOSI and MISO are typically tied together between two or more SPI

devices. Data ﬂows from master to slave on MOSI (Master Out Slave In) pin and ﬂows

from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output

in the Master mode and is input in the Slave mode. If the SPI system is disabled, i.e.,

SPEN (SPCTL.6) = 0 (reset value), these pins are conﬁgured for port functions.

• SS is the optional slave select pin. In a typical conﬁguration, an SPI master asserts

one of its port pins to select one SPI device as the current slave. An SPI slave device

uses its SS pin to determine whether it is selected.

Typical connections are shown in Figure 10 through Figure 12.

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7.24.1 Typical SPI conﬁgurations

master

slave

MISO

MOSI

MISO

MOSI

8-BIT SHIFT

SPICLK

PORT

SPICLK

SPI CLOCK

GENERATOR

002aaa901

Fig 10. SPI single master single slave conﬁguration

master

slave

MISO

MOSI

8-BIT SHIFT

MOSI

SPICLK

SPI CLOCK

GENERATOR

SPI CLOCK

GENERATOR

002aaa902

Fig 11. SPI dual device conﬁguration, where either can be a master or a slave

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master

slave

MISO

MOSI

MISO

MOSI

8-BIT SHIFT

SPICLK

port

SPICLK

SPI CLOCK

GENERATOR

slave

MISO

MOSI

8-BIT SHIFT

SPICLK

port

002aaa903

Fig 12. SPI single master multiple slaves conﬁguration

7.25 Analog comparators

Two analog comparators are provided on the P89LPC9301/931A1. Input and output

options allow use of the comparators in a number of different conﬁgurations. Comparator

operation is such that the output is a logical one (which may be read in a register and/or

routed to a pin) when the positive input (one of two selectable inputs) is greater than the

negative input (selectable from a pin or an internal reference voltage). Otherwise the

output is a zero. Each comparator may be conﬁgured to cause an interrupt when the

output value changes.

The overall connections to both comparators are shown in Figure 13. The comparators

function to V_DD= 2.4 V.

When each comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are not

guaranteed to be stable for 10 µs. The corresponding comparator interrupt should not be

enabled during that time, and the comparator interrupt ﬂag must be cleared before the

interrupt is enabled in order to prevent an immediate interrupt service.

When a comparator is disabled the comparator’s output, COn, goes HIGH. If the

comparator output was LOW and then is disabled, the resulting transition of the

comparator output from a LOW to HIGH state will set the comparator ﬂag, CMFn. This will

cause an interrupt if the comparator interrupt is enabled. The user should therefore

disable the comparator interrupt prior to disabling the comparator. Additionally, the user

should clear the comparator ﬂag, CMFn, after disabling the comparator.

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CP1

OE1

comparator 1

CO1

(P0.4) CIN1A

(P0.3) CIN1B

CMP1 (P0.6)

(P0.5) CMPREF

change detect

ref(bg)

CMF1

CMF2

CN1

CP2

interrupt

change detect

comparator 2

(P0.2) CIN2A

(P0.1) CIN2B

CMP2 (P0.0)

CO2

OE2

002aae456

CN2

Fig 13. Comparator input and output connections

7.25.1 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single

comparator input pin is used. The value of the internal reference voltage, referred to as

V_ref(bg), is 1.23 V ± 10 %.

7.25.2 Comparator interrupt

Each comparator has an interrupt ﬂag contained in its conﬁguration register. This ﬂag is

set whenever the comparator output changes state. The ﬂag may be polled by software or

may be used to generate an interrupt. The two comparators use one common interrupt

vector. If both comparators enable interrupts, after entering the interrupt service routine,

the user needs to read the ﬂags to determine which comparator caused the interrupt.

7.25.3 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is

activated, but both comparators are disabled automatically in Total Power-down mode.

If a comparator interrupt is enabled (except in Total Power-down mode), a change of the

comparator output state will generate an interrupt and wake-up the processor. If the

comparator output to a pin is enabled, the pin should be conﬁgured in the push-pull mode

in order to obtain fast switching times while in Power-down mode. The reason is that with

the oscillator stopped, the temporary strong pull-up that normally occurs during switching

on a quasi-bidirectional port pin does not take place.

Comparators consume power in Power-down and Idle modes, as well as in the normal

operating mode. This fact should be taken into account when system power consumption

is an issue. To minimize power consumption, the user can disable the comparators via

PCONA.5, or put the device in Total Power-down mode.

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7.26 KBI

8-bit microcontroller with accelerated two-clock 80C51 core

The Keypad Interrupt function (KBI) is intended primarily to allow a single interrupt to be

generated when Port 0 is equal to or not equal to a certain pattern. This function can be

used for bus address recognition or keypad recognition. The user can conﬁgure the port

via SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to deﬁne which input pins

connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is

used to deﬁne a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag

(KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is

matched while the Keypad Interrupt function is active. An interrupt will be generated if

enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to

deﬁne equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in P87LPC76x series,

the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key

connected to Port 0 which is enabled by the KBMASK register will cause the hardware to

set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to

wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in

handheld, battery-powered systems that need to carefully manage power consumption

yet also need to be convenient to use.

In order to set the ﬂag and cause an interrupt, the pattern on Port 0 must be held longer

than six CCLKs.

7.27 Watchdog timer

The watchdog timer causes a system reset when it underﬂows as a result of a failure to

feed the timer prior to the timer reaching its terminal count. It consists of a programmable

12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap

taken from the prescaler. The clock source for the prescaler can be the PCLK, the nominal

400 kHz watchdog oscillator or crystal oscillator. The watchdog timer can only be reset by

a power-on reset. When the watchdog feature is disabled, it can be used as an interval

timer and may generate an interrupt. Figure 14 shows the watchdog timer in Watchdog

mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the

watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog

timer has a time-out period that ranges from a few µs to a few seconds. Please refer to the

P89LPC9301/931A1 User manual for more details.

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8-bit microcontroller with accelerated two-clock 80C51 core

WDL (C1H)

MOV WFEED1, #0A5H

MOV WFEED2, #05AH

PCLK

8-BIT DOWN

COUNTER

watchdog

oscillator

(1)

PRESCALER

reset

÷32

crystal

oscillator

XTALWD

SHADOW REGISTER

PRE2

PRE1

PRE0

WDRUN WDTOF WDCLK

WDCON (A7H)

002aae015

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed

sequence.

Fig 14. Watchdog timer in Watchdog mode (WDTE = 1)

7.28 Additional features

7.28.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,

as if an external reset or watchdog reset had occurred. Care should be taken when writing

to AUXR1 to avoid accidental software resets.

7.28.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address

used with certain instructions. The DPS bit in the AUXR1 register selects one of the two

Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may

be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,

without the possibility of inadvertently altering other bits in the register.

7.29 Flash program memory

7.29.1 General description

The P89LPC9301/931A1 ﬂash memory provides in-circuit electrical erasure and

programming. The ﬂash can be erased, read, and written as bytes. The Sector and Page

Erase functions can erase any ﬂash sector (1 kB) or page (64 bytes). The Chip Erase

operation will erase the entire program memory. ICP using standard commercial

programmers is available. In addition, IAP and byte-erase allows code memory to be used

for non-volatile data storage. On-chip erase and write timing generation contribute to a

user-friendly programming interface. The P89LPC9301/931A1 ﬂash reliably stores

memory contents even after 100,000 erase and program cycles. The cell is designed to

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8-bit microcontroller with accelerated two-clock 80C51 core

optimize the erase and programming mechanisms. The P89LPC9301/931A1 uses V_DDas

the supply voltage to perform the Program/Erase algorithms. When voltage supply is

lower than 2.4 V, the BOD FLASH is tripped and ﬂash erase/program is blocked.

7.29.2 Features

• Programming and erase over the full operating voltage range.

• Byte erase allows code memory to be used for data storage.

• Read/Programming/Erase using ISP/IAP/ICP.

• Internal ﬁxed boot ROM, containing low-level IAP routines available to user code.

• Default loader providing ISP via the serial port, located in upper end of user program

memory.

• Boot vector allows user-provided ﬂash loader code to reside anywhere in the ﬂash

memory space, providing ﬂexibility to the user.

• Any ﬂash program/erase operation in 2 ms.

• Programming with industry-standard commercial programmers.

• Programmable security for the code in the ﬂash for each sector.

• 100,000 typical erase/program cycles for each byte.

• 10 year minimum data retention.

7.29.3 Flash organization

The program memory consists of four/eight 1 kB sectors on the P89LPC9301/931A1

devices. Each sector can be further divided into 64-byte pages. In addition to sector

erase, page erase, and byte erase, a 64-byte page register is included which allows from

1 byte to 64 bytes of a given page to be programmed at the same time, substantially

reducing overall programming time.

7.29.4 Using ﬂash as data storage

The ﬂash code memory array of this device supports individual byte erasing and

programming. Any byte in the code memory array may be read using the MOVC

instruction, provided that the sector containing the byte has not been secured (a MOVC

instruction is not allowed to read code memory contents of a secured sector). Thus any

byte in a non-secured sector may be used for non-volatile data storage.

7.29.5 Flash programming and erasing

Four different methods of erasing or programming of the ﬂash are available. The ﬂash may

be programmed or erased in the end-user application (IAP) under control of the

application’s ﬁrmware. Another option is to use the ICP mechanism. This ICP system

provides for programming through a serial clock/serial data interface. As shipped from the

factory, the upper 512 bytes of user code space contains a serial ISP routine allowing for

the device to be programmed in circuit through the serial port. The ﬂash may also be

programmed or erased using a commercially available EPROM programmer which

supports this device. This device does not provide for direct veriﬁcation of code memory

contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire

user code space.

Remark: When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and ﬂash

erase/program is blocked.

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NXP Semiconductors

7.29.6 ICP

8-bit microcontroller with accelerated two-clock 80C51 core

ICP is performed without removing the microcontroller from the system. The ICP facility

consists of internal hardware resources to facilitate remote programming of the

P89LPC9301/931A1 through a two-wire serial interface. The NXP ICP facility has made

in-circuit programming in an embedded application - using commercially available

programmers - possible with a minimum of additional expense in components and circuit

board area. The ICP function uses ﬁve pins. Only a small connector needs to be available

to interface your application to a commercial programmer in order to use this feature.

Additional details may be found in the P89LPC9301/931A1 User manual.

7.29.7 IAP

IAP is performed in the application under the control of the microcontroller’s ﬁrmware. The

IAP facility consists of internal hardware resources to facilitate programming and erasing.

The NXP IAP has made in-application programming in an embedded application possible

without additional components. Two methods are available to accomplish IAP. A set of

predeﬁned IAP functions are provided in a Boot ROM and can be called through a

common interface, PGM_MTP. Several IAP calls are available for use by an application

program to permit selective erasing and programming of ﬂash sectors, pages, security

bits, conﬁguration bytes, and device ID. These functions are selected by setting up the

microcontroller’s registers before making a call to PGM_MTP at FF03H. The Boot ROM

occupies the program memory space at the top of the address space from FF00H to

FEFFH, thereby not conﬂicting with the user program memory space.

In addition, IAP operations can be accomplished through the use of four SFRs consisting

of a control/status register, a data register, and two address registers. Additional details

may be found in the P89LPC9301/931A1 User manual.

7.29.8 ISP

ISP is performed without removing the microcontroller from the system. The ISP facility

consists of a series of internal hardware resources coupled with internal ﬁrmware to

facilitate remote programming of the P89LPC9301/931A1 through the serial port. This

ﬁrmware is provided by NXP and embedded within each P89LPC9301/931A1 device. The

NXP ISP facility has made in-system programming in an embedded application possible

with a minimum of additional expense in components and circuit board area. The ISP

function uses ﬁve pins (V_DD, V_SS, TXD, RXD, and RST). Only a small connector needs to

be available to interface your application to an external circuit in order to use this feature.

7.29.9 Power-on reset code execution

The P89LPC9301/931A1 contains two special ﬂash elements: the Boot Vector and the

Boot Status bit. Following reset, the P89LPC9301/931A1 examines the contents of the

Boot Status bit. If the Boot Status bit is set to zero, power-up execution starts at location

0000H, which is the normal start address of the user’s application code. When the Boot

Status bit is set to a value other than zero, the contents of the Boot Vector are used as the

high byte of the execution address and the low byte is set to 00H.

Table 8 shows the factory default Boot Vector setting for these devices. A factory-provided

bootloader is pre-programmed into the address space indicated and uses the indicated

bootloader entry point to perform ISP functions. This code can be erased by the user.

P89LPC9301_931A1_1

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P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

Remark: Users who wish to use this loader should take precautions to avoid erasing the

1 kB sector that contains this bootloader. Instead, the page erase function can be used to

erase the ﬁrst eight 64-byte pages located in this sector.

A custom bootloader can be written with the Boot Vector set to the custom bootloader, if

desired.

Table 8.

Device

Default boot vector values and ISP entry points

Default

Default bootloader 1 kB sector

boot vector

bootloader

entry point

code range

range

P89LPC9301

0FH

1FH

0F00H

1F00H

0E00H to 0FFFH

1E00H to 1FFFH

0C00H to 0FFFH

1C00H to 1FFFH

P89LPC931A1

7.29.10 Hardware activation of the bootloader

The bootloader can also be executed by forcing the device into ISP mode during a

power-on sequence (see the P89LPC9301/931A1 User manual for speciﬁc information).

This has the same effect as having a non-zero status byte. This allows an application to

be built that will normally execute user code but can be manually forced into ISP

operation. If the factory default setting for the boot vector is changed, it will no longer point

to the factory pre-programmed ISP bootloader code. After programming the ﬂash, the

status byte should be programmed to zero in order to allow execution of the user’s

application code beginning at address 0000H.

7.30 User conﬁguration bytes

Some user-conﬁgurable features of the P89LPC9301/931A1 must be deﬁned at power-up

and therefore cannot be set by the program after start of execution. These features are

conﬁgured through the use of the ﬂash byte UCFG1 and UCFG2. Please see the

P89LPC9301/931A1 User manual for additional details.

7.31 User sector security bytes

There are four/eight User Sector Security Bytes on the P89LPC9301/931A1. Each byte

corresponds to one sector. Please see the P89LPC9301/931A1 User manual for

additional details.

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Preliminary data sheet

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P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

8. Limiting values

Table 9.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

T_amb(bias)

T_stg

Parameter

Conditions

Min

−55

−65

Max

+125

+150

Unit

°C

bias ambient temperature

storage temperature

°C

I_OH(I/O)

HIGH-level output current per

input/output pin

I_OL(I/O)

LOW-level output current per

input/output pin

I_I/Otot(max)

V_n

maximum total input/output current

voltage on any other pin

100

3.5

except V_SS, with respect to

V_DD

P_tot(pack)

total power dissipation (per package) based on package heat

transfer, not device power

1.5

consumption

[2]

V_esd

electrostatic discharge voltage

human body model; all pins

−2000

−500

+2000

+500

charged device model; all

pins

[1] The following applies to Table 9:

a) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over ambient temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

[2] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

system frequency

(MHz)

2.4

2.7

3.0

(V)

3.3

3.6

002aae351

Fig 15. Frequency vs. supply voltage

P89LPC9301_931A1_1

Preliminary data sheet

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41 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

9. Static characteristics

Table 10. Static characteristics

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

Symbol

I_DD(oper)

Parameter

Conditions

Min

Typ^[1]

Max

Unit

µA

[2]

[3]

[4]

operating supply current

V_DD= 3.6 V; f_osc= 12 MHz

V_DD= 3.6 V; f_osc= 18 MHz

V_DD= 3.6 V; f_osc= 12 MHz

V_DD= 3.6 V; f_osc= 18 MHz

I_DD(idle)

Idle mode supply current

3.25

I_DD(pd)

I_DD(tpd)

(dV/dt)_r

V_DDR

Power-down mode supply

current

V_DD= 3.6 V; voltage

comparators powered down

[5]

total Power-down mode

supply current

V_DD= 3.6 V

µA

V/s

rise rate

of V_DD; to ensure power-on

reset signal

5000

data retention supply

voltage

1.5

V_th(HL)

HIGH-LOW threshold

voltage

except SCL, SDA

0.22V_DD

0.4V_DD

V_IL

LOW-level input voltage

SCL, SDA only

−0.5

0.3V_DD

0.7V_DD

V_th(LH)

LOW-HIGH threshold

voltage

except SCL, SDA

0.6V_DD

V_IH

HIGH-level input voltage

hysteresis voltage

SCL, SDA only

port 1

0.7V_DD

5.5

V_hys

V_OL

0.2V_DD

0.6

[6]

LOW-level output voltage

I_OL= 20 mA; V_DD= 2.4 V to

3.6 V all ports, all modes

except high-Z

1.0

I_OL= 3.2 mA; V_DD= 2.4 V to

0.2

0.3

3.6 V all ports, all modes

except high-Z

V_OH

HIGH-level output voltage

I_OH= −20 µA;

_DD− 0.3

_DD− 0.2

_DD− 0.4

V_DD= 2.4 V to 3.6 V;all ports,

quasi-bidirectional mode

_OH= −3.2 mA;

_DD= 2.4 V to 3.6 V;all ports,

push-pull mode

_DD− 0.7

I_OH= −10 mA;

3.2

V_DD= 2.4 V to 3.6 V; all ports,

push-pull mode

V_xtal

V_n

crystal voltage

on XTAL1, XTAL2 pins; with

respect to V_SS

−0.5

+4.0

+5.5

[7]

voltage on any other pin

except XTAL1, XTAL2, V_DD

with respect to V_SS

;

[8]

[9]

C_iss

I_IL

input capacitance

µA

LOW-level input current

input leakage current

V_I= 0.4 V

−80

±1

[10]

I_LI

V_I= V_IL, V_IH, or V_th(HL)

P89LPC9301_931A1_1

Preliminary data sheet

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42 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

Table 10. Static characteristics …continued

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

Symbol

I_THL

Parameter

Conditions

Min

Typ^[1]

Max

Unit

[11]

HIGH-LOW transition

current

all ports; V_I= 1.5 V at

−30

−450

µA

V_DD= 3.6 V

R_{RST_N(int)}internal pull-up resistance

on pin RST

pin RST

kΩ

V_ref(bg)

TC_bg

band gap reference voltage

1.11

1.23

1.34

band gap temperature

coefﬁcient

ppm/

°C

[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.

[2] The I_DD(oper)speciﬁcation is measured using an external clock with code while(1) {} executed from on-chip ﬂash.

[3] The I_DD(idle)speciﬁcation is measured using an external clock with no active peripherals, with the following functions disabled: real-time

clock and watchdog timer.

[4] The I_DD(pd)speciﬁcation is measured using internal RC oscillator with the following functions disabled: comparators, real-time clock, and

watchdog timer.

[5] The I_DD(tpd)speciﬁcation is measured using an external clock with the following functions disabled: comparators, real-time clock,

brownout detect, and watchdog timer.

[6] See Section 8 “Limiting values” for steady state (non-transient) limits on I_OLor I_OH. If I_OL/I_OHexceeds the test condition, V_OL/V_OHmay

exceed the related speciﬁcation.

[7] This speciﬁcation can be applied to pins which have A/D input or analog comparator input functions when the pin is not being used for

those analog functions. When the pin is being used as an analog input pin, the maximum voltage on the pin must be limited to 4.0 V with

respect to V_SS

[8] Pin capacitance is characterized but not tested.

[9] Measured with port in quasi-bidirectional mode.

[10] Measured with port in high-impedance mode.

[11] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is

highest when V_Iis approximately 2 V.

P89LPC9301_931A1_1

Preliminary data sheet

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43 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

9.1 Current characteristics

Note: The graphs provided are a statistical summary based on a limited number of

samples and only for information purposes. The performance characteristics listed are not

tested or guaranteed.

002aae363

18 MHz

(mA)

12 MHz

8 MHz

6 MHz

4 MHz

2 MHz

1 MHz

32 kHz

2.4

2.8

3.2

3.6

(V)

Test conditions: normal mode, code while(1) {} executed from on-chip ﬂash; using an external

clock.

Fig 16. I_DD(oper)vs. frequency at +25 °C

002aae364

18 MHz

(mA)

12 MHz

8 MHz

6 MHz

4 MHz

2 MHz

1 MHz

32 kHz

2.4

2.8

3.2

3.6

(V)

Test conditions: normal mode, code while(1) {} executed from on-chip ﬂash; using an external

clock.

Fig 17. I_DD(oper)vs. frequency at −40 °C

P89LPC9301_931A1_1

Preliminary data sheet

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P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

002aae365

18 MHz

(mA)

12 MHz

8 MHz

6 MHz

4 MHz

2 MHz

1 MHz

32 kHz

2.4

2.8

3.2

3.6

(V)

Test conditions: normal mode, code while(1) {} executed from on-chip ﬂash; using an external

clock.

Fig 18. I_DD(oper)vs. frequency at +85 °C

002aae366

5.0

18 MHz

12 MHz

(mA)

4.0

3.0

2.0

1.0

0.0

8 MHz

6 MHz

4 MHz

2 MHz

1 MHz

32 kHz

2.4

2.8

3.2

3.6

(V)

Test conditions: Idle mode entered executing code from on-chip ﬂash; using an external clock with

no active peripherals, with the following functions disabled: real-time clock and watchdog timer.

Fig 19. I_DD(idle)vs. frequency at +25 °C

P89LPC9301_931A1_1

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P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

002aae367

18 MHz

5.0

(mA)

4.0

12 MHz

3.0

2.0

1.0

0.0

8 MHz

6 MHz

4 MHz

2 MHz

1 MHz

32 kHz

2.4

2.8

3.2

3.6

(V)

Test conditions: Idle mode entered executing code from on-chip ﬂash; using an external clock with

no active peripherals, with the following functions disabled: real-time clock and watchdog timer.

Fig 20. I_DD(idle)vs. frequency at −40 °C

002aae368

5.0

18 MHz

12 MHz

(mA)

4.0

3.0

2.0

1.0

0.0

8 MHz

6 MHz

4 MHz

2 MHz

1 MHz

32 kHz

2.4

2.8

3.2

3.6

(V)

Test conditions: Idle mode entered executing code from on-chip ﬂash; using an external clock with

no active peripherals, with the following functions disabled: real-time clock and watchdog timer.

Fig 21. I_DD(idle)vs. frequency at +85 °C

P89LPC9301_931A1_1

Preliminary data sheet

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46 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

002aae369

(1)

20.0

(µA)

18.0

16.0

14.0

12.0

10.0

(2)

(3)

2.4

2.8

3.2

3.6

(V)

Test conditions: Power-down mode, using internal RC oscillator with the following functions

disabled: comparators, real-time clock, and watchdog timer.

(1) +85 °C

(2) +25 °C

(3) −40 °C

Fig 22. I_DD(pd)vs. V_DD

002aae370

(1)

1.2

(µA)

0.8

0.4

(2)

(3)

0.0

2.4

2.8

3.2

3.6

(V)

Test conditions: Total Power-down mode, using internal RC oscillator with the following functions

disabled: comparators, brownout detect, real-time clock, and watchdog timer.

(1) +85 °C

(2) −40 °C

(3) +25 °C

Fig 23. I_DD(tpd)vs. V_DD

P89LPC9301_931A1_1

Preliminary data sheet

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47 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

9.2 Internal RC/watchdog oscillator characteristics

Note: The graphs provided are a statistical summary based on a limited number of

samples and only for information purposes. The performance characteristics listed are not

tested or guaranteed.

002aae344

0.2

frequency

deviation

(%)

0.1

−0.1

−0.2

2.4

2.8

3.2

3.6

(V)

Central frequency of internal RC oscillator = 7.3728 MHz

Fig 24. Average internal RC oscillator frequency vs. V_DDat +25 °C

002aae346

0.2

frequency

deviation

(%)

0.1

−0.1

−0.2

2.4

2.8

3.2

3.6

(V)

Note: Central frequency of internal RC oscillator = 7.3728 MHz

Fig 25. Average internal RC oscillator frequency vs. V_DDat −40 °C

P89LPC9301_931A1_1

Preliminary data sheet

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48 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

002aae347

0.2

frequency

deviation

(%)

−0.2

−0.4

−0.6

2.4

2.8

3.2

3.6

(V)

Central frequency of internal RC oscillator = 7.3728 MHz

Fig 26. Average internal RC oscillator frequency vs. V_DDat +85 °C

002aae348

2.5

frequency

deviation

(%)

1.5

0.5

−0.5

−1.5

2.4

2.8

3.2

3.6

(V)

Central frequency of watchdog oscillator = 400 kHz

Fig 27. Average watchdog oscillator frequency vs. V_DDat +25 °C

P89LPC9301_931A1_1

Preliminary data sheet

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49 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

002aae349

0.5

frequency

deviation

(%)

−0.5

−1.5

−2.5

−3.5

2.4

2.8

3.2

3.6

(V)

Central frequency of watchdog oscillator = 400 kHz

Fig 28. Average watchdog oscillator frequency vs. V_DDat −40 °C

002aae350

1.5

frequency

deviation

(%)

0.5

−0.5

−1.5

−2.5

2.4

2.8

3.2

3.6

(V)

Central frequency of watchdog oscillator = 400 kHz

Fig 29. Average watchdog oscillator frequency vs. V_DDat +85 °C

P89LPC9301_931A1_1

Preliminary data sheet

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50 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

9.3 BOD characteristics

Table 11. BOD static characteristics

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

Symbol Parameter

BOD interrupt

Conditions

Min

Typ^[1]

Max

Unit

V_trip

trip voltage

falling stage

BOICFG1, BOICFG0 = 01

BOICFG1, BOICFG0 = 10

BOICFG1, BOICFG0 = 11

rising stage

2.25

2.60

3.10

2.55

2.80

3.40

BOICFG1, BOICFG0 = 01

BOICFG1, BOICFG0 = 10

BOICFG1, BOICFG0 = 11

2.30

2.70

3.15

2.60

2.90

3.45

BOD reset

V_trip

trip voltage

falling stage

BOE1, BOE0 = 01

BOE1, BOE0 = 10

BOE1, BOE0 = 11

rising stage

2.10

2.25

2.80

2.30

2.55

3.20

BOE1, BOE0 = 01

BOE1, BOE0 = 10

BOE1, BOE0 = 11

2.20

2.30

2.90

2.40

2.60

3.30

BOD EEPROM/ﬂash

V_triptrip voltage

falling stage

rising stage

2.25

2.30

2.55

2.60

[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.

trip

(BOF/BOIF

set by hardware)

(BOF/BOIF can be

cleared in software)

BOF/BOIF

002aae352

Fig 30. BOD interrupt/reset characteristics

P89LPC9301_931A1_1

Preliminary data sheet

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P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

10. Dynamic characteristics

Table 12. Dynamic characteristics (12 MHz)

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.^[1][2]

Symbol

Parameter

Conditions

Variable clock

f_osc= 12 MHz Unit

Min Max

Min

Max

f_osc(RC)

internal RC oscillator

frequency

nominal f = 7.3728 MHz

trimmed to ± 1 % at

7.189

7.557

7.189 7.557 MHz

_amb= 25 °C; clock

doubler option = OFF

(default)

nominal f = 14.7456 MHz;

clock doubler option = ON,

14.378

380

15.114

420

14.378 15.114 MHz

V_DD= 2.7 V to 3.6 V

f_osc(WD)

internal watchdog

oscillator frequency

T_amb= 25 °C

380

420 kHz

f_osc

oscillator frequency

clock cycle time

MHz

T_cy(clk)

f_CLKLP

see Figure 32

low-power select clock

frequency

MHz

Glitch ﬁlter

t_gr

glitch rejection time

P1.5/RST pin

any pin except P1.5/RST

t_sa

signal acceptance time P1.5/RST pin

125

any pin except P1.5/RST

External clock

t_CHCX

t_CLCX

t_CLCH

t_CHCL

clock HIGH time

see Figure 32

_cy(clk)− t_CLCX

clock LOW time

clock rise time

clock fall time

T_cy(clk)− t_CHCX

Shift register (UART mode 0)

T_XLXL

t_QVXH

t_XHQX

t_XHDX

t_XHDV

serial port clock cycle

time

see Figure 31

16T_cy(clk)

1333

1083

output data set-up to

clock rising edge time

13T_cy(clk)

output data hold after

clock rising edge time

T_cy(clk)+ 20

103 ns

input data hold after

clock rising edge time

input data valid to clock see Figure 31

rising edge time

150

SPI interface

f_SPI

SPI operating frequency

CCLK

slave

⁄

2.0

3.0

MHz

CCLK

master

⁄

P89LPC9301_931A1_1

Preliminary data sheet

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P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

Table 12. Dynamic characteristics (12 MHz) …continued

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.^[1][2]

Symbol

Parameter

Conditions

Variable clock

f_osc= 12 MHz Unit

Min

Max

Min

Max

T_SPICYC

SPI cycle time

slave

see Figure 33, 34, 35, 36

⁄

500

333

CCLK

master

CCLK

t_SPILEAD

SPI enable lead time

slave

see Figure 35, 36

250

t_SPILAG

SPI enable lag time

slave

see Figure 35, 36

t_SPICLKH

SPICLK HIGH time

master

see Figure 33, 34, 35, 36

⁄

165

250

CCLK

slave

⁄

CCLK

t_SPICLKL

SPICLK LOW time

master

see Figure 33, 34, 35, 36

⁄

165

250

100

CCLK

slave

⁄

CCLK

t_SPIDSU

t_SPIDH

t_SPIA

SPI data set-up time

master or slave

SPI data hold time

master or slave

SPI access time

slave

see Figure 33, 34, 35, 36

see Figure 35, 36

100

120

240

120 ns

240 ns

t_SPIDIS

SPI disable time

slave

see Figure 35, 36

t_SPIDV

SPI enable to output

data valid time

see Figure 33, 34, 35, 36

slave

240

167

240 ns

167 ns

master

t_SPIOH

t_SPIR

SPI output data hold

time

see Figure 33, 34, 35, 36

SPI rise time

SPI outputs (SPICLK,

MOSI, MISO)

100

100 ns

2000 ns

SPI inputs (SPICLK,

MOSI, MISO, SS)

2000

t_SPIF

SPI fall time

see Figure 33, 34, 35, 36

SPI outputs (SPICLK,

MOSI, MISO)

100

100 ns

2000 ns

SPI inputs (SPICLK,

MOSI, MISO, SS)

2000

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

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8-bit microcontroller with accelerated two-clock 80C51 core

Table 13. Dynamic characteristics (18 MHz)

V_DD= 3.0 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.^[1][2]

Symbol Parameter

Conditions

Variable clock

f_osc= 18 MHz Unit

Min Max

Min

Max

f_osc(RC)

internal RC oscillator

frequency

nominal f = 7.3728 MHz

trimmed to ± 1 % at

7.189

7.557

7.189 7.557 MHz

_amb= 25 °C; clock

doubler option = OFF

(default)

nominal f = 14.7456 MHz;

clock doubler option = ON

14.378

380

15.114

420

14.378 15.114 MHz

f_osc(WD)internal watchdog

oscillator frequency

T_amb= 25 °C

380

420 kHz

f_osc

oscillator frequency

clock cycle time

MHz

T_cy(clk)

f_CLKLP

see Figure 32

low-power select clock

frequency

MHz

Glitch ﬁlter

t_gr

glitch rejection time

P1.5/RST pin

any pin except P1.5/RST

t_sa

signal acceptance time P1.5/RST pin

125

any pin except P1.5/RST

External clock

t_CHCX

t_CLCX

t_CLCH

t_CHCL

clock HIGH time

see Figure 32

_cy(clk)− t_CLCX

clock LOW time

clock rise time

clock fall time

_cy(clk)− t_CHCX

Shift register (UART mode 0)

T_XLXL

t_QVXH

t_XHQX

t_XHDX

t_XHDV

serial port clock cycle

time

see Figure 31

16T_cy(clk)

888

722

output data set-up to

clock rising edge time

13T_cy(clk)

output data hold after

clock rising edge time

T_cy(clk)+ 20

input data hold after

clock rising edge time

input data valid to clock see Figure 31

rising edge time

150

SPI interface

f_SPISPI operating frequency

CCLK

slave

⁄

3.0

4.5

MHz

CCLK

master

⁄

T_SPICYCSPI cycle time

see Figure 33, 34, 35, 36

slave

⁄

333

222

CCLK

master

⁄

CCLK

P89LPC9301_931A1_1

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8-bit microcontroller with accelerated two-clock 80C51 core

Table 13. Dynamic characteristics (18 MHz) …continued

V_DD= 3.0 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.^[1][2]

Symbol Parameter

Conditions

Variable clock

Min Max

f_osc= 18 MHz Unit

Min

250

Max

t_SPILEADSPI enable lead time

slave

see Figure 35, 36

see Figure 33, 34, 35, 36

250

t_SPILAG

SPI enable lag time

slave

t_SPICLKHSPICLK HIGH time

slave

⁄

167

111

CCLK

master

t_SPICLKLSPICLK LOW time

slave

⁄

CCLK

see Figure 33, 34, 35, 36

⁄

167

111

CCLK

master

⁄

CCLK

t_SPIDSU

t_SPIDH

t_SPIA

SPI data set-up time

master or slave

SPI data hold time

master or slave

SPI access time

slave

see Figure 33, 34, 35, 36

see Figure 35, 36

100

160

t_SPIDIS

SPI disable time

slave

see Figure 35, 36

160 ns

t_SPIDV

SPI enable to output

data valid time

see Figure 33, 34, 35, 36

slave

160

111

160 ns

111 ns

master

t_SPIOH

t_SPIR

SPI output data hold

time

see Figure 33, 34, 35, 36

SPI rise time

SPI outputs (SPICLK,

MOSI, MISO)

100

100 ns

2000 ns

SPI inputs (SPICLK,

MOSI, MISO, SS)

2000

t_SPIF

SPI fall time

see Figure 33, 34, 35, 36

SPI outputs (SPICLK,

MOSI, MISO)

100

100 ns

2000 ns

SPI inputs (SPICLK,

MOSI, MISO, SS)

2000

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

P89LPC9301_931A1_1

Preliminary data sheet

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NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

10.1 Waveforms

XLXL

clock

XHQX

QVXH

output data

write to SBUF

input data

XHDX

set TI

valid

XHDV

valid

clear RI

set RI

002aaa906

Fig 31. Shift register mode timing

CHCX

CHCL

CLCX

CLCH

cy(clk)

002aaa907

Fig 32. External clock timing (with an amplitude of at least V_i(RMS)= 200 mV)

SPICYC

SPIR

SPIF

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(output)

SPIF

SPIR

SPICLKL

SPICLKH

SPICLK

(CPOL = 1)

(output)

SPIDH

SPIDSU

MISO

(input)

LSB/MSB in

MSB/LSB in

SPIR

SPIDV

SPIOH

SPIDV

MOSI

SPIF

(output)

master MSB/LSB out

master LSB/MSB out

002aaa908

Fig 33. SPI master timing (CPHA = 0)

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Preliminary data sheet

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8-bit microcontroller with accelerated two-clock 80C51 core

SPICYC

SPIR

SPIF

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(output)

SPIR

SPIF

SPICLKL

SPICLK

(CPOL = 1)

(output)

SPICLKH

SPIDH

SPIDSU

MISO

(input)

LSB/MSB in

MSB/LSB in

SPIDV

SPIOH

SPIDV

SPIF

SPIR

MOSI

(output)

master MSB/LSB out

master LSB/MSB out

002aaa909

Fig 34. SPI master timing (CPHA = 1)

SPIR

SPICYC

SPIR

SPIF

SPILAG

SPILEAD

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(input)

SPIR

SPIF

SPICLKL

SPICLK

(CPOL = 1)

(input)

SPICLKH

SPIOH

SPIDIS

SPIOH

SPIA

SPIDV

MISO

(output)

slave MSB/LSB out

slave LSB/MSB out

not defined

SPIDH

SPIDSU

SPIDH

SPIDSU

MOSI

(input)

MSB/LSB in

LSB/MSB in

002aaa910

Fig 35. SPI slave timing (CPHA = 0)

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Preliminary data sheet

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NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

SPIR

SPICYC

SPIR

SPIF

SPILAG

SPILEAD

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(input)

SPIR

SPIF

SPICLKL

SPICLK

(CPOL = 1)

(input)

SPICLKH

SPIOH

SPIDIS

SPIDV

SPIA

MISO

(output)

slave LSB/MSB out

slave MSB/LSB out

not defined

SPIDH

SPIDSU

SPIDH

SPIDSU

MOSI

(input)

MSB/LSB in

LSB/MSB in

002aaa911

Fig 36. SPI slave timing (CPHA = 1)

10.2 ISP entry mode

Table 14. Dynamic characteristics, ISP entry mode

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

Symbol Parameter Conditions

V_DDactive to RST active delay time pin RST

Min

Typ

Max

Unit

µs

t_VR

t_RH

t_RL

RST HIGH time

RST LOW time

pin RST

µs

RST

002aaa912

Fig 37. ISP entry waveform

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Preliminary data sheet

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8-bit microcontroller with accelerated two-clock 80C51 core

11. Other characteristics

11.1 Comparator electrical characteristics

Table 15. Comparator electrical characteristics

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IO

input offset voltage

±20

V_IC

common-mode input voltage

common-mode rejection ratio

total response time

V_DD− 0.3

[1]

CMRR

t_res(tot)

t_(CE-OV)

I_LI

−50

500

250

chip enable to output valid time

input leakage current

µs

0 V < V_I< V_DD

±10

µA

[1] This parameter is characterized, but not tested in production.

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Preliminary data sheet

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8-bit microcontroller with accelerated two-clock 80C51 core

12. Package outline

TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm

SOT361-1

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

(2)

(1)

UNIT

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

9.8

9.6

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.8

0.5

1.1

0.65

0.25

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT361-1

MO-153

Fig 38. TSSOP package outline (SOT361-1)

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Preliminary data sheet

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13. Abbreviations

Table 16. Abbreviations

Acronym

BOD

CCU

CPU

Description

Brownout Detection

Capture/Compare Unit

Central Processing Unit

CRC

DAC

Cyclic Redundancy Check

Digital to Analog Converter

Erasable Programmable Read-Only Memory

Electrically Erasable Programmable Read-Only Memory

Electro-Magnetic Interference

Programmable Gain Ampliﬁer

Phase-Locked Loop

EPROM

EEPROM

EMI

PGA

PLL

PWM

RAM

Pulse-Width Modulator

Random Access Memory

Resistance-Capacitance

RTC

Real-Time Clock

SAR

Successive Approximation Register

Special Function Register

Serial Peripheral Interface

Universal Asynchronous Receiver/Transmitter

WatchDog Timer

SFR

SPI

UART

WDT

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14. Revision history

Table 17. Revision history

Document ID

Release date

20090409

Data sheet status

Change notice

Supersedes

P89LPC9301_931A1_1

Preliminary data sheet

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Preliminary data sheet

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8-bit microcontroller with accelerated two-clock 80C51 core

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

15.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

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8-bit microcontroller with accelerated two-clock 80C51 core

17. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

7.18.3

7.19

7.19.1

7.20

7.20.1

7.20.2

7.20.3

7.20.4

7.20.5

7.20.6

7.21

Total Power-down mode. . . . . . . . . . . . . . . . . 26

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Timers/counters 0 and 1 . . . . . . . . . . . . . . . . 27

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Timer overﬂow toggle output . . . . . . . . . . . . . 27

RTC/system timer. . . . . . . . . . . . . . . . . . . . . . 28

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Baud rate generator and selection. . . . . . . . . 29

Framing error . . . . . . . . . . . . . . . . . . . . . . . . . 29

Break detect. . . . . . . . . . . . . . . . . . . . . . . . . . 29

Double buffering. . . . . . . . . . . . . . . . . . . . . . . 29

Transmit interrupts with double buffering

2.1

2.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Principal features . . . . . . . . . . . . . . . . . . . . . . . 1

Additional features . . . . . . . . . . . . . . . . . . . . . . 1

3.1

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.22

7.22.1

7.22.2

7.22.3

7.22.4

7.22.5

7.22.6

7.22.7

7.22.8

7.22.9

7.1

7.2

7.3

7.3.1

7.3.2

7.4

7.4.1

7.4.2

7.4.3

7.5

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.13

7.14

7.15

7.15.1

7.16

7.16.1

Functional description . . . . . . . . . . . . . . . . . . 10

Special function registers . . . . . . . . . . . . . . . . 10

Enhanced CPU. . . . . . . . . . . . . . . . . . . . . . . . 18

Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Clock deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . 18

CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 18

Crystal oscillator option . . . . . . . . . . . . . . . . . 18

Low speed oscillator option . . . . . . . . . . . . . . 18

Medium speed oscillator option . . . . . . . . . . . 18

High speed oscillator option . . . . . . . . . . . . . . 18

Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 19

On-chip RC oscillator option. . . . . . . . . . . . . . 19

Watchdog oscillator option . . . . . . . . . . . . . . . 19

External clock input option . . . . . . . . . . . . . . . 19

Clock sources switch on the ﬂy. . . . . . . . . . . . 19

CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 20

CCLK modiﬁcation: DIVM register . . . . . . . . . 20

Low power select . . . . . . . . . . . . . . . . . . . . . . 20

Memory organization . . . . . . . . . . . . . . . . . . . 21

Data RAM arrangement . . . . . . . . . . . . . . . . . 21

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

External interrupt inputs . . . . . . . . . . . . . . . . . 22

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Port conﬁgurations . . . . . . . . . . . . . . . . . . . . . 23

enabled (modes 1, 2 and 3) . . . . . . . . . . . . . . 30

7.22.10 The 9^thbit (bit 8) in double buffering

(modes 1, 2 and 3). . . . . . . . . . . . . . . . . . . . . 30

7.23

7.24

7.24.1

7.25

7.25.1

7.25.2

7.25.3

7.26

7.27

7.28

I²C-bus serial interface. . . . . . . . . . . . . . . . . . 30

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Typical SPI conﬁgurations . . . . . . . . . . . . . . . 33

Analog comparators. . . . . . . . . . . . . . . . . . . . 34

Internal reference voltage. . . . . . . . . . . . . . . . 35

Comparator interrupt . . . . . . . . . . . . . . . . . . . 35

Comparators and power reduction modes . . . 35

KBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 36

Additional features . . . . . . . . . . . . . . . . . . . . . 37

Software reset . . . . . . . . . . . . . . . . . . . . . . . . 37

Dual data pointers . . . . . . . . . . . . . . . . . . . . . 37

Flash program memory . . . . . . . . . . . . . . . . . 37

General description . . . . . . . . . . . . . . . . . . . . 37

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Flash organization . . . . . . . . . . . . . . . . . . . . . 38

Using ﬂash as data storage . . . . . . . . . . . . . . 38

Flash programming and erasing. . . . . . . . . . . 38

ICP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

IAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Power-on reset code execution . . . . . . . . . . . 39

7.28.1

7.28.2

7.29

7.16.1.1 Quasi-bidirectional output conﬁguration . . . . . 23

7.16.1.2 Open-drain output conﬁguration . . . . . . . . . . . 23

7.16.1.3 Input-only conﬁguration . . . . . . . . . . . . . . . . . 24

7.16.1.4 Push-pull output conﬁguration . . . . . . . . . . . . 24

7.16.2

7.16.3

7.17

7.17.1

7.17.2

7.18

7.18.1

7.18.2

7.29.1

7.29.2

7.29.3

7.29.4

7.29.5

7.29.6

7.29.7

7.29.8

7.29.9

Port 0 analog functions. . . . . . . . . . . . . . . . . . 24

Additional port features. . . . . . . . . . . . . . . . . . 24

Power monitoring functions. . . . . . . . . . . . . . . 24

Brownout detection. . . . . . . . . . . . . . . . . . . . . 25

Power-on detection. . . . . . . . . . . . . . . . . . . . . 25

Power reduction modes . . . . . . . . . . . . . . . . . 25

Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Power-down mode . . . . . . . . . . . . . . . . . . . . . 25

7.29.10 Hardware activation of the bootloader . . . . . . 40

7.30

User conﬁguration bytes. . . . . . . . . . . . . . . . . 40

continued >>

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

64 of 65

P89LPC9301/931A1

NXP Semiconductors

8-bit microcontroller with accelerated two-clock 80C51 core

7.31

User sector security bytes . . . . . . . . . . . . . . . 40

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 41

9.1

9.2

Static characteristics. . . . . . . . . . . . . . . . . . . . 42

Current characteristics . . . . . . . . . . . . . . . . . . 44

Internal RC/watchdog oscillator

characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 48

BOD characteristics . . . . . . . . . . . . . . . . . . . . 51

9.3

10.1

10.2

Dynamic characteristics . . . . . . . . . . . . . . . . . 52

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

ISP entry mode. . . . . . . . . . . . . . . . . . . . . . . . 58

11.1

Other characteristics. . . . . . . . . . . . . . . . . . . . 59

Comparator electrical characteristics . . . . . . . 59

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 60

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 61

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 62

Legal information. . . . . . . . . . . . . . . . . . . . . . . 63

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 63

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 63

15.1

15.2

15.3

15.4

Contact information. . . . . . . . . . . . . . . . . . . . . 63

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 9 April 2009

Document identifier: P89LPC9301_931A1_1

P89LPC9301FDH [NXP]

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