P90CL301 [NXP]
Low voltage 16-bit microcontroller; 低电压16位微控制器
| 型号： | P90CL301 |
| 厂家： | 
NXP |
| 描述： | Low voltage 16-bit microcontroller |
| 文件： | 总92页 (文件大小：524K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
P90CL301BFH (C100)
Low voltage 16-bit microcontroller
1996 Dec 11
Preliminary specification
File under Integrated Circuits, IC17
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
CONTENTS
12
SERIAL INTERFACES
12.1
12.2
12.3
12.4
12.5
UART interface
1
FEATURES
Baud rate generator
UART queue
I2C-bus interface
2
DESCRIPTION
2.1
Compatibility between P90CL301AFH and
P90CL301BFH
Serial Control Register (SCON)
13
PULSE WIDTH MODULATION OUTPUTS
(PWM)
3
4
5
ORDERING INFORMATION
BLOCK DIAGRAM
13.1
13.2
Prescaler PWM Register (PWMP)
PWM Data Registers (PWM0 and PWM1)
PINNING INFORMATION
5.1
5.2
Pinning
Pin description
14
ANALOG-TO-DIGITAL CONVERTER (ADC)
ADC Control Register (ADCON)
14.1
15
6
SYSTEM CONTROL
ON-BOARD TEST CONCEPT
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Memory organization
Programmable chip-select
Dynamic bus port sizing
System Control Register (SYSCON)
Reset operation
Clock generation
Interrupt controller
Power reduction modes
15.1
15.2
ONCE mode
Test ROM
16
17
18
19
20
21
22
23
24
25
26
ON-CHIP RAM
REGISTER MAPPING
LIMITING VALUES
DC CHARACTERISTICS
ADC CHARACTERISTICS
AC CHARACTERISTICS
8051 BUS TIMING
7
CPU FUNCTIONAL DESCRIPTION
7.1
7.2
7.3
7.4
7.5
7.6
7.7
General
Programming model and data organization
Processing states and exception processing
Tracing
Stack format
CPU interrupt processing
Bus arbitration
TIMING DIAGRAMS
CLOCK TIMING
PIN STATES IN VARIOUS MODES
INSTRUCTION SET AND ADDRESSING
MODES
8
PORTS
8.1
8.2
8.3
Port P Control Register (PCON)
Port SP
Ports schematics
26.1
27
Addressing modes
INSTRUCTION TIMING
PACKAGE OUTLINE
SOLDERING
28
9
8051 PERIPHERAL BUS
ON-CHIP PERIPHERAL FUNCTIONS
Peripheral interrupt control
TIMERS
29
10
10.1
11
29.1
29.2
29.3
29.4
Introduction
Reflow soldering
Wave soldering
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Timer array
Timebase
Channel function
Pin parallel functions for the timer
Timer Control Registers
Timer Status Register
Watchdog Timer
Repairing soldered joints
30
31
32
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
1996 Dec 11
2
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
• 512 bytes RAM on-chip
1
FEATURES
• On-Circuit Emulation (ONCE) mode and internal
Test-ROM (256 bytes) for on-board testing
• Fully 68000 software compatible
• Static design with 32-bit internal structure
• 80-pin LQFP package
• Power saving modes: Power-down, Standby and Idle
mode
• Temperature range −40 to +85 °C
• 0.5 micron CMOS low voltage technology.
• External clock input: 27 MHz at 2.7 V
• Single supply voltage of 2.7 to 3.6 V; down to 1.8 V for
RAM retention
2
DESCRIPTION
• 68000 compatible bus interface
• Intel 8051 compatible bus interface
• 16 Mbytes program/data address range
• 8 programmable chip-selects
The P90CL301BFH is a highly integrated low-voltage
16/32-bit microcontroller especially suitable for digital
mobile systems such as GSM, DCS1900, IS54/95 and
other applications requiring low voltage, low power
consumption and high computing power. It is fully software
compatible with the 68000.
• Dynamic bus sizing, 16 or 8-bit memory bus port size
• 56 powerful instruction types:
The P90CL301BFH optimizes system cost by providing
both standard as well as advanced peripheral functions
on-chip. The P90CL301BFH has a full static design and
special Idle, Standby and Power-down modes which allow
further reduction of the total system power consumption.
An 80-pin LQFP package dramatically reduces system
size requirements.
– 5 basic data types, and
– 14 addressing modes
• 7 programmable interrupt inputs:
– a Non-Maskable Interrupt input (NMIN)
– 14 auto-vectored interrupts and 7 interrupt priority
levels
2.1
Compatibility between P90CL301AFH and
P90CL301BFH
• 24 port pins (multiplexed with other functions)
• 2 UART serial interfaces; an independent baud rate
generator with two programmable outputs (UART0 and
UART1)
For functional compatibility between P90CL301AFH
(SAC1 process) and P90CL301BFH (C100 process), the
following points should be considered when using the
P90CL301BFH:
• UART queue with maximum 256 bytes
• I2C-bus serial interface 100 kbaud
• 2 timer arrays including:
• Wake-up; to wake-up the processor from Power-down
mode via the activation of an external SPn pin, it is
necessary to enable the interrupt mode first by setting
the corresponding bit in the SPCON register.
– two 16-bit reference counters and 8-bit
programmable prescalers
• SYSCON register; for the P90CL301AFH bits 11 to 15
in the SYSCON register should not be set in order to
keep additional functionality in the P90CL301BFH
inactive.
– six 16-bit match/capture registers with equality
comparators
• Watchdog Timer with 21-bit resolution
• Two 8-bit Pulse Width Modulation (PWM) outputs with
8-bit prescaler
• Four 8-bit Analog-to-Digital Converter (ADC) inputs with
Power-down mode
3
ORDERING INFORMATION
PACKAGE
TEMPERATURE
RANGE (°C)
TYPE NUMBER
NAME
DESCRIPTION
VERSION
P90CL301BFH
LQFP80
plastic low profile quad flat package; 80 leads;
SOT315-1
−40 to +85
body 12 × 12 × 1.4 mm
1996 Dec 11
3
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
4
BLOCK DIAGRAM
CS0 to CS2
CS3 to CS6
a
CSBT/ONCE
A23 to A1
AS
D15 to D0
LDS
UDS
BUS
INTERFACE
CPU 68000
HALT
R/W
A31 to A0
D15 to D0
DTACK
BSIZE
2 × 16-BIT TIMERS
6 CHANNELS
WATCHDOG
TIMER
CP0 to CP5
BAUD RATE
GENERATOR
RESET
RESET
RESETIN
TX0
RX0
UART0
UART1
PWM
SYSTEM CTRL
CLOCK
TX1
RX1
XTAL1
PWM0
PWM1
INT0 to INT6
NMIN
INTERRUPTS
SCL
SDA
2
I C-BUS
INTERFACE
V
DDA
RAM
512 BYTES
8-BIT ADC
V
SSA
ADC0 to ADC3
V
ref(A)
SP0 to SP7
P0 to P15
PORT
address bus
A31 to A0
UART QUEUE
TEST ROM
data bus
D15 to D0
MGD780
V
V
V
V
V
DD1 DD2 DD3 SS1 SS2
Fig.1 P90CL301BFH block diagram.
4
1996 Dec 11
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
5
PINNING INFORMATION
Pinning
5.1
n
AS
D7
D6
D5
D4
D3
D2
D1
D0
1
2
60 P15/ADC3
59
V
DDA
3
58 BSIZE
4
57 P11/SDA
56 P10/SCL
5
6
55
P9/PWM1 (CP1)
7
54 P8/PWM0 (CP0)
53 SP0/RX1/INT0
8
9
52
51
50
49
48
47
46
SP1/TX1/INT1 (CLK0)
V
10
11
12
13
14
15
V
DD3
SS2
P90CL301BFH
XTAL1
SP2/RX0/INT2 (CP2)
SP3/TX0/INT3 (CP3)
SP4/INT4 (CP4)
V
SS1
UDS/A0/AD0
A1/AD1
SP5/INT5 (CP5)
A2/AD2
SP6/INT6 (CLK1)
A3/AD3 16
45 NMIN/SP7
17
18
44
43
A4/AD4
A5/AD5
CS0/FC0
CS1/FC1
A6/AD6 19
42 CS2/FC2
CS3/ALE
41
A7/AD7
20
MGD773
Fig.2 Pinning diagram of the P90CL301BFH (LQFP80).
5
1996 Dec 11
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
5.2
Pin description
Table 1 Pin description for the P90CL301BFH
SYMBOL(1)
PIN
DESCRIPTION
AS
1
address strobe
D7 to D0
VDD3
2 to 9 lower 8-bits of data bus
10
11
12
13
supply voltage; third pin
external clock input
ground; first pin
XTAL1
VSS1
UDS/A0/AD0
A1/AD1 to A7/AD7
A8 to A18
VDD2
upper data strobe or LSB of address bus or LSB of 8051 address/data
14 to 20 lower 7-bits of the 68000 address bus or lower 7-bits of the 8051 bus
21 to 31 upper 11-bits of the 68000 address bus
32
supply voltage; second pin
A19/PCS0 to A22/PCS3 33 to 36 upper 4-bits of the address bus or 8051 bus chip-select
CS6/A23
37
38
39
40
41
chip-select 6 or address bit 23
CSBT/ONCE
CS5/WR
chip-select boot or ONCE mode forced input
chip-select 5 or 8051 bus write strobe
chip-select 4 or 8051 bus read strobe
chip-select 3 or 8051 bus address latch
CS4/RD
CS3/ALE
CS2/FC2 to CS0/FC0
NMIN/SP7
42 to 44 chip-select 2 to 0 or data bus function code 2 to 0
45
46
47
48
49
Non-Maskable Interrupt or second port pin (bit 7)
SP6/INT6 (CLK1)
SP5/INT5 (CP5)
SP4/INT4 (CP4)
SP3/TX0/INT3 (CP3)
second port pin (bit 6) external interrupt input 6 (external clock of timer 1)
second port pin (bit 5) or external interrupt input 5 (Timer 1 capture input 5)
second port pin (bit 4) or external interrupt input 4 (Timer 1 capture input 4)
second port pin (bit 3) or Transmit data for UART0 or external interrupt input 3
(Timer 1 capture input 3)
SP2/RX0/INT2 (CP2)
50
second port pin (bit 2) or Receive data for UART0 or external interrupt input 2
(Timer 0 capture input 2)
VSS2
51
52
ground; second pin
SP1/TX1/INT1 (CLK0)
second port pin (bit 1) or transmit data for UART1 or external interrupt input 1
(external clock of Timer 0)
SP0/RX1/INT0
P8/PWM0 (CP0)
P9/PWM1 (CP1)
P10/SCL
53
54
55
56
57
58
59
60
61
second port pin (bit 0) or receive data for UART1 or external interrupt input 0
port pin (bit 8) or PWM0 output (Timer 0 capture input 0)
port pin (bit 9) or PWM1 output (Timer 0 capture input 1)
port pin (bit 10) or I2C-bus Serial Clock.
port pin (bit 11) or I2C-bus Serial Data.
data bus size; 8 or 16-bit wide
P11/SDA
BSIZE
VDDA
ADC supply voltage
P15/ADC3
Vref(A)
port pin (bit 15) or ADC input 3
ADC reference voltage
P14/ADC2 to P12/ADC0 62 to 64 port pin (bit 14 to bit 12) or ADC inputs 2 to 0
VSSA
65
66
ADC ground
RESETIN
external Power-on-reset input
1996 Dec 11
6
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
SYMBOL(1)
RESET
PIN
DESCRIPTION
67
68
69
reset (bidirectional)
halt (bidirectional)
HALT
VDD1
supply voltage; first pin
D15/P7 to D8/P0
70 to 77 upper 8-bits of data bus or 8-bit Port 7 to Port 0; the selected function after reset
is defined by pin BSIZE
DTACK
78
79
80
data transfer acknowledge
R/W / TROM
LDS [DS]
read/write bus control or Test-ROM forced input
lower data strobe [word data strobe]
Note
1. The following notation is used to describe the multiple pin definitions:
a) Function1/Function2/Function3: multiplexed functions on the same pin. During and after reset the Function1 is
selected.
b) Function1 (Function2): function done in parallel.
c) Function1 [Function2]: equivalent function.
1996 Dec 11
7
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
6
SYSTEM CONTROL
Memory organization
6.2
Programmable chip-select
In order to reduce the external components associated
with memory interface, the P90CL301BFH provides
8 programmable chip-selects. A specific chip-select CSBT
provides default reset values to support a bootstrap
operation.
6.1
The maximum external address space of the controller is
16 Mbytes. It can be partitioned into five address spaces.
These address spaces are designated as either User or
Supervisor space and as either Program or Data space or
as interrupt acknowledge.
Each chip-select can be programmed with:
• A base address (A23 to A19)
For slow memories the CPU can be programmed to insert
a number of wait states. This is done via the eight
Chip-select Control Registers CS0N to CS7N; further to
be denoted as CSnN, where n = 0 to 7. The number of
inserted wait states can vary from 0 to 6, or wait states are
inserted until the DTACK is pulled LOW by the external
address decoding circuitry. If DTACK is asserted
continuously, the P90CL301BFH will run without wait
states using bus cycles of three or four clock periods
depending on the state of the FBC bit in the SYSCON
register.
• A memory bank width of 512 kbytes, 1, 2, 4 or 8 Mbytes
memory size
• A number of wait states (0 to 6 states, or wait for
DTACK) to adapt the bus cycle to the memory cycle
time.
Chip-selects can be synchronized with read, write, or both
read and write, either Address strobe or Data strobe. They
can also be programmed to address low byte, high byte or
word.
Each chip-select is controlled by a control register CSnN
(n = 0 to 7). The control registers are described in
Table 3 to 7.
6.1.1
MEMORY MAP
The memory address space is divided as shown in
Table 2; short addressing space with A31 to A15 = 1.
The RESET instruction does not affect the contents of the
CSnN registers.
Table 2 Memory address space
Register CS7N corresponds to register CSBT (address
FFFF 8A0EH). After reset CSBT is programmed with a
block size of 8 Mbytes with:
ADDRESS (HEX)
DESCRIPTION
0000 0000 to 00FF FFFF external 16 Mbytes
memory
• A19 to A23 at logic 0
• M19 to M22 at logic 1
• 6 wait states
0100 0000 to 8000 FFFF not used
8001 0000 to 8001 FFFF off-chip 64 kbytes on 8051
bus
• read only mode.
8002 0000 to FFFF 7FFF not used
The other chip-selects are held HIGH and will be activated
after initialization of their control registers.
FFFF 8000 to FFFF 8AFF internal registers
FFFF 8B00 to FFFF 8FFF not used
When programmed in reduced access mode (read only,
write only, low byte, high byte), the wait states are
generated internally and if there is any access-violation
when the bit WD in the SYSCON register is set to a logic 1
(time-out), the processor will execute a bus error after the
time-out delay.
FFFF 9000 to FFFF 91FF internal 512 bytes RAM
FFFF 9200 to FFFF BFFF not used
FFFF C000 to FFFF C0FF internal 256 bytes
Test-ROM
FFFF C100 to FFFF FFFF not used
1996 Dec 11
8
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
6.2.1
CHIP SELECT CONTROL REGISTERS (CS0N TO CS7N)
Table 3 Chip Select Control Registers CS0N to CS7N (address FFFF 8A00H to FFFF 8A0CH)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
M22 M21 M20 M19 RW1 RW0 MD1 MD0 A23
A22
A21
A20
A19 WS2 WS1 WS0
Table 4 Description of CS0N to CS7N bits
BIT
SYMBOL
DESCRIPTION
15 to 12
11 to 10
9 to 8
M22 to M19 Address mask for block size selection; see Table 5.
RW1 to RW0 Read/Write bus control (R/W); see Table 6.
MD1 to MD0 MODE selection; see Table 7.
7 to 3
A23 to A19 Decoded base address; this should be a multiple of the block size (other codes are
reserved for test or reset state); after reset: A23 to A19 = 11111 except for CSBT.
2 to 0
WS2 to WS0 Wait states 0 to 6 (see Table 8); 7 wait states for DTACK to be pulled LOW by the
external address decoding circuitry. The default value after reset is ‘110B’ for CSBT and
‘111B’ for the other chip-selects.
Table 5 Address mask for block size selection
M22 M21 M20 M19 BLOCK SIZE
512 kbytes
Table 8 Wait states selection
WS2
WS1
WS0
WAIT STATES
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1 Mbyte
2 Mbytes
4 Mbytes
1
2
3
8 Mbytes; default value
after a CPU reset
4
5
6(1)
Table 6 Read/Write bits (R/W)
RW1 RW0 FUNCTION
Note
1. The default value after a CPU reset.
0
0
1
1
0
1
0
1
Read only with length of AS
Write only with length of DS
Write only with length of AS
Read/write with length of AS; default
value after a CPU reset
Table 7 Mode selection
MD1 MD0
FUNCTION
Alternate function
0
0
1
1
0
1
0
1
Low byte access only
High byte access only
Word access; default value after a CPU
reset
1996 Dec 11
9
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 9 Number of clock periods per bus cycle
Number of clock periods per bus cycle, dependent on the programmed length of FBC (Fast Bus Cycle bit in the
SYSCON register) and CSn (chip-select).
LENGTH OF CSn = LENGTH OF AS
LENGTH OF CSn = LENGTH OF DS
FBC = 1 FBC = 0
WRITE WRITE
WAIT
STATES
FBC = 1
WRITE
FBC = 0
R/W
READ
READ
READ
0
1
2
3
4
5
6
3
4
5
6
7
8
9
4
4
5
6
7
8
9
4
4
5
6
7
8
9
3
4
5
6
7
8
9
4
5
4
4
5
6
7
8
9
4
5
6
6
7
7
8
8
9
9
10
10
corresponding bit of the register BSREG is used to define
the sequence of bus transfer in 16 or 8-bit mode. Several
chip-selects with different bus sizes should not address
the same memory segment. For each case the number of
bus cycles necessary to transfer a byte, word or long word
is a function of the bus size. For example, a word read on
a 8-bit bus will take 2 bus cycles and the high byte is read
first. The 8-bit port uses the pins D7 to D0.
6.3
Dynamic bus port sizing
The memory bus size can be selected to be 16 or 8-bit
wide depending on the ports width of external memories
and peripherals. It is possible via the register BSREG to
define for each chip-select the bus width to 16-bit or 8-bit
used for the transfer of data to or from external memory.
The 7-bit register BSREG defines the bus size associated
with each chip-select function (except for CSBT).
See Table 11 and 12 and also Section 6.2 for more
detailed information on the programmable chip-selects
and the dynamic bus sizing.
The bus size of the chip-select boot CSBT (CS7N) is
hardware defined by the pin BSIZE.The state of the pin
BSIZE is latched at the end of the reset sequence.
When an address generated by the CPU is identified by a
chip-select block as belonging to it’s address segment, the
6.3.1
BUS SIZE REGISTER (BSREG)
Table 10 Bus Size Register (address FFFF A811H)
7
6
5
4
3
2
1
0
−
BS6
BS5
BS4
BS3
BS2
BS1
BS0
Table 11 Description of BSREG bits
BIT
7
SYMBOL
DESCRIPTION
−
Reserved.
6 to 0
BS6 to BS0 Bus size for the data transfer with respect to the corresponding chip-select
(CS6 to CS0). If BSn = 0, then the bus size is in 16-bit mode; the default value after a
CPU reset. If BSn = 1, then the bus size is in 8-bit mode. Where n = 0 to 6.
1996 Dec 11
10
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 12 Bus size depending on BSIZE, CSBTX and BSn (n = 0 to 6)
BUS SIZE OF CS0 TO CS6(1)
BUS SIZE OF CSBTX
PORT PL AVAILABLE
PIN BSIZE BIT CSBTX
AT
AFTER
(P0 TO P7)
BSn = 0
BSn = 1
BOOT
BOOT
0
0
1
1
0
1
0
1
16 bit
16 bit
note 2
16 bit
8 bit
8 bit
8 bit
8 bit
16
16
8
16
8
no
yes
yes
no
8
8
16
Notes
1. Depending on bit BSn in register BSREG.
2. The default value after reset of bits BSn in register BSREG is logic 0 which corresponds to 16-bit mode for CS0 to
CS6. In this case, it is recommended to set BSn to logic 1 in the boot routine. Afterwards if CSBTX is set to logic 1,
BSn can be reset to logic 0 by software for further transfers in 16-bit mode.
6.4
System Control Register (SYSCON)
The P90CL301BFH uses a System Control Register (SYSCON) for adjusting system parameters.
Table 13 System Control Register (address FFFF 8000H)
15
14
13
12
11
10
9
8
7(1)
6(1)
5
4
3
2
1(2)
0
WDSC BPE CSBTX STBY PCLK3 PCLK2 PDE GF PCLK1 PCLK0 IM WD FBC PD IDL DOFF
Notes
1. The default values after a CPU reset: PCLK1 = 1 and PCLK0 = 1; all other SYSCON bits are a logic 0.
2. All bits are reset by the RESET instruction, except the IDL bit which is only reset by a CPU reset.
1996 Dec 11
11
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 14 Description of SYSCON bits
BIT
SYMBOL
DESCRIPTION
15
WDSC
Bus error Watchdog short cycle. WDSC = 0 for normal mode; the bus error Watchdog
counts 2048 periods before activating the bus error sequence. WDSC = 1 for Bus error
Watchdog short cycle; the Watchdog counts 16 periods before activating the bus error
sequence.
14
13
BPE
Bus pull-up enable. If BPE = 0, the Address and Data bus internal pull-ups are switched
off. If BPE = 1, the Address and Data bus internal pull-ups are switched on.
CSBTX
Invert bus size for chip select boot and mode of port P0 to P7. CSBTX = 0 for normal
mode; bus size is defined by the pin BSIZE. If CSBTX = 1, the chip select boot is defined
by the inverted value of the pin BSIZE. The mode change should be executed from the
internal RAM or from a memory activated by any other chip select than CSBT. For further
details see also Section 6.3.
12
STBY
CPU Standby mode. STBY = 0, for normal mode. STBY = 1, for Standby mode; only the
CPU clock is switched off, the peripheral clocks are still running (see Fig.4).
11, 7
and 6
PCLK3, PCLK1 Prescaler for primary peripheral clock (FCLK) and the UART clock in mode 0.
and PCLK0
The CPU clock = CLK; FCLK = 1⁄divisor × CLK. See Table 15 for the divisor values.
10
PCLK2
Prescaler for secondary peripheral clock FCLK2 (derived from the primary peripheral
clock FCLK), used for the ADC; the maximum value of the FCLK2 clock is dependent on
the supply voltage VDD; see Section 19. If PCLK2 = 0, then FCLK is divided by 2;
if PCLK2 = 1, then FCLK is divided by 4.
9
PDE
If PDE = 0, then bits A22 to A19 are in normal operation; If PDE =1, then bits A22 to A19
are used as 8051 peripheral chip-select PCS3 to PCS0.
8
5
GF
IM
General purpose flag bit; reset to a logic 0 after CPU reset.
For IM = 0, level 7 is loaded into the Status Register during interrupt processing to
prevent the CPU from being interrupted by another interrupt source. For IM = 1, the
current interrupt level is loaded into the Status Register allowing nested interrupts.
4
3
WD
For WD = 0, the time-out for bus error detection is switched off. If the time-out is not
used, the Watchdog Timer can be used to stop a non-acknowledged bus transfer.
For WD = 1, the time-out for bus error detection is activated. If no DTACK has been sent
by the addressed device after 128 × 16 internal clock cycles the on-chip bus error signal
is activated.
FBC
FBC = 0, normal bus cycle; FBC = 1, fast bus cycle. An external read bus cycle can take
a minimum of 3 clock periods; the minimum write cycle is still 4 clock periods; in order to
get this access time DTACK should be asserted on time.
2
1
0
PD
IDL
PD = 0, for normal mode; PD = 1, for Power-down mode (see Section 6.8).
IDL = 0, for normal mode; IDL = 1, for Idle mode (see Section 6.8).
DOFF
DOFF = 0, for normal mode. DOFF = 1, for delay counter off; if set at wake-up from
Power-down the delay counter waiting period is skipped.
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 15 Selection of prescaler divisor values
PCLK3
PCLK1
PCLK0
DIVISOR (D)
DIVISOR FOR UART IN MODE 0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
2
6
6
3
4
6
5 (default value after a CPU reset)
6
6
8
12
12
12
10
The RESET pin can also be pulled LOW internally by a
pull-down transistor activated by an overflow of the
Watchdog Timer. When the CPU executes a RESET
instruction, the RESET pin is pulled LOW. When the CPU
is internally halted (at double bus fault), the HALT pin is
pulled LOW and only a CPU reset can restart the
processor.
6.5
Reset operation
The reset circuitry of the P90CL301BFH is connected to
the pins RESET, HALT, RESETIN and to the internal
Watchdog Timer. A Schmitt trigger is used at the input pin
for noise rejection. After Power-on a CPU reset is
accomplished by holding the RESET pin and the HALT pin
LOW for at least 50 oscillator clocks after the oscillator has
stabilized.
The internal signal RESET_AS (Reset Asynchronous)
resets the core and all registers.
For further information on the clock generation, see
Section 6.6. The CPU responds by reading the reset
vectors; the long word at address 000000H is loaded into
the Supervisor stack and the long word data at address
000004H is loaded into the program counter PC. The
interrupt level is set to 7 in the Status Register and
execution starts at the PC location. By pulling the RESET
pin LOW and keeping HALT HIGH, only the peripherals
are reset.
When an internal Watchdog Timer overflow occurs, an
internal CPU reset is generated which resets all registers
except the SYSCON, PCON, PRL and PRH registers and
pulls the RESET pin LOW during 12 clock cycles.
When VDD is turned on and its rise time does not exceed
10 ms, an automatic reset can be performed by
connecting the RESETIN pin to VDD via an external
capacitor. The external capacitor is charged via an internal
pull-down resistor.
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
peripheral
instruction RESET
Watchdog reset
RESET
reset
LATCH
CLK
RESET_AS
CPU-reset
LATCH
CLK
double bus fault
Watchdog reset
HALT
V
CPU HALT
DD
external reset
capacitor
RESETIN
R
stin
MBG330
Fig.3 Reset circuitry.
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
The prescaler is controlled by the System Control Register
(SYSCON). The internal clock is divided by a factor 2, 3, 4,
5, 6, 8 or 10 (function of bits PCLK0, PCLK1 and PCLK3;
see Table 15).
6.6
Clock generation
An external clock can be used with the P90CL301BFH.
The duty cycle of the external clock should be 50/50 ±5%
over the full temperature and voltage range.
For the ADC a secondary peripheral clock FCLK2 is
derived from the peripheral clock by dividing it either by
4 or 2 (function of the bit PCLK2; see Table 14).
For peripherals like Watchdog Timer, I2C-bus, PWM,
Timer and baud rate generator, a programmable prescaler
generates a peripheral clock FCLK.
XTAL1
SYSCON
Idle mode
(IDL)
1/512
CPU
CLK
SYSCON
(PCLK3)
1
1/2
mode 0 clock
SYSCON
(PCLK0, 1)
1/2
1/3
1/4
1/5
BCON
UART1
1 1/4
FCLK
UART0
SCON
BRG
SYSCON
(PCLK2)
1/4
FCLK2
1/2
PRESCALER TIMER 0/TIMER 1
2
S1CON
I C-BUS INTERFACE
ADC
PWM0/PWM1
WATCHDOG
MGD781
Fig.4 P90CL301BFH internal clock generation.
1996 Dec 11
15
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
6.7
Interrupt controller
Table 16 Priority order
SIGNAL
An interrupt controller handles all internal and external
interrupts. It delivers the interrupt with the highest priority
level to the CPU. The following interrupt requests are
generated by the on-chip peripherals:
PRIORITY ORDER
NMIN
INT6
INT5
INT4
INT3
INT2
INT1
INT0
I2C-bus
ADC
highest
• I2C-bus
• UARTs: received data / transmitted data
• Timers: two flags for the timers T0 and T1
• ADC: analog-to-digital conversion completed.
The external interrupt requests are generated with the pins
NMIN and the seven external interrupts INT0 to INT6.
6.7.1
INTERRUPT ARBITRATION
UART1 receiver
UART1 transmitter
UART0 receiver
UART0 transmitter
Timer 1
The interrupt priority levels are programmable with a value
between 0 and 7. Level 7 has the highest priority, level 0
disables the corresponding interrupt source. In case of
interrupt requests of equal priority level at the same time a
hardware priority mechanism gives priority order as shown
in Table 16.
Timer 0
lowest
The execution of interrupt routines can be interrupted by
another interrupt request of a higher priority level. In 68070
mode (SYSCON bit IM = 1) when an interrupt is serviced
by the CPU, the corresponding level is loaded into the
Status Register. This prevents the current interrupt from
getting interrupted by any other interrupt request on the
same or a lower priority level. If IM is reset, priority level 7
will always be loaded into the Status Register and so the
current interrupt cannot be interrupted by an interrupt
request of a level less than 7.
6.7.2
EXTERNAL LATCHED INTERRUPTS
NMIN and INT0 to INT6 are 8 external interrupt inputs.
These pins are connected to the interrupt function only
when the corresponding bit in the SPCON control register
is set (see Section 8.2; Table 29). Seven interrupt inputs
INT0 to INT6 are edge sensitive on HIGH-to-LOW
transition and their priority levels are programmable.
The interrupt NMIN is non-maskable (except if it is
programmed as a port) and is also edge sensitive on
HIGH-to-LOW transition. The priority level of NMIN is fixed
to 7.
Each on-chip peripheral unit including the eight interrupt
lines generate only auto-vectored interrupts. No
acknowledge is necessary. For external interrupts the
vectors 25 to 31 are used, for on-chip peripheral circuits a
second table of 7 vectors are used (57 to 63); see
Section 7.3.2.
The external interrupts are controlled by the registers
LIR0 to LIR3; see Tables 17 and 18.
6.7.2.1
Latched Interrupt Registers (LIR0 to LIR3)
Table 17 Latched Interrupt Registers
ADDRESS REGISTER
7
6
5
4
3
2
1
0
FFF 8101H
FFF 8103H
FFF 8105H
FFF 8107H
LIR0
LIR1
LIR2
LIR3
PIR1
PIR3
PIR5
PIR7
IPL1.2
IPL3.2
IPL5.2
1
IPL1.1
IPL3.1
IPL5.1
1
IPL1.0
IPL3.0
IPL5.0
1
PIR0
PIR2
PIR4
PIR6
IPL0.2
IPL2.2
IPL4.2
IPL6.2
IPL0.1
IPL2.1
IPL4.1
IPL6.1
IPL0.0
IPL2.0
IPL4.0
IPL6.0
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 18 Description of LIR0 to LIR3 bits
BIT
SYMBOL
DESCRIPTION
7 and 3
PIRn
Pending interrupt request. n = 0 to 7; INT7 corresponds to the interrupt NMIN;
PIRn = 1, pending interrupt request for pin INTn. PIRn = 0 (default value after a CPU
reset), no pending interrupt. When a valid interrupt request has been detected this bit
is set. It is automatically reset by the interrupt acknowledge cycle from the CPU. It
can be reset by software by writing a logic 0, however writing a logic 1 has no effect
on the flag. To reset only one flag, a logic 0 should be written to the bit address and a
logic 1 to the other interrupt requests. The use of BCLR instruction should be
avoided (PIR7 is cleared when the pin NMIN is set HIGH)
6 to 4
2 to 0
Interrupt priority level of pins INT0 to INT6 (fixed to ‘111B’ for NMIN in LIR3);
m = 0 to 6.
IPLm.2 to IPLm.0
6.7.2.2
Pending Interrupt Flag Register (PIFR)
An additional register PIFR contains copies of the PIR flags. The PIF flags are set at the same time as the PIR flags when
an interrupt is activated, but these flags are not reset automatically during the interrupt acknowledge cycle. They can only
be cleared by software and keep a trace of the interrupt event. The detection of an external interrupt is indicated by the
corresponding PIF-bit being set to a logic 1.
Table 19 Pending Interrupt Flag Register (address FFFF 810F)
7
6
5
4
3
2
1
0
PIF7
PIF6
PIF5
PIF4
PIF3
PIF2
PIF1
PIF0
When the CPU acknowledges the first internal interrupt the
auto-vector acknowledge signal cannot be asserted as its
WIN flag was reset, and the CPU hangs up.
6.7.3
NOTE ON SIMULTANEOUS INTERRUPTS
If an internal interrupt is immediately followed by an
external interrupt (i.e. both interrupts occurring within 12
clock cycles) and both these interrupts have the same
interrupt level, then the CPU might hang up during the
acknowledge cycle of the internal interrupt.
This situation can be solved by using the bus time-out
counter controlled by the System Control Register
(SYSCON) with the bits WD and WDSC set. In the case of
hang-up an internal bus error condition will be asserted
after 16 clocks and the CPU will execute the exception
SPURIOUS INTERRUPT at vector 60H. In the exception
service routine the interrupt flags PIR should be polled to
detect which interrupts caused the conflict, the
In the interrupt controller a flag WIN is set for each interrupt
as soon as the interrupt is activated and will be reset when
an interrupt of higher priority occurs or during the
acknowledge cycle. The WIN flag is used to determine
which PIR flag should be reset.
corresponding PIR flags should be cleared by software
and a call to the interrupt routines executed.
A conflict occurs if within the interval starting at the CPU
sampling of the first internal interrupt and ending at the
acknowledge cycle, a second external interrupt resets the
WIN flag of the first interrupt (external interrupts have
higher priority than internal).
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
6.8
Power reduction modes
6.8.2
STANDBY MODE
The P90CL301BFH supports three power reduction
modes. A Power-down mode where the clock is frozen, a
Standby mode where only the CPU is stopped, and an Idle
mode where the external clock is divided by 512
(see Fig.4).
When the STBY bit in the SYSCON register is set, the
CPU clock is stopped and the status of the processor is
frozen, however, the clocks of all other on-chip peripherals
are still running at the nominal frequency; these
peripherals are:
• Timers
6.8.1
POWER-DOWN MODE
• External and internal interrupts
• UARTs and baud rate generator
• I2C-bus interface
• Watchdog Timer
• PWMs
The Power-down operation freezes the oscillator. It can
only be activated by setting the PD bit in the SYSCON
register and thereafter execute the STOP instruction.
The instruction flow to enter the Power-down mode is:
BSET #PD, SYSCON
• ADC.
STOP #$2700.
The CPU exits this mode when an internal or external
interrupt is activated, and proceeds with the normal
program execution.
In this state all the register contents are preserved.
The CPU remains in this state until an internal reset occurs
or a LOW level is present on any of the external interrupt
pins INT0 to INT6 or NMIN. If the wake-up is done via an
external interrupt, the processor will first execute an
external interrupt of level 7. If the IPL level in the LIR
register is set to 7, a second interrupt of level 7 will be
executed. It is preferable to set the IPL to 0.
For minimum power consumption internal pull-ups on
address and data buses can be switched on by setting the
control bit BPE in the SYSCON register. The pull-ups
should be switched off in normal mode if not needed.
6.8.3
IDLE MODE
In Power-down mode VDD may be reduced to minimize
power consumption. However, the supply voltage must not
be reduced until Power-down mode is active, and must be
In the Idle mode the crystal or external clock is divided by
a factor 512. The current is reduced drastically but the
restored before a external reset or an interrupt is activated. controller continues to operate. This mode is entered by
setting the bit IDL in the SYSCON register. The next
instruction will be executed at a slower speed. To return to
normal mode the IDL bit should be reset.
In case of an external reset, the pin should be held active
until the external oscillator has restarted and stabilized.
In case of an external interrupt wake-up, any INTn or NMIN
It should be noted that all peripheral functions are also
pin should go LOW and the corresponding bit ESn
slowed down, and some cannot be used normally, for
(n = 0 to 7) in register SPCON should be set. If the DOFF
example UART, I2C-bus, ADC and PWM.
bit in the SYSCON is not set, an internal delay counter
The Power-down mode can also be entered from the Idle
ensures that the internal clock is not active before
mode. After a wake-up the controller restarts in Idle mode.
1536 clock cycles. After that time the oscillator is stable
and normal exception processing can be executed.
The PD bit is cleared automatically during the wake-up.
In order to have a fast start-up the DOFF bit should be set,
switching off the delay counter and enabling the immediate
clocking and restart of the controller.
For minimum power consumption during Power-down
mode, the address and data pins should be pulled HIGH
externally or bit BPE in register SYSCON should be set
(i.e. internal pull-ups enabled).
1996 Dec 11
18
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
7
CPU FUNCTIONAL DESCRIPTION
General
7.2
Programming model and data organization
The programming model is identical to that of the
MC68000 (see Fig.5), with seventeen 32-bit registers, a
32-bit Program Counter and a 16-bit Status Register.
The eight data registers (D0 to D7) are used for byte, word
and long-word operations. The Address Registers
(A0 to A6) and the System Stack Pointer A7 can be used
as software stack pointers and base address registers. In
addition, these registers can be used for word and
long-word address operations. All seventeen registers can
be used as index registers.
7.1
The CPU of the P90CL301BFH is software compatible
with the Motorola MC68000, hence programs written for
the MC68000 will run on the P90CL301BFH without
modifications. However, for certain applications the
following differences between processors should be
noted:
• Differences exist in the address/bus error exception
processing since the P90CL301BFH can provide full
error recovery.
The P90CL301BFH supports 8, 16 and 32-bit integers as
well as BCD data and 32-bit addresses. Each data type is
arranged in the memory as shown in Fig.6.
• The timing is different for the P90CL301BFH due to a
new internal architecture and technology.
The instruction execution timing is different for the same
reasons.
Table 20 Format of the Status Register and description of the bits; r = reserved
15
T
14
−
13
S
12 11 10
9
8
7
6
−
r
5
4
3
2
1
0
−
−
12 11 10
Interrupt mask
−
−
X
N
Z
V
C
Trace mode
r
Supervisor
r
Extend Negative Zero Overflow Carry
1996 Dec 11
19
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
31
16 15
8
7
0
n
DO
D1
D2
D3
D4
D5
D6
D7
Eight
Data
Registers
31
16 15
0
A0
A1
A2
Seven
A3 Address
Registers
A4
A5
A6
USER STACK POINTER
SUPERVISOR STACK POINTER
Two Stack
A7
Pointers
31
0
0
Program
Counter
15
8
7
Status
Register
USER
BYTE
SYSTEM
BYTE
MCD504
Fig.5 Programming model.
20
1996 Dec 11
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
7
6
5
4
3
2
1
0
bit
(a) Bit data (1 Byte = 8 bits).
bit 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MSB
BYTE 0
BYTE 2
LSB
BYTE 1
BYTE 3
(b) Integer data (1 Byte = 8 bits).
bit 15 14 13 12 11 10
MSB
9
8
7
6
5
4
3
2
1
0
WORD 0
WORD 1
WORD 2
LSB
(c) Word data (16 bits).
bit 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MSB
HIGH ORDER
LOW ORDER
HIGH ORDER
LOW ORDER
HIGH ORDER
LOW ORDER
LONG WORD 0
LSB
LONG WORD 1
LONG WORD 2
(d) Long-word data (32 bits).
bit 15 14 13 12 11 10
MSB
9
8
7
6
5
4
3
2
1
0
HIGH ORDER
LOW ORDER
HIGH ORDER
LOW ORDER
HIGH ORDER
LOW ORDER
ADDRESS 0
LSB
ADDRESS 1
ADDRESS 2
(e) Addresses (1 address =32 bits).
bit 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MSB BCD 0
BCD 4
BCD 1
BCD 5
LSB
BCD 2
BCD 6
BCD 3
BCD 7
(f) BCD data (2 BCD digits = 1 Byte).
MCD505
Fig.6 Memory data organization.
21
1996 Dec 11
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
7.3
Processing states and exception processing
7.3.1
REFERENCE CLASSIFICATION
The P90CL301BFH operates with a maximum internal
clock frequency of 27 MHz down to static operation. Each
clock cycle is divided into 2 states. A non-access machine
cycle has 3 clock cycles or 6 states (S0 to S5). A minimum
bus cycle normally consists of 3 clock cycles (6 states).
When DTACK is not asserted, indicating that data transfer
has not yet been terminated, wait states (WS) are inserted
in multiples of 2.
When the processor makes a reference, it classifies the
kind of reference being made, using the encoding of the
three function code internal lines. This allows external
translation of addresses, control of access, and
differentiation of special processor states, such as
interrupt acknowledge. Table 21 shows the classification
of references.
Table 21 Reference classification
The CPU is always in one of the four processing states:
FUNCTION CODE
• Normal
• Exception
• Halt
REFERENCE CLASS
FC2
0
FC1
0
FC0
0
unassigned
• Stopped.
0
0
1
User Data
0
1
0
User Program
unassigned
The Normal processing state is associated with instruction
execution; the memory references fetch instructions or
load/save results. A special case of the Normal state is the
Stopped state which is entered by the processor when a
STOP instruction is executed. In this state the CPU does
not make any further memory references.
0
1
1
1
0
0
unassigned
1
0
1
Supervisor Data
Supervisor Program
interrupt acknowledge
1
1
0
1
1
1
The Exception state is associated with interrupts, trap
instruction, tracing and other exceptional conditions.
The exception may be generated internally by an
instruction or by any unusual condition arising during the
execution of an instruction. Externally, exception
processing can be forced by an interrupt or by reset.
7.3.2
EXCEPTION VECTORS
Exception vectors are memory locations from where the
CPU fetches the address of a routine that will handle that
exception. All exception vectors are 2 words long, except
for the reset vector which consists of 4 words, containing
the PC and the SSP. All exception vectors are in the
Supervisor Data space.
The halted processing state is an indication of a
catastrophic hardware failure. For example, if during
exception processing of a bus error another bus error
occurs, the CPU assumes that the system is unusable and
halts. Only an external reset can restart a halted
processor. Note that a CPU in the stopped state is not in
the halted state or vice versa.
A vector number is an 8-bit number which, multiplied by 4,
gives the address of an exception vector. Vector numbers
are generated internally. The memory map for the
exception vectors is shown in the Table 22.
The Supervisor can work in the User or Supervisor state
determined by the state of bit S in the Status Register.
Accesses to the on-chip peripherals are achieved in the
Supervisor state.
All exception processing is performed in the Supervisor
state once the current contents of the Status Register has
been saved. Then the exception vector number is
determined and copies of the Status Register, the program
counter and the format/vector number are saved on the
Supervisor stack using the Supervisor Stack Pointer
(SSP). Finally the contents of the exception vector location
is fetched and loaded into the Program Counter (PC).
1996 Dec 11
22
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 22 Exception vector assignment
VECTOR NO.
DECIMAL
HEX
ASSIGNMENT
0
0
4
000
004
reset: initial SSP
reset: initial PC
bus error
−
2
8
008
3
12
00C
address error
illegal instruction
zero divide
4
16
010
5
20
014
6
24
018
CHK instruction
TRAPV instruction
privilege violation
trace
7
28
01C
8
32
020
9
36
024
10
40
028
line 1010 emulator
line 1111 emulator
11
44
02C
12(1)
48
030
unassigned, reserved
13(1)
52
034
unassigned, reserved
14
56
038
format error
15
60
03C
uninitialized interrupt vector
unassigned, reserved
16 to 23(1)
64 to 95
96
040 to 05C
060
24
spurious interrupt
25
100
104
108
112
116
120
124
128 to 191
192 to 227
228
232
236
240
244
248
252
256 to 1023
064
level 1 external interrupt auto-vector
level 2 external interrupt auto-vector
level 3 external interrupt auto-vector
level 4 external interrupt auto-vector
level 5 external interrupt auto-vector
level 6 external interrupt auto-vector
level 7 external interrupt auto-vector
TRAP instruction vectors
26
068
27
06C
28
070
29
074
30
078
31
32 to 47
48 to 56(1)
57
07C
080 to 0BF
0C0 to 0E3
0E4
reserved
level 1 on-chip interrupt auto-vector
level 2 on-chip interrupt auto-vector
level 3 on-chip interrupt auto-vector
level 4 on-chip interrupt auto-vector
level 5 on-chip interrupt auto-vector
level 6 on-chip interrupt auto-vector
level 7 on-chip interrupt auto-vector
reserved
58
0E8
59
0EC
0F0
60
61
0F4
62
0F8
63
0FC
64 to 255
100 to 3FF
Note
1. Vectors 12, 13, 16 to 23 and 48 to 56 are reserved for future enhancements.
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
The trace facility uses the T-bit in the Supervisor part of the
Status Register. If the T-bit is cleared, tracing is disabled
and instructions are executed normally. If the T-bit is set at
the beginning of the execution of an instruction, a trace
exception will be generated once the instruction has been
executed. If the instruction is not executed, either because
of an interrupt, or because the instruction is illegal or
privileged, the trace exception does also not occur if the
instruction is aborted by a reset, bus error, or address error
exception. If the instruction is executed, and an interrupt is
pending, the trace exception is processed before the
interrupt. If the execution of an instruction forces an
exception, the forced exception is processed before the
trace exception.
7.3.3
INSTRUCTION TRAPS
Traps are exceptions caused by instructions arising from
CPU recognition of abnormal conditions during instruction
execution or from instructions whose normal behaviour is
to cause traps.
Some instructions are used specifically to generate traps.
The TRAP instruction always forces an exception and is
useful for implementing system calls for User Programs.
The TRAPV and CHK instructions force an exception if the
User Program detects a run-time error, possibly an
arithmetic overflow or a subscript out of bounds.
The signed divide (DIVS) and unsigned divide (DIVU)
instructions will force an exception if a divide-by-zero
operation is attempted.
As an extreme illustration of the above rules, consider the
arrival of an interrupt during the execution of a TRAP
instruction, while tracing is enabled. First the trap
exception is processed, followed by the trace exception,
and finally the interrupt handling routine.
7.3.4
ILLEGAL AND UNIMPLEMENTED INSTRUCTIONS
Illegal instruction is the term used to refer to any word that
is not the first word of a legal instruction. During execution,
if such an instruction is fetched an illegal exception occurs.
7.5
Stack format
Words with bits 15 to 12 equal to ‘1010’ or ‘1111’ are
defined as unimplemented instructions and separate
exception vectors are allocated to these patterns for
efficient emulation. This facility means the operating
system can detect program errors, or can emulate
unimplemented instructions in software.
The stack format for exception processing is similar to the
MC68010 although the instruction stored is not the same,
due to the different architecture. To handle this format the
P90CL301BFH differs from the MC68000 in that:
• The stack format is changed.
7.3.5
PRIVILEGE VIOLATIONS
• The minimum number of words put into or restored from
stack is 4 (MC68010 compatible, not 3 as with the
MC68000).
To provide system security, various instructions are
privileged and any attempt to execute one of the privileged
instruction while the CPU is in the User state provokes an
exception. The privileged instructions are:
• The RTE instruction decides (with the aid of the 4 format
bits) whether or not more information has to be restored
as follows:
• STOP
• RESET
– The P90CL301BFH long format is used for bus errors
and address error exceptions.
• RTE
• MOVE to SR
– All other exceptions use the short format.
• AND (word) immediate to SR
• EOR (word) immediate to SR
• OR (word) immediate to SR
• MOVE to USP.
• If another format code, other than those listed above, is
detected during the restored action, a FORMAT ERROR
occurs.
If the user wants to finish the instruction in which the bus
or address error occurred, the P90CL301BFH format must
be used on RTE. If no changes to the stack are required
during exception processing, the stack format is
transparent to the user.
7.4
Tracing
The CPU includes a facility to trace instructions one by one
to assist in program development. In the trace state, after
each instruction is executed, an exception is forced so that
the debugging program can monitor execution of the
program under test.
1996 Dec 11
24
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
d
SP
SR
PCH
Short
Stack
Format
PCL
FORMAT (4 bits)
BASE VECTOR ADDRESS
SSW
MM
INTERNAL INFORMATION
INTERNAL INFORMATION
Long
Stack
Format
TPDH
TPDL
TPFH
TPFL
DBINH
DBINL
IR
IRC
INTERNAL INFORMATION
MBG426
Fig.7 Stack format; see Table 23.
Table 23 Description of the stack format
SYMBOL
DESCRIPTION
SR
Status Register.
Program Counter High/Low Word.
PCH/PCL
FORMAT
Indicating either a short stack (only the first four words), or the long for bus and address error
exceptions.
BASE VECTOR
ADDRESS
The base vector address of the exception in the vector table; e.g. 8 for a bus error and 12 for
an address error.
SSW
Special Status Word.
MM
Current Move Multiple Mask.
TPDH/TPDL
TPFH/TPFL
DBINH/DBINL
IR
In the event of faulty write cycle, the data can be found here.
The address used during the faulty bus cycle.
Data that has been read prior to the faulty bus cycle can in some cases be found here.
Holds the present instruction executed.
IRC
Holds either the present instruction executed or the prefetched instruction.
1996 Dec 11
25
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
As all P90CL301BFH interrupts are auto-vectored, the
processor internally generates a vector number
corresponding to the interrupt level number.
7.6
CPU interrupt processing
The general interrupt handling mechanism is described in
Section 6.7. An interrupt controller handles all interrupts,
resolves the priority problem and passes the highest level
interrupt to the CPU.
The processor starts normal exception processing by
saving the format word, program counter and Status
Register on the Supervisor stack. The value of the vector
in the format word is an internally generated vector number
multiplied by 4 (format is all zeros). The program counter
value is the address of the instruction that would have
been executed if the interrupt had not been present. Then
the interrupt vector contents are fetched and loaded into
the program counter. The interrupt handling routine starts
with normal instruction execution.
The CPU interrupt handling follows the same basic rules
as in the MC68000. However, some remarks must be
made:
• Interrupts with a priority level equal to or lower than the
current priority level will not be accepted.
• During the acknowledge cycle of an interrupt, the IPL
bits of the Status Register are set to the priority of the
acknowledged interrupt or to 7. An exception occurs
when bit IM = 0 (SYSCON bit 5). In this case level 7 is
loaded into the Status Register (see Section 6.4;
Table 14).
7.7
Bus arbitration
If the HALT pin is held LOW with RESET HIGH the CPU
will stop after completion of the current bus cycle. As long
as HALT is LOW, all control signals are inactive and all
3-state lines are placed in the high-impedance state. If the
HALT pin is held LOW during the transfer of a word in 8-bit
mode, the CPU will continue the transfer of the two bytes
before it halts.
If the priority level of the pending interrupt is greater than
the current processor priority then:
• The exception processing sequence is started
• A copy of the Status Register is saved
• The privilege level is set to Supervisor state
• Tracing is suppressed
• The priority level of the processor is set to that of the
interrupt being acknowledged or to 7 depending on the
IM flag in the System Control Register.
The processor then gets the vector number from the
interrupting device, classifies it as an interrupt
acknowledge and displays the interrupt level number
being acknowledged on the internal address bus.
1996 Dec 11
26
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Each port pin consists of a latch, an output driver with
pull-ups and an input buffer.
8
PORTS
For general purpose input/output operations the following
ports can be used:
To use the port as input the port latch should be written
with a logic 1. This means only a weak pull-up is on and
can be overwritten by an external source logic 0.
• 16-bit bidirectional port lines P15 to P0 composed of two
8-bit ports PL (P7 to P0) and PH (P15 to P8)
When outputting a logic 1, a strong pull-up is turned on
only for 1 clock period, and then only the weak pull-up
maintains the HIGH level. In read mode, two different
internal addresses correspond to the port latch or the port
pin.The port values are read via register PPL and PPH.
• 8-bit port lines SP7 to SP0.
All port pins are multiplexed with other functions, but each
one can be individually switched to the port function by
setting the corresponding bit in the Port P Control Register
(PCON) for ‘port Pn’ and Port SP Control Register
(SPCON) for ‘port SPn’.
After reset all ports are initialized as input, and the pins are
connected to the port latch with exception for the pin
NMIN/SP7 which is connected to the interrupt block.
The port P7 to P0 is multiplexed with the data bus
D15 to D8 and is selected by the pin BSIZE.
8.1
Port P Control Register (PCON)
The port Pn is controlled via the Port P Control Register (PCON). The register PCON is only reset by an external reset,
and not by the RESET instruction. The port latches are accessed through the registers PRL and PRH.
Table 24 Port P Control Register (address FFFF 8503H)
7
6
5
4
3
2
1
0
E15
E14
E13
E12
E11
E10
E9
E8
Table 25 Description of PCON bits
BIT
SYMBOL
DESCRIPTION
7 to 0
E15 to E8 If En = 0, then ‘port Pn’ is enabled; if En = 1, then the alternate function is enabled;
n = 8 to 15. The default value after reset is logic 0.
8.1.1
PORT P LATCHES
Table 26 Port P Latch least significant byte (PRL; address FFFF 8505H)
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
Table 27 Port Latches High most significant byte (PRH; address FFFF 8509H)
7
6
5
4
3
2
1
0
P15
P14
P13
P12
P11
P10
P9
P8
1996 Dec 11
27
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
8.2
Port SP Control Register (SPCON)
The special ports SPn (SP0 to SP7) consist of 8 I/O lines and are controlled via the two registers SPCON and SPR. The
registers SPCON and SPR are reset by a peripheral reset. The port latch is accessed through the register SPR.
8.2.1
PORT SP CONTROL REGISTER (SPCON)
Table 28 Port SP Control Register (address FFFF 8109H)
7
6
5
4
3
2
1
0
ES7
ES6
ES5
ES4
ES3
ES2
ES1
ES0
Table 29 Description of SPCON bits
BIT
SYMBOL
DESCRIPTION
7 to 0
ES7 to ES0 If ESn = 0, then ‘port SPn’ is enabled; if ESn = 1, then the alternate function is enabled;
n = 0 to 7. The default value after reset is logic 0, except for ES7 which is set at reset.
8.2.2
PORT SP LATCH (SPR)
Table 30 Port SP latch (FFFF 810BH)
7
6
5
4
3
2
1
0
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
8.2.3
ALTERNATIVE FUNCTIONS FOR PORTS P AND SP
Table 31 Alternative functions for P0 to P15 and
SP0 to SP7 pins
Functions within brackets are parallel functions.
PORT PIN
ALTERNATE FUNCTION
ADC0
PORT PIN
ALTERNATE FUNCTION
P12
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
D8
P13
P14
P15
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
ADC1
D9
ADC2
D10
D11
D12
D13
D14
D15
ADC3
RX1/INT0
TX1/INT1 (CLK0)
RX0/INT2 (CP2)
TX0/INT3 (CP3)
INT4 (CP4)
INT5 (CP5)
INT6 (CLK1)
NMIN
PWM0 (CP0)
PWM1 (CP1)
SCL
SDA
1996 Dec 11
28
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
V
DD
from port
DELAY
latch Q
p
p
p
I/O pin
n
MGD784
data input
a. WP2 + WP4 port.
V
DD
from port
latch Q
DELAY
p
p
p
I/O pin
n
data input
enable
ADC BLOCK
p
CIA
virtual
ground
n
MGD787
b. AN + WP2 (P15 to P12) port.
Fig.8 Port schematics (continued in Fig.9).
29
1996 Dec 11
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
external
pull-up
pin
n
data input
MGD783
a. Open-drain port.
V
DD
handbook, halfpage
V
handbook, halfpage
DD
p
R
Vref
pin
pin
power
down
n
n
MGD786
data input
MGD785
b. 3-state port.
c. AREF input.
Fig.9 Port schematics (continued from Fig.8).
To reduce the number of interface circuits, the address
9
8051 PERIPHERAL BUS
lines A22 to A19 can be used as peripheral chip-select
outputs PCS0 to PCS3. This is done by setting the PDE bit
(SYSCON) to a logic 1;
The P90CL301BFH can also directly access the peripheral
circuits which are compatible with the 8048/8051 bus.
When the CPU accesses locations located in the
64 kbytes peripheral space, an Address/Data multiplexed
access is generated using the AD0 to AD7 lines, the
non-multiplexed A8 to A15 lines and the 8051 control bus
(ALE, RD, WR). In order to use these three signals the
alternate mode of the CS5 to CS3 should be set. A 8051
bus access is performed by addressing a byte in the
8001 0000H to 8001 FFFFH range.
• PCS0 selects memory range 0 kbytes to 16 kbytes
• PCS1 selects memory range 16 kbytes to 32 kbytes
• PCS2 selects memory range 32 kbytes to 48 kbytes
• PCS3 selects memory range 48 kbytes to 64 kbytes.
The timing of the peripheral bus is fixed and compatible
with the 8051 peripheral circuits.
1996 Dec 11
30
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
10 ON-CHIP PERIPHERAL FUNCTIONS
10.1 Peripheral interrupt control
The P90CL301BFH integrates a number of peripheral
functions connected to the internal bus:
The timers T0 and T1, I2C-bus, UART and ADC use a
common set of Peripheral Interrupt Control Registers
(PICRn; n = 0 to 3). These registers are accessible from
the CPU and contain the Interrupt Priority Level flags
IPL2 to IPL0 as well as the Pending Interrupt flags PIR.
• Timers (T0 and T1)
• Watchdog
• 2 UART interfaces with one UART queue controller
using the internal RAM as data buffers.
• I2C-bus interface
PIR is set when a valid interrupt request has been
detected. It is automatically reset by the interrupt
acknowledge cycle from the CPU. The PIR flag can be
reset by software.
• PWM (Pulse Width Modulation)
• ADC (Analog-to-Digital Converter).
The Interrupt Priority Level code ‘111B’ represents the
interrupt with the highest priority. The code ‘000B’ inhibits
the interrupt.
These functions are accessible as memory locations on a
byte or word basis. The access is auto-acknowledged by
on-chip logic. The on-chip peripheral functions can
generate auto-vectored interrupts to the CPU using the
second vector table (vectors 57 to 63).
10.1.1 TIMER INTERRUPT REGISTER (PICR0)
On timer overflow or on channel capture/match the pending interrupt request flag PIRTn is set. If the interrupt priority
level is different from zero, the timer activates an interrupt to the CPU.
Table 32 Timer Interrupt Register (address FFFF 8701H)
7
6
5
4
3
2
1
0
PIRT1
IPLT1.2
IPLT1.1
IPLT1.0
PIRT0
IPLT0.2
IPLT0.1
IPLT0.0
Table 33 Description of PICR0 bits
BIT
7
SYMBOL
PIRT1
DESCRIPTION
pending interrupt for timer T1
6 to 4
3
IPLT1.2 to IPLT1.0
PIRT0
interrupt priority level for timer T1
pending interrupt for timer T0
interrupt priority level for timer T0
2 to 0
IPLT0.2 to IPLT0.0
1996 Dec 11
31
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
10.1.2 UART INTERRUPT REGISTERS
Each UART can generate two interrupts in transmission and reception via the two registers PICR1 and PICR2.
Table 34 UART Interrupt Registers PICR1 (address FFFF 8703H)
7
6
5
4
3
2
1
0
PIRR0
IPLR0.2
IPLR0.1
IPLR0.0
PIRT0
IPLT0.2
IPLT0.1
IPLT0.0
Table 35 Description of PICR1 bits
BIT
7
SYMBOL
PIRR0
DESCRIPTION
pending interrupt for UART0 in reception
interrupt priority level for UART0 in reception
pending interrupt for UART0 in transmission
interrupt priority level for UART0 in transmission
6 to 4
3
IPLR0.2 to IPLR0.0
PIRT0
2 to 0
IPLT0.2 to IPLT0.0
Table 36 UART Interrupt Registers PICR2 (address FFFF 8705H)
7
6
5
4
3
2
1
0
PIRR1
IPLR1.2
IPLR1.2
IPLR1.2
PIRT1
IPLT1.2
IPLT1.1
IPLT1.0
Table 37 Description of PICR2 bits
BIT
7
SYMBOL
PIRR1
DESCRIPTION
pending interrupt for UART1 in reception
interrupt priority level for UART1 in reception
pending interrupt for UART1 in transmission
interrupt priority level for UART1 in transmission
6 to 4
3
IPLR1.2 to IPLR1.0
PIRT1
2 to 0
IPLT1.2 to IPLT1.0
10.1.3 I2C-BUS AND ADC INTERRUPT REGISTER (PICR3)
The I2C-bus and the ADC respectively, can generate one interrupt.
Table 38 I2C-bus and ADC Interrupt Register (address FFFF 8707H)
7
6
5
4
3
2
1
0
PIRI
IPLI2
IPLI1
IPLI0
PIRA
IPLA2
IPLA1
IPLA0
Table 39 Description of PICR3 bits
BIT
SYMBOL
DESCRIPTION
7
PIRI
pending interrupt for I2C-bus
6 to 4
3
IPLI2 to IPLI0
PIRA
interrupt priority level for I2C-bus
pending interrupt for ADC
2 to 0
IPLA2 to IPLA0
interrupt priority level for ADC
1996 Dec 11
32
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
The 16-bit counter register is incremented at each
prescaler overflow. When the counter reaches FFFFH, the
status flag TOV is set and on the next clock the counter
reload value is loaded into the counter. By resetting the
control bit RUN in the timer control register the timebase is
stopped, and by setting this bit, the prescaler and counter
are reloaded and incremented on the next external or
internal clock.
11 TIMERS
11.1 Timer array
Two identical 16-bit timer blocks are provided:
• Timer 0 (T0)
• Timer 1 (T1).
Each timer block consists of:
• A timebase
11.3 Channel function
• Three capture/compare channels
• A Control Register
Each channel consists of a register and an equality
comparator. For each of the three channels two modes
can be selected:
• A Status Register.
• Compare mode: sets the status flag CFn in TnSR when
there is a match between the counter register and the
channel register value.
11.2 Timebase
The timebase contains an 8-bit prescaler with a write only
reload register, and a 16-bit counter register. This counter
register can only be read by software. The prescaler is
clocked either by the peripheral clock FCLK or by an
external clock enabled by the flag C/TN in the timer control
register TnCR (T0CT for timer T0 and T1CR for timer T1).
On prescaler overflow the prescaler reload value is loaded
into the prescaler, which starts incrementing.
• Capture mode: stores the counter register value into
the channel register and sets the status flag CFn when
a transition occurs at the corresponding input pin CPn.
In both modes, each channel can generate a global
interrupt request if the corresponding enable bit in the
Control Register TnCR is set.
11.4 Pin parallel functions for the timer
In order to use the multiplexed pins for the timer, the other functions using these pins as output pins should be forced
HIGH via a weak pull-up, enabling an external source to drive them LOW.
Table 40 Parallel functions
PARALLEL
FUNCTION
PIN
SETTING
SP1/TX1/INT1 if SPCON.1 = 0, SPR.1 = 1; else UART1 should not be used
SP2/RX0/INT2 if SPCON.2 = 0, SPR.2 = 1; else UART0 should not be used
SP3/TX0/INT3 if SPCON.3 = 0, SPR.3 = 1; else UART0 should not be used
CLK0
CP2
CP3
CP4
CP5
CLK1
CP0
CP1
SP4/INT4
SP5/INT5
SP6/INT6
P8/PWM0
P9/PWM1
if SPCON.4 = 0, SPR.4 = 1
if SPCON.5 = 0, SPR.5 = 1
if SPCON.6 = 0, SPR.6 = 1
if PCON.0 = 0, PWM0 should output a logic 1 (write 00H to register PWM0)
if PCON.1 = 0, PWM1 should output a logic 1 (write 00H to register PWM1)
1996 Dec 11
33
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
internal bus
PIRT0 (PIRT1)
4
4
TOV
TIMER STATUS
REGISTER T0SR (T1SR)
16
4
CP2
(CP5)
CHANNEL REGISTER T0C2 (T1C5)
EDGE DETECTION
EDGE DETECTION
EDGE DETECTION
16
16
C2F
COMPARE UNIT
(C5F)
16
16
CP1
(CP4)
CHANNEL REGISTER T0C1 (T1C4)
16
16
C1F
COMPARE UNIT
(C4F)
16
16
CP0
(CP3)
CHANNEL REGISTER T0C0 (T1C3)
16
16
C0F
COMPARE UNIT
16
(C3F)
16
16
FCLK
0
1
COUNTER REGISTER T0 (T1)
PRESCALER
8
CLK0
(CLK1)
16
16
8
COUNTER RELOAD REGISTER
T0RR (T1RR)
PRESCALER RELOAD
REGISTER
CP0
(CP3)
GATE
C/TN
16
TIMER CONTROL REGISTER
T0CR (T1CR)
MBG332
Fig.10 Timer block diagram T0 (identical with timer block T1, corresponding names indicated within brackets).
1996 Dec 11
34
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
11.5 Timer Control Registers
The Timer 0 (T0) is controlled via Timer 0 Control Registers (T0CRH and T0CRL), and Timer 1 (T1) via Timer 1 Control
Registers (T1CRH and T1CRL); see Fig.10 and Tables 41 to 44. The default value after a CPU reset for all bits of
T0CRH; T1CRH; T0CRL and T1CRL is a logic 0.
Table 41 Timer Control Registers T0CRH and T1CRH
ADDRESS REGISTER
15
14
13
12
11
10
9
8
FFFF 8300H
FFFF 8310H
T0CRH
T1CRH
ECM2
C2M2
C2M1
C2M0
ECM1
C1M2
C1M1
C1M0
Table 42 Timer Control Registers T0CRL and T1CRL
ADDRESS REGISTER
7
6
5
4
3
2
1
0
FFFF 8301H
FFFF 8311H
T0CRL
T1CRL
ECM0
C0M2
C0M1
C0M0
ETOV
GATE
C/TN
RUN
Table 43 Description of T0CRH; T1CRH; T0CRL and T1CRL bits
BIT SYMBOL
DESCRIPTION
15, 11 and 7 ECM2 to ECM0 Channel n interrupt enable (n = 0 to 2);
ECMn = 0, the channel n interrupt is disabled;
ECMn = 1, the channel n interrupt is enabled.
14 to 12
10 to 8
6 to 4
3
C2M2 to C2M0 Channel mode; see Table 44.
C1M2 to C1M0
C0M2 to C0M0
ETOV
Timer overflow interrupt enable;
ETOV = 0, the timer overflow interrupt is disabled;
ETOV = 1, the timer overflow interrupt is enabled.
Gated external clock;
2
1
GATE
GATE = 0, disable gate function;
GATE = 1, the prescaler increments only if the CP0 pin is HIGH for each rising edge
transition of CLK0 if C/TN = 1 or with FCLK if C/TN = 0.
C/TN
RUN
Counter/timer mode;
C/TN = 0, timer mode; the prescaler is incremented on the rising edge of the
peripheral clock (FCLK);
C/TN = 1, counter mode; the prescaler increments on the rising edge of CLK0 for
Timer 0 (CLK1 for Timer 1).
0
Timer run enable;
RUN = 0, timer prescaler stopped and registers value held;
RUN = 1, when set the prescaler and counter are loaded and the prescaler is then
incremented.
1996 Dec 11
35
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 44 Description of channel mode; n = 0 to 5; X = don’t care
CnM2
CnM1
CnM0
DESCRIPTION
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
channel n inhibited
channel n capture on LOW-to-HIGH transition of pin CPn
channel n capture on HIGH-to-LOW transition of pin CPn
channel n capture on any transitions of pin CPn
channel compare mode
11.6 Timer Status Registers
Four events can occur: a timer overflow or three channel matches/captures. These event flags are stored in the 4-bit
Timer 0 Status Register (T0SR for T0) and Timer 1 Status Register (T1SR for T1). They can be cleared by software but
cannot be set. By writing a logic 1 the flags stay unchanged. In order to clear a particular flag one has to write a logic 0
to the corresponding position and logic 1s to the others. One should avoid to use the instruction BCLR, which can reset
accidentally several flags.
11.6.1 TIMER 0 STATUS REGISTER (T0SR)
Table 45 Timer 0 Status Register (address FFFF 830DH)
7
6
5
4
3
2
1
0
−
−
−
−
C2F
C1F
C0F
TOV
Table 46 Description of T0SR bits
BIT
SYMBOL
DESCRIPTION
7 to 4
3 to 1
−
Reserved.
C2F to C0F Channel n event flag (n = 2 to 0); CnF = 0, no event (default value after a CPU reset).
CnF = 1, capture mode: a capture occurred.
0
TOV
Timer Overflow Flag; TOV = 0, no overflow (default value after a CPU reset).
TOV = 1, timer overflow occurred.
11.6.2 TIMER 1 STATUS REGISTER (T1SR)
Table 47 Timer 1 Status Register (address FFFF 831DH)
7
6
5
4
3
2
1
0
−
−
−
−
C5F
C4F
C3F
TOV
Table 48 Description of T1SR bits
BIT
SYMBOL
DESCRIPTION
7 to 4
3 to 1
−
Reserved.
C5F to C3F Channel n event flag (n = 5 to 3); CnF = 0, no event (default value after a CPU reset).
CnF = 1, capture mode: a capture occurred.
0
TOV
Timer Overflow Flag; TOV = 0, no overflow (default value after a CPU reset).
TOV = 1, timer overflow occurred.
1996 Dec 11
36
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
11.7 Watchdog Timer
For FCLK in MHz, the Watchdog period is:
8192
--------------
FCLK
The P90CL301BFH contains a Watchdog Timer consisting
of a 13-bit prescaler and an 8-bit timer WDTIM.
The prescaler is incremented by the peripheral clock.
The 8-bit timer is incremented every 8192 cycles of the
peripheral clock FCLK.
(256 – WDTIM) ×
µ s
The Watchdog Timer is controlled by the register WDCON.
A value of A5H in WDCON clears both the prescaler and
timer WDTIM. After reset, WDCON contains A5H.
If the FCLK frequency is 2 MHz, the Watchdog Timer can
operate in the range of 4.1 ms up to 1 s. The Watchdog
Timer is disabled after reset. It can be enabled by writing
any value to the WDCON register. The only way to disable
a running Watchdog Timer is to reset the P90CL301BFH.
Every value other than A5H in WDCON enables the
Watchdog Timer. Since the bit 0 of the WDCON input is
tied to a logic 0 by hardware during write operations on
WDCON, the reset value A5H can not be programmed
again and can only be restored by a reset.
When a timer overflow occurs the microcontroller will be
reset (except registers SYSCON, PCON, PRL and PRH
which will not be reset). To prevent an overflow of the
Watchdog Timer, the User Program must reload the
Watchdog register within a period shorter than the
programmed timer interval.
Timer WDTIM can be written only if WDCON has
previously been loaded with 5AH, otherwise WDTIM and
the prescaler are not affected. A successful write operation
to WDTIM also clears the prescaler and clears WDCON.
Only the values A5H or 5AH are stored, all other values
are stored with a dummy value 00H.
This timer interval is determined by the 8-bit timer value
written to the register WDTIM.
FCLK/8192
overflow
Internal
reset
COUNTER REGISTER
8-BIT
PRESCALER
FCLK
13-BIT
enable
WDTIM
8-BIT RELOAD
REGISTER
WDCON
REGISTER
INTERNAL BUS
MBG325
Fig.11 Watchdog Timer block diagram.
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Mode 2 11 bits are transmitted (through TXD) or received
(through RXD): a start bit at logic 0, 8 data bits
(LSB first) a programmable 9th data bit, and a
stop bit at logic 1. On transmit the 9th bit is taken
from the bit TB8 from the SCON register. On
receive the 9th bit goes into RB8 of SCON, while
the stop bit is ignored. The baud rate is equal to
1⁄6 × CLK. The UART clock should not exceed
4.5 Mbaud.
12 SERIAL INTERFACES
12.1 UART interface
The UART can operate in 4 modes. The baud rate for
receive and transmit can be generated internally or by the
baud rate generator. The UART is full duplex, meaning it
can receive and transmit simultaneously. The receive and
transmit registers are both accessed as a unique register
SBUF. Writing to SBUF loads the transmit register, and
reading from SBUF accesses a physically separate
receive register.
Mode 3 Same as mode 2 except for the baud rate, which
is given by the baud rate generator output
BGCLK0 for the UART0 and BGCLK1 for the
UART1.
12.1.1 UART OPERATING MODES
The serial port can operate in one of the four modes:
In all four modes, transmission is initiated by any
instruction loading SBUF. In Mode 0, reception is initiated
by the condition RI = 0 and REN = 1. In the remaining
modes reception is initiated by the incoming start bit if
REN = 1.
Mode 0 Serial data enters and exits through RXD. TXD
pin delivers the synchronous shift clock. 8 bits
are transmitted/received (LSB first). When the bit
PCLK3 in the SYSCON register is reset, the baud
rate is equal to 1⁄6 × CLK. When the bit PCLK3 in
register SYSCON is set, the baud rate is equal to
1
⁄
12 × CLK. The UART baud rate should not
exceeds 4.5 Mbaud.
Mode 1 10 bits are transmitted (through TXD) or received
(through RXD): a start bit at logic 0, 8 data bits
(LSB first) and a stop bit at logic 1. On receive the
stop bit goes into RB8 in the register SCON.
The baud rate is given by the baud rate generator
output BGCLK0 for the UART0 and BGCLK1 for
the UART1.
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
12.1.2 UART CONTROL REGISTERS SCON0 AND SCON1
The registers SCON0 and SCON1 control UART0 and UART1 modes respectively, and contain the interrupt flags.
Table 49 UART Control Registers SCON0 and SCON1
ADDRESS
REGISTER
7
6
5
4
3
2
1
0
FFFF 8603H
FFFF 8607H
SCON0
SCON1
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Table 50 Description of register SCON0 and SCON1 bits
BIT
7 to 6
5
SYMBOL
DESCRIPTION
SM0 to SM1 Mode bits; see Table 51.
SM2
Multiprocessor; enable the multiprocessor communication feature in Modes 2 and 3.
If SM2 is set the RI will not be activated if the received 9th data bit RB8 = 0. In Mode 1,
if SM2 is set the RI will not be activated if a valid stop bit is not received. In Mode 0,
SM2 should be a logic 0.
4
3
REN
TB8
Receive enable; enables serial reception; set and cleared by software.
Transmit extra bit; 9th data bit that will be transmitted in Modes 2 and 3; set and
cleared by software.
2
1
RB8
TI
Receive extra bit; in Modes 2 and 3, RB8 is the 9th bit received. In Mode 1, if SM2 = 0,
RB8 is the stop bit which is received.
Transmit interrupt; it is set by hardware at the end of the 8th bit time in Mode 0, or
halfway through the stop bit in the other modes (except: see bit SM2). TI must be
cleared by software (cannot be set by software). By writing a logic 1 the flags stay
unchanged. In order to clear a particular flag one has to write a logic 0 to the
corresponding position and a logic 1 to the others. One should avoid to use the
instruction BCLR, which can reset accidentally several flags.
0
RI
Receive interrupt; set by hardware at the end of the 8th bit time in Mode 0, or halfway
through the stop bit in the other modes (except: see SM2). RI must be cleared by
software (cannot be set by software). By writing a logic 1 the flags stay unchanged. In
order to clear a particular flag one has to write a logic 0 to the corresponding position
and a logic 1 to the others. One should avoid to use the instruction BCLR, which can
reset accidentally several flags.
Table 51 Mode defined by bits SM0 and SM1
SM0
SM1
MODE
DESCRIPTION
0
0
1
1
0
1
0
1
0
1
2
3
shift register; 1⁄6 × CLK
8-bit UART; BGCLK0 and BGCLK1
9-bit UART; 1⁄16 × CLK
9-bit UART; BGCLK0 and BGCLK1
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
The timer is clocked by the peripheral clock. The baud
rates for UART0 and UART1 in Mode 1 and 3 are
determined by the timer overflow rate as follows
(FCLK is in Hz):
12.2 Baud rate generator
A dedicated baud rate generator is directly connected to
the UART0. For the UART1 this clock can be divided by
1 or 4 as a function of the bit BDIV in the BCON control
register.
FCLK
BGCLK0 =
BGCLK1 =
--------------------------------------------------------------
(16x (65536 – BREG) )
The baud rate generator consists of a 16-bit timer, two
8-bit registers BREGL (least significant byte) and BREGH
(most significant byte) to store the 16-bit reload value, and
a control register BCON.
FCLK
-----------------------------------------------------------------------------------
16 × (65536 – BREG) x4BDIV
When an overflow occurs the timer is reloaded with the
contents of the registers BREGH, BREGL.
12.2.1 UART BAUD RATE CONTROL REGISTER (BCON)
The default value after a CPU reset for all bits of BCON is a logic 0.
Table 52 UART Baud Rate Control Register (address FFFF 860FH)
7
6
5
4
3
2
1
0
−
−
−
−
−
−
BST
BDIV
Table 53 Description of BCON bits
BIT
7 to 2
1
SYMBOL
DESCRIPTION
−
Reserved.
BST
BST = 0, stop timer; BST = 1, start timer increment after loading of timer register with
the reload register value.
0
BDIV
BDIV = 0, UART1 baud rate not divided; BDIV = 1, UART1 baud rate divided by 4.
The RAM can be accessed by the CPU any time.
The queue controller accesses the RAM either in read
12.3 UART queue
The UART queue performs the sending and receiving of a
frame of bytes of variable length through the UART without
the support of the CPU. Only the UART0 has a frame
buffer located at the lower 256 bytes section of the internal
RAM. A controller ensures the sequencing of the transfers
between the RAM and the UART and generates interrupts
to the CPU. This UART queue can be used for
mode for the transmission or in write mode for the
reception. When the queue controller accesses the RAM,
the CPU waits for the end of the access cycle (maximum 4
CLK clocks). The RAM space can be partitioned in one or
several buffers for transmission or reception or for normal
data storage. The maximum size of a buffer is limited to
256 bytes. In addition to these buffers the queue consists
of a set of control and data registers:
transmission and reception simultaneously or for only one
of the two modes.
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
data bus
address bus
UQTS
UQRS
UQRA
UQTA
MUX
DECR
INCR
RAM
256 BYTES
MUX
zero
data bus
UQRM
UQRC UQTC
ten
MUX
=
UART QUEUE CONTROL
TX SBUF0
RX SBUF0
TX
RX
TI
RI
MGD782
SCON0
RIF
TIF
Fig.12 UART queue block diagram.
Table 54 Function of UART queue registers
NAME FUNCTION
DESCRIPTION
Reception control and status flags.
SIZE
byte
byte
UQRC(1) Reception Control Register
UQTC(1) Transmission Control Register
and Interrupt Flags.
Transmission control and status flags and interrupt flags.
UQTA(2) Transmit Buffer Address Register
Start address of transmission buffer from 00H to FFH,
corresponds to CPU address from FFFF 9000H to
FFFF 90FFH.
byte
UQTS (2) Transmit Buffer Size Register
Size of the transmission buffer. Limited to 256 bytes.
byte
byte
UQRA(3) Reception Buffer Address Register Start address of reception buffer from 00H to FFH,
corresponds to CPU address from FFFF 9000H to
FFFF 90FFH.
UQRS(3) Reception Buffer Size Register
Size of the reception buffer. Limited to 256 bytes.
byte
byte
UQRM
Reception Match Register
The received characters are compared with the value
contained in this register and an interrupt is generated when
they are equal.
Notes
1. UQRC and UQTC can be accessed together as a word or as two bytes.
2. For each byte transmitted the UQTA is incremented, the UQTS is decremented.
3. For each byte received the UQRA is incremented, the UQRS is decremented.The CPU can read this register on the
fly, but in this case the accuracy is not guaranteed so it is recommended to halt the queue and read the values.
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
12.3.1 RECEPTION CONTROL REGISTER (UQRC)
In order to keep the bit unchanged when writing to the control register, it is recommended to write a logic 1 when it can
only be reset, and to write a logic 0 when it can only be set. After peripheral reset all bits are set to a logic 0.
Table 55 Reception Control Register (address FFFF 8B00H)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ACTION OF
REN
S/R
−
RME
S/R
−
RIE
S/R
−
ROE
S/R
−
ROF
R
RAR
S/R
−
RHLT
S/R
−
RSTF
CPU(1)
QUEUE(2)
S
R
S
Notes
1. CPU. R: the CPU can reset this bit. S: the CPU can set this bit.
2. QUEUE. R: the queue controller can reset this bit. S: the queue controller can set this bit.
Table 56 Description of UQRC bits
BIT
SYMBOL
DESCRIPTION
7
REN
Receive queue enable. This bit enables the queue controller. It connects the reception
data buffer SBUF0 to the queue controller. It should be set before activating the RSTF bit.
When it is reset SBUF0 can be accessed directly by the CPU. REN = 0 means receive
queue disable. Received byte can be read directly from SBUF0. REN = 1 means receive
queue enable: The transfers from the SBUF0 to the RAM can be activated by setting the
bit RSTF.
6
5
4
RME
RIE
Reception match enable. If it is set each received byte is compared with the content of
the UART Queue Receive Match register (UQRM) and if their value match the receive
interrupt flag RIF is set. RME = 0 means match function disabled. RME = 1 means match
function enabled.
Reception interrupt enable. When this bit is set, each time a byte is received the receive
interrupt flag RIF is set. If it is not set, an interrupt is only generated at the end of the
frame. RIE = 0 means no interrupt after the reception of each byte, only at the end of the
frame. RIE = 1 means interrupt after the reception of each byte.
ROE
Reception overflow enable. When this bit is set, the RSTF bit is not reset when the
reception buffer size reached 0, setting the RIF flag, so the reception of further bytes is
allowed. The bit ROF is not set because RSTF stays set. This bit can be set in conjunction
of RAR to implement a circular buffer. ROE = 0 means no overflow enable. ROE = 1
means overflow enable.
3
ROF
Reception overflow flag. This flag is set by the queue controller, when a character is
received with the RSTF flag reset and REN set. This event can occur after the end of
reception of a frame, and if the CPU had no time to unload the RAM and set RSTF.
ROF = 0 means no overflow detection. ROF = 1 means overflow.
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
BIT
SYMBOL
DESCRIPTION
2
RAR
Reception address reset. If this flag is set, when the buffer size has been decremented
to zero, the reception address is reset. This way a circular reception buffer can be located
at address 0. RAR = 0 means no reset of reception address. RAR = 1 means reset of
reception address.
1
0
RHLT
RSTF
Reception halt. This bit is set by the CPU to interrupt the reception of the frame. The byte
currently received by the UART will be stored in the buffer, but the next bytes will be lost
until the CPU reset the bit RHLT. In order to stop all activity in the UART it is preferable to
reset the bit REN reception enable of the register SCON0. RHLT = 0 means reception not
halted. RHLT = 1 means reception halted.
Reception start flag. This bit is set by the CPU to enable the reception of a frame
through the UART and it is reset automatically by the queue controller at the end of
reception. When RHLT is set this bit stays set. When REN is reset, this bit is reset.
RSTF = 0 means reception not started or ended. RSTF = 1 means reception started and
in progress.
12.3.2 TRANSMISSION CONTROL REGISTER AND INTERRUPT FLAGS (UQTC)
Table 57 Transmission Control Register and Interrupt Flags (address FFFF 8B01H)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ACTION OF
TIF
R
RIF
R
reserved
TIWF
−
TEN
S/R
−
TIE
S/R
−
THLT
S/R
−
TSTF
CPU(1)
QUEUE(2)
−
−
S
R
S
S
S/R
Notes
1. CPU. R: the CPU can reset this bit. S: the CPU can set this bit.
2. QUEUE. R: the queue controller can reset this bit. S: the queue controller can set this bit.
Table 58 Description of UQTC bits
BIT
SYMBOL
DESCRIPTION
7
TIF
Transmission interrupt flag. This flag is set either at the end of the transmission buffer
or at the transmission of each byte if TIE is set. The TIF flag should be reset by the CPU in
the exception routine in order to detect further interrupts as they are edge detected for
LOW-to-HIGH transitions.
6
RIF
Reception interrupt flag. This flag is set either at the end of the reception buffer or during
a character match if RME is set or at the reception of each byte if RIE is set. The RIF flag
should be reset by the CPU in the exception routine in order to detect further interrupts as
they are edge detected for LOW-to-HIGH transitions.
5
4
−
Reserved.
TIWF
Transmission interrupt waiting. TIWF = 0(1) means queue controller is not waiting for
UART transmit interrupt.TIWF = 1 means queue controller is waiting for UART transmit
interrupt.
3
TEN
Transmission queue enable. TEN = 0(1) means transmission queue disable.
Transmitted byte can be written directly into SBUF0. TEN = 1 means transmission queue
enable; the transfers from the RAM to SBUF0 can be activated by setting the bit TSTF.
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
BIT
SYMBOL
DESCRIPTION
2
TIE
Transmission interrupt enable. If it is set, each time a byte is transmitted the transmit
interrupt flag TIF is set. If it is not set, an interrupt is only generated at the end of the
frame. TIE = 0(1) means no interrupt after the reception of each byte. TIE = 1 means
interrupt after the reception of each byte.
1
0
THLT
TSTF
Halt transmission. This bit is set by the CPU to interrupt the transmission of the frame.
The byte currently loaded in the UART will be transmitted entirely, but the next byte will
wait until the CPU reset the bit HLTT. THLT = 0(1) means transmission not halted.
THLT = 1 means transmission halted.
Start transmission. This bit is set by the CPU to start the transmission of a frame through
the UART and it is reset automatically by the queue controller at the end of transmission.
TSTF = 0(1) means transmission not started or ended. TSTF = 1 means transmission
started and in progress.
Note
1. State after peripheral reset.
12.3.3 UART QUEUE REGISTERS
Table 59 UART Queue Registers
REGISTER
UQTA
ADDRESS
FFFF 8B03H
FFFF 8B05H
FFFF 8B07H
FFFF 8B09H
FFFF 8B0BH
7
6
5
4
3
2
1
0
A7
S7
A7
S7
M7
A6
S6
A6
S6
M6
A5
S5
A5
S5
M5
A4
S4
A4
S4
M4
A3
S3
A3
S3
M3
A2
S2
A2
S2
M2
A1
S1
A1
S1
M1
A0
S0
A0
S0
M0
UQTS
UQRA
UQRS
UQRM
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
12.3.4 UART QUEUE OPERATION: TRANSMISSION
The UART queue transmit operation is as follows:
12.3.5.1 Mode 0: Normal reception buffer.
We want to receive 80 characters, store then in a buffer
starting at the address FFFF 9020H and generate an
interrupt. The CPU is able to down-load the 80 characters,
before the reception of any further character.
1. The UART control register is initialized for a certain
transmission mode (0, 1, 2 and 3) and the baud rate
generator loaded for a defined baud rate.
After reception of the first character the queue controller
reads the data reception register SBUF0 and transfers it’s
contents into the buffer at the address of the UQRA
register, at the same time the buffer size register UQRS is
decremented, the address register UQRA is incremented
to point to the next byte. If the buffer size is not equal to
zero the same operation is repeated automatically for the
next byte to be transmitted.
2. The CPU loads the data to be transmitted (for example
80 characters) at successive addresses of the internal
RAM starting at a certain base address (for example
FFFF 9010H). Then it writes the buffer start address
and the buffer size in the pointer registers, and
initializes the control register.
3. The queue controller reads the byte at the address
pointed by the address register and writes it to the
transmit data buffer of the UART and the buffer size
register is decremented, the address register is
incremented pointing to the next byte in the buffer.
The transmission starts. The controller waits for the
end of transmission, then compares the buffer size
value to zero, if they are not equal the same operation
is repeated automatically.
If the buffer size is zero the receive interrupt flag RIF is set
issuing an interrupt to the CPU. The interrupt routine
should reset RIF and can read the content of the buffer and
re-initialize the control registers.
Table 61 Reception routine
move.b #$50, UQRS ;set buffer size
4. If the buffer size is zero the transmit interrupt flag TIF
is set issuing an interrupt to the CPU.The interrupt
routine should reset TIF and can reload the buffer with
other values.
move. #$20, UQRA ;set buffer start address
bset
bset
REN, UQRC
;Enable queue controller
RSTF, UQRC ;Start reception.
5. Before checking the buffer size value, the halt bit THLT
is tested and if it is set the controller enters a
transmission wait state.
Table 62 Interrupt routine
move.b
move.b
#$BE,UQTC
#$28,d0
;reset RIF bit
;buffer size in words
Table 60 Transmission routine
move.l
#$FFFF9020,a0 ;buffer start address
move.b #$50,UQTS ;buffer size
L1 move.l
#$00008000,a1 ;external memory
start address
move.b #$10,UQTA ;buffer start address
bset
bset
TEN,UQTC; ;Enable transmission queue
STF,UQTC; ;Start transmission.
dbne
d0,L1
;loop
12.3.5 UART QUEUE OPERATION: RECEPTION
The UART queue reception operation is as follows:
The UART control register is initialized for a certain
reception mode (Mode 0, 1, 2 and 3) and the baud rate
generator loaded for a defined baud rate.
The CPU writes the buffer start address and the buffer size
in the data registers, and the control register. Several
modes can be used:
1996 Dec 11
45
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
12.3.5.2 Mode 1: Special termination character match.
12.3.5.4 Mode 3: Circular buffer with interrupt.
Suppose that we want to generate an interrupt after the
reception of a Carriage Return character, we load in the
reception match register the value 0DH, to guarantee that
the buffer does not overflow if the buffer size is limited to
80 characters. The buffer is located in RAM at the address
FFFF 9050H.
If we want to implement a circular buffer which generates
an interrupt each time the size register is equal to 0, the
UQRA address register is reset and points to the beginning
of the RAM.
Table 65 Mode 3 routine
The same operations as described before are performed
but in addition each received characters compared with
the character Carriage Return and if they match the
receive interrupt flag RIF is set, RSTF is reset and the
reception queue is stopped.
move.b #$50,UQRS
move.b #$00,UQRA
; buffer size
; buffer start address
; enable queue
bset
bset
bset
REN,UQRC
RAR,UQRC
RSTF,UQRC
; reception reset address
; start reception (note 1)
Table 63 Mode 1 routine
Note
move.b #$50,UQRS
move.b #$50,UQRA
move.b #$0d,UQRM
; buffer size
1. All these control bits can be set at the same time.
; buffer start address
; set match character
; enable queue
12.3.6 UART QUEUE OPERATION: RECEPTION HALT
bset
bset
bset
REN,UQRC
RME,UQRC
RSTF,UQRC
Before to check the buffer size value, the halt bit HLTR0 is
tested and if it is set the controller enters a reception wait
state.
; reception match enable
; start reception (note 1)
Note
12.3.7 UART QUEUE OPERATION: EMULATION
1. All these control bits can be set at the same time.
When the pin PHALT (on the emulation package) is
asserted LOW, the queue is halted the same way as when
THLT and RHLT are set. The queue operation is continued
when the pin PHALT is released HIGH.
12.3.5.3 Mode 2: Linear buffer with continuous
reception.
If we want to continue to receive characters in the buffer
after the end of the buffer and the setting of RIF:
In this case RSTF is not reset at the end of the buffer, but
the CPU will receive an interrupt (RIF = 1) when the size
register UQRS equals zero.
Table 64 Mode 2 routine
move.b #$50,UQRS
move.b #$50,UQRA
; buffer size
; buffer start address
; enable queue
bset
bset
bset
REN,UQRC
ROE,UQRC
RSTF,UQRC
; reception overflow enable
; start reception (note 1)
Note
1. All these control bits can be set at the same time.
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
12.4 I2C-bus interface
These functions are controlled by the SCON register.
SSTA is the Status Register whose contents may be used
as a vector to various service routines. SDAT is the data
shift register and SADR the slave address register. Slave
address recognition is performed by hardware.
The serial port supports the twin line I2C-bus. The I2C-bus
consists of a data line SDA and a clock line SCL. These
lines also function as I/O port lines P11 and P10
respectively (always open drain). The system is unique
because data transport, clock generation, address
recognition and bus control arbitration are all controlled by
hardware. The I2C-bus serial I/O has complete autonomy
in byte handling and operates in four modes:
For more details on the I2C-bus functions, see user
manual “The I2C-bus and how to use it (including
specifications)”; order number 9398 393 40011.
• Master transmitter mode
• Master receiver mode
• Slave transmitter mode
• Slave receiver mode.
12.5 Serial Control Register (SCON)
Table 66 Serial Control Register (address FFFF 8207H)
7
6
5
4
3
2
1
0
CR2
ENS
STA
STO
SI
AA
CR1
CR0
Table 67 Serial Control Register SCON bits
BIT
SYMBOL
DESCRIPTION
7, 1 and 0
CR2 to CR0 These three bits determine the serial clock frequency when SIO is in a master mode
function of the peripheral clock FCLK (see Tables 68 and 69).
6
5
ENS
Enable serial I/O. If ENS = 0, the serial interface I/O is disabled and reset; if ENS = 1,
the serial interface is enabled.
Start flag. When this bit is set in slave mode, the hardware checks the I2C-bus and
generates a START condition if the bus is free or after the bus becomes free. If the
device operates in master mode it will generate a repeated START condition.
STA
4
STO
Stop flag. If this bit is set in the master mode a STOP condition is generated. A STOP
condition detected on the I2C-bus clears this bit. The STOP bit may also be set in slave
mode in order to recover from an error condition. In this case no STOP condition is
generated to the I2C-bus, but the hardware releases the SDA and SCL lines and
switches to the not selected slave receiver mode. The STOP flag is cleared by the
hardware.
3
SI
Serial Interrupt flag. This flag is set, and an interrupt is generated, after any of the
following events occur:
• A START condition is generated in master mode.
• The own slave address has been received during AA = 1.
• The general call address has been received while bit SADR.0 = 1 and AA = 1.
• A data byte has been received or transmitted in master mode.
• A data byte has been received or transmitted as selected slave.
• A STOP or START condition is received as selected slave receiver or transmitter.
While the SI flag is set, SCL remains LOW and the serial transfer is suspended. SI must
be reset by software.
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
BIT
SYMBOL
DESCRIPTION
2
AA
Assert Acknowledge When this bit is set, an acknowledge is returned after any one of
the following conditions:
• Slave address is received.
• The general call address is received (bit SADR.0 = 1).
• A data byte is received, while the device is programmed to be a master receiver.
• A data byte is received, while the device is a selected slave receiver.
When bit AA is reset, no acknowledgement is returned. Consequently, no interrupt is
requested when the own slave address or general call address is received.
Table 68 CLK/SCL divide factor
Values greater than 100 kbits are outside the specified frequency range.
CLK/SCL DIVIDE FACTOR
CR2
CR1
CR0
D = 2(1)
128
112
96
D = 3
192
168
144
120
720
90
D = 4
256
224
192
160
960
120
60
D = 5
320
280
240
200
1200
150
75
D=6
384
336
288
240
1440
180
90
D=8
512
448
384
320
1920
240
120
D=10
640
560
480
400
2400
300
150
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
80
480
60
30
45
Table 69 I2C-bus serial clock rates
Values greater than 100 kbits are outside the specified frequency range.
BIT FREQUENCY (kHz) AT CLK = 26 MHz
CR2
CR1
CR0
D = 2(1)
D = 3
D = 4
D = 5
D = 6
D = 8
D = 10
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
−
−
−
−
101
−
81
93
−
68
77
90
−
51
58
68
81
13
−
41
46
54
65
10
87
−
−
−
−
−
−
−
−
54
−
36
−
27
−
22
−
18
−
−
−
−
−
−
−
Note to Tables 68 and 69
1. D = divisor = CLK
FCLK; see Table 15.
⁄
1996 Dec 11
48
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
12.5.1 I2C-BUS STATUS REGISTER (SSTA)
SSTA is an 8-bit read only Special Function Register. The contents of SSTA may be used as a vector to a service routine.
This optimizes response time of the software and consequently that of the I2C-bus. Tables 73 to 77 show the list of the
status codes defined by the contents of register SSTA.
Table 70 I2C-bus Status Register (address FFFF 8205H)
7
6
5
4
3
2
1
0
SC4
SC3
SC2
SC1
SC0
−
−
−
Table 71 Description of SSTA bits
BIT
SYMBOL
SC4 to SC0 The bits SC4 to SC0 hold a status code.
Reserved; held LOW.
DESCRIPTION
7 to 3
2 to 0
−
Table 72 Used abbreviations in the mode descriptions; see Tables 73 to 77
SYMBOL DESCRIPTION
SLA
R
7-bit slave address
read bit
W
write bit
ACK
acknowledgement (acknowledge bit = 0)
ACKNOT
DATA
MST
not acknowledge (acknowledge bit = 1)
8-bit (byte) to or from the I2C-bus
master
SLV
slave
TRX
transmitter
receiver
REC
Table 73 Master transmitter (MST/TRX) mode
SSTA VALUE
DESCRIPTION
A START condition has been transmitted
A repeated START condition has been transmitted
08H
10H
18H
20H
28H
30H
38H
SLA and W have been transmitted, ACK has been received
SLA and W have been transmitted, ACKNOT received
DATA of S1DAT has been transmitted, ACK received
DATA of S1DAT has been transmitted, ACKNOT received
Arbitration lost in SLA, R/W or DATA
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 74 Master receiver (MST/REC) mode
SSTA VALUE
DESCRIPTION
38H
40H
48H
50H
58H
Arbitration lost while returning ACKNOT
SLA and R have been transmitted, ACK received
SLA and R have been transmitted, ACKNOT received
DATA has been received, ACK returned
DATA has been received, ACKNOT returned
Table 75 Slave transmitter (SLV/TRX) mode
S1STA VALUE
DESCRIPTION
A8H
B0H
B8H
C0H
C8H
Own SLA and R received, ACK returned
Arbitration lost in SLA, R/W as MST. Own SLA and R received, ACK returned
DATA byte has been transmitted, ACK received
DATA byte has been transmitted, ACK received
Last DATA byte has been transmitted, ACKNOT received
Table 76 Slave receiver (SLV/REC) mode
SSTA VALUE
DESCRIPTION
60H
68H
70H
78H
80H
88H
90H
98H
A0H
Own SLA and W have been received, ACK returned
Arbitration lost in SLA, R/W as MST. Own SLA and W have been received, ACK returned
General call has been received, ACK returned
Arbitration lost in SLA, R/W as MST. General call received, ACK returned
Previously addressed with own SLA. DATA byte received, ACK returned
Previously addressed with own SLA. DATA byte received, ACKNOT returned
Previously addressed with general call. DATA byte received, ACK has been returned
Previously addressed with general call. DATA byte received, ACKNOT has been returned
A STOP condition or repeated START condition received while still addressed as SLV/REC or
SLV/TRX
Table 77 Miscellaneous
S1STA VALUE
DESCRIPTION
00H
Bus error during MST mode or selected SLV mode, due to an erroneous START or STOP
condition
1996 Dec 11
50
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
12.5.2 I2C-BUS DATA SHIFT REGISTER (SDAT)
Table 78 I2C-bus Data Shift Register (address FFFF 8201H)
7
6
5
4
3
2
1
0
DATA.7
DATA.6
DATA.5
DATA.4
DATA.3
DATA.2
DATA.1
DATA.0
Table 79 Description of SDAT bits
BIT
SYMBOL
DESCRIPTION
7 to 0
DATA.7 to DATA.0
The serial data to be transmitted or data that has just been received.
Bit 7 is transmitted or received first; i.e. data is shifted from right to left.
12.5.3 I2C-BUS ADDRESS REGISTER (SADR)
This 8-bit register may be loaded with the 7-bit address to which the controller will respond when programmed as a slave
receiver/transmitter.
Table 80 I2C-bus Address Register (address FFFF 8203H)
7
6
5
4
3
2
1
0
SADR.7
SADR.6
SADR.5
SADR.4
SADR.3
SADR.2
SADR.1
SADR.0
Table 81 Description of SADR bits
BIT
7 to 1
0
SYMBOL
SADR.7 to SADR.1
SADR.0
DESCRIPTION
Slave address.
SADR.0 = GC, is used to determine whether the general CALL address
is recognized. If GC = 0, general CALL address is not recognized (default
value after a CPU reset). If GC = 1, general CALL address is recognized.
1996 Dec 11
51
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
The pulse width ratio is in the range of 0 to 255
⁄255 and may
13 PULSE WIDTH MODULATION (PWM) OUTPUTS
be programmed in increments of 1⁄255
.
Two Pulse Width Modulation outputs are provided on the
P90CL301. These channels output pulses of
programmable length and interval. The repetition
frequency is defined by an 8-bit prescaler PWMP, which
generates the clock for the counter. The 8-bit counter
counts modulo 255 (from 0 to 254 inclusive).
The repetition frequency:
FCLK
fPWM
=
Hz; for FCLK in Hz.
--------------------------------------------------
(1 + PWMP) × 255
When using a peripheral clock of 6 MHz for example, the
above formula gives a repetition frequency range of
23 kHz to 91 Hz.
The prescaler and counter are used for the two channel
outputs. The value of the 8-bit counter is compared to the
content of the registers PWM0 (resp. PWM1) for the
channel output PWM0 (resp. PWM1). Provided the
content of this register is greater than the counter value,
the output of PWM0 (resp. PWM1) is set LOW. If the
content of this register is equal to, or less than the counter
value, the output will stay high. The pulse width ratio is
therefore defined by the content of the register PWM0
(respectively PWM1).
By loading the PWM0 (resp. PWM1) with either 00H or
FFH, the PWM0 output can be retained at a constant HIGH
or LOW level respectively. When loading FFH to the
PWM0 (respectively PWM1) register, the 8-bit counter will
never actually reach this value.
13.1 Prescaler PWM Register (PWMP)
Table 82 Prescaler PWM Register (address FFFF 8801H)
7
6
5
4
3
2
1
0
PWMP.7
PWMP.6
PWMP.5
PWMP.4
PWMP.3
PWMP.2
PWMP.1
PWMP.0
Table 83 Description of PWMP bits
BIT
SYMBOL
DESCRIPTION
7 to 0
PWMP.7 to PWMP.0
Prescaler division factor = (PWMP + 1).
13.2 PWM Data Registers (PWM0 and PWM1)
Table 84 PWM Data Registers PWM0 and PWM1
ADDRESS
FFFF 8803H
FFFF 8805H
REGISTER
PWM0
7
6
5
4
3
2
1
0
PWM0.7 PWM0.6 PWM0.5 PWM0.4 PWM0.3 PWM0.2 PWM0.1 PWM0.0
PWM1.7 PWM1.6 PWM1.5 PWM1.4 PWM1.3 PWM1.2 PWM1.1 PWM1.0
PWM1
Table 85 Description of PWM0 and PWM1 bits; n = 0 to 1
BIT
SYMBOL
DESCRIPTION
(PWMn)
Pulse width ratio. LOW/HIGH ratio of PWMn signals =
7 to 0
PWMn.7 to PWMn.0
-----------------------------------------
255 – (PWMn)
1996 Dec 11
52
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
n
PWM0 REGISTER
I
OUTPUT
BUFFER
N
T
E
R
N
A
L
PWM0
8-BIT COMPARATOR
8-BIT COUNTER
PWMP
8-BIT PRESCALER
FCLK
B
U
S
OUTPUT
BUFFER
PWM1
8-BIT COMPARATOR
PWM1 REGISTER
MBG326
Fig.13 PWM block diagram.
1996 Dec 11
53
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
By resetting the EADC bit in the control register ADCON or
by entering Power-down it is possible to switch off this
current to reduce the static power consumption.
14 ANALOG-TO-DIGITAL CONVERTER (ADC)
The analog input circuitry consist of a 4 input analog
multiplexer and an analog-to-digital converter (ADC) with
8-bit resolution. The analog reference voltage Vref(A) and
the analog supplies VDDA, VSSA are connected via
separate input pins.
The ADC is controlled using the ADCON control register.
Input channels are selected by the analog multiplexer
function of register bits ADCON.0 and ADCON.1.
The completion of the 8-bit ADC conversion is flagged by
ADCI in the ADCON register and the result is stored in the
register ADCDAT (address FFFF 8809H). The result of a
completed conversion remains unaffected provided ADCI
is HIGH. While ADCS or ADCI are HIGH, a new ADC start
will be blocked and consequently lost. An ADC conversion
already in progress is aborted when Power-down mode is
entered.
The conversion time takes 24 periods of the secondary
peripheral clock FCLK2 (see Section 6.6). The maximum
value of the FCLK2 clock is dependant on the supply
voltage (see Section 20).
As the ADC is based on a successive approximation
algorithm using a resistor scale connected to Vref(A) and
VSSA, a continuous current flows in this resistor.
14.1 ADC Control Register (ADCON)
Table 86 ADC Control Register (address FFFF 8807H)
7
6
5
4
3
2
1
0
−
EADC
−
ADCI
ADCS
−
A1
A0
Table 87 Description of ADCON bits
BIT
7, 5 and 2
6
SYMBOL
−
DESCRIPTION
Reserved; set to LOW.
EADC
ADC enable. If EADC = 1, then ADC is enabled. If EADC = 0, then ADC is disabled;
the resistor reference is switched off to save power even while the CPU is operating.
4
ADCI
ADC interrupt flag. This flag is set when an ADC conversion result is ready to be read.
An interrupt is invoked if the level IPLA is different from ‘0’. The flag must be cleared by
software (it cannot be set by software). The ADCI bit must be cleared before a new
conversion is started.
3
ADCS
A1, A0
ADC start and status. Setting this bit starts a conversion. The logic ensures that this
signal is HIGH while the conversion is in progress. On completion, ADCS is reset at the
same time the interrupt flag ADCI is set. ADCS cannot be reset by software.
1, 0
Analog input select. This binary coded address selects one of the four analog inputs
ADC0 to ADC3. It can only be changed when ADCI and ADCS are both LOW. A1 is the
MSB; e.g. ‘11’ selects analog input channel ADC3.
Table 88 Operation of ADCI and ADCS
ADCI
ADCS
OPERATION
ADC not busy, a conversion can be started.
0
0
1
1
0
1
0
1
ADC busy, start of a new conversion is blocked.
Conversion completed, start of a new conversion is blocked.
Intermediate status for a maximum of one machine cycle before conversion is
completed (ADCI = 1, ADCS = 0).
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
V
DDA
+
8-BIT ANALOG-TO-DIGITAL CONVERTER
(succesive approximation)
V
ref(A)
AD0
AD1
AD2
AD3
−
+
ANALOG INPUT
MULTIPLEXER
LOGIC
V
SSA
START
END
ADCON
0
1
-
3
4
-
6
-
0
1
2
3
4
5
6
7
ADCDAT
PD
(SYSCON.2)
INTERNAL BUS
MGD779
Fig.14 Functional diagram of the ADC.
1996 Dec 11
55
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
The internal access time is in this case 3 cycles long. It can
only be accessed in supervisor mode.
15 ON-BOARD TEST CONCEPT
To improve the on-board debugging two functions are
implemented, the ON-Circuit Emulation (ONCE) mode and
the on-chip Test-ROM.
The purpose of the Test-ROM is to offer the user a simple
software interface to load programs for testing its own
application and to transmit back the test result.
15.1 ONCE mode
The program can be loaded from the host into either the
on-chip RAM or the external memory. The Test-ROM
mode is entered by pulling LOW the R/W / TROM pin
during reset.
The ON-Circuit Emulation (ONCE) mode eases the testing
of an application without having to remove the controller
from the board. The ONCE mode is entered by pulling
CSBT LOW during reset. In this mode the address bus,
data bus and bus control signals are in 3-state mode, all
other output or bidirectional pins are weakly pulled HIGH.
In this mode an emulator probe can be hooked-up to the
circuit. Normal operation is restored with a normal reset.
Just after the RESET initialization, the user should send a
character of 9 bits (one stop bit plus eight data bits) with all
bits being zero, on the RX0 line.
Using the timer, the character length is captured and then
the baud rate is automatically calculated and the baud rate
generator is initialized. The UART0 is then initialized in
Mode 3 with SM2 multiprocessor bit set, REN and TB8 bit
set (SCON = F8H). The hardware is now ready to handle
the protocol using the following 4 commands
15.2 Test-ROM
A second on-board debugging function is introduced for
the situation where no extra connector can be placed on
the PCB. It consists of an internal Test-ROM of 256 bytes
which is used as boot ROM after a special test mode is
activated during reset. The CPU will execute the code
placed in the Test-ROM and initialize the UART0 and its
baud rate generator and wait for commands to be sent to
UART0.
(Code 00 to 11).
Table 89 Command format
7
6
5
4
3
2
1
0
Code
NB byte − 1
Table 90 Command description
BIT
7, 6
SYMBOL
DESCRIPTION
Code
Pointer commands; see Table 91.
5 to 0
NB byte − 1 Indicates the length of the transfer; e.g. (NB byte − 1) = 0 means a 1 byte transfer,
(NB byte − 1) = 63 means a 64 byte transfer.
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 91 Pointer commands
CODE
DESCRIPTION
BIT 7 BIT 6
0
0
The pointer (A0 register) is initialized with a value depending of the number of transferred bytes.
The most significant byte should be transferred first. Protocol:
To start a data transfer, the pointer should be initialized first. It is incremented by one at each byte
transfer between the memory and the host. The following registers are reserved for the protocol and
should not be used by the user: D0, D1, D2, D3, A0, A1 and A2.
0
1
1
1
0
1
Read command. Read 1 to 64 bytes (load to the host). The pointer is incremented at each transfer.
Write command. Write 1 to 64 bytes (load from the host). The pointer is incremented at each transfer.
Jump command. If the NB field is 0 then a jump to the pointer address (A0) is done to start code
execution. If the NB field ≠ 0, the complete protocol initialization is restarted (same effect as reset and
R/W / TROM = 0).
RESET
HALT
R/W / TROM
Write
command/data
RX0
9 bits
baud rate
calculation
TX0
data
MBG333
Fig.15 Test-ROM: Timing data transfer.
16 ON-CHIP RAM
The P90CL301BFH contains a 512 bytes RAM which can be used to store program code or data. As this memory does
not need wait states, it can speed up some time consuming tasks like stack operation, table references, or small program
loops, compared with slow external memory or when using the 8-bit data bus. For a read or write access, 3 CPU clocks
are used. The memory content is kept even when the supply voltage is lowered down to 1.8 V after entering Power-down
mode. The base address is FFFF 9000H. It can be accessed in long word, word or bytes.
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
17 REGISTER MAPPING
The internal register map of the P90CL301BFH is summarized in Table 92. Note that the internal registers can be
accessed:
• only in Supervisor mode for version P90CL301BFH-3/4
• both in Supervisor and User mode for version P90CL301BFH-5.
Table 92 Register map
STATE AFTER
ADDRESS
SYMBOL
WIDTH(1)
RESET
(HEX)(2)
REGISTER
ACCESS(3)
(HEX)
System register
FFFF 8000 SYSCON
W
00C0
System Control Register
R/W
Interrupt registers
FFFF 8101 LIR0
FFFF 8103 LIR1
FFFF 8105 LIR2
FFFF 8107 LIR3
FFFF 810F PIFR
B
B
B
B
B
00
00
00
00
00
Latched Interrupt 0/1 Register
Latched Interrupt 2/3 Register
Latched Interrupt 4/5 Register
Latched Interrupt 6/7 Register
Pending Interrupt Flag Register
R/W
R/W
R/W
R/W
R/C
I2C-bus registers
FFFF 8201 SDAT
FFFF 8203 SADR
FFFF 8205 SSTA
FFFF 8207 SCON
B
B
B
B
00
00
F8
00
I2C-bus Data Register
I2C-bus Address Register
I2C-bus Status Register
I2C-bus Control Register
R/W
R/W
R
R/W
Timers registers
FFFF 8300 T0CRH
FFFF 8301 T0CRL
FFFF 8302 T0RR
FFFF 8304 T0
B/W
B
0000
00
Timer 0 Control Register (High byte)
Timer 0 Control Register (Low byte)
Timer 0 Reload Register
R/W
R/W
W
W
W
W
W
W
B
0000
0000
XXXX
XXXX
XXXX
X0
Timer 0 Register
R
FFFF 8306 T0C0
FFFF 8308 T0C1
FFFF 830A T0C2
FFFF 830D T0SR
FFFF 830F T0PR
FFFF 8310 T1CRH
FFFF 8311 T1CRL
FFFF 8312 T1RR
FFFF 8314 T1
Timer 0 Channel 0 Register
Timer 0 Channel 1 Register
Timer 0 Channel 2 Register
Timer 0 Status Register
R/W
R/W
R/W
R/C
W
B
00
Timer 0 Prescaler Reload Register
Timer 1 Control Register (High byte)
Timer 1 Control Register (Low byte)
Timer 1 Reload Register
B/W
B
0000
00
R/W
R/W
W
W
W
W
W
W
B
0000
0000
XXXX
XXXX
XXXX
X0
Timer 1 Register
R
FFFF 8316 T1C0
FFFF 8318 T1C1
FFFF 831A T1C2
FFFF 831D T1SR
Timer 1 Channel 0 Register
Timer 1 Channel 1 Register
Timer 1 Channel 2 Register
Timer 1 Status Register
R/W
R/W
R/W
R/C
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
STATE AFTER
ADDRESS
(HEX)
SYMBOL
WIDTH(1)
RESET
(HEX)(2)
REGISTER
ACCESS(3)
FFFF 831F T1PR
FFFF 8401 WDTIM
FFFF 8403 WDCON
B
B
B
00
00
A5
Timer 1 Prescaler Reload Register
Watchdog Timer Register
W
R/W
S
Watchdog Control Register
(only A5H or 5AH)
Port registers
FFFF 8503 PCON
FFFF 8505 PRL
FFFF 8507 PPL
FFFF 8509 PRH
FFFF 850B PPH
FFFF 8109 SPCON
FFFF 810B SPR
FFFF 810D SPP
B
B
B
B
B
B
B
B
00
FF
FF
FF
FF
80
FF
FF
Port Control Register
R/W
R/W
R
P Port Latch (least significant byte)
P Port Pin (least significant byte)
P Port Latch (most significant byte)
P Port Pin (most significant byte)
SP Port Control Register
SP Port Latch
R/W
R
R/W
R/W
R
SP Port Pin
UART registers
FFFF 8601 SBUF0
FFFF 8603 SCON0
FFFF 8605 SBUF1
FFFF 8607 SCON1
B
B
B
B
XX
00
XX
00
UART0 Transmit/Receive Register
UART0 Control Register
R/W
R/W
R/W
R/W
UART1 Transmit/Receive Register
UART1 Control Register
Baud rate generator registers
FFFF 860B BREGL
B
B
B
00
00
00
UART Baud Rate Register
(least significant byte)
R/W
R/W
R/W
FFFF 860D BREGH
UART Baud Rate Register
(most significant byte)
FFFF 860F BCON
UART Baud Rate Control Register
Peripheral interrupt registers
FFFF 8701 PICR0
FFFF 8703 PICR1
FFFF 8705 PICR2
FFFF 8707 PICR3
B
B
B
B
00
00
00
00
Timer Interrupt Register
R/W
R/W
R/W
R/W
UART0 Interrupt Register
UART1 Interrupt Register
I2C and ADC Interrupt Register
Pulse Width Modulation registers
FFFF 8801 PWMP
FFFF 8803 PWM0
FFFF 8805 PWM1
B
B
B
00
00
00
PWM Prescaler Register
PWM0 Data Register
PWM1 Data Register
W
R/W
R/W
ADC registers
FFFF 8807 ADCON
FFFF 8809 ADCDAT
B
B
00
FF
ADC Control Register
ADC Data Register
R/W
R
Chip-select registers
FFFF 8A00 CS0N
W
FFFF
Chip-select 0 Control Register
R/W
1996 Dec 11
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Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
STATE AFTER
ADDRESS
(HEX)
SYMBOL
WIDTH(1)
RESET
(HEX)(2)
REGISTER
ACCESS(3)
FFFF 8A02 CS1N
FFFF 8A04 CS2N
FFFF 8A06 CS3N
FFFF 8A08 CS4N
FFFF 8A0A CS5N
FFFF 8A0C CS6N
FFFF 8A0E CSBT
FFFF 8A11 BSREG
UART queue registers
FFFF 8B00 UQRC
FFFF 8B01 UQTC
FFFF 8B03 UQTA
FFFF 8B05 UQTS
FFFF 8B07 UQRA
FFFF 8B09 UQRS
FFFF 8B0B UQRM
W
W
W
W
W
W
W
B
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
F306
00
Chip-select 1 Control Register
Chip-select 2 Control Register
Chip-select 3 Control Register
Chip-select 4 Control Register
Chip-select 5 Control Register
Chip-select 6 Control Register
Chip-select Boot Control Register
Bus Size Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
B
B
B
B
B
B
B
00
00
00
00
00
00
00
UART Queue Receive Control Register
UART Queue Transmit Control Register
UART Queue Transmit Address Register
UART Queue Transmit Status Register
UART Queue Receive Address Register
UART Queue Receive Status Register
UART Queue Receive Match Register
R/W
R/W
R/W
R/C
R/W
R/C
R/W
Notes
1. Width when specified is in byte (B) or word (W).
2. X = don’t care.
3. Access when specified is in read (R) write (W) or clear (C) only. The Watchdog Control Register is special (S).
1996 Dec 11
60
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
18 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
VI
PARAMETER
MIN.
−0.5
MAX.
+3.6
VDD + 0.5 V
UNIT
supply voltage
V
input voltage on any pin with respect to ground (VSS
DC current into any input or output
total power dissipation
)
−0.5
−
II, IO
Ptot
5
mA
mW
−
300
+150
+85
+125
Tstg
storage temperature range
−65
−40
−
°C
°C
°C
Tamb
Tj
operating ambient temperature range
operating junction temperature range
19 DC CHARACTERISTICS
DD = 2.7 to 3.6 V; VSS = 0 V; Tamb = −40 to +85 °C; all voltages with respect to VSS unless otherwise specified.
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Supply
VDD
supply voltage
2.7
−
3.6
V
IDD
supply current operating; note 1
VDD = 3 V; CLK = 13.8 MHz
VDD = 3 V; CLK = 27 MHz
VDD = 3 V; CLK = 13.8 MHz
VDD = 3 V; CLK = 27 MHz
−
−
−
−
−
−
−
16
32
400
800
9
22
mA
mA
µA
µA
mA
mA
µA
40
IDD(ID)
supply current Idle mode; note 2a
500
1000
15
IDD(STB)
supply current Standby mode; note 2b VDD = 3 V; CLK = 13.8 MHz
VDD = 3 V; CLK = 27 MHz
18
2
25
IDD(PD)
supply current Power-down mode;
note 3
VDD = 3 V
40
Inputs
VIL
LOW level input voltage
VSS
VSS
−
−
0.3VDD
0.1VDD
V
V
VIL
LOW level input voltage; D15 to D8,
XTAL1, HALT, RESET, RESETIN
VIH
IIL
HIGH level input voltage
LOW level input current
0.7VDD
−
VDD
50
V
VDD = 3 V; VIN = 0.4 V
VDD = 3 V; VIN = 0.5VDD
−
−
−
13
140
1
µA
µA
µA
ITL
ITSI
input current HIGH-to-LOW transition
3-state input current
500
10
Outputs
IOH4
HIGH level output current;
TS4 and OD4; note 4
VDD = 3 V; VOH = VDD − 0.4 V 4
13
−
mA
IOH2
IOL8
HIGH level output current; WP2; note 4 VDD = 3 V; VOH = VDD − 0.4 V 2
7
−
−
mA
mA
LOW level output current; OD8 and S8; VDD = 3 V; VOL = 0.4 V
note 4
8
24
IOL4
LOW level output current;
TS4 and OD4; note 4
VDD = 3 V; VOL = 0.4 V
4
15
−
mA
IOL2
CIN
LOW level output current; WP2; note 4 VDD = 3 V; VOL = 0.4 V
input capacitance; note 5
2
8
−
mA
pF
−
−
10
1996 Dec 11
61
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
SYMBOL
RUP
PARAMETER
CONDITIONS
MIN.
16
TYP.
26
MAX. UNIT
pull-up resistor UP; note 6a
pull-up resistor UP2; note 6b
pull-up resistor UP3; note 6c
RESETIN resistor
60
kΩ
kΩ
kΩ
kΩ
RUP2
8
15
30
RUP3
70
15
100
31
500
120
RSTIN
Notes
1. The operating supply current through VDD1, VDD2 and VDD3 is measured with all output pins disconnected;
RESETIN = RESET = HALT = 0; A23 to A0 = VDD; D15 to D0 = VDD
.
2. Idle and Standby current:
a) The Idle supply current through VDD1, VDD2 and VDD3 is measured with all port pins disconnected;
A23 to A0 = VDD; D15 to D0 = VDD; the circuit is executing NOP instructions from an external memory.
b) The Standby current through VDD1, VDD2 and VDD3 is measured with all port pins disconnected;
A23 to A0 = VDD; D15 to D0 = VDD;
3. The Power-down current through VDD1, VDD2 and VDD3 is measured with all output pins disconnected;
XTAL1 = RESET = HALTN = VDD; A23 to A0 = VDD; D15 to D0 = VDD; RESETIN = VSS
.
4. See Table 95 for the different types.
5. Not tested in production.
6. Pull-ups:
a) These pull-ups are only present on the emulation pins PHALT and NMINE.
b) These active pull-ups are active on all WP2 WP4 port pins for output voltages greater than Vdd/2. They are only
active during the reset sequence on the pins CS0, CS1, R/W, CSBT and FETCH for test purpose.
c) These active pull-ups are only active on D15 to D0 and A23 to A0 pins when BPE is set in the SYSCON register.
1996 Dec 11
62
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
20 ADC CHARACTERISTICS
VDD = 2.7 to 3.6 V; Vref(A) = VDDA = VDD; VSSA = VSS; VSS = 0 V; FCLK2 = 250 kHz to 2 MHz; Tamb = −40 to +85 °C;
for ADC test conditions see note 1; all voltages with respect to VSS unless otherwise specified.
SYMBOL
PARAMETER
analog supply voltage
analog reference voltage
analog ground
CONDITIONS
MIN.
TYP.
MAX.
VDD + 0.2
VDD + 0.2
VSS + 0.2
Vref(A)
UNIT
VDDA
Vref(A)
VSSA
VIN(A)
IDDA
V
V
V
0
DD − 0.2
DD − 0.2
SS − 0.2
−
−
−
−
V
V
V
analog input voltage
supply current operating
V
VDDA = 3.0 V
−
−
150
0.1
250
µA
µA
IDD(PD)(A) analog supply current
Power-down mode
VDDA = 3.0 V
5
RVref
CIA
resistor between Vref(A) and VSSA note 2
20
−
34
150
12
1
kΩ
analog input capacitance
input leakage current
ADC clock frequency;
sampling time
note 3
−
pF
IIA
VDDA = 3.0 V
VDDA = 2.7 V; note 4
−
−
µA
FCLK2
tADS
tADC
Ae
0.25
−
−
2
MHz
µs
6 × tFCLK2
−
total conversion time
absolute voltage error
offset error
−
24 × tFCLK2
−
µs
note 1 and 5
note 1 and 6
note 1 and 7
note 1 and 8
note 3 and 9
−
−
−
−
−
−
1
LSB
LSB
LSB
LSB
LSB
OSe
ILe
−
1
integral non-linearity
differential non-linearity
channel-to-channel matching
−
1
DLe
Mctc
−
1
−
1
Notes
1. ADC test conditions: VDD = 2.7 V, Vref(A) = 2.7 V, CLK = 20 MHz, FCLK2 = 2 MHz.
2. This resistor is switched off during Power-down mode and when the ADC is switched off (EADC = 0).
3. Parameter not measured in production, only verified on sampling basis.
4. See Fig.17 for specific FCLK2 range as function of VDD
.
5. Absolute voltage error: the maximum difference between actual and ideal code transitions. Absolute voltage error
accounts for all deviations of an actual converter from an ideal converter.
6. Offset error: the difference between the actual and ideal input voltage corresponding to the first actual code transition.
7. Integral non-linearity: the maximum deviation between the edges of the steps of the transfer curve and the edges of
the steps of the ideal curve. The ideal step curve follows the line of least squares.
8. Differential non-linearity: the maximum deviation of the actual code width from the average code width.
9. Channel-to-channel matching: The difference between corresponding code transitions of actual characteristics taken
from different channels under the same temperature, voltage and frequency conditions.
1996 Dec 11
63
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
255
254
253
252
251
(4)
(1)
(2)
250
code
out
5
4
3
2
1
0
(3)
7
1 LSB (ideal)
1
2
3
4
5
6
250 251 252 253 254 255
AV (LSB
)
ideal
IN
zero offset
error
MGC758
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential non-linearity.
(4) Absolute voltage error.
Vref(A) – VSSA
----------------------------------
256
1 LSB =
Fig.16 ADC conversion characteristics.
MGD774
3
FCLK2
(MHz)
2
1
0.25
0
2
2.7
3
3.6
4
V
(V)
DD
Fig.17 ADC clock (FCLK2) frequency range as a function of VDD
.
1996 Dec 11
64
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
21 AC CHARACTERISTICS
VSS = 0 V; Tamb = −40 to +85 °C; tCLK = CPU clock cycle time; no fast bus cycle (FBC = 0); no wait status; all voltages
with respect to VSS unless otherwise specified.
SYMBOL
PARAMETER
address valid to AS LOW
MIN.
0.5tCLK − 10
2.5tCLK − 10
0.5tCLK − 10
−5
TYP.
MAX.
UNIT
tAVSL
0.5tCLK + 2
2.5tCLK + 2
0.5tCLK
1
−
−
−
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSL
AS/DS LOW level
tSHAZ
tASCSL
tASCSH
tSLSH
AS HIGH to address invalid
AS/DS to CS LOW
AS/DS to CS HIGH
−5
1
AS LOW to DS LOW (write)
DS LOW level (write)
t
CLK − 15
tCLK
tCLK + 15
tDSL
1.5tCLK − 10
1.5tCLK + 2
tCLK
−
−
−
−
−
−
tAVRL
address valid to R/W LOW (write)
R/W LOW to DS LOW (write)
DATA-OUT valid to DS LOW (write)
AS HIGH to DATA-OUT invalid
HALT/RESET pulse width
AS LOW to DTACK LOW
AS HIGH to DTACK HIGH
DTACK LOW to DATA-IN (set-up time)
AS LOW to DATA-IN (set-up time)
AS HIGH to DATA invalid (hold time)
AS HIGH to R/W HIGH (write)
AS HIGH to A0 HIGH
tCLK - 5
tCLSL
t
CLK − 10
tCLK − 2
tDOSL
tSHDO
tHRPW
tASLDTA
tASHDTA
tDCLDI
tDATSETUP
tSHDI
0.5tCLK − 10
0.5tCLK − 1
0.5tCLK − 3
−
0.5tCLK − 10
24tCLK
−
1.5tCLK − 28
2.5tCLK − 25
tCLK
1.5t − 10
clk
−
2.5t
clk
−
tCLK + 10
2.5tCLK − 20
−
-
2.5tCLK − 25
0
0
tSHRH
tSHAH
tSHAWH
0.5tCLK − 5
0.5tCLK − 2
tCLK + 3
−
−
t
CLK − 10
tCLK + 10
0.5tCLK +10
AS HIGH to A0 (first byte of word cycle in 8-bit 0.5tCLK − 10
mode)
tSHW
LDS HIGH level before write
2.5tCLK − 5
2.5tCLK − 2
−
ns
0.7 V
DD
0.7 V
DD
handbook, halfpage
0.9 V
DD
test points
0.4 V
DD
MLA586
0.3 V
DD
0.3 V
DD
Fig.18 AC testing input waveform.
1996 Dec 11
65
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
I
MGC759
TL
handbook, 4 columns
500 µA
−I
L
I
IL
100 µA
V
1/2V
DD
DD
Fig.19 Input current.
22 8051 BUS TIMING
VDD = 2.7 V to 3.6 V; VSS = 0 V; Tamb = −40 to +85 °C; tCLK = CPU clock cycle time; all voltages with respect to VSS
unless otherwise specified. These AC parameters are not tested in production.
SYMBOL
tRR
tWW
tAL
PARAMETER
read pulse duration
MIN.
MAX.
UNIT
4.5tCLK − 10
4.5tCLK − 10
1.5tCLK − 20
4.5tCLK + 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
write pulse duration
address set-up time
address hold time
4.5tCLK + 10
−
tLA
t
CLK − 5
−
tRD
RD to valid data input
data float after read
ALE to valid data input
ALE to RD WR
−
3.5tCLK − 15
2tCLK − 10
6tCLK − 20
3tCLK + 20
−
tDFR
tLD
−
−
tLW
3tCLK − 20
6.5tCLK − 20
0.5tCLK − 10
tDW
tWD
tWHLH
data set-up time before WR
data hold time after WR
RD WR HIGH to ALE HIGH
−
t
CLK − 10
tCLK + 10
1996 Dec 11
66
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
23 TIMING DIAGRAMS
b
t
CLK
XTAL1
t
t
LW
WW
ALE
WR
t
AL
t
LA
t
DW
data out
A7 to A0
AD7 to AD0
A15 to A8
AD15 to AD8
t
MBG335
WD
Fig.20 Write to 8051-compatible peripheral circuits.
t
t
WHLH
LD
t
AL
ALE
RD
t
t
LW
RR
t
t
LA
RD
AD7 to AD0
AD7 to AD0
data in
t
MBG336
DFR
Fig.21 Read from 8051-compatible peripheral circuits.
67
1996 Dec 11
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
A7 to A1
A23 to A8
t
t
AVSL
SHAZ
t
SL
AS
t
SHAZ
t
t
ASCSL
ASCSH
CS
LDS
UDS
t
SHRH
R/W
HALT
RESET
t
HRPW
t
ASHDTA
DTACK
t
ASLDTA
t
SHDI
DATA IN
t
DCLDI
t
MGD775
DATSETUP
Fig.22 Read cycle timing 16-bit mode.
68
1996 Dec 11
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
A7 to A1
A23 to A8
t
t
AVSL
SHAZ
t
SL
AS
t
SHAZ
t
t
ASCSH
ASCSL
CS
t
SHW
t
t
DSL
SLSH
LDS
UDS
t
AVRL
t
CLSL
R/W
t
t
DOSL
SHDO
DATA OUT
HALT
RESET
t
HRPW
t
ASHDTA
DTACK
t
MGD776
ASLDTA
Fig.23 Write cycle timing 16-bit mode.
69
1996 Dec 11
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
A7 to A1
A23 to A8
t
AVSL
t
SL
AS/LDS
t
SHAZ
t
t
ASCSH
ASCSL
CS
t
t
SHAWH
SHAH
A0
R/W
t
t
DATSETUP
SHDI
DATA IN
t
ASHDTA
DTACK
t
ASLDTA
MGD777
(no fast bus cycle, FBC = 0)
Fig.24 Read cycle timing 8-bit mode.
70
1996 Dec 11
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
T1
T2
T3
T3
T1
T2
T3
T3
T1
S0 S1 S2 S3 SB SB S4 S5 S0 S1 S2 S3 SB SB S4 S5 S0 S1
CLK
t
CLK
A7 to A1
A23 to A8
t
AVSL
t
SL
AS
CS
t
SHAZ
t
t
ASCSH
ASCSL
t
SLSH
t
DSL
LDS
t
AVRL
t
t
SHAH
SHAWH
A0
t
CLSL
R/W
t
DOSL
t
SHDO
DATA OUT
t
ASHDTA
DTACK
t
ASLDTA
(no fast bus cycle, FBC = 0)
word transfer
MGD778
Fig.25 Write cycle timing 8-bit mode clock timing.
71
1996 Dec 11
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
24 CLOCK TIMING
Table 93 P90CL301BFH clock timing
VDD = 2.7 V.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
MHz
fXTAL1
tCLK
tCL
input frequency
cycle time
0
27
−
37
13
13
−
ns
ns
ns
ns
ns
pulse width LOW
pulse width HIGH
rise time
−
tCH
−
tCR
5
tCF
fall time
−
5
tCH
----------
tCLK
duty cycle
45
55
%
t
CLK
handbook, halfpage
0.8 V
t
CH
t
CL
DD
0.7 V
t
t
CR
CF
MBG341
Fig.26 P90CL301BFH clock timing.
1996 Dec 11
72
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
25 PIN STATES IN VARIOUS MODES
Table 94 describes the function, I/O, type and state in various modes - RESET, Power-down, HALT, ONCE and BPE
(Bus Pull-up Enable) - of the pins.
Table 94 Pin states in various modes
STATE(3)
PIN
FUNCTION
I/O(1) TYPE(2)
BPE ON
RESET PD HALT ONCE
A22 to A19
address bus
O
O
O
TSW4
TS4
Z
−
Z
H
Z
Z
Z
W
S
H
H
H
H
−
Z
Z
Z
−
W
W
W
W
W
W
W
−
PCS0 to PCS3 8051 chip-select
A18 to A1
AD7 to AD1
D7 to D0
D15 to D8
PL7 to PL0
AS
address bus
TSW4
Z
−
Z
Z
8051 data bus
I/O TSW4
I/O TSW4
I/O TSW4
I/O WP4
Z
−
lower 8-bits of data bus
upper 8-bits of data bus
port PL
Z
Z
−
Z
Z
Z
Z
W
Z
W
Z
address strobe
O
O
O
O
TS4
H
H
H
H
−
LDS
low data strobe
TS4
Z
Z
−
UDS
upper data strobe
address 0
TS4
Z
Z
W
W
W
−
A0
TSW4
Z
Z
AD0
8051 address/data 0
read write strobe
Test-ROM mode
I/O TSW4
Z
Z
R/W
O
I
TS4
UP2
N
Z
−
H
−
Z
Z
TROM
DTACK
RESET
−
−
−
data transfer acknowledgement
CPU peripheral reset
peripheral reset output
external power-on-reset
reset input; HALT input
peripheral reset; fault output
data bus size
I
−
−
−
−
−
I
N
−
−
−
−
−
OD OD8
L
Z
−
Z
Z
−
RESETIN
HALT
I
I
RS
N
−
−
−
−
−
−
−
−
−
OD OD8
L
Z
−
Z
Z
−
BSIZE
NMIACK
SP0
I
N
−
−
−
−
emulation NMIN acknowledgement
second port pin 0
UART1 receive
OD OD8
I/O WP2
I/O WP2
Z
W
−
Z
S
S
−
Z
Z
−
W
W
−
W
W
−
−
RX1
−
INT0
SP1
interrupt input 0
I
N
−
−
second port pin 1
UART1 transmit
I/O WP2
W
−
S
S
−
W
W
−
W
W
−
−
TX1
O
I
WP2
N
−
INT1
CLK0
SP2
interrupt input 1
−
−
external clock Timer 0
second port pin 2
UART0 receive
I
N
−
−
−
−
−
I/O WP2
W
−
S
−
W
−
W
−
−
RX0
I/O
N
N
N
−
INT2
CP2
interrupt input 2
I
I
−
−
−
−
−
timer capture 2
−
−
−
−
−
SP3
second port pin 3
UART0 transmit
I/O WP2
I/O WP2
W
−
S
S
W
W
W
W
−
TX0
−
1996 Dec 11
73
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
STATE(3)
BPE ON
PIN
FUNCTION
interrupt input 3
I/O(1) TYPE(2)
RESET PD HALT ONCE
INT3
CP3
SP4
INT4
CP4
SP5
INT5
CP5
SP6
INT6
CLK1
NMIN
SP7
P8
I
I
N
N
−
−
−
−
S
−
−
S
−
−
S
−
−
−
S
S
H
−
S
H
−
−
H
S
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
timer capture 3
second port pin 4
interrupt input 4
timer capture 4
second port pin 5
interrupt input 5
timer capture 5
second port pin 6
interrupt input 6
external clock Timer 1
non-maskable interrupt
second port pin 7
port PH pin 8
I/O WP2
W
−
W
−
W
−
I
I
N
N
−
−
−
I/O WP2
W
−
W
−
W
−
I
I
N
N
−
−
−
I/O WP2
W
−
W
−
W
−
I
I
I
N
N
N
−
−
−
−
−
−
I/O WP2
I/O WP2
W
W
−
W
W
W
−
W
W
W
−
PWM0
CP0
PWM output 0
O
I
WP2
N
timer capture 0
port PH pin 9
−
P9
I/O WP2
W
−
W
W
−
W
W
−
PWM1
CP1
PWM output 1
O
I
WP2
N
timer capture 1
external crystal input
chip-select 1 to 0
function code
−
XTAL1
CS1 to CS0
FC1 to FC0
I
XI
−
−
−
O
O
I
TS4
TS4
UP2
W
−
Z
Z
Z
Z
TSM1 to TSM0 test mode inputs multiplexed with
CS1N/0N for test purpose only.
−
−
−
CS2
chip-select 2
O
O
O
O
O
O
O
TS4
TS4
TS4
TS4
TS4
TS4
TS4
H
H
−
H
H
H
H
H
H
H
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
−
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
−
Z
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
CS3
chip-select 3
ALE
8051 address strobe
chip-select 4
CS4
H
−
RD
8051 read strobe
chip-select 5
CS5
H
−
WR
8051 write strobe
port PH pin 10
I2C-bus clock
P10
I/O OD8
OD OD8
I/O OD8
OD OD8
Z
SCL
−
Z
P11
port PH pin 11
I2C-bus data
Z
Z
SDA
CS6
−
Z
chip-select 6
O
O
O
I
TS4
TS4
TS4
UP2
−
H
S
H
−
A23
address pin 23
chip-select boot
ONCE mode
H
W
−
CSBT
ONCE
P15 to P12
port PH pins 15 to 12
I/O WP2
W
W
1996 Dec 11
74
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
STATE(3)
BPE ON
RESET PD HALT ONCE
PIN
FUNCTION
I/O(1) TYPE(2)
ADC3 to ADC0 analog inputs 3 to 0
I
I
AN
−
Z
W
−
−
Z
Z
−
−
S
−
−
R
Z
−
−
S
−
−
R
Z
−
−
S
−
−
−
−
−
−
−
−
Vref(A)
ADC reference voltage
fetch output
AREF
TS4
UP2
UP
FETCH(4)
EMUL(4)
NMINE(4)
CLKOUT(4)
PHALT(4)
O
I
emulation mode
emulation NMIN
emulation clock output
emulation HALT
I
−
O
I
S4
S
−
UP
Notes to the pin states in various modes
1. I = input; O = output; I/O = bidirectional.
2. See Table 95 for pin type description.
3. State of the pin in different modes RESET, PD (Power-down), HALT, ONCE and BPE (Bus Pull-up Enable).
a) − = not available.
b) Z = 3-state.
c) W = weak pull-up.
d) S = state logic 0 or logic 1.
e) R = resistive
f) H = HIGH state.
g) L = LOW state.
4. Emulation version only.
Table 95 Pin type description
MAXIMUM LOAD
(pF)
PIN TYPE
TS4
DESCRIPTION
3-state output, normal input
100
100
80
80
−
TSW4
WP2
WP4
N
3-state output, normal input with internal pull-up
weak pull-up output, normal input
weak pull-up output, normal input
normal input
UP
input with internal pull-up
input with internal pull-up
open drain
−
UP2
OD8
AN
−
400
−
analog input
S4
strong output
100
−
RS
Schmitt trigger input
AREF
analog reference input
−
1996 Dec 11
75
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
26 INSTRUCTION SET AND ADDRESSING MODES
The P90CL301BFH is completely code compatible with the 68000, which means that programs developed for the 68000
will run on the P90CL301BFH. This applies to both the source and object codes. The instruction set was designed to
minimize the number of mnemonics that the programmer has to remember. Following tables give an overview of the
instruction set and the different addressing modes.
Table 96 Instruction set; for Condition codes see notes 1 to 7
CONDITION
CODES
MNEMONIC
DESCRIPTION
OPERATION
X
N
Z
V
C
ABCD
Add Decimal with Extend
Add Binary
(Destination)10 + (Source)10 + X → Destination
(Destination) + (Source) → Destination
(Destination) + (Source) → Destination
(Destination) + Immediate Data → Destination
(Destination) + Immediate Data → Destination
(Destination) + (Source) + X → Destination
(Destination) (Source) → Destination
(Destination) Immediate Data → Destination
(Destination) Shifted by <count > → Destination
If CC then PC + d → PC
*
U
*
*
U
*
*
ADD
*
*
−
*
*
*
*
*
*
−
*
*
ADDA
ADDI
Add Address
−
*
−
*
−
*
−
*
Add Immediate
Add Quick
ADDQ
ADDX
AND
*
*
*
*
Add Extended
*
*
*
*
AND Logical
−
−
*
*
0
0
*
0
0
*
ANDI
AND Immediate
Arithmetic Shift
Branch Conditionally
Test a Bit and Change
*
ASL, ASR
BCC
*
−
−
−
−
−
−
−
−
BCHG
~(< bit number >) of Destination → Z
~(< bit number >) of Destination → < bit number >
of Destination
BCLR
BRA
Test a Bit and Clear
Branch Always
~(< bit number >) of Destination → Z
PC + d → PC
−
−
−
−
−
−
*
−
−
−
−
−
−
−
*
BSET
Test a Bit and Set
~(< bit number >) of Destination → Z
1 → < bit number > of Destination
PC → SP @ −; PC + d → PC
BSR
BTST
CHK
Branch to Subroutine
Test a Bit
−
−
−
−
−
*
−
*
−
−
U
−
−
U
~(< bit number >) of Destination → Z
If Dn < 0 or Dn > (< source >) then TRAP
Check Register against
Bounds
U
CLR
Clear an Operand
Compare
0 → Destination
−
−
−
−
−
−
0
*
1
*
0
*
0
*
CMP
(Destination) − (Source)
(Destination) − (Source)
(Destination) − Immediate Data
(Destination) − (Source)
CMPA
CMPI
CMPM
DBcc
Compare Address
Compare Immediate
Compare Memory
*
*
*
*
*
*
*
*
*
*
*
*
Test Condition,
Decrement & Branch
If (not CC) then Dn − 1 → Dn;
if Dn ≠ −1 then PC + d → PC
−
−
−
−
DIVS
DIVU
EOR
EORI
EXG
Signed Divide
(Destination) / (Source) → Destination
(Destination) / (Source) → Destination
(Destination) (Source) → Destination
(Destination) Immediate Data → Destination
Rx ↔ Ry
−
−
−
−
−
*
*
*
*
−
*
*
*
*
−
*
0
0
0
0
−
Unsigned Divide
*
Exclusive OR Logical
Exclusive OR Immediate
Exchange Register
0
0
−
1996 Dec 11
76
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
CONDITION
CODES
MNEMONIC
DESCRIPTION
OPERATION
X
−
−
−
−
−
*
N
*
Z
V
0
−
−
−
−
0
0
C
0
−
−
−
−
*
EXT
Sign Extend
(Destination) Sign − extended → Destination
Destination → PC
*
JMP
Jump
−
−
−
−
*
−
−
−
−
*
JSR
Jump to Subroutine
Load Effective Address
Link and Allocate
Logical Shift
PC → SP @ −; Destination → PC
Destination → An
LEA
LINK
An → SP @ −; SP → An; SP + d → SP
(Destination) Shifted by < count > → Destination
LSL, LSR
MOVE
Move Data from Source to (Source) → Destination
−
*
*
0
Destination
MOVE to CCR Move to Condition Code
(Source) → CCR
(Source) → SR
*
*
*
*
*
*
*
*
*
*
MOVE to SR
Move to the Status
Register
MOVE from SR Move from the Status
Register
SR → Destination
−
−
−
−
−
MOVE USP
MOVEA
MOVEM
MOVEP
MOVEQ
MULS
Move User Stack Pointer
Move Address
USP → An; An → USP
−
−
−
−
−
−
−
*
−
−
−
−
*
−
−
−
−
*
−
−
−
−
0
*
−
−
−
−
0
0
0
*
(Source) → Destination
Move Multiple Registers
Move Peripheral Data
Move Quick
Registers → Destination; (Source) → Registers
(Source) → Destination
Immediate Data → Destination
(Destination) * (Source) → Destination
(Destination) * (Source) → Destination
0 − (Destination)10 − X → Destination
Signed Multiply
*
*
MULU
Unsigned Multiply
*
*
*
NBCD
Negate Decimal with
Extend
U
*
U
NEG
Negate
0 − (Destination) → Destination
0 − (Destination) − X → Destination
−
*
*
*
*
*
NEGX
NOP
Negate with Extend
No Operation
*
*
*
*
*
−
−
−
−
−
−
−
*
−
*
−
*
−
0
0
0
−
−
0
0
*
−
0
0
0
−
−
*
NOT
Logical Complement
Inclusive OR Logical
Inclusive OR Immediate
Push Effective Address
Reset External Devices
Rotate (Without Extend)
Rotate with Extend
Return from Exception
~(Destination) → Destination
(Destination) (Source) → Destination
(Destination) Immediate Data → Destination
Destination → SP @ −
OR
*
*
ORI
*
*
PEA
−
−
*
−
−
*
RESET
ROL, ROR
ROXL, ROXR
RTE
−
(Destination) Rotated by < count > → Destination
(Destination) Rotated by < count > → Destination
SP @ + → SR; SP @ + → PC
SP @ + → CC; SP @ + → PC
*
*
*
*
*
*
*
RTR
Return and Restore
Condition Codes
*
*
*
*
*
RTS
Return from Subroutine
SP @ + → PC
−
−
−
−
−
SBCD
Subtract Decimal with
Extend
(Destination)10 − (Source)10 − X → Destination
*
U
*
U
*
SCC
Set According to Condition if CC then 1 → Destination; else 0 → Destination
−
−
−
−
−
1996 Dec 11
77
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
CONDITION
CODES
MNEMONIC
DESCRIPTION
OPERATION
X
N
Z
V
C
STOP
Load Status Register and Immediate Data → SR; STOP
*
*
*
*
*
Stop
SUB
Subtract Binary
Subtract Address
Subtract Immediate
Subtract Quick
(Destination) − (Source) → Destination
(Destination) − (Source) → Destination
(Destination) − Immediate Data → Destination
(Destination) − Immediate Data → Destination
(Destination) − (Source) − X → Destination
Register [ 31:16 ] ↔ Register [ 15:0 ]
(Destination) Tested → CC; 1 → [ 7 ] of Destination
PC → SSP @ −; SR → SSP @ −; (Vector) → PC
If V then TRAP
*
*
*
*
*
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS
−
*
−
*
−
*
−
*
−
*
*
*
*
*
*
Subtract with Extend
Swap Register Halves
Test and Set an Operand
Trap
*
*
*
*
*
−
−
−
−
−
−
*
*
0
0
−
−
0
−
0
0
−
−
0
−
*
*
TRAP
TRAPV
TST
−
−
*
−
−
*
Trap on Overflow
Test and Operand
Unlink
(Destination) Tested → CC
UNLK
An → SP; SP @ + → An
−
−
Notes
1. [ ] = bit number.
2. * = affected.
3. − = unaffected.
4. 0 = cleared.
5. 1 = set.
6. U = defined.
7. @ = location addressed by.
1996 Dec 11
78
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
26.1 Addressing modes
Table 97 Data addressing modes; see notes 1 to 14
MODE
GENERATION
Register Direct Addressing
Data Register Direct
EA = Dn
EA = An
Address Register Direct
Absolute Data Addressing
Absolute Short
Absolute Long
EA = (Next Words)
EA = (Next Two Words)
Program Counter Relative Addressing
Relative with Offset
EA = (PC) + d16
Relative with Index and Offset
EA = (PC) + (Xn) + d8
Register Indirect Addressing
Register Indirect
EA = (An)
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset
EA = (An), An ← An + N
An ← An − N, EA = (An)
EA = (An) + d16
EA = (An) + (Xn) + d8
Immediate Data Addressing
Immediate
DATA = Next Word(s)
Inherent Data
Quick Immediate
Implied Addressing
Implied Register
EA = SR, USP, SSP, PC, SP
Notes
1. EA = Effective Address.
2. An = Address Register.
3. Dn = Data Register.
4. Xn = Address or Data Register used as Index Register.
5. N = 1 for bytes; 2 for words; 4 for long words.
6. ← = Replaces.
7. SR = Status Register.
8. PC = Program Counter.
9. () = Contents of.
10. d8 = 8-bit offset (displacement).
11. d16 = 16-bit offset (displacement).
12. SP = Stack Pointer.
13. SSP = System Stack Pointer.
14. USP = User Stack Pointer.
1996 Dec 11
79
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
27 INSTRUCTION TIMING
In the Tables 98 to 110 the number of bus read and write cycles are shown in parentheses as (R/W). The timing is given
for operation in 16-bit mode. For operation in 8-bit mode the numbers shown in parentheses should be multiplied by a
factor 2.
Table 98 Effective address calculation times
INSTRUCTION
ADDRESSING MODE
Data or Address Register Direct
Address Register Indirect
BYTE; WORD
0 (0/0)
LONG
0 (0/0)
Rn
(An)
4 (1/0)
8 (2/0)
(An)+
Address Register Indirect postincrement
Address Register Indirect predecrement
Address Register Indirect Displacement
Address Register Indirect with Index
Absolute Short
4 (1/0)
8 (2/0)
−(An)
7 (1/0)
11 (2/0)
12 (3/0)
8 (3/0)
d(An)
11 (2/0)
14 (2/0)
8 (2/0)
d(An, Xi)
xxx.S
12 (3/0)
16 (4/0)
15 (3/0)
16 (4/0)
8 (2/0)
xxx.L
Absolute Long
12 (3/0)
11 (2/0)
14 (2/0)
4 (1/0)
d(PC)
d(PC, Xi)
#xxx
Program Counter with Displacement
Program Counter with Index
Immediate
Table 99 MOVE Byte and MOVE Word Instruction clock periods
INSTR.
Rn
Rn
(An)
(An)+
−(An)
d(An)
d(An, Xi)
xxx.S
xxx.L
7 (1/0)
11 (1/1)
15 (2/1)
15 (2/1)
18 (2/1)
22 (3/1)
25 (3/1)
19 (3/1)
23 (4/1)
22 (3/1)
25 (3/1)
15 (2/1)
11 (1/1)
15 (2/1)
15 (2/1)
18 (2/1)
22 (3/1)
25 (3/1)
19 (3/1)
23 (4/1)
22 (3/1)
25 (3/1)
15 (2/1)
14 (1/1)
18 (2/1)
18 (2/1)
22 (2/1)
25 (2/1)
28 (3/1)
22 (3/1)
26 (4/1)
25 (3/1)
28 (3/1)
18 (2/1)
18 (1/1)
22 (2/1)
22 (2/1)
25 (2/1)
29 (2/1)
32 (3/1)
26 (3/1)
30 (4/1)
29 (3/1)
32 (3/1)
22 (2/1)
21 (1/1)
25 (2/1)
25 (2/1)
28 (2/1)
32 (2/1)
35 (3/1)
29 (3/1)
33 (4/1)
32 (3/1)
35 (3/1)
25 (2/1)
15 (1/1)
19 (2/1)
19 (2/1)
22 (2/1)
26 (2/1)
29 (3/1)
23 (3/1)
27 (4/1)
26 (3/1)
29 (3/1)
19 (2/1)
19 (1/1)
23 (2/1)
23 (2/1)
26 (2/1)
30 (2/1)
33 (3/1)
27 (3/1)
31 (4/1)
30 (3/1)
33 (3/1)
23 (2/1)
(An)
11 (2/0)
11 (2/0)
14 (2/0)
18 (3/0)
21 (3/0)
15 (3/0)
19 (4/0)
18 (3/0)
21 (3/0)
11 (3/0)
(An)+
−(An)
d(An)
d(An, Xi)
xxx.S
xxx.L
d(PC)
d(PC, Xi)
#xxx
1996 Dec 11
80
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 100 MOVE long instruction clock periods
INSTR.
Rn
Rn
(An)
(An)+
−(An)
d(An)
d(An, Xi)
xxx.S
xxx.L
7 (1/0)
15 (2/0)
15 (3/0)
18 (3/0)
22 (4/0)
25 (4/0)
19 (4/0)
23 (5/0)
22 (4/0)
25 (4/0)
15 (3/0)
15 (1/2)
23 (2/2)
23 (3/2)
26 (3/2)
30 (4/2)
33 (4/2)
27 (4/2)
31 (5/2)
30 (4/2)
33 (4/2)
23 (3/2)
15 (1/2)
23 (2/2)
23 (3/2)
26 (3/2)
30 (4/2)
33 (4/2)
27 (4/2)
31 (5/2)
30 (4/2)
33 (4/2)
23 (3/2)
18 (1/2)
26 (2/2)
26 (3/2)
29 (3/2)
33 (4/2)
36 (4/2)
30 (4/2)
34 (5/2)
33 (4/2)
36 (4/2)
26 (3/2)
22 (2/2)
30 (4/2)
30 (4/2)
33 (4/2)
37 (5/2)
40 (5/2)
34 (5/2)
38 (6/2)
37 (5/2)
40 (5/2)
30 (4/2)
25 (2/2)
33 (4/2)
33 (4/2)
36 (4/2)
40 (5/2)
43 (5/2)
37 (5/2)
41 (6/2)
40 (5/2)
43 (5/2)
33 (4/2)
19 (2/2)
27 (4/2)
27 (4/2)
30 (4/2)
34 (5/2)
37 (5/2)
31 (5/2)
35 (6/2)
34 (5/2)
37 (5/2)
27 (4/2)
23 (3/2)
31 (5/2)
31 (5/2)
34 (5/2)
38 (6/2)
41 (6/2)
35 (6/2)
39 (7/2)
38 (6/2))
41 (6/2)
31 (5/2)
(An)
(An)+
−(An)
d(An)
d(An, Xi)
xxx.S
xxx.L
d(PC)
d(PC, Xi)
#xxx
Table 101 Standard Instruction clock periods
INSTRUCTION
ADD
SIZE
op<ea>, An
op<ea>, Dn
op<ea>, M
Byte, Word
Long
7
7
(1) (1/0)
(1) (1/0)
7(1) (1/0)
7(1) (1/0)
11(1) (1/1)
15(1) (1/2)
11(1) (1/1)
15(1) (1/2)
−
AND
CMP
Byte, Word
Long
−
7
7
(1) (1/0)
(1) (1/0)
−
Byte, Word
Long
7
7
(1) (1/0)
(1) (1/0)
7(1) (1/0)
7(1) (1/0)
−
DIVS
DIVU
EOR
−
−
−
−
−
−
−
−
−
169(1)(2) (1/0)
130(1)(3) (1/0)
−
−
−
Byte, Word
Long
7
(1) (1/0)
(1) (1/0)
11(1) (1/1)
15(1) (1/2)
−
7
MULS
MULU
OR
−
76(1)(3) (1/0)
76(1)(3) (1/0)
−
−
Byte, Word
Long
7
(1) (1/0)
(1) (1/0)
11(1) (1/1)
15(1) (1/2)
11(1) (1/1)
15(1) (1/2)
7
SUB
Byte, Word
Long
7(1) (1/0)
(1) (1/0)
7(1) (1/0)
7(1) (1/0)
7
Notes
1. Add effective address calculation time.
2. Indicates maximum value.
3. The duration of the instruction is constant.
1996 Dec 11
81
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 102 Immediate instruction clock periods
INSTRUCTION
ADDI
SIZE
op<#>, Dn
14 (2/0)
op<#>, An
op<#>, M
Byte, Word
Long
−
18(1) (2/1)
26(1) (3/2)
11(1) (1/1)
15(1) (1/2)
18(1) (2/1)
26(1) (3/2)
14 (2/0)
18 (3/0)
−
ADDQ
ANDI
CMPI
EORI
Byte, Word
Long
7
7
(1) (1/0)
(1) (1/0)
7(1) (1/0)
7(1) (1/0)
Byte, Word
Long
14 (2/0)
18 (3/0)
14 (2/0)
18 (3/0)
14 (2/0)
−
−
−
Byte, Word
Long
−
−
18 (3/0)
Byte, Word
Long
−
18(1) (2/1)
26(1) (3/2)
−
18(1) (2/1)
26(1) (3/2)
18(1) (2/1)
26(1) (3/2)
11(1) (1/1)
15(1) (1/2)
−
MOVEQ
ORI
Long
7 (1/0)
14 (2/0)
18 (3/0)
14 (2/0)
18 (3/0)
−
Byte, Word
Long
−
−
−
SUBI
Byte, Word
Long
−
SUBQ
Byte, Word
Long
7
(1) (1/0)
(1) (1/0)
7 (1/0)
7 (1/0)
7
Note
1. Add effective address calculation time.
Table 103 Shift/rotate instruction clock periods
INSTRUCTION
SIZE
Byte
REGISTER
MEMORY
ASR, ASL
13 + 3n (1/0)
13 + 3n (1/0)
13 + 3n (1/0)
13 + 3n (1/0)
13 + 3n (1/0)
13 + 3n (1/0)
13 + 3n (1/0)
13 + 3n (1/0)
14 (1/1)(1)
Word
−
LSR, LSL
Byte, Word
Long
14 (1/1)(1)
−
ROR, ROL
ROXR, ROXL
Byte, Word
Long
14 (1/1)(1)
−
14 (1/1)(1)
−
Byte, Word
Long
Note
1. Add effective address calculation time.
1996 Dec 11
82
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 104 Single operand instruction clock periods
INSTRUCTION
CLR
SIZE
REGISTER
MEMORY
Byte, Word
Long
7 (1/0)
7 (1/0)
10 (1/0)
7 (1/0)
7 (1/0)
7 (1/0)
7 (1/0)
7 (1/0)
7 (1/0)
13 (1/0)
13 (1/0)
10 (1/0)
7 (1/0)
7 (1/0)
11 (1/1)(1)(2)
15 (1/2)(1)(3)
14 (1/1)(1)
11 (1/1)(1)
15 (1/2)(1)
11 (1/1)(1)
15 (1/2)(1)
11 (1/1)(1)
15 (1/2)(1)
17 (1/1)(1)
14 (1/1)(1)
15 (2/1)(1)(2)
7 (1/0)(1)
NBCD
NEG
Byte, Word
Byte, Word
Long
NEGX
NOT
Scc
Byte, Word
Long
Byte, Word
Long
Byte, Word
Long
TAS
TST
Byte
Byte, Word
Long
7 (1/0)(1)
Notes
1. Add effective address calculation time.
2. Subtract one read cycle (−4(1/0)) from effective address calculation.
3. Subtract two read cycles (−8(2/0)) from effective address calculation.
Table 105 Bit manipulation instruction clock periods
DYNAMIC
STATIC
INSTRUCTION
BCHG
SIZE
Byte
REGISTER
MEMORY
REGISTER
MEMORY
−
10 (1/0)
−
14 (1/1)(1)
−
17 (2/0)
−
21 (2/1)(1)
Long
Byte
Long
Byte
Long
Byte
Long
−
−
BCLR
BSET
BTST
14 (1/1)(1)
21 (2/1)(1)
10 (1/0)
−
−
17 (2/0)
−
−
14 (1/1)(1)
21 (2/1)(1)
10 (1/0)
−
−
17 (2/0)
−
−
14 (2/0)(1)
−
7 (1/0)(1)
7 (1/0)
−
14 (2/0)
Note
1. Add effective address calculation time.
1996 Dec 11
83
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 106 Conditional instruction clock periods
TRAP OR BRANCH
INSTRUCTION
DISPLAY
Byte
TAKEN
NOT TAKEN
Bcc
13 (1/0)
14 (2/0)
13 (1/0)
14 (2/0)
21 (1/2)
22 (2/2)
−
13 (1/0)
14 (2/0)
−
Word
Byte
Word
Byte
Word
cc True
cc False
−
BRA
BSR
DBcc
−
−
−
14 (2/0)
17 (3/2)
19 (1/0)(1)
10 (1/0)
17 (2/0)
70 (3/4)(1)
55 (3/4)
CHK
TRAPV
−
Note
1. Add effective address calculation time.
Table 107 JMP, JSR, LEA, PEA, MOVEM instruction clock periods
n = number of registers to move.
INSTRUCTION SIZE
(An)
7 (1/0)
18 (1/2)
7 (1/0)
18 (1/2)
(An)+
−(An)
d(An) d(An, Xi) xxx.S
xxx.L
d(PC) d(PC, Xi)
JMP
JSR
LEA
PEA
−
−
−
−
−
−
−
−
−
14 (2/0) 17 (2/0)
25 (2/2) 28 (2/2)
14 (2/0) 17 (2/0)
25 (2/2) 28 (2/2)
14 (2/0) 18 (3/0) 14 (2/0) 17 (2/0)
25 (2/2) 28 (2/2) 25 (2/2) 28 (2/2)
14 (2/0) 18 (3/0) 14 (2/0) 17 (2/0)
25 (2/2) 28 (2/2) 25 (2/2) 28 (2/2)
−
−
−
−
MOVEM
Word 26+7n
26+7n
30+7n
33+7n
30+7n
34+7n
30+7n
33+7n
M → R
(2+n/0) (2+n/0)
(3+n/0) (3+n/0)
(3+n/0) (4+n/0) (3+n/0) (3+n/0)
Long 26+11n 26+11n
(2+2n/0) (2+2n/0)
−
30+11n 33+11n
(3+2n/0) (3+2n/0) (3+2n/0) (4+2n/0) (3+2n/0) (3+2n/0)
30+11n 34+11n 30+11n 33+11n
MOVEM
R → M
Word 23+7n
(2/n)
−
23+7n 27+7n
(2/n) (3/n)
30+7n
(3/n)
27+7n
(3/n)
31+7n
(4/n)
−
−
Long 23+11n
(2/2n)
−
23+11n 27+11n 30+11n
(2/2n) (3/2n) (3/2n)
27+11n 31+11n
(3/2n) (4/2n)
−
−
Table 108 Multi-precision Instruction Clock Periods
INSTRUCTION
SIZE
Byte, Word
Long
op Dn, An
7 (1/0)
7 (1/0)
−
op M, M
28 (3/1)
40 (5/2)
18 (3/0)
26 (5/0)
28 (3/1)
40 (5/2)
31 (3/1)
31 (3/1)
ADDX
CMPM
SUBX
Byte, Word
Long
−
Byte, Word
Long
7 (1/0)
7 (1/0)
10 (1/0)
10 (1/0)
ABCD
SBCD
Byte
Byte
1996 Dec 11
84
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 109 Miscellaneous Clock Periods
REGISTER TO
MEMORY
MEMORY TO
REGISTER
INSTRUCTION
SIZE
REGISTER
MEMORY
ANDI to CCR
ANDI to SR
EORI to CCR
EORI to SR
EXG
−
−
−
−
−
14 (2/0)
14 (2/0)
14 (2/0)
14 (2/0)
13 (2/0)
7 (1/0)
7 (1/0)
25 (2/2)
7 (1/0)
10 (1/0)
10 (1/0)
7 (1/0)
7 (1/0)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
EXT
Word
−
−
−
Long
−
−
−
LINK
−
−
−
−
MOVE from SR
MOVE to CCR
MOVE to SR
MOVE from USP
MOVE to USP
MOVEP
−
11 (1/1)(1)
10 (1/0)(1)
10 (1/0)(1)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Word
25 (2/2)
22 (4/0)
Long
−
39 (2/4)
36 (6/0)
NOP
−
−
−
−
−
7 (1/0)
14 (2/0)
14 (2/0)
154 (1/0)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ORI to CCR
ORI to SR
RESET
RTE short format
RTE long format
no rerun
with rerun
return of TAS
RTR
−
−
−
−
−
−
−
−
140 (18/0)
146 (18/0)
151 (19/0)
22 (4/0)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
RTS
15 (3/0)
STOP
17 (2/0)
SWAP
7 (1/0)
UNLK
15 (3/0)
Note
1. Add effective address calculation time.
1996 Dec 11
85
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 110 Exception processing clock periods
EXCEPTION
NUMBER OF CLOCK PERIODS
Address error
Bus error
158 (3/17)
158 (3/17)
65 (4/4)(1)
55 (3/4)
Interrupt
Illegal instruction
Privilege instruction
Trace
55 (3/4)
55 (3/4)
Trap
52 (3/4)
Divide by zero
RESET(3)
64 (3/4)(2)
43 (4/0)
Notes
1. The interrupt acknowledge bus cycle is assumed to take four external clock periods.
2. Add effective address calculation time.
3. Indicates the maximum time from when RESET and HALT are first sampled as negated to first instruction fetch.
1996 Dec 11
86
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
28 PACKAGE OUTLINE
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SOT315-1
y
X
A
60
41
Z
61
40
E
e
Q
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
L
pin 1 index
80
21
detail X
1
20
Z
D
v M
A
e
w M
b
p
D
B
H
v M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
4o
0o
0.16 1.5
0.04 1.3
0.25 0.18 12.1 12.1
0.13 0.12 11.9 11.9
14.15 14.15
13.85 13.85
0.7 0.70
0.3 0.58
1.45 1.45
1.05 1.05
mm
1.6
0.25
0.5
1.0
0.2 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-03-24
95-12-19
SOT315-1
1996 Dec 11
87
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
If wave soldering cannot be avoided, the following
conditions must be observed:
29 SOLDERING
29.1 Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
29.2 Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
29.4 Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
29.3 Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1996 Dec 11
88
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
30 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
31 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
32 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Dec 11
89
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
NOTES
1996 Dec 11
90
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
NOTES
1996 Dec 11
91
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© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
647021/50/01/pp92
Date of release: 1996 Dec 11
Document order number: 9397 750 01261
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