PC33996EKR2 [NXP]
1.2A SIPO BASED PRPHL DRVR, PDSO32, LEAD FREE, PLASTIC, SOIC-32;
| 型号： | PC33996EKR2 |
| 厂家： | 
NXP |
| 描述： | 1.2A SIPO BASED PRPHL DRVR, PDSO32, LEAD FREE, PLASTIC, SOIC-32 驱动 CD 光电二极管 接口集成电路 驱动器 |
| 文件： | 总16页 (文件大小：626K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Document order number: MC33996
Rev 1.0, 01/2004
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Preliminary Information
33996
16-Output Switch with SPI Control
The 33996 is a 16-output low-side switch with a 24-bit serial input control.
It is designed for a variety of applications including inductive, incandescent,
and LED loads. The Serial Peripheral Interface (SPI) provides both input
control and diagnostic readout. A Pulse Width Modulation (PWM) control input
is provided for pulse width modulation of multiple outputs at the same duty
cycle. A dedicated reset input provides the ability to clear all internal registers
and turn all outputs off.
DUAL OCTAL SERIAL SWITCH
WITH SERIAL PERIPHERAL
INTERFACE I/O
The 33996 directly interfaces with microcontrollers and is compatible with
both 3.3 V and 5.0 V CMOS logic levels. The 33996, in effect, serves as a bus
expander and buffer with fault management features that reduce the MCU’s
fault management burden.
Features
• Designed to Operate 5.0 V < VPWR < 27 V
• 24-Bit SPI for Control and Fault Reporting, 3.3 V/5.0 V Compatible
• Outputs Are Current Limited (0.9 A to 2.5 A) to Drive Incandescent
Lamps
• Output Voltage Clamp of +50 V During Inductive Switching
• On/Off Control of Open Load Detect Current (LED Application)
• VPWR Standby Current < 10 µA
EK (Pb-FREE) SUFFIX
CASE 1454-01
32-LEAD SOICW EXPOSED PAD
ORDERING INFORMATION
Temperature
• RDS(ON) of 0.55 Ω at 25°C Typical
Device
Package
Range (T )
A
• Independent Overtemperature Protection
• Output Selectable for PWM Control
PC33996EK/R2
-40°C to 125°C
32 SOICW-EP
• Output ON Short-to-VBAT and OFF Short-to-Ground/Open Detection
• 32-Pin Exposed Pad Package for Thermal Performance
• Pb-Free Packaging Designated by Suffix Code EK
33996 Simplified Application Diagram
V
V
BAT
3.3 V/5.0 V
PWR
33996
VDD
SOPWR
VPWR
MCU
SCLK
CS
MISO
MOSI
PWM
RST
SCLK
CS
SI
SO
PWM
RST
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
Solenoid/Relay
LED
Lamp
GND
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
For More Information On This Product,
© Motorola, Inc. 2004
Go to: www.freescale.com
Freescale Semiconductor, Inc.
VPWR
6
OUT0
1
Overvoltage
Detect
Voltage
VDD
Bias
VDD
Regulator
50 V
GE
OT
SF
OF
OVD
VDD
RB
SFPDB
SFL
SCLK
CSB
SI
SO
CSI
PWM
30
Gate
Control
OUT1–OUT15:
10 µA
25 µA
2, 4, 5, 12, 13,
15, 16, 17, 18,
20, 21, 28, 29,
31, 32
To Gates
1to15
RST
27
VRef
10 µA
CS
14
Open
Input
Load
Detect
Enable
ILimit
Buffers
SCLK
11
RS
50 µA
10 µA
10 µA
CSBI
Short and
Open
SI
19
GND Pins:
7–10
SPI
Load
Interface
Logic
Detect
23–26
Serial D/O
Line Driver
SO
22
Overtemperature
Detect
SOPWR
3
From Detectors 1to15
Figure 1. 33996 Simplified Internal Block Diagram
33996
2
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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OUT0
OUT1
SOPWR
OUT2
OUT3
VPWR
GND
OUT15
OUT14
PWM
OUT13
OUT12
RST
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
GND
GND
9
GND
GND
SCLK
OUT4
OUT5
CS
GND
10
11
12
13
14
15
16
GND
SO
OUT11
OUT10
SI
OUT6
OUT7
OUT9
OUT8
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Formal Name
Definition
1, 2, 4, 5, 12, 13, OUT0–OUT15
15–18, 20, 21,
28, 29, 31, 32
Output 0–Output 15
Open drain output pin.
3
SOPWR
SOPWR Supply Pin
Power supply pin to the SO output driver.
6
VPWR
GND
Battery Input
Ground
Battery supply input pin.
7–10, 23–26
Ground for logic, analog, and power output devices.
System Clock for internal shift registers of the 33996.
SPI control chip select input pin from the MCU to the 33996.
Serial data input pin to the 33996.
11
14
19
22
27
30
SCLK
System Clock
Chip Select
Serial Input
Serial Output
Reset
CS
SI
SO
Serial data output pin.
RST
Active low reset input pin.
PWM
PWM Control
PWM control input pin. Supports PWM on any combination of outputs.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33996
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
VPWR Supply Voltage (Note 1)
VPWR
-1.5 to 50
V
SO Output Driver Power Supply Voltage (Note 1)
SPI Interface Logic Input Voltage (CS, PWM, SI, SO, SCLK, RST) (Note 1)
Output Drain Voltage
SOPWR
VIN
-0.3 to 7.0
-0.3 to 7.0
-0.3 to 45
6.0
V
V
VD
V
MHz
mJ
V
fSPI
Frequency of SPI Operation (Note 2)
Output Clamp Energy (Note 3)
ECLAMP
50
ESD Voltage (Note 4)
VESD1
VESD2
±2000
±200
Human Body Model (Note 5)
Machine Model (Note 6)
Storage Temperature
TSTG
TC
-50 to 150
-40 to 125
-40 to 150
1.5
°C
°C
°C
W
Operating Case Temperature
Operating Junction Temperature
Power Dissipation (TA = 25°C) (Note 7)
TJ
PD
Lead Soldering Temperature (Note 8)
TSOLDER
260
°C
Thermal Resistance
°C/W
R
JA
θ
Junction-to-Ambient (Note 9)
Junction- to-Lead (Note 10)
Junction-to-Flag
75
8.0
1.2
R
R
JL
θ
JC
θ
Notes
1. Exceeding these limits may cause malfunction or permanent damage to the device.
2. This parameter is guaranteed by design but not production tested.
3. Maximum output clamp energy capability at 150°C junction temperature using single nonrepetitive pulse method.
4. ESD data available upon request.
5. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
6. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
7. Maximum power dissipation with no heat sink used.
8. Lead soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
9. Tested per JEDEC test JESD52-2 (single-layer PWB).
10. Tested per JEDEC test JESD51-8 (two-layer PWB).
33996
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 3.1 V ≤ SOPWR ≤ 5.5 V, 5.0 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted.
Where applicable, typical values noted reflect the parameter ‘s approximate value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER SUPPLY
V
V
Supply Voltage Range
Fully Operational
PWR(FO)
5.0
–
27
I
mA
Supply Current
PWR(ON)
–
4.0
8.0
10
All Outputs ON, IOUT = 0.3 A
I
-10
1.0
µA
Sleep State Supply Current at RST ≤ 0.2 SO
and/or
PWR(SS)
PWR
SO
≤ 0.5 V
PWR
Overvoltage Shutdown
VOV
27.5
0.8
–
31.5
1.4
3.2
–
35
2.3
3.5
5.5
500
10
V
V
Overvoltage Shutdown Hysteresis
VPWR Undervoltage Shutdown
SPI Interface Logic Supply Voltage
VOV(HYS)
V
V
PWR(UV)
SOPWR
3.1
100
-10
2.0
V
ISOPWR(RSTH)
ISOPWR(RSTL)
SOPWR(UNVOL)
–
µA
µA
V
SPI Interface Logic Supply Current (RST Pin High)
SPI Interface Logic Supply Current (RST Pin Low)
SPI Interface Logic Supply Undervoltage Lockout Threshold
–
2.5
3.0
POWER OUTPUT
Drain-to-Source ON Resistance (IOUT = 0.35 A, V
= 13 V)
RDS(ON)
Ω
PWR
–
–
–
0.75
0.55
0.45
1.2
1.2
1.2
T = 125°C
J
T = 25°C
J
T = -40°C
J
Output Self-Limiting Current
Outputs Programmed ON
IOUT(
lim
A
V
)
0.9
2.5
1.2
3.0
2.5
3.5
Output Fault Detect Threshold (Note 11)
Outputs Programmed OFF
VOUTth(F)
Output Off Open Load Detect Current (Note 12)
µA
Outputs Programmed OFF (V
Outputs Programmed OFF (V
= 5.0 V)
IOCO(5)
25
30
50
50
100
100
PWR
PWR
= 13 V, 18 V)
IOCO(13,18)
Output Clamp Voltage
VCL
V
IOUT = 20 ≤ mA
45
50
55
10
Output Leakage Current
IOUT(
lkg
µA
)
SOPWR ≤ 2.0 V
-10
2.0
TLIM
TLIM(
155
5.0
165
10
180
20
°C
°C
Overtemperature Shutdown (Outputs OFF) (Note 13)
Overtemperature Shutdown Hysteresis (Note 13)
Notes
)
hys
11. Output Fault Detect Thresholds with outputs programmed OFF. Output Fault Detect Thresholds are the same for output open and shorts.
12. Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an open
load condition when the specific output is commanded to be OFF.
13. This parameter is guaranteed by design but not production tested.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33996
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 3.1 V ≤ SOPWR ≤ 5.5 V, 5.0 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted.
Where applicable, typical values noted reflect the parameter ‘s approximate value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE
Input Logic Voltage Thresholds (Note 14)
VINLOGIC
0.8
–
2.2
V
V
V
SO
/2-0.7
SO
/2
SO
/ 2+0.7
PWR
Input Logic Voltage Thresholds for RST
INRST
PWR
PWR
SI Pull-Down Current
SI = 5.0 V
ISI
µA
2.0
-30
2.0
10
30
-2.0
30
ICS
µA
µA
µA
CS Pull-Up Current
CS = 0 V
-10
SCLK Pull-Down Current
SCLK = 5.0 V
ISCLK
10
RST Pull-Down Current
RST = 5.0 V
IRST
5.0
2.0
25
10
50
30
PWM Pull-Down Current
IPWM
VSOH
µA
SO High State Output Voltage
V
I
SO-high = -1.6 mA
SO Low State Output Voltage
SO-low = 1.6 mA
SOPWR - 0.4
SOPWR -0.2
–
VSOL
V
I
–
–
–
–
0.4
20
CIN
pF
Input Capacitance on SCLK, SI, Tri-State SO, RST (Note 15)
Notes
14. Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, and PWM.
15. This parameter is guaranteed by design but not production tested.
33996
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions of 3.1 V ≤ SOPWR ≤ 5.5 V, 5.0 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Slew Rate
SR
V/µs
RL = 56 Ω (Note 16)
1.0
1.0
1.0
100
100
–
2.0
15
15
–
10
50
Output Turn ON Delay Time (Note 17)
Output Turn OFF Delay Time (Note 17)
Output ON Short Fault Disable Report Delay (Note 18)
Output OFF Open Fault Delay Time (Note 18)
Output PWM Frequency
µs
µs
t
t
DLY(on)
DLY(off)
50
450
450
2.0
µs
t
t
DLY(short)
DLY
–
µs
(open)
t
–
kHz
FREQ
DIGITAL INTERFACE TIMING
Required Low State Duration on VPWR for Reset
tRST
µs
–
–
10
V
PWR ≤ 0.2 V (Note 19)
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
ns
ns
ns
ns
t
LEAD
100
50
–
–
–
–
–
–
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
t
LAG
SI to Falling Edge of SCLK
Required Setup Time
t
SI(su)
16
Falling Edge of SCLK to SI
Required Hold Time
t
t
SI(hold)
20
–
–
–
–
t
5.0
ns
ns
ns
ns
ns
SI, CS, SCLK Signal Rise Time (Note 20)
R(SI)
t
–
–
–
–
5.0
–
–
SI, CS, SCLK Signal Fall Time (Note 20)
F(SI)
t
50
50
80
Time from Falling Edge of CS to SO Low Impedance (Note 21)
Time from Rising Edge of CS to SO High Impedance (Note 22)
Time from Rising Edge of SCLK to SO Data Valid (Note 23)
SO(en)
SO(dis)
–
t
25
VALID
Notes
16. Output slew rate measured across a 56 Ω resistive load.
17. Output turn ON and OFF delay time measured from 50% rising edge of CS to 90% and 10% of initial voltage.
18. Duration of fault before fault bit is set. Duration between access times must be greater than 450 µs to read faults.
19. This parameter is guaranteed by design; however, it is not production tested.
20. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
21. Time required for valid output status data to be available on SO pin.
22. Time required for output states data to be terminated at SO pin.
23. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33996
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Timing Diagram
CS
0.2 VDD
t
t
LAG
LEAD
0.7 VDD
0.2 VDD
SCLK
SI
tSI(su)
tSI(hold)
0.7 VDD
0.2 VDD
MSB IN
tSO(dis
tSO(en)
t
)
VALID
0.7 VDD
0.2 VDD
Don t
'
SO
VTri-State
LSB OUT
MSB OUT
Care
Figure 2. SPI Timing Characteristics
33996
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33996 is designed and developed for automotive and
and independent DMOS power output transistors. Many
benefits are realized as a direct result of using this mixed
technology. A simplified internal block diagram of the 33996 is
shown in Figure 1, page 2.
industrial applications. It is a 16-output power switch having
24-bit serial control. The 33996 incorporates SMARTMOS
technology having CMOS logic, bipolar/MOS analog circuitry,
MCU INTERFACE DESCRIPTION
In operation the 33996 functions as a 16-output serial switch
serving as a microcontroller (MCU) bus expander and buffer
with fault management and fault reporting features. In doing so,
the device directly relieves the MCU of the fault management
functions.
The 33996 may be controlled and provide diagnostics using
a daisy chain configuration or in parallel mode. Figure 4 shows
the daisy chain configuration using the 33996. Data from the
MCU is clocked daisy chain through each device while the Chip
Select bit (CS) is commanded low by the MCU. During each
clock cycle, output status from the daisy-chained 33996s is
being transferred back to the MCU via the Master In Slave Out
(MISO) line. On rising edge of CS, data stored in the input
register is transferred to the output driver. Daisy chain control of
the 33996 requires 24 bits per device.
The 33996 directly interfaces to an MCU and operates at
system clock serial frequencies up to 6.0 MHz using a Serial
Peripheral Interface (SPI) for control and diagnostic readout.
Figure 3 shows the basic SPI configuration between an MCU
and one 33996.
Multiple 33996 devices can be controlled in a parallel input
fashion using the SPI. Figure 5, page 10, illustrates potentially
32 loads being controlled by two dedicated parallel MCU ports
used for chip select.
MC68HCXX
Microcontroller
33996
MOSI
MISO
SI
MC68HCXX
Microcontroller
Shift Register
24-Bit Shift Register
33996
SO
MOSI
SI
Shift Register
SCLK
MISO
SO
Receive
Buffer
SCLK
SCLK
To Logic
RST
CS
PWM
CS
PWM
PWM1
PWM2
Parallel
Ports
Parallel
Ports
RST
33996
Figure 3. 33996 SPI Interface with Microcontroller
SI
All inputs are compatible with 3.3 V/5.0 V CMOS logic levels
and incorporate positive logic. An input that is programmed to a
logic low state (< 0.8 V) will have the corresponding output
OFF. Conversely, an input programmed to a logic high state
(> 2.2 V) will have the output being controlled ON. Diagnostics
is treated in a similar manner—outputs with a fault will feedback
(via SO) to the MCU a logic [1], while normal operating outputs
will provide a logic [0].
SO
SCLK
CS
PWM
RST
Figure 4. 33996 SPI System Daisy Chain
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33996
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MC68HCXX
Microcontroller
33996
MOSI
SI
Shift Register
MISO
SCLK
SO
SCLK
CS
PWM1
PWM2
PWM
Parallel
Ports
RST
SI
33996
SO
SCLK
CS
PWM
RST
Figure 5. Parallel Inputs SPI Control
FUNCTIONAL PIN DESCRIPTION
device is not accessed (CS in logic high state). When the CS is
Chip Select (CS) Pin
in a logic high state, any signal at the SCLK and SI pins is
ignored and the SO is tri-stated (high impedance).
The system MCU selects the 33996 to be communicated
with through the use of the Chip Select (CS) pin. When the CS
pin is in a logic low state, data can be transferred from the MCU
to the 33996 and vise versa. Clocked-in data from the MCU is
transferred from the 33996 Shift register and latched into the
power outputs on the rising edge of the CS signal. On the falling
edge of the CS signal, output fault status information is
transferred from the Power Outputs Status register into the
device’s SO Shift register. The SO pin output driver is enabled
when CS is low, allowing information to be transferred from the
33996 to the MCU. To avoid any spurious data, it is essential
the high-to-low transition of the CS signal occur only when
SCLK is in a logic low state.
Serial Input (SI) Pin
The Serial Input (SI) pin is used to enter one of seven serial
instructions into the 33996. SI SPI bits are latched into the Input
Shift register on each falling edge of SCLK. The Shift register is
full after 24 bits of information are entered. The 33996 operates
on the command word on the rising edge of CS. To preserve
data integrity, exercise care not to transition SI as SCLK
transitions from high to low state (see Figure 2, page 8).
Serial Output (SO) Pin
The Serial Output (SO) pin transfers fault status data from
the 33996 to the MCU. The SO pin remains tri-state until the CS
pin transitions to a logic low state. All faults on the 33996 are
reported to the MCU as logic [1]. Conversely, normal operating
outputs with nonfaulted loads are reported as logic [0]. On the
falling edge of the CS signal, output fault status information is
transferred from the Power Outputs Status register into the
device’s SO Shift register. The first eight positive transitions of
SCLK will provide Any Fault (bit 23), Overvoltage Fault (bit 22),
followed by six logic [0]s (bits 21 to 16). The next 16 successive
positive transitions of SCLK provides fault status for output 15
System Clock (SCLK) Pin
The System Clock (SCLK) pin clocks the Internal Shift
registers of the 33996. The Serial Input (SI) pin accepts data
into the Input Shift register on the falling edge of the SCLK
signal, while the Serial Output (SO) pin shifts data information
out of the Shift register on the rising edge of the SCLK signal.
False clocking of the Shift register must be avoided, ensuring
validity of data. It is essential that the SCLK pin be in a logic low
state whenever the CS pin makes any transition. For this
reason, it is recommended, though not necessary, that the
SCLK pin is commanded to a low logic state as long as the
33996
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to output 0. Refer to the LOGIC OPERATION section (below)
Battery Input (VPWR) Pin
for more information. The SI/SO shifting of data follows a first-
in, first-out protocol, with both input and output words
transferring the Most Significant Bit (MSB) first.
The VPWR pin is used as the input power source for the
33996. The voltage on VPWR is monitored for overvoltage
protection and shutdown. An overvoltage condition (> 50 µs) on
the VPWR pin will cause the 33996 to shut down all outputs
until the overvoltage condition is removed. Upon return to
normal input voltage, the outputs will respond as programmed
by the overvoltage bit in the Global Shutdown/Retry Control
register. The overvoltage threshold on the VPWR pin is
specified as 27.5 V to 35 V with 1.4 V typical hysteresis.
Following an overvoltage shutdown of output drivers, the
Overvoltage Fault and the Any Fault bits in the SO bit stream
will be logic [1].
SO Output Driver Power Supply (SOPWR) Pin
The SOPWR pin is used to supply power to the 33996 SO
output driver and Power-ON Reset (POR) circuit. To achieve
low standby current on VPWR supply, power must be removed
from the SOPWR pin. The 33996 will be in reset with all drivers
OFF when SOPWR is below 2.5 V. The 33996 does not detect
overvoltage on the SOPWR supply pin.
Output/Input (OUT0–OUT15) Pins
PWM Pin
These pins are low-side output switches controlling the load.
The PWM Control pin is provided to support PWM of any
combination of outputs. The LOGIC OPERATION section
describes the logic for PWM control.
Reset (RST) Pin
The Reset (RST) pin is the active low reset input pin used to
turn OFF all outputs, thereby clearing all internal registers.
LOGIC OPERATION
The 33996 message set consists of seven messages as
shown in Table 1. Bits 23 through18 determine the specific
command and bits 15 through 0 determine how a specific
output will operate. The 33996 operates on the command word
on the rising edge of CS.
Introduction
The 33996 provides flexible control of 16 low-side driver
outputs. The device allows PWM and ON/OFF control through
the use of several 24-bit input command words. This section
describes the logic operation and command registers of the
33996.
Note Upon Power-ON Reset all bits are defined as shown in
Table 1.
Table 1. SPI Control Commands
MSB
Bits
LSB
Commands
23
22
0
21
0
20
0
19
0
18
0
17
X
16
X
15
0
14
0
13
12
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
ON/OFF Control
0
0
0
0
0
0
0
0=off, 1=on
Open Load Current Enable
0=disable, 1=enable
0
0
0
0
0
0
0
1
1
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Global Shutdown/Retry
Control
Over-
voltage
0
Thermal
Bit 0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0=shutdown, 1=retry
SFPD Control
0
0
0
0
0
0
0
1
1
0
1
0
X
X
X
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1=therm only, 0=V
DS
PWM Enable
0=SPI only, 1=PWM
AND/OR Control
0=PWM pin AND with SPI
1=PWM pin OR with SPI
0
0
0
0
0
1
0
1
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
0
1
0
1
0
0
0
X
0
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SO Response
Any Over-
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
15 14 13 12 11 10
0=No Fault, 1=Fault
Fault voltage
9
8
7
6
5
4
3
2
1
0
the remaining 16 bits are used to turn ON or OFF the specific
output driver.
ON/Off Control Register
To program the 16 outputs of the 33996 ON or OFF, a 24-bit
serial stream of data is entered into the SI pin. The first 8 bits of
the control word are used to identify the on/off command and
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33996
11
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Open Load Current Enable Control Register
AND/OR Control Register
The Open Load Current Enable Control register is provided
to enable or disable the 50 µA open load detect pull-down
current. This feature allows the device to be used in LED
applications. Power-ON Reset (POR) or the RST pin or the
RESET command disables the 50 µA pull-down current. No
open load fault will be reported with the pull-down current
disabled. For open load to be active, the user must program the
Open Load Current Enable Control register with logic [1].
The AND/OR Control register describes the condition by
which the PWM pin controls the output driver. A logic [0] in the
AND/OR Control register will AND the PWM input pin with the
ON/OFF Control register bit. Likewise, a logic [1] in the AND/
OR Control register will OR the PWM input pin with the ON/OFF
Control register bit (see Figure 6). For the AND/OR control to
occur, the PWM Enable bit must be set to logic [1].
On/Off Control Bit
Global Shutdown/Retry Control Register
PWM Enable Bit
On/Off Control Bit
To Gate
The Global Shutdown/Retry Control register allows the user
to select the global fault strategy for the outputs. The
Control
PWM IN
AND/OR Control Bit
overvoltage control bit (bit 16) sets the operation of the outputs
when returning from overvoltage. Setting the overvoltage bit to
logic [0] will force all outputs to remain off when VPWR returns to
On/Off control Bit
PWM IN
normal level. Setting the overvoltage bit to logic [1] will
command outputs to resume their previous state when VPWR
returns to normal level. Bit 17 is the global thermal bit. When
bit 17 is set to logic [0], all outputs will shut down when thermal
limit is reached and remain off even after cooled. With bit 17 set
to logic [1], all outputs will shut down when thermal limit is
reached and will retry when cooled.
Figure 6. PWM Control Logic Diagram
Serial Output (SO) Response Register
Fault reporting is accomplished through the SPI interface. All
logic [1s] received by the MCU via the SO pin indicate fault. All
logic [0s] received by the MCU via the SO pin indicate no fault.
All fault bits are cleared on the positive edge of CS. SO bits 15
to 0 represent the fault status of outputs 15 to 0. SO bits 21 to
16 will always return logic [0]. Bit 22 provides overvoltage
condition status and bit 23 is set when any fault is present in the
IC. The timing between two write words must be greater than
450 µs to allow adequate time to sense and report the proper
fault status.
Short Fault Protect Disable (SFPD) Control Register
All outputs contain current limit and thermal shutdown with
programmable retry. The SFPD control bits are used for fast
shutdown of the output when overcurrent condition is detected
but thermal shutdown has not been achieved.
The SFPD Control register allows the user to select specific
outputs for incandescent lamp loads and specific outputs for
inductive loads. By programming the specific SFPD bit as
logic [1], output will rely on overtemperature shutdown only.
Programming the specific SFPD bit as logic [0] will shut down
the output after 100 µs to 450 µs during turn on into short
circuit. The decision for shutdown is based on output drain-to-
source voltage (VDS) > 2.7 V. This feature is designed to
RESET Command
The RESET command turns all outputs OFF and sets all
internal registers to their Power-ON Reset state (refer to
Table 1).
provide protection to loads that experience more than expected
currents and require fast shutdown. The 33996 is designed to
operate in both modes with full device protection.
PWM Enable Register
The PWM Enable register determines the outputs that are
PWM controlled. The first 8 bits of the 24 bit SPI message word
are used to identify the PWM enable command, and the
remaining 16 bits are used to enable and disable the PWM of
the output drivers.
A logic [0] in the PWM Enable register will disable the
outputs as PWM. A logic [1] in the PWM Enable register will set
the specific output as a PWM. Power-ON Reset or the RST pin
or the RESET command will set the PWM Enable register to
logic [0].
33996
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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FAULT OPERATION
On each SPI communication, a 24-bit command word is sent
Command Register Definition:
0 = Output Command Off
1 = Output Command On
to the 33996 and 24-bit fault word is received from the 33996.
The Most Significant Bit (MSB) is sent and received first.
SO Definition:
0 = No fault
1 = Fault
Table 2. Fault Operation
Serial Output (SO) Pins Reports
Overtemperature
Fault reported by Serial Output (SO) pin.
SO pin reports short to battery/supply or overcurrent condition.
Not reported.
Overcurrent
Output “ON’ Open Load Fault
Output “OFF’” Open Load Fault
Device Shutdowns
Overvoltage
SO pin reports output “OFF’” open load condition.
Total device shutdown at VPWR = 27.5 V to 35 V. Resumes normal operation with proper voltage. Upon
recovery all outputs assume previous state or OFF based on the Overvoltage bit in the Global Shutdown/
Retry Control Register.
Only the output experiencing an overtemperature fault shuts down. Output may auto-retry or remain off
according to the control bits in the Global Shutdown/Retry Control Register.
Overtemperature
Overcurrent
Output will remain in current limit 0.9 A to 2.5 A until thermal limit is reached. When thermal limit is reached,
device will enter overtemperature shutdown. Output will operate as programmed in the Global Shutdown/
Retry Control Register. Fault flag in SO Response word will be set.
APPLICATIONS
Care must be taken when paralleling outputs for inductive
loads. The Output Voltage Clamp of the output drivers may not
Power Consumption
The 33996 has been designed with one Sleep mode and one
match. One MOSFET output must be capable of the inductive
energy from the load turn OFF.
Operational mode. In Sleep mode (SOPWR ≤ 2.0 V) the current
consumed by the VPWR pin is less than 10 µA. To place the
33996 in Sleep mode, turn all outputs OFF and remove power
from the SOPWR pin. During normal operation, 500 µA is
drawn from the SOPWR supply and 8.0 mA from the VPWR
supply.
SPI Integrity Check
Checking the integrity of the SPI communication is
recommended upon initial power-up of the SOPWR pin. After
initial system start-up or reset, the MCU writes one 48-bit
pattern to the 33996.
Paralleling of Outputs
The first 24 bits read by the MCU is the fault status of the
outputs, while the second 24 bits is the first bit pattern sent. By
the MCU receiving the same bit pattern it sent, bus integrity is
confirmed. Please note the second 24 bits the MCU sends to
the 33996 are the command bits and will program registers or
activate outputs on the rising edge of CS.
Using MOSFETs as output switches allows the connection of
any combination of outputs together. The RDS(ON) of MOSFETs
has an inherent positive temperature coefficient, providing
balanced current sharing between outputs without destructive
operation. This mode of operation may be desirable in the event
the application requires lower power dissipation or the added
capability of switching higher currents. Performance of parallel
operation results in a corresponding decrease in RDS(ON), while
Output OFF Open Load Fault
the Output Current Limit increases correspondingly. Output
OFF Open Load Detect current may increase based on how the
Output OFF Open Load Detect is programmed. Paralleling
outputs from two or more different IC devices is possible but not
recommended.
An Output OFF Open Load Fault is the detection and
reporting of an open load when the corresponding output is
disabled (input bit programmed to a logic low state). The Output
OFF Open Load Fault is detected by comparing the drain-to-
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33996
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source voltage of the specific MOSFET output to an internally
Output Voltage Clamp
generated reference. Each output has one dedicated
comparator for this purpose.
Each output of the 33996 incorporates an internal voltage
clamp to provide fast turn-OFF and transient protection of each
output. Each clamp independently limits the drain-to-source
voltage to 50 V. The total energy clamped (EJ) can be
calculated by multiplying the current area under the current
curve (IA) times the clamp voltage (VCL) (see Figure 7).
Each 33996 output has an internal 50 µA pull-down current
source. The pull-down current is disabled on power-up and
must be enabled for Open Load Detect to function. Once
enabled, the 33996 will only shut down the pull-down current in
Sleep mode or when disabled via SPI.
Characterization of the output clamps, using a single pulse
non-repetitive method at 0.3 A, indicates the maximum energy
to be 50 mJ at 150°C junction temperature per output.
During output switching, especially with capacitive loads, a
false Output OFF Open Load Fault may be triggered. To
prevent this false fault from being reported, an internal fault filter
of 100 µs to 450 µs is incorporated. The duration for which a
false fault may be reported is a function of the load impedance,
Drain-to-Source Clamp
Drain Voltage
Voltage (VCL = 50 V)
R
DS(ON), COUT of the MOSFET, as well as the supply voltage,
VPWR. The rising edge of CS triggers the built-in fault delay
Clamp Energy
Drain Current
timer. The timer must time out before the fault comparator is
enabled to detect a faulted threshold. Once the condition
causing the Open Load Fault is removed, the device resumes
normal operation. The Open Load Fault, however, will be
latched in the output SO Response register for the MCU to
read.
(ID= 0.3 A)
(EJ = IA x VCL
)
Drain-to-Source ON
Voltage (VDS(ON)
)
Current
Area (I )
A
Time
GND
GND
Shorted Load Fault
A shorted load (overcurrent) fault can be caused by any
output being shorted directly to supply, or by an output
experiencing a current greater than the current limit.
Figure 7. Output Voltage Clamping
Reverse Battery Protection
The 33996 device requires external reverse battery
protection on the VPWR pin.
Three safety circuits progressively in operation during load
short conditions afford system protection:
All outputs consist of a power MOSFET with an integral
substrate diode. During reverse battery condition, current will
flow through the load via the substrate diode. Under this
circumstance relays may energize and lamps will turn on. If load
reverse battery protection is desired, a diode must be placed in
series with the load.
1. The device’s output current is monitored in an analog
fashion using a SENSEFET approach and is current
limited.
2. With the output in current limit, the drain-to-source
voltage will increase. By setting the SFPD bit to 0, the
output will shut down on VDS > 2.7 V typical after 450 µs.
3. The device’s output thermal limit is sensed and when
attained causes only the specific faulted output to
shutdown. The device remains OFF until cooled. The
device then operates as programmed by the shutdown/
retry bit. The cycle continues until the fault is removed or
the command bit instructs the output OFF.
Overtemperature Fault
Overtemperature detect circuits are specifically incorporated
for each individual output. The shutdown following an
overtemperature condition depends on the control bit set in the
Global Shutdown/Retry Control register. Each independent
output shuts down at 155°C to 180°C. When an output shuts
down due to an Overtemperature Fault, no other outputs are
affected. The MCU recognizes the fault by a logic [1] in the Fault
Status bit (bit 23 in the SO Response register). After the 33996
has cooled below the switch point temperature and 10°C
hysteresis, the output will function as defined by the shutdown/
retry bit 17 in the Global Shutdown/Retry Control register.
All three protection schemes set the Fault Status bit (bit 23 in
the SO Response register) to logic [1].
Undervoltage Shutdown
An undervoltage SOPWR condition results in the global
shutdown of all outputs and reset of all control registers. The
undervoltage threshold is between 2.0 V and 3.0 V.
An undervoltage condition at the VPWR pin results in an
output shutdown and reset. The undervoltage threshold is
between 3.2 V and 3.5 V. When VPWR is between 5.0 V and
3.5 V, the output may operate per the command word and the
status is reported on SO pin, though this is not guaranteed.
33996
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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PACKAGE DIMENSIONS
EK (Pb-FREE) SUFFIX
32-LEAD SOICW EXPOSED PAD
PLASTIC PACKAGE
CASE 1454-01
ISSUE O
10.3
7.6
7.4
C
B
2.65
2.35
5
9
30X
0.65
1
32
PIN 1 ID
4
11.1
10.9
C
L
NOTES:
9
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
B
B
3. DATUMS B AND C TO BE DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURRS. MOLD FLASH,
PROTRUSION OR GATE BURRS SHALL NOT EXCEED
0.15 mm PER SIDE. THIS DIMENSION IS DETERMINED
AT THE PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
16
17
SEATING
PLANE
A
32X
5.15
2X 16 TIPS
5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSIONS. INTERLEAD FLASH AND
PROTRUSIONS SHALL NOT EXCEED 0.25 mm PER
SIDE. THIS DIMENSION IS DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS EXIT
THE PLASTIC BODY.
0.10
A
0.3
A B C
6. THIS DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4
mm PER SIDE. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD
SHALL NOT LESS THAN 0.07 mm.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.10 mm AND 0.3 mm FROM
THE LEAD TIP.
(0.29)
BASE METAL
0.25
0.19
(0.203)
0.38
0.22
PLATING
6
9. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. THIS DIMENSION IS
0.3
A B C
M
M
DETERMINED AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE
BAR BURRS, GATE BURRS AND INTER-LEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
0.13
C A
B
4.96
4.44
8
SECTION A-A
ROTATED 90 CLOCKWISE
°
4.96
4.44
R0.08 MIN
0.25
°
0
0.3
A
B
C
0.29
0.13
GAUGE PLANE
MIN
0.9
0.5
°
°
8
0
SECTION B-B
VIEW C-C
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33996
15
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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be
provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license
under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for
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respective owners.
© Motorola, Inc. 2004
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MC33996
相关型号：
PC33999EKR2
1.2A PWM BASED PRPHL DRVR, PDSO54, 0.65 MM PITCH, LEAD FREE, EXPOSED PAD, PLASTIC, SOIC-54
NXP
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