PC34848EP [NXP]
LED DISPLAY DRIVER, QCC48, 7 X 7 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, MO-220VKKD-2, QFN-48;
| 型号： | PC34848EP |
| 厂家： | 
NXP |
| 描述： | LED DISPLAY DRIVER, QCC48, 7 X 7 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, MO-220VKKD-2, QFN-48 驱动 接口集成电路 |
| 文件： | 总38页 (文件大小：1042K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC34848
Rev. 1.0, 5/2010
Freescale Semiconductor
Advance Information
8-Channel LED Driver with Differential
Interface
MC34848
The 34848 is a high efficiency, 8-channel LED driver for use in LCD
backlighting applications. It is designed to support up to 160 mA /
channels in scan backlight mode, or 80 mA/channels in local dimming
mode. Current reference is set using a single resistor to GND and LED
current tolerance is accurate to ±1% channel-to-channel and IC-to-IC.
The current can be programmed in both local dimming and scan modes.
POWER MANAGEMENT IC
Each channel has independent PWM control with 10-bit resolution,
programmed with high speed differential interface. The frequency
between ICs is synchronized and derived from Controller (LED Driver
Controller) signals. When the SCAN pin is pulled high, it enables the
Scan mode. In this mode, each of 8 channels is on for nominally 3/8 of
the frame.
EP SUFFIX (PB-FREE)
98ARH99048A
The integrated boost controller is used to generate the minimum
output voltage required to keep all LEDs illuminated with the selected
current, providing the highest efficiency possible. The integrated boost
clock can be programmed from 200 kHz to 1.2 MHz.
48-PIN QFN
Features
ORDERING INFORMATION
Temperature
• Drives 8 LED channels: ±1% current tolerance
• Local dimming mode, scan mode (2/8, 3/8, 4/8, 5/8), test mode
• Output voltage up to 45 V supporting up to 12 LEDs
• Auto drive voltage (VOUT) selection: Minimum feedback voltage
500 mV for low power
Device
Package
Range (T )
A
PC34848EP
-40°C to 85°C
48 QFN EP
• Differential Interface: Initial setup (LED current, fPWM, OVP, etc.), PWM data in normal operation
• Integrated PLL for synchronization: 177 to 200 Hz in 1.0 Hz steps
• 10-bit PWM control per channel: Dimming ratio: >1000:1, turn-on time: <200 ns
• Pb-free packaging designated by suffix code EP”
24 V
3.0 V
DVDD
12 V
PVCC
CPLL
VDC
GD
OUT_SW
CS
COMP
VLOGIC
OVP
SLEW
AGND
DGND
PGND
SCAN
SCAN
SHUT_B
SHUT_B
MC34848
SCAN-RESET
SETUP
SCAN-RESET
SETUP
ISET
LS
LS
CTRL
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CLK(+),(-)
DATA(+).(-)
DIO1
CLK
DATA
STH
Figure 1. 34848 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2010. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
GD
PVCC
VDC
OUT_SW
CS
REG 1
UVLO 0
UVLO 1
BOOST
CONTROLLER
WITH
SLEW
COMP
OVP
OVP/OCP
SHUT_B
SYNC_IN
OSCILLATOR
SYNC_OUT
OTP
DVDD
V SENSE
VLOGIC
REG 2
UVLO 2
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
DIO1
SHL
SHIFT
REGISTER
8 CHANNEL
CURRENT
DRIVER
DIO2
DATA+
DATA-
CLK+
CLK-
DIFFERENTIAL
INTERFACE
DGND
AGND
SETUP
RESET-SCAN
SCAN
CONTROL
LOGIC
LS
SETUPD
TEST
REFERENCE
GENERATOR
ISET
REFIO
SYNC_PWM
CPLL
PWM
GENERATOR
GNDIO
PGND
Figure 2. 34848 Simplified Internal Block Diagram
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
PIN CONNECTIONS
PIN CONNECTIONS
CH1
PGND
CH2
1
2
36
35
34
33
32
31
30
29
28
27
26
25
DIO1
SHUT_B
LS
3
CH3
4
RESET_SCAN
SETUP
DATA-
DATA+
CLK-
PGND
CH4
5
6
EXPOSED PAD
PGND
CH5
7
PGND
CH6
8
9
CLK+
CH7
10
11
12
DVDD
DIO2
PGND
CH8
DGND
Figure 3. 34848 Pin Connections
Table 1. 34848 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section.
Pin Number
Pin Name
Pin Function
Formal Name
Definition
1
LED connection - channel 1
Power ground
CH1
2, 5, 8, 11,
13, 44
PGND
3
4
LED connection - channel 2
LED connection - channel 3
LED connection - channel 4
LED connection - channel 5
LED connection - channel 6
LED connection - channel 7
LED connection - channel 8
CH2
CH3
CH4
CH5
CH6
CH7
CH8
SHL
6
7
9
10
12
14
Shift register direction (‘H’ - DIO1 input, CH1 - CH8, DIO2 output, ‘L’ - -
DIO2 input, CH8 - CH1, DIO1 output)
15
16
Enable test mode
TEST
Setup default value select
SETUPD
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 34848 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section.
Pin Number
Pin Name
Pin Function
Formal Name
Definition
17, 39
Analog ground
AGND
PLLC
Ground
18
PLL compensation network connection
Current reference setting
Ground reference REFIO supply
Reference voltage supply
Enable scan made (‘H’ enabled, ‘L’ disabled)
Decouple for internally generated 2.5 V rail
Boost clock output
19
ISET
20
GNDIO
REFIO
SCAN
21
22
23
VLOGIC
SYNC-OUT
DGND
DIO2
24
25
Digital ground
26
Data shift register I/O2
27
DVDD
Logic supply voltage
28
CLK+
Differential interface clock+
Differential interface clock -
Data+
29
CLK-
30
DATA+
DATA-
SETUP
RESET_SCAN
LS
31
Data-
32
SETUP input. Setup mode and clear data register when high
RESET_SCAN input. Reset internal counter
Data Latch
Input
Input
33
34
35
SHUT_B
DIO1
Shutdown pin, active low
Data shift register I/O1
36
37
SYNC_IN
SYNC_PWM
VDC
Boost clock input
Input
Input
38
PWM sync input
40
Decouple for internal gate driver voltage
Boost driver slew rate control
Control to power switch for input voltage VIN
Boost compensation pin
41
SLEW
42
GD
43
COMP
CS
45
Current sense input pin
Input
46
OUT-SW
OVP
FET driver output
Output
47
48
Over-voltage protection sense pin
Switch driver power supply
Power ground
PVCC
Exposed Pad
PGND
Ground
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Maximum Pin Voltage
CH1 - CH8
GD
VMAX
V
45
28
PVCC
14
VDC, OUT_SW
6.2
2.6
PLLC, ISET, REFIO, VLOGIC, OVP, CS, COMP, SLEW, SYNC_PWM, CLK,
DATA
All other pins
3.6
12 to 28
6.0 to 14
2.6 to 3.6
82
VIN Input Voltage Range
V
VIN
PVCC
PVCC Input Voltage Range
V
DVDD Input Voltage Range
DVDD
V
Maximum LED Current - Local Dimming Mode
Maximum LED Current - Scan Mode
mA
mA
ILED_LDM
ILED_SM
VESD
164
ESD Voltage(1)
V
Human Body Model (HBM)
Machine Model (MM)
±2000
±200
THERMAL RATINGS
Ambient Temperature Range
Storage Temperature
°C
TA
-40 to 85
-40 to150
Note 2
TSTO
TPPRT
TJ_MAX
°C
Peak Package Reflow Temperature During Reflow(2),
Maximum Junction Temperature
Thermal Resistance, Junction to Ambient(3)
Thermal Resistance, Junction to Case(4)
Notes
°C
150
28
°C
R
°C/W
°C/W
J-A
θ
R
2.0
J-C
θ
1. ESD testing is performed in accordance with the Human Body Model (HBM) (AEC-Q100-2), and the Machine Model (MM) (AEC-Q100-
003), RZAP = 0 Ω).
2. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and
enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
3. Thermal resistance measured in accordance with EIA/JESD51-2.
4. Theoretical thermal resistance from the die junction to the exposed pad.
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions VIN = 24 V, VPVCC = 12 V, VDVDD = 3.3 V, ILED = 70 mA (Local Dimming Mode);
140 mA (Scan Mode), fS = 700 kHz, fPWM = 660 Hz, GND = 0 V, unless otherwise noted. Typical values noted reflect the
approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SUPPLY
Supply Voltage at PVCC
VPVCC
IPVCC
6.0
-
12
14
22
V
Supply Current at PVCC, Device Enabled
SHUT_B = High, VPVCC = 14 V
mA
18.5
Supply Current at PVCC, Device Disabled
SHUT_B = Low, VPVCC = 14 V
IPVCC-DIS
mA
V
-
-
14.5
-
18
PVCC Under-voltage Lockout
VPVCC Falling
VPVCC_UVLO
5.5
PVCC Under-voltage Lockout Hysteresis
VPVCC Rising
VPVCC_UVLO_HY
V
ST
-
0.24
3.3
-
Supply Voltage at DVDD
VDVDD
IDVDD
2.6
3.6
V
Supply Current at DVDD, Device Enabled
SHUT_B = High, VDVDD = 3.6 V
mA
-
-
7.5
7.5
2.4
12
12
Supply Current, Device Disabled
SHUT_B = Low, VDVDD = 3.6 V
IDVDD-DIS
mA
V
DVDD Under-voltage Lockout
VDVDD Falling
VDVDD_UVLO
2.3
2.55
DVDD Under-voltage Lockout Hysteresis
VPVCC Rising
VDVDD_UVLO_HY
V
ST
-
0.15
6.0
-
VDC Output Voltage(5)
VDC
V
CVDC = 2.2 μF
5.8
2.4
6.2
2.6
VLOGIC Output Voltage(5)
VLOGIC
V
CVLOGIC = 2.2 μF
2.5
Notes
5. This pin is for internal use only, and not to be used for other purposes.
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions VIN = 24 V, VPVCC = 12 V, VDVDD = 3.3 V, ILED = 70 mA (Local Dimming Mode);
140 mA (Scan Mode), fS = 700 kHz, fPWM = 660 Hz, GND = 0 V, unless otherwise noted. Typical values noted reflect the
approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
BOOST CONVERTER
SW Output Voltage
CS Sense Voltage
VSW
VCS
5.8
-
6.0
6.2
-
V
V
RCS = 50 mΩ, ILIMIT Threshold = 3.5 A
0.175
Boost Efficiency(6)
ILOAD = 0.5 A
EFFBOOST
%
-
-
94
-
-
Boost Line Regulation
IOUT/VIN
%/V
(VIN = 24 V 15%, ILOAD = 0.5 A)
0.1
Current Sense Amplifier Gain
Slope Compensation Voltage Ramp
LED CURRENT DRIVER
ACSA
-
-
4.5
-
-
VSLOPE
0.34
V
Maximum sink current
Local Dimming Mode
Scan Mode
IS
mA
-
-
-
-
82
164
Regulated Minimum voltage across drivers
VMIN
400
500
600
mV
Off-state Leakage Current, all channels
(VCH = 45 V)
ICH_LEAK
μA
-
-
10
LED Current Tolerance
ITOLERANCE
%
Channel-to-Channel/ Chip-to-Chip
-1
-
+1
ISET pin voltage
VSET
ILDM
1.252
1.265
1.277
V
Local Dimming Mode Drive Current
mA
IL = 000
IL = 111
61.8
79.2
62.5
80
63.2
80.8
Scan Mode Drive Current
IS = 00000
ISCAN
mA
120.0
158.4
121.2
160
122.4
161.6
IS = 11111
FAULT PROTECTION
Over-temperature Threshold
OTT
140
150
160
°C
V
Short Failure Detection Voltage
SFDV
C = 00
C = 01
C = 10
C = 11
-
Disabled
3.0
-
2.7
3.6
4.5
3.3
4.4
5.5
4.0
5.0
Notes
6. Boost efficiency test is performed under the following conditions: fSW = 700 kHz, VIN = 24 V, TA = 25°C, VPVCC = 12 V, VDVDD = 3.3 V,
and RL = 70 Ω. The following external components are used: FDS3692 (Boost FET), FDS4675 (Q-FET), L = 22 μH (DCR = 54 mΩ),
CTOUT = 30 μF, SS36-E3 (Schottky diode). The measurement does not include Q-FET losses. Note: Freescale does not assume liability,
endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables. While Freescale offers
component recommendations in this configuration, it is the customer’s responsibility to validate their application.
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions VIN = 24 V, VPVCC = 12 V, VDVDD = 3.3 V, ILED = 70 mA (Local Dimming Mode);
140 mA (Scan Mode), fS = 700 kHz, fPWM = 660 Hz, GND = 0 V, unless otherwise noted. Typical values noted reflect the
approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OVP Threshold(7)
V = 000
OVP
V
27.9
29.7
31.5
33.3
35.1
36.9
38.7
40.5
31
33
35
37
38
41
43
45
34.1
36.3
38.5
40.7
42.9
45.1
47.3
49.5
V = 001
V = 010
V = 011
V = 100
V = 101
V = 110
V = 111
LOGIC INPUTS (SHUT_B, DIO1, DIO2, RESET, LS, SHL)
Input Threshold Low
VIL
VIH
-
-
-
0.8
-
V
V
Input Threshold High
2.0
SHUT_B Input Leakage Current
VSHUT_B = 1.0 V
ISHUT_B_LEAK
μA
-
-
-
-
10
10
DIO1, DIO2 Input Leakage Current
VDIO = 1.0 V
IDIO_LEAK
μA
SETUP, RESET_SCAN Input Leakage Current
V = 1.0 V
ILEAK
μA
μA
-
-
-
-
10
10
LS Input Leakage Current
VLS = 1.0 V
ILS_LEAK
SHL Input Leakage Current
VSHL = 1.0 V
ISHL_LEAK
μA
-
-
10
Notes
7. Measurements performed using a resistor divider network with a ratio of 23.71.
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions VIN = 24 V, VPVCC = 12 V, VDVDD = 3.3 V, ILED = 70 mA (Local Dimming Mode);
140 mA (Scan Mode), fS = 700 kHz, fPWM = 660 Hz, GND = 0 V unless otherwise noted. Typical values noted reflect the
approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
BOOST CONVERTER
Minimum duty cycle
Maximum duty cycle
DMIN
DMAX
fS
25
-
-
-
75
98
ns
%
Switching Frequency
F = 000
kHz
160
240
320
400
480
560
720
960
200
300
400
500
600
700
900
1200
240
360
F = 001
480
F = 010
F = 011
600
F = 100
720
F = 101
840
F = 110
1080
1440
F = 111
Soft Start Period
SW Drive
tSS
-
20
-
ms
ns
SWDR
Rise time (10% to 90%), CLOAD = 1.2 nF, VSW = 6.0 V, RSLEW = 4.7 kΩ
Fall time (90% to 10%), CLOAD = 1.2 nF, VSW = 6.0 V, RSLEW = 4.7 kΩ
-
-
12.5
16.5
-
-
PWM GENERATOR
RESET_SCAN Frequency
FRESET_SCAN
fPWM
80
120
180
Hz
Hz
PWM frequency(8)
P = 0000000000
FRESET_SCAN = 80 Hz
112
168
253
118
177
266
124
186
279
FRESET_SCAN = 120 Hz
FRESET_SCAN = 180 Hz
P = 1111111111
FRESET_SCAN = 80 Hz
760
1140
1710
800
1200
1800
840
1260
1890
FRESET_SCAN = 120 Hz
FRESET_SCAN = 180 Hz
PWM Synchronization Frequency(8)
fPWM = 177 Hz
fSYNC_PWM
kHz
172
181
190
fPWM = 1200 Hz
1166
1228
1289
LED CURRENT DRIVER
Channel Rise Time - 10% to 90%, ILED_PEAK = 70 mA
Channel Fall Time - 90% to 10%, ILED_PEAK = 70 mA
tR
tF
-
-
-
-
200
200
ns
ns
Notes
8. For Slave mode, the IC to IC matching is under 1%
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
The differential interface for data and clock control is specified as below.
CHP
CLP
+120 mV
+120 mV
+120 mV
50%
50%
50%
0 V
-120 mV
-120 mV -120 mV
-120 mV
-120 mV
CLK
(DIFFERENTIAL
CLOCK SIGNAL)
SPSTU
2.0 V
SPHLD
2.0 V
0.9 V
STH
DIFFERENTIAL DATA
+120 mV +120 mV
st
1 -120 mV
-120 mV
+120 mV +120 mV
nd
rd
3
Invalid Data
2
-120 mV -120 mV
NOTE: Max CLK Frequency - 85 MHz
Figure 4. Timing Specifications 1
Table 5. Timing Specification 1
Symbol
CHP
Parameter
Conditions
f = 85 MHz
Min
Typ. Max Unit
Clock (CLK) High Period
-
5.7
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Clock (CLK) Low Period
f = 85 MHz
CLP
-
5.8
(R.G.B.) Setup to falling or rising edge of CLK
(R.G.B.) Hold from falling or rising edge of CLK
STH rising to CLK falling
f = 85 MHz
STU
1.875
0.225
3.0
-
-
-
-
I
= 100 μA, f = 85 MHz
HLD
PI
R
R
= 100 Ω, C = 5.0 pF, f = 85 MHz
SPSTU
SPHLD
T
T
T
STH falling to CLK falling
= 100 Ω, C = 5.0 pF, f = 85 MHz
1.5
T
VDIFF
N
VIL
VCM
VIH
VIH
VDIFF
P
GND
O V
VIL
(VDIFFP) - (VDIFFN)
Figure 5. CLK and Data input Specification
Table 6. Timing Specification 1
Symbol
VIH
Parameter
Conditions
VCM = +1.2 V(9)
Min
Typ. Max Unit
High Input Voltage
Low Input Voltage
70
-
200
-200
1.2
-
-
mV
VIL
VCM = +1.2 V(9)
-70
1.4
10
VCM
Common Mode Input Voltage Range
Input Leakage Current
VIH = +70 mV, VIL = -70 mV
DxxP, DxxN, CLKP, CLKN
V
0.9
-10
IDL
μA
Notes:
9. VCM = (VCLKP+VCLKN)/2 or VCM = (VDxxP+VDxxN)/2
The positive sign means that DxxP (or CLKP) is higher than ground DxxN (or CLKN)
The negative sign means that DxxP (or CLKP) is lower than ground DxxN (or CLKN)
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
0.7 V
DD
SHUT_B
SETUP
PW
SETUP
0.7
t
V
0.7 V
DD
DD
t
PW
SETUP1
HOLD1
CLK
CLK
(Differential)
0V
t
SETUP2
t
HOLD2
0.7 V
DD
0.7V
PW
DD
STH
t
t
SETUP-STH
SETUP3
HOLD3
STH
t
DATA
(Differential)
D0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
9
8
D95D94
0V
0V
LSB
MSB
t
PLH1
CARRY
LS
PW
t
CARRY
t
LS-CLK
PW
LDT
0.7 V
LS
t
DD
LS-STH
V
0.7
DD
V
0.7
t
DD
0.7 V
0.7 V
RESET_SCAN
SETUP
DD
DD
RESET_SCAN-STH
PW
STH
0.7 V
0.7 V
DD
DD
3 Times Receiving Setup Data
CLK
OV
OV
D95 D94 D93 D92 D91 D90 D89 D88 D87 D6 D5 D4 D3 D2 D1 D0
OV
DATA
Figure 6. Total Interface Detailed Timing
Min
Table 7. Interface Timing Specifications
Symbol
Typ
Max
Unit
tSHUT_DVDD
tSETUP-DVDD
tSETUP1
tHOLD1
200
1.0
2.0
2.0
48
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ms
ms
ns
-
-
-
ns
PWSETUP
tSETUP-STH
PWCLK
-
CLK
CLK
ns
2.0
11.7
2.0
2.0
4.0
1.0
2.0
2.0
-
333
tSETUP2
tHOLD2
-
ns
-
ns
tLS-CLK
-
2.0
-
PWSTH
CLK
ns
tSETUP3
tHOLD3
-
ns
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 7. Interface Timing Specifications
Symbol
Min
Typ
Max
Unit
PWCARRY
tPLH1 (CL = 15 pf)
tLDT
-
-
-
-
-
-
-
1.0
CLK
ns
1.0
1.0
2.0
1.0
5.0
10.7
-
-
-
-
CLK
CLK
CLK
CLK
tLS-STH
tRESET_SCAN-STH
PWLS
reprogrammed again until a complete POR (Power-on-reset)
is applied. Although the setup register is only 32 bits, the
34848 requires the data to be written 3 times (i.e. 96 bits).
When SETUP is taken low, the 3 sets of data are compared.
If 2 or more sets match, then that data is used. Otherwise, the
default values are used. This interface programs the LED
current, boost frequency, PWM frequency, OVP voltage, and
LED short detection voltage.
CONFIGURATION
When the SETUPD pin is high, the configuration registers
are set to the default values in Table 8. When the SETUPD
pin is low, the configuration registers can be programmed via
the differential interface.
When the SETUPD and SHUT_B pins are low and SETUP
is high, data can be written to the set-up register through the
differential interface. Once the register has been
programmed, the data is locked and the register cannot be
Table 8. Setup Interface Registers
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IL2
P1
IL1
P0
IL0
F2
IS4
F1
IS3
F0
IS2
V2
IS1
V1
IS0
V0
P9
S1
P8
S0
P7
C1
P6
C0
P5
R3
P4
R2
P3
R1
P2
R0
• IL[2:0] = Local dimming mode current control (‘000’ = 62.5 mA, ‘111’ = 80 mA). Default = ‘011’ = 70 mA
• IS[4:0] = Scan mode current control (‘00000’ = 121.25 mA, ‘11111’ = 160 mA) Default = ‘01111’ = 140 mA
• P[9:0] = PWM frequency (‘0000000000’ = 177 Hz, ‘1111111111’ = 1200 Hz). Default = ‘0111100011’ = 660 Hz
• F[2:0] = Boost switching frequency (000 = 200 kHz, 001 = 300 kHz, 010 = 400 kHz, 011 = 500 kHz, 100 = 600 kHz,
101 = 700 kHz, 110 = 900 kHz, 111 = 1.2 MHz). Default = ‘101’ = 700 kHz
• V[2:0] = Over-voltage protection threshold (‘000’ = 31 V, ‘111’ = 45 V). Default = ‘111’ = 45 V
• S[1:0] = Scan mode row count (‘00’ = 2/8 row, ‘01’ = 3/8 row, ‘10’ = 4/8 row, ‘11’ = 5/8 row). Default = ‘01’ 3/8
• C[1:0] = LED short detection voltage (‘00’ = disabled, ‘01’ = 3.0 V, ‘10’ = 4.0 V, ‘11’ = 5.0 V). Default = ‘10’ = 4.0 V
• R[3:0] = reserved
• Control register loaded with default values
• All PWM drivers set to 95% duty cycle
• No input data and clock (no CLK, no LS)
• Master device needs to use an on-chip oscillator to serve
as the reference frequency to PLL
TEST MODE
The TEST input can be used to place the 34848 into test
mode. In this mode, the device is placed in to a pre-
determined mode of operation as follows:
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
TYPICAL PERFORMANCE CURVES (T =25°C)
A
70.00
69.90
69.80
69.70
69.60
69.50
69.40
69.30
69.20
69.10
69.00
100.0
99.0
98.0
97.0
96.0
95.0
94.0
93.0
92.0
91.0
90.0
20
21
22
23
24
25
26
27
28
19
20
21
22
23
24
25
26
27
28
29
Vin, volts
Vin, volts
Figure 7. Line Regulation, VIN Changing
Figure 10. Boost Efficiency vs Input Voltage
100.0
70.00
99.0
98.0
97.0
96.0
95.0
94.0
93.0
92.0
91.0
90.0
69.90
69.80
69.70
69.60
69.50
69.40
69.30
69.20
69.10
69.00
10
11
12
13
14
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
Load Current, Amps
VPVCC, volts
Figure 11. Boost Efficiency vs Load Current
Figure 8. Line Regulation, VPVCC Changing
Note: Typical Performance Curves were performed under
the following conditions: fSW = 700 kHz, VIN = 24 V, VPVCC
=
70.00
12 V, VDVDD = 3.3 V, and RL = 70 Ω. The following external
components are used: FDS3692 (Boost FET), FDS4675 (Q-
FET), L = 22 μH (DCR = 54 mΩ), CTOUT = 30 μF, SS36-E3
(Schottky diode). The efficiency measurements do not
include Q-FET losses.
69.90
69.80
69.70
69.60
69.50
69.40
69.30
69.20
69.10
69.00
2.8
3.0
3.2
3.4
3.6
3.8
VDVDD, volts
Figure 9. Line Regulation, VDVDD Changing
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 34848 is a high efficiency, 8-channel LED driver for
use in LCD backlighting applications. The 34848 is designed
to support up to 160 mA per channel in scan backlight mode,
or 80 mA per channel in local dimming mode. The current
reference is set using a single resistor to GND, and LED
current tolerance is accurate to ±1% channel-to-channel and
IC-to-IC. The current can be programmed in both local
dimming and scan modes independently.
interface. The frequency between ICs is synchronized and
derived from Controller signals. When the SCAN pin is pulled
high, it enables the scan mode. In this mode, each of 8
channels is on for nominally 3/8 (programmable from 2/8 to 5/
8) of the frame.
The integrated boost controller is used to generate the
minimum output voltage required to keep all LEDs illuminated
with the selected current, providing the highest efficiency
possible. The integrated boost clock can be programmed
from 200 kHz and 1.2 MHz using the control interface.
Each channel has independent PWM control with 10-bit
resolution, programmed via the high speed differential
FUNCTIONAL PIN DESCRIPTION
LED CONNECTION (CH1 - CH8)
GROUND FOR REFIO SUPPLY (GNDIO)
LED current driver inputs, with maximum sink current
capabilities in local dimming mode of 80 mA, and in scan
mode of 160 mA.
Ground reference for the REFIO pin.
ENABLE SCAN MODE (SCAN)
If this pin is taken high, the IC enters in scan mode from
the local dimming mode.
POWER GROUND (PGND)
Power ground of the IC. Internal LED drivers and
regulators are referenced to this pin.
DECOUPLED LOGIC INTERNAL VOLTAGE
(VLOGIC)
SHIFT REGISTER DIRECTION (SHL)
This pin is for internal use only, and not to be used for other
purposes. A capacitor of 2.2 μF is connected between this
pin and ground for decoupling purposes.
The direction of the internal shift register is set by this pin.
TEST MODE (TEST)
BOOST CLOCK OUTPUT (SYNC_OUT)
This pin is used to enable the test mode.
Boost converter frequency is the output on this pin.
SETUP DATA (SETUPD)
DIGITAL GROUND (DGND)
When this pin is high, the configuration registers are set to
the default values. When this pin is low, the configuration
registers can be programmed via the differential interface.
Digital ground of the IC. Internal digital signals are
referenced to this pin.
ANALOG GROUND (AGND)
DATA SHIFT REGISTER INPUT/OUTPUT (DIO1/
DIO2)
Analog ground of the IC. Internal analog signals are
referenced to this pin.
These pins are used as inputs and outputs to the shift
register depending on the status of SHL.
PLL NETWORK (PLLC)
LOGIC SUPPLY VOLTAGE (DVDD)
PLL compensation network connection.
Input voltage pin which ranges from 2.6 to 3.6 V, and used
to power the internal logic circuits.
CURRENT REFERENCE SETTING (ISET)
The LED current is set with a 2.0 k resistor connected from
this pin to ground. The precision of the resistor is
recommended to be no higher than 0.1%.
CLOCK SIGNALS (CLK+,CLK-)
Differential data clock signals.
REFERENCE VOTALGE SUPPLY (REFIO)
DATA SIGNALS (DATA+, DATA-)
This voltage supply pin is used as a reference for
achieving high current matching ratios when two or more ICs
are connected together.
Differential data signals.
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
SETUP INPUT (SETUP)
BOOST DRIVER SLEW RATE CONTROL (SLEW)
When this pin is taken high, the differential interface
programs the data registers and the device is in the setup
mode.
This pin is used to control the slew rate on the OUT_SW
pin for different application needs. The slew rate can be
adjusted by connecting a resistor with a value of 4.7 k, 14 k,
or 24 k, from this pin to GND.
RESET_SCAN INPUT (RESET_SCAN)
Q-FET CONTROL (GD)
This pin is taken high at the start of each frame to reset the
internal counter.
This pin is used to control the ON/OFF operation of the
Q-FET.
DATA LATCH (LS)
BOOST COMPENSATION (COMP)
When this pin is pulsed, the PWM data in each of the
Sample and Hold blocks is transferred to the corresponding
PWM controller to start the PWM for the LED driver, and
increase the internal counter by 1 in each LED driver device.
Boost converter compensation network connects to this
pin.
POWER MOSFET DRIVER OUTPUT (OUT_SW)
SHUT_B
Boost converter power MOSFET driver output.
When this pin is high, the boost and LED drivers are
enabled.
CURRENT SENSE (CS)
Boost power MOSFET current is sensed across a resistor
connected to this pin and ground, as well as for over-current
protection (OCP) and current sensing for current mode
control.
BOOST CLOCK INPUT (SYNC_IN)
The Boost converter frequency can be synchronized to an
external signal if provided at this pin. If this pin is connected
to ground, an On-Chip oscillator is used to generate the boost
frequency.
USER PRGRAMABLE OVER-VOLTAGE
PROTECTION (OVP)
PWM SYNC CONNECTIONS (SYNC_PWM)
Over-voltage protection sense pin.
When the IC is operated as a Master, the resulting clock
for PWM pulse generation is output on this pin. For Slave
chips, this pin acts as an input for the reference clock for the
PWM generator.
SWITCH DRIVER POWER SUPPLY (PVCC)
Input voltage pin that can range from 6.0 to 14 V and used
to power the LED drivers and gate drive for the boost
controller.
DECOUPLED INTERNAL GATE DRIVER VOLTAGE
(VDC)
This pin is for internal use only, and not to be used for other
purposes. A capacitor of 2.2 μF is connected between this
pin and ground for decoupling purposes.
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
If the input voltage at either supply falls below their
respective UVLO threshold, the device automatically enters
the power down mode. Likewise, operation of the device is
only possible when the two input voltages are above the
UVLO threshold levels.
INTERNAL POWER SUPPLY
The internal circuitry of the 34848 uses two separate
power supplies. The first is a high voltage input at PVCC that
can range from 6.0 to 14 V, and is used to power the LED
drivers and gate drive for the boost controller. The external
Boost low side FET gate drive is equal to the input voltage at
VDC. The second supply is DVDD, which ranges from 2.6 to
3.6 V, and is used to power the internal logic circuits.
In addition to the above, PVCC voltage is also monitored
for UVLO.
The SHUT_B pin can be used to enable/disable the Boost
Controller and LED drivers.
Internally there are two regulators, which both have
external decoupling capacitors. VDC is used to regulate the
PVCC input to produce a constant drive voltage for the
internal LED drivers, and is decoupled on the VDC pin.
VLOGIC is used to produce 2.5 V for internal logic from the
DVDD supply and is decoupled using a capacitor on the
VLOGIC pin.
DIFFERENTIAL INTERFACE AND CONTROL
LOGIC
The 34848 uses a differential interface. The clock rate
supported is up to 85 MHz. In addition, 6 logic pins are also
used as part of the interface.
Figure 12. Control Interface
When SETUP is taken high the interface programs data
registers which are in setting mode. An integrated 10-bit shift
register selects which bit is being written. After the pulsing
from SETUP and RESET_SCAN, the STH triggers the PWM
data in from the differential interface. An internal counter
(SIC) selects which channel is being written. The 10-bit shift
register in multiple devices are connected to generate a long
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
chain of bit selects through all of the LED driver ICs in a
system (10 x N bits. N = # of LED Driver IC).
Hs in all LED Driver ICs, respectively. When LS is pulsed, the
10-bit PWM data is transferred from S/H to the PWM
controller to start the PWM for LED driver, and the SIC
counter increases by 1 in each LED Driver device.
RESET_SCAN is taken high at the start of each frame to
reset the internal counter. Following the STH pulsing the
input to the 10-bit register, the Controller is set to 1, which
ripples through the connected shift registers with each data
write. Once 10-bit data for this LED Driver has been written,
the DIO1 (or DIO2) pin is taken high. This latches the data in
the Sample and Hold (S/H) of the corresponding PWM
channel (selected by SIC counter) for this LED Driver device.
The DIO1 (or DIO2) pulsing from this LED Driver is input to
the next LED Driver, as its STH signal at DIO2 (or DIO1) pin.
Then the next 10-bit data can be written to the S/H of the
selected PWM channel for this LED Driver device. This
process continues until all the 10-bit data is written to the S/
For multiple devices, another 10 x N bits are then written
for the next selected PWM channels in each LED Drivers
using the same procedure. This continues and repeats for the
N = 8 PWM channels in each LED Driver device.
The direction of the internal shift register is set using the
SHL input. The DIO1 and DIO2 pins are used as inputs and
output to the shift register depending on the status of SHL.
The differential interface control also features a default
configuration mode for device setup. This is enabled by
taking the SETUPD pin high.
10
CH1 PWM
S/H
(001)
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CONTROL
PWM_CLK
10
10
10
10
10
10
10
CH2 PWM
CONTROL
PWM_CLK
S/H
(010)
32 BIT CONFIGURATION
REGISTER
CH3 PWM
CONTROL
PWM_CLK
S/H
(011)
32
CH4 PWM
CONTROL
PWM_CLK
S/H
(100)
DATA+
10
DATA-
CH5 PWM
CONTROL
PWM_CLK
S/H
(101)
CH6 PWM
CONTROL
PWM_CLK
S/H
(110)
AGND
CH7 PWM
CONTROL
PWM_CLK
S/H
(111)
CH8 PWM
CONTROL
PWM_CLK
S/H
(000)
CLK+
3
SHIFT REGISTER
CLK-
OUT INTERNAL PWM
REF OSCILLATOR
STH
SETUPD
INTERNAL
COUNTER
DIO1 SHL DIO2
RESETSCANSETUP
LS
SCAN
PLLC
SYNC_PWM
Figure 13. Control Register Block Diagram
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
SHUT_B
SETUP
RESET_SCAN
STH(1)
st
th
1
LED Driver(10 bit)
N
N
N
LED Driver(10 bit)
Carry
1ST ROW BLOCK
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
N X 10 DATA
LS(1)
STH(2)
st
th
1
LED Driver(10 bit)
LED Driver(10 bit)
Carry
2nd ROW BLOCK
1
0
1
1
1
0
1 1 0 1 1 0
N X 10 DATA
LS(2)
STH(8)
st
th
1
LED Driver(10 bit)
LED Driver(10 bit)
Carry
8
th ROW BLOCK
LS(8)
1
0
1
1
1
0
1 1 0 1 1 0
N X 10 DATA
Figure 14. differential Interface Control
Figure 15. Connection Among LED Drivers Thru the Differential Interface Control and to the LED Panels
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Figure 16. Local Dimming Mode Control
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Figure 17. Scan Mode Control
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
PROTECTION FUNCTIONS
8 CHANNEL LED CURRENT DRIVER
The 34848 monitors the backlighting application from
several fault conditions to protect itself and the LED strings.
See Protection and Diagnostic Features for a detailed
description.
The programmable current driver matches the current in
up to 8 LED strings to within ±1%. The current can be
programmed independently for scan and local dimming
modes. In scan mode, the current can be programmed from
121.25 to 160 mA in 32 steps. In local dimming mode, the
current range is from 62.5 to 80 mA in 8 steps. To provide this
high matching ratio between ICs, the voltage references used
in the ICs are connected between each chip using the REFIO
and GNDIO pins.
BOOST CONTROLLER
The integrated boost controller operates in non-
synchronous mode and uses an external boost low side FET.
Current is sensed across the sense resistor between the low
side FET and ground, and is used for over-current protection
(OCP) and current sensing for current mode control.
The current driver circuits are also used to disable current
flow in the LEDs when the LEDs are in the Off state, or when
PWM is off. This enhances the performance of the PWM
dimming function by maintaining a constant current through
the LEDs when illuminated.
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL DEVICE OPERATION
The boost converter also features Over-current Protection
(OCP). The OCP operates on a cycle by cycle basis.
However, if the OCP condition remains for more than 60 ms
then the boost regulator is latched off and GD asserts high to
shutoff the Q-FET. The device can only be restarted by
recycling the power supply.
BOOST
An integrated sense circuit is used to sense the voltage at
the LED current driver inputs and automatically sets the
output voltage to the minimum voltage needed to keep all
LEDs biased with the required current. Care has been taken
to ensure that the minimum required output voltage (also the
minimum VF of the LEDs) is used in order to minimize on-
chip power dissipation. The boost frequency is programmed
in the setup routine (see 'Configuration' below) from 200 kHz
to 1.2 MHz, or can be synchronized to an input signal if
provided at the SYNC_IN pin. If SYNC_IN is connected to
GND, an on-chip oscillator is used to generate the boost
frequency and the boost frequency is output on the
SYNC_OUT pin.
The SLEW pin is used to limit the slew on the OUT_SW pin
to reduce noise and avoid EMI problems. If the slew rate is
reduced too much, the efficiency of the device will reduce.
The slew rate can be changed by tying a resistor from the
SLEW pin to GND.
The Boost converter has been designed to operate over a
wide range of switching frequencies. Table 9 shows the
recommended external components to ensure stable
operation under all operating conditions.
Table 9. Recommended External Components (VIN = 24 V 10%)
Switching Frequency [kHz]
L [μH]
CO [μF]
RCOMP [kΩ]
CCOMP1 [nF]
CCOMP2 [pF]
200
300
400
500
600
700
900
1200
100
68
47
33
33
22
22
15
150
100
68
130
130
130
130
130
130
130
130
1.5
1.0
0.7
0.6
0.5
0.4
0.3
0.2
59
39
29
24
20
-
47
47
33
33
-
22
-
The output capacitor CO should be a low ESR type,
preferably a MLCC. If an electrolytic capacitor is used, a
small value ceramic capacitor should be connected in parallel
to CO to reduce the ESR, thus reducing the output ripple
voltage of the converter.
control registers, and is generated by a PLL using RESET-
SCAN as the frequency reference. To operate in Master
mode, the SYNC_IN pin is connected to GND. The resulting
clock for PWM pulse generation is output on the SYNC_PWM
pin. A compensation network is connected between the
PLLC pin and GND. For Slave mode, the SYNC_PWM pin
acts as an input for the reference clock for the PWM
generator. In this manner, one device can be used as the
master IC, SYNC_IN tied to GND, (compensation network on
PLLC, and SYNC_PWM as output) and the remainder as
slaves (PLLC grounded, SYNC_PWM as input) just by
connecting the SYNC_PWM pins together.
PWM DIMMING
Each channel has an independently programmable 10-bit
PWM generator. The data for the PWM generator is
programmed using the differential interface in standard
operating mode. If the channel is programmed with 0 duty
cycle, that channel is programmed off, and is ignored for
automatic output voltage control and for LED failure detection
(see Protection and Diagnostic Features).
The default Frame Frequency is 120 Hz. However, the
RESET-SCAN frequency input range can be between 80 and
180 Hz. Therefore, the resulting PWM frequency is given by
The PWM generator frequency can be programmed from
177 to 1200 Hz in 1.0 Hz step using a register in the start-up
(FRESET-SCAN/120) x FPWM
.
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
CLK
LS
LS
LS
LS
CLK
CLK
CLK
SYNC_PWM
PLLC
SYNC_PWM
PLLC
SYNC_PWM
PLLC
SYNC_IN
SYNC_IN
SYNC_IN
SYNC_OUT
SYNC_OUT
SYNC_OUT
MASTER
SLAVE 1
SLAVE N
Figure 18. PWM, Boost Clock and Current Synchronization
PWM FREQUENCY
SCAN
When the SCAN pin is set high, the 34848 enters scan
mode. In this mode, the LED current is set as determined in
the IS register. The number of banks illuminated at any one
time is set using the configuration register. (See Figure 19)
When the scan pin is set low, the 34848 device goes into
local dimming mode.
For master mode the PWM frequency is set by the internal
register while for slave mode it is synchronized to
SYNC_PWM.
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
1/8 Frame
ON
OFF
1/8 Frame
3 Rows Turn On for 1/8 Frame
1/8 Frame
Figure 19. Scan Mode Operation
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
PROTECTION AND DIAGNOSTIC FEATURES
This results in a divider ratio of 23.71 (RUPPER + RLOWER
RLOWER), which sets the max OVP value.
/
OVER-CURRENT PROTECTION
The boost converter features Over-current Protection
(OCP). The OCP operates on a cycle by cycle basis.
However, if the OCP condition remains for more than 60 ms
then the boost regulator is latched off and GD asserts high to
shutoff the Q FET. The device can only be restarted by
cycling the power supply.
The OVP voltage can be programmed from 31 to 45 V.
LED OPEN PROTECTION
The 34848 monitors the LED status at all 8 channels. The
output voltage is continuously maintained at the minimum
voltage possible to drive all LEDs, i.e. the maximum forward
voltage of the 8 strings plus the minimum threshold needed
(0.5 V, typ) for the current sense circuit and the current driver
to regulate.
OVER-VOLTAGE PROTECTION
The 34848 features user programmable Over-voltage
Protection (OVP). The OVP level can be programmed
between 31 and 45 V in 2.0 V steps. When OVP is reached,
the VOUT voltage is clamped at the OVP level, and the 50 ms
timer is started. If the VOUT is clamped at the OVP level for
more than 50 ms, the VOUT voltage is lowered by 4.0 V, the
DHC is turned off, and another 150 ms timer starts After the
150 ms timer has elapsed, the DHC is turned on again.
If an LED fails open, the voltage at the CHx pin for the
effected LED string falls close to ground, and therefore the
correspondent LED channel will be disabled.
LED SHORT PROTECTION
The 34848 also protects against LED short failures. If delta
VFB, |VFB_MAX – VFB_MIN|, is higher than SFDV and PWM
duty of each channels are more than 0%, then this VFB_MAX
channel is disabled.
If VOUT drops below the OVP before the 50 ms timer
expires, normal operation continues. However, if OVP is still
reached after the 50 ms timer expires, the device will repeat
the OVP sequence two more times. If the OVP fault condition
is still present after the third sequence, the Q-FET, LED
drivers, and boost are turned off.
OVER-TEMPERATURE PROTECTION
The 34848 has an on-chip temperature sensor that
measures die temperature. If the IC temperature exceeds the
OTP threshold, the IC will turn off. While off, the GD pin is set
to high-impedance to turn off the Q-FET. The device turns
back on after recycling the power.
The 34848 uses an internal ADC to measure the voltage
level at the OVP pin and compares it with the configured OVP
level. A resistor divider network needs to be added between
VOUT and ground, with the center tap connected to OVP. The
typical value for the upper divider resistor RUPPER is 243 k
(1%) and 10.7 k (1%) for the lower resistor RLOWER
.
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
TYPICAL APPLICATIONS
INTRODUCTION
TYPICAL APPLICATIONS
INTRODUCTION
24V
22 µH
FD4675
LED
LEG 1
LED
LEG 2
LED
LEG 3
LED
LEG 4
LED
LEG 5
LED
LEG 6
LED
LEG 7
LED
LEG 8
Schottky
SS36-E3
10 kO
47uf
100nf
33uf
0.01uf
0.01uf
10 kO
243 kO
1%
12V
3.3V
GD
42
FD3692
180O
DVDD
OUT_SW
CS
27
46
45
0.47uf
10.7 kO
1%
0.05O
470pf
PVCC
SLEW
48
41
0.47uf
4.7 kO
OVP
130 kO
COMP
68pf
47
43
390pf
CH1
CH2
1
3
CH3
CH4
VDC
4
40
23
VLOGIC
6
2.2uf
2.2uf
CH5
CH6
7
MC34848
9
CH7
CH8
SCAN
10
12
22
35
32
33
SHUT_B
SETUP
ISET
RESET_SCAN
19
REFIO
GNDIO
LS
21
20
34
28
29
30
CTRL
CLK+
100nf
2 kO
0.1%
CLK-
AGND
AGND
DGND
DATA+
17
39
25
DATA-
DIO1
31
36
SYNC_OUT
SYNC_IN
To Slaves SYNC_IN
24
PGND
PGND
49
44
37
18
56 kO
PLLC
14 26 15 16 38
2
5
8
11 13
68nf
0.47nf
To Slaves
SYNC_PWM
Figure 20. Typical Application Circuit for Master Mode Operation (10 LEDs per channel, VF = 3.3 V typical)
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
TYPICAL APPLICATIONS
24V
22 µH
FD4675
LED
LEG 1
LED
LEG 2
LED
LEG 3
LED
LEG 4
LED
LEG 5
LED
LEG 6
LED
LEG 7
LED
LEG 8
Schottky
SS36-E3
10 kO
47uf
100nf
33uf
0.01uf
0.01uf
10 kO
243 kO
1%
12V
3.3V
GD
42
FD3692
180O
DVDD
OUT_SW
CS
27
46
0.47uf
10.7 kO
1%
45
0.05O
470pf
PVCC
SLEW
48
41
0.47uf
4.7 kO
OVP
130 kO
COMP
68pf
47
43
390pf
CH1
CH2
1
3
CH3
CH4
VDC
4
40
23
VLOGIC
6
2.2uf
2.2uf
CH5
CH6
7
MC34848
9
CH7
CH8
SCAN
10
12
22
35
32
33
SHUT_B
SETUP
ISET
RESET_SCAN
LS
19
REFIO
GNDIO
21
20
34
28
CTRL
100nf
CLK+
CLK-
2 kO
0.1%
29
30
AGND
AGND
DGND
DATA+
17
39
25
DATA-
DIO1
31
36
SYNC_OUT
24
PGND
PGND
49
44
From Master
SYNC_OUT
SYNC_IN
PLLC
37
18
14 26 15 16 38
2
5
8 11 13
From Master
SYNC_PWM
Figure 21. Typical Application Circuit for Slave Mode Operation (10 LEDs per channel, VF = 3.3 V typical)
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
TYPICAL APPLICATIONS
COMPONENT SELECTION AND PCB DESIGN CONSIDERATIONS
This section provides a comprehensive procedure for the
selection of external components to achieve proper device
operation. It also explains PCB layout design considerations.
CTRL
Figure 22. Component Selection Application Diagram for the 34848
COMPONENT SELECTION
of the inductor never falls to zero. Then the following formula
is used,
ASSUMPTIONS FOR CALCULATIONS
VIN = 21.6 V
VPVCC = 12 V
VDVDD = 3.3 V
VOUT = 39 V
IOUT = 0.9 A.
VOUT +VD
IOUT ×r × fSW
2
L =
× D
(
1− D
)
fSW = 700 kHz
RMAP = 0.23 V/A
ESR = 10 mΩ
where:
Current ripple ratio = 0.4, which is a good
design target for any switching frequency.
ΔI
r =
SELECTING THE INDUCTOR FOR THE BOOST
CONVERTER
IL
A first approach to determine the value of the inductor is to
consider the continuous conduction mode, that is, the current
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
28
TYPICAL APPLICATIONS
SELECTING THE INPUT CAPACITOR FOR THE
BOOST CONVERTER
Average inductor current.
IOUT
What matters most about the input capacitor selection is
its RMS current capability, ESR, and the voltage rating, more
than the value itself. As a result, when selecting the input
capacitor, the user must take into consideration:
IL =
1− D
Diode forward voltage drop, e.g. 0.7 V
Boost converter duty cycle,
VD
1. The RMS current rating of the capacitor(s) should be
equal or higher than:
D
VOUT +VD −VIN
= 0.46
IOUT
r
VOUT +VD
IRMS _ IN
=
×
1− D
12
2. The lower the ESR, the lower the conduction losses
and the input ripple voltage, which implies less input
noise and EMI effects
⇒ L ≅ 21 μH. An off the shelf inductor value of 22 μH can
be used.
Note: When selecting an inductor, make sure that both the
saturation current (ISAT) & RMS current (IRMS) > IL + (ΔI / 2).
The saturation current (ISAT) is the current at which the
inductance value drops a specified amount below its
measured value with no DC current. The inductance drop is
attributed to core saturation.
3. The voltage rating must be at least 50% higher than
the maximum input voltage.
4. The bigger the capacitor, the smaller the input ripple
voltage. Nevertheless, the bigger the capacitor, the
higher the inrush current the input protection MOSFET
should handle, probably causing turn on failures.
The RMS current (IRMS) is the root mean square current
that causes the temperature of the part to rise a specific
amount above 25°C ambient. The temperature rise is
attributed to I2R losses.
SELECTING THE COMPENSATION NETWORK
COMPONENTS
As Freescale´s 34848 uses current mode control for the
boost converter output voltage regulation, the ramp to the
PWM modulator is derived from the inductor-switch current.
As a result, there is no double LC pole anymore, and a simple
Type-II network compensation is implemented by using a
Transconductance Operational Amplifier.
SELECTING THE OUTPUT CAPACITOR FOR THE
BOOST CONVERTER
The minimum output capacitor can be determined as
follows:
D
The most common way of producing the ramp is to simply
sense the forward drop across a current sense resistor. This
small sensed voltage is then amplified by a current sense
amplifier to get the voltage ramp, which is applied to the PWM
modulator.
COUT
=
⎡
⎢
⎣
⎤
⎥
⎦
⎛
⎞
VOUT
IOUT
ΔVOUT
2VOUT
⎜
⎜
⎟
⎟
× fSW
×
⎝
⎠
where:
One of the subtleties of current mode of control is that it
needs a small ramp to the comparator ramp, which is called
slope compensation. Its purpose is to prevent an odd artifact
of current mode control called sub-harmonic instability.
Peak to peak output voltage ripple, e.g. 50 mV
ΔVOUT
The following design equations are presented for the
⇒ COUT ≅ 23 μF. The next bigger off the shelf capacitor
value of 33 μF is chosen. In the case of switching power
supplies, it is a good practice to use electrolytic capacitors (to
increase the ripple current capability) and ceramic capacitors
(to reduce the ESR effects) together, and consider their
capacitance value over temperature.
compensation network [1][2]
,
A
Vref
A
RCOMP
=
=
12.6528×10−6
gm
VOUT
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
TYPICAL APPLICATIONS
where,
G
⎛
⎜
⎞
⎟
20
⎠
A =10⎝
⎛
⎜
⎞
⎟
⎛
⎞⎛
⎞
s
s
⎜
⎜
⎟⎜
⎟⎜
⎟
⎟
1+
1−
1+
⎜
⎟
⎟
⎟
FESR
FRHP
⎝
⎠⎝
⎞⎛
⎠
G = ABS
(
20×logG(s)
)
= ABS 20×logG
⎜
0
⎛
⎞
s
s
⎜
⎜
⎜
⎟⎜
⎟⎜
⎟
⎟
1+
⎜
⎝
⎟
⎠
FP1
FP2
⎝
⎠⎝
⎠
VOUT
(
1− D
)
IOUT
G0 =
RMAP × KD
1
FESR
=
=
2π × ESR×COUT
⎛
⎞
VOUT
IOUT
2
⎜
⎜
⎟
⎟
(
1− D
)
⎝
⎠
FRHP
2π × L
2
⎛
⎜
⎜
⎞
⎛
⎞
1
2IOUT
(
1− D
)
1
K
⎟
⎟
⎠
⎜
⎟
⎟
FP1 =
FP2 =
+
+
⎜
2π ×COUT VOUT
RMAP KM 1− D
⎝
⎠
⎝
KM RMAP
2π × L
VOUT
2
(
1− D
)
⎛
⎞
IOUT
1
K
⎜
⎜
⎟
⎟
KD = 2 +
+
RMAP
KM 1− D
⎝
⎠
1
KM =
⎛
⎞
1
VPP
⎜
⎜
⎟
⎟
(
0.5− D
)
× RMAP
×
+
L× fSW VOUT
⎝
⎠
VOUT −VIN
0.18 RMAP
⎛
⎝
⎞
VPP =
× 1−
×
⎜
⎟
⎠
L
D
fSW
D
(
1− D
)
K = 0.5× RMAP
×
L× fSW
In order to determine the value of the RCOMP resistor it is
necessary to choose the crossover frequency. Although the
typical target is one-third of the switching frequency, it is
necessary to confirm that this crossover frequency is
significantly below the location of the RHP zero. As a result,
one fifth of the RHP frequency it´s a good approach. Then:
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
30
TYPICAL APPLICATIONS
⎛
⎞
VOUT
IOUT
⎜
⎜
⎟
⎟
2
(
1− D
)
⎝
⎠
FCROSS
=
×
≈18.6 kHz
2π × L
5
Plotting the transfer function of G(s) and locating the
crossover frequency, the DC gain needed for the
compensator can be obtained, as shown in Figure 23.
G0 = 32.42
FCROSS = 18.6 kHz
}
DC gain needed for the
compensator ≈ 4.0627 dB
Figure 23. Transfer Function of G(s).
This DC gain needed for the compensator is actually the
value of G, whose value can be substituted above. As a
result, RCOMP = 126.16 kΩ. A precision 130 kΩ @ 1%
resistor is chosen.
1
CCOMP2
=
≅15 pF
2π × RCOMP × FP
3. Set a zero at one fifth of the crossover frequency that
The steps to calculate the compensation capacitors are as
follows:
compensates the pole, that comes from the output
capacitor and the “load resistor = VOUT OUT,
/I
1. Knowing the frequency of the Right Half Plane Zero,
FCROSS
⎛
⎞
VOUT
IOUT
FZ =
≈ 3.7 kHz
⎜
⎜
⎟
⎟
5
2
⎝
⎠
Then,
FRHPZ
=
×
(
1− D ≈ 92.8 kHz
)
2π × L
2. Set a pole FZ at the Right Half Plane Zero, FP = FRHZP
,
then:
1
CCOMP1
=
≅ 390 pF
2π × RCOMP × FZ
Note: Some jitter (noise) may be present in the switching
frequency of the converter due to certain instability. The
designer should corroborate this effect by using a spectrum
analyzer. Using this instrument, the designer should play with
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
TYPICAL APPLICATIONS
the value of the CCOMP2 capacitor, until acquiring an
appropriate stability of the converter. For the previous design
a 56 pF capacitor was used.
G(s) H(s)
Compensated system
G(s)
Boost converter
H(s)
Compensation network
Figure 24. Plotting the Results for the Transconductance Op-amp Based Compensation Example.
resistor, so the noise can be attenuated properly while the
current sense signal is kept as close as possible to its original
shape (a trapezoid in CCM or a triangle in DCM). The ringing
frequency should be attenuated by 20 dB at least through the
selection of the proper low pass RC filter.
SELECTING THE SLEW RATE OF THE SWITCHING
RATE
The SLEW pin is used to limit the slew on the OUT_SW pin
to reduce noise and avoid EMI problems. If the slew rate is
reduced too much, it will reduce the efficiency of the device.
The slew rate can be changed by tying a resistor from the
SLEW pin to GND. The lower the value of this resistor, the
steeper the rising and the falling times of the switching
frequency. The value of this resistor could be within three
different ranges:
An example: let’s assume that the sense signal (CS)
shows a ringing of 60 MHz, and you want to attenuate it at a
rate of 20 dB per decade. Based on these conditions, the cut-
off frequency (-3.0 dB) of the low pass filter should be set to
6.0 MHz which still allows passing the maximum boost
switching frequency signal of 1.2 MHz. The following formula
is used for calculating the RC components:
• RSLEW < 10 kΩ.
• 10 kΩ ≤ RSLEW < 20 kΩ.
• RSLEW > 20 kΩ.
f_3 db = 1 / (2πRC)
It is important to consider that the value of the resistor (R)
should be no higher than 200 ohms, to avoid adding a
significant offset in the CS signal. A resistor of 180 ohms is
selected for this example. The capacitor (C) of the filter is
then selected as follows:
SELECTING THE CS LOW PASS FILTER TO
REDUCE NOISE.
Since any changes in the PCB layout (track length,
grounding, component connections, etc.) around the
switching FET and the current sense circuitry has an impact
on the PCB parasitics, a low pass RC filter is recommended
to be added at the CS pin for noise reduction.
C = 1 / (2π*180*6E6)
C = 147 pf
Once the filter is added on the CS pin, as shown on figures
20 and 21, measurements should be performed again to
confirm that the noise has been reduced.
The selection of this filter should be made based on the
amplitude and frequency of the ringing across the sense
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
32
TYPICAL APPLICATIONS
• ID should be higher than,
SELECTING SEMICONDUCTORS
Input Protection P-MOSFET
IOUT ΔI
• VDSS should be at least 1.5 times VIN ⇒ VDSS ≥ 1.5 x
21.6 V = 32.4 V.
+
1− D
2
• ID should be higher than IOUT/(1-D) ⇒ ID ≥ 1.67 A
• The pulsed drain current capability of the MOSFET
should be of several tens of amps due to the inrush
current. If this current causes serious problems to the
transistor during turn on, a small capacitor of
approximately 100 nF can be placed in parallel with the
triggering resistor RG1, to minimize and smooth such
an effect.
⇒ ID ≥ 1.67 + 0.33 = 2.0 A
Switching Diode
• VRRM should be at least 1.2 times than VOUT ⇒ VRRM
1.2 x 39 V ≈ 47 V.
• IF-AV should be higher than,
≥
As this transistor will be on at all times, the power
dissipation must be considered (ID2 x RDS-ON), as well as the
thermal dissipation pad.
IOUT ΔI
+
1− D
2
⇒ IF-AV ≥ 1.67 + 0.33 = 2.0 A
Switching MOSFET
• VDSS should be at least 1.5 times VOUT + VD ⇒ VDSS
1.5 x (39 V + 0.7 V) ≈ 60 V
≥
PCB LAYOUT RECOMMENDATIONS
• to know that routing between planes eliminates the
potential for coupling external noise.
• to route other signals al least 5h (microstrip) or 4h
(stripline) away from the differential pairs.
• to know that is it not essential to route them together, if
the traces are inner layered and have the same length.
• to design a PCB with 4 or more layers in order to get
better results on the impedances of the traces
LAYOUT HINTS AND TIPS
• Connect the exposed pad of the IC to the ground planes of
the board using as many vias as possible. These ground
planes must be as large as possible to dissipate the heat
from the IC.
• All references pins, i.e. PGND, AGND and DGND must be
connected together. Their corresponding ground planes
must be joined together with as many vias as possible.
• Try to place all components on just one Layer.
• When tracing differential pairs, it is advisable:
(referenced to a next layer ground plane), as well as to
minimize capacitive and inductive cross talk between
layers. As a result, the following PCB layer stacking is
suggested [3]
:
Ground
Signal/Power
Signal/Power
Ground
Signal/Poured
Ground
Power
Signal/Power
Ground
Signal/Ground
Power
Ground
Signal/Power
Ground
Signal/Poured
Ground
Signal/Power
Ground
Power
Signal/Ground
Figure 25. Recommended PCB Layer Stacking.
• Never trace the Feedback and Control signals like CS,
COMP, SLEW, GD and OVP close to the switching node.
• Make sure that each of the channel traces are capable of
handling the LED currents. As a directly proportional
reference, a 10 mils trace with a thickness of 1.0 oz/ft2 is
capable of handling one ampere.
REFERENCES
[1] MANIKTALA, Sanjaya. Switching Power Supplies A to
Z. US: Newnes, 2006.
[2] ERICKSON, Robert W and MAKSIMOVIC, Dragan.
Fundamentals of Power Electronics, Second Edition,
University of Colorado.
[3] HARTLEY, Rick. Signal Integrity and EMI Control in
High Speed Circuits and PCBs. US: Lectures notes for
Freescale Semiconductor Mexico presentation,2008.
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
EP SUFFIX
48-PIN
98ARH99048A
REVISION F
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
34
PACKAGING
PACKAGE DIMENSIONS
EP SUFFIX
48-PIN
98ARH99048A
REVISION F
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
PACKAGING
PACKAGE DIMENSIONS
EP SUFFIX
48-PIN
98ARH99048A
REVISION F
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
36
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
5/2010
• Initial release
1.0
34848
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
Freescale Semiconductor reserves the right to make changes without further
notice to any products herein. Freescale Semiconductor makes no warranty,
representation or guarantee regarding the suitability of its products for any
particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters that may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer
application by customer’s technical experts. Freescale Semiconductor does
not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other
application in which the failure of the Freescale Semiconductor product could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part.
Beijing 100022
China
+86 10 5879 8000
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or +1-303-675-2140
Fax: +1-303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Freescale™ and the Freescale logo are trademarks of
Freescale Semiconductor, Inc. All other product or service names
are the property of their respective owners.
© Freescale Semiconductor, Inc. 2009. All rights reserved.
MC34848
Rev. 1.0
5/2010
相关型号：
PC34S-1
Board Connector, 34 Contact(s), 2 Row(s), Female, Right Angle, 0.1 inch Pitch, Solder Terminal, Guide Slot, Black Insulator, Plug,
BEL
PC34SFBB-1
Card Edge Connector, 68 Contact(s), 2 Row(s), Straight, 0.156 inch Pitch, Solder Terminal, Receptacle,
AMPHENOL
PC350M0220ST
Aluminum Electrolytic Capacitor, Polarized, Aluminum (wet), 350V, 20% +Tol, 20% -Tol, 220uF, Chassis Mount
YAGEO
©2020 ICPDF网 联系我们和版权申明