PC56651GC [NXP]
16-BIT, 16.8MHz, MIXED DSP, PBGA196, 17 X 17 MM, PLASTIC, BGA-196;
| 型号： | PC56651GC |
| 厂家： | 
NXP |
| 描述： | 16-BIT, 16.8MHz, MIXED DSP, PBGA196, 17 X 17 MM, PLASTIC, BGA-196 时钟 外围集成电路 |
| 文件： | 总76页 (文件大小：523K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document by:
DSP56651/D
Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Rev 0, 6/98
DSP56651
Advance Information
INTEGRATED CELLULAR BASEBAND PROCESSOR
DEVELOPMENT IC
Motorola designed the RAM-based DSP56651 emulation device to support the rigorous
demands of developing applications for the cellular subscriber market. The high level of on-chip
integration in the DSP56651 and its volume production companion device DSP56652 minimizes
application system design complexity and component count, resulting in very compact
implementations. This integration also yields very low-power consumption and cost-effective
system performance. The DSP56651 chip combines the power of Motorola’s 32-bit M• CORE TM
MicroRISC Engine (MCU) and the DSP56600 digital signal processor (DSP) core with on-chip
memory, protocol timer, and custom peripherals to provide a single-chip cellular base-band
processor. Figure 1 shows the basic block diagram of the DSP56651.
Timer/
PWM
Program
Interrupt Timer
Watch
Dog
Edge
I/O
Smart
Card
I/F
External
Memory
M•CORE
MicroRISC
Core
RAM
512 x 32
Keypad
I/F
ROM
4K x 32
Queued
SPI
Clocks
MCU - DSP INTERFACE
UART
MUX
DSP PLL
1K x 16
MESSAGING
RAM
UNIT
MCU
OnCE
DSP56651
DSP
OnCE
X Data
X Data
ROM
56600
DSP
Core
RAM
(7+1)K x 16
9K x 16
Protocol
Timer
Y Data
ROM
9K x 16
Y Data
RAM
8K x 16
Serial Audio
CODEC I/F
Program
RAM
24K x 24
Program
ROM
24K x 24
Baseband
CODEC I/F
AA1617
Figure 1-1 DSP56651 System Block Diagram
Development Part Only—Not intended for production.
Requires a higher voltage than the production part
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preliminary
©1998 MOTOROLA, INC.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
DSP56652
TABLE OF CONTENTS
SECTION 1
SECTION 2
SECTION 3
SECTION 4
SECTION 5
PIN AND SIGNAL DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . .1-1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
FOR TECHNICAL ASSISTANCE:
Telephone:
Email:
1 (800) 521-6274
dsphelp@dsp.sps.mot.com
http:/ / www.motorola-dsp.com
Internet:
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted”
“deasserted”
Examples:
Used to indicate a signal that is active when pulled low; for example, the RESET
pin is active when low
Means that a high true (active high) signal is high or that a low true (active low)
signal is low
Means that a high true (active high) signal is low or that a low true (active low)
signal is high
1
Signal/Symbol
Logic State
Signal State
Voltage
PIN
PIN
PIN
PIN
True
False
True
False
Asserted
Deasserted
Asserted
V / V
IL
OL
OH
OH
OL
V
V
/ V
/ V
IH
IH
Deasserted
V / V
IL
Note:
Values for V , V , V , and V are defined by individual product specifications.
OH
IL
OL
IH
Preliminary
ii
DSP56652 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
DSP56651
Features
FEATURES
RISC M•CORE MCU
•
•
•
•
•
•
32-bit load/ store RISC architecture
Fixed 16-bit instruction length
16-entry 32-bit general-purpose register file
32-bit internal address and data buses
Efficient four-stage, fully interlocked execution pipeline
Single-cycle execution for most instructions, two cycles for branches and memory
accesses
•
•
•
Special branch, byte, and bit manipulation instructions
Support for byte, half-word, and word memory accesses
Fast interrupt support via vectoring/ auto-vectoring and a 16-entry dedicated
alternate register file
High Performance DSP56600 Core
•
•
•
•
•
•
•
•
•
•
1 × engine (e.g., 70 MHz = 70 MIPS)
Fully pipelined 16 × 16-bit parallel multiplier-accumulator (MAC)
Two 40-bit accumulators including extension bits
40-bit parallel barrel shifter
Highly parallel instruction set with unique DSP addressing modes
Position-independent code support
Nested hardware DO loops
Fast auto-return interrupts
On-chip support for software patching and enhancements
Realtime trace capability via address bus visibility mode
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
iii
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
DSP56651
Features
On-chip Memories
•
•
•
•
•
•
4K × 32-bit MCU ROM
512 × 32-bit MCU RAM
24K × 24-bit DSP program ROM
24K × 24-bit DSP program RAM
18K × 16-bit DSP data ROM, split into 9K × 16-bit X and 9K x 16 Y data ROM spaces
16K × 16-bit DSP data RAM, split into (7+1)K × 16-bit X and 8K x 16-bit Y data RAM
spaces
On-chip Peripherals
•
•
•
•
•
Fully programmable phase-locked loop (PLL) for DSP clock generation
External interface module (EIM) for glueless system integration
External 22-bit address and 16-bit data MCU buses
Thirty-two source MCU interrupt controller
Intelligent MCU/ DSP interface (MDI) dual 1K x 16-bit RAM (shares 1K DSP X data
RAM) with messaging status and control
•
•
•
•
•
•
•
•
•
•
•
•
Serial audio codec port
Serial baseband codec port
Protocol timer frees the MCU from radio channel timing events
Queued serial peripheral interface (SPI)
Keypad port capable of scanning up to an 8 × 8 matrix keypad
General-purpose MCU and DSP timers
Pulse width modulation output
Universal asynchronous receiver/ transmitter (UART) with FIFO
IEEE 1149.1-compliant boundary scan JTAG test access port (TAP)
Integrated DSP/ M• CORE On-Chip Emulation (OnCE™) module
DSP address bus visibility mode for system development
ISO 7816-compatible Smart Card port
Preliminary
iv
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
DSP56651
Target Applications
Operating Features:
•
•
•
•
•
Comprehensive static and dynamic power management
M• CORE operating frequency: dc to 16.8 MHz at 2.4 V
DSP operating frequency: dc to 58.8 MHz at 2.4 V
Operating temperature: –40˚ to 85˚C ambient
Package option: 17 × 17 mm, 196-lead PBGA
TARGET APPLICATIONS
The DSP56651 is intended for the development of cellular subscriber applications and other
applications needing both DSP and control processing.
PRODUCT DOCUMENTATION
The four manuals listed in Table 1 are required for a complete description of the DSP56651 and
are necessary to design with the part properly. Documentation is available from a local Motorola
distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or
the World Wide Web.
Table 1 DSP56651 Documentation
Document Name
DSP56600
Description of Contents
Order Number
Detailed description of the DSP56600 family core processor DSP56600FM/ AD
architecture and instruction set
Family Manual
M• CORE Reference
Manual
Detailed description of the M• CORE MCU and instruction MCORERM/ AD
set
DSP56652
User’s Manual
Detailed description of DSP56652 memory, peripherals,
and interfaces, much of which are common to the
DSP56651
DSP56652UM/ AD
DSP56651
Technical Data
DSP56651 pin and package descriptions; electrical and
timing specifications
DSP56651/ D
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
v
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
DSP56651
Product Documentation
Preliminary
vi
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
SECTION 1
PIN AND SIGNAL DESCRIPTIONS
INTRODUCTION
The pins and signals of the DSP56651 are described in the following sections.
Figure 1-1 and Figure 1-2 on page 1-3 are top and bottom views of the package,
respectively, showing the pin-outs. Subsequent tables list the pins by number and
signal name. Figure 1-3 on page 1-11 is a representational pin-out of the chip
grouping the signals by their function. Subsequent tables identify the signals of each
group.
DSP56651 PIN DESCRIPTION
The following section provides information about the available packages for this
product, including diagrams of the package pinouts and tables describing how the
signals of the DSP56651 are allocated for the 196-pin plastic ball grid array (PBGA)
package. Top and bottom views of the PBGA package are shown in Figure 1-1 and
Figure 1-2 on page 1-3 with their pin-outs.
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Pin Description
PBGA Package Description
Top View
1
2
3
4
5
6
7
8
9
10
SRDB GND
E
11
12
13
14
DSP_IRQ
A
B
NC
A20
TOUT0 TOUT3 TOUT6 SPICS4 GND
V
SRDA STDA
NC
H
CCHQ
GND
A18
A17
A15
A12
A7
A21
A19
A16
A11
A9
TOUT2 TOUT7 SPICS1
V
MOSI
SC2B SC0A SCKA PSTAT2 PSTAT1 GND
K
A
CCQ
VCCA
A13
TOUT1 TOUT5
VCCH
GNDQ SCKB STDB SC1A PSTAT3 VCCK PSTAT0 SIZ1
C
D
E
F
MUX_CTL
A14
A10
A6
TOUT4 SPICS3
SCK
MISO
NC
SC1B SC2A
VCCE
RTS
SIZ0
RX
CTS
TX
A8
GND SPICS2 SPICS0
SC0B
GND
GND
TDO
TEST
TDI
VCCA
A5
A2
GND
GND
GND
GND
GND
GND
GND
GND
GND
TCK
DSP_DE
TRST
G
A0
GNDA
A4
A3
GND MCU_DE ROW7 VCCHQ ROW6 TMS
CKIH
GNDF
CKO
CS0
EB1
A1
EB0
CKIL
GND
GNDG
VCCG
VCCQ ROW4 ROW5
H
J
DSP56651
VCCQ
VCCF
CS1
CS2
CS5
D2
VCCHQ CKOH GNDQ
GND
D12
D11
D8
GND
GND
GND
VCCP
GNDQ ROW2 INT7 ROW1 ROW3
K
OE
VCCC
CS4
D0
R/W
D5
D1
D4
D6
GND
GNDD
VCCD
D7
PWR_EN GNDB
SIMCLK VCCB
GND
INT6
INT5
INT4 ROW0
RESET_
IN
PCAP
VCCG
INT0
GNDG
INT3
INT2
INT1
L
SIM
DATA
RESET_
OUT
M
GNDC
CS3
D13
VCCQ
COL1 COL5 COL7
SIM
RESET
N
P
D10
D15
GNDQ
GNDP1 COL0 COL3 COL6
NC
D3
D9
D14
VCCHQ SENSE GNDP
MOD
STO
COL2 COL4
NC
AA1694
Figure 1-1 DSP56651 Plastic Ball Grid Array (PBGA), Top View
Preliminary
1-2
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Pin Description
Bottom View
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DSP_IRQ
A
B
NC
STDA SRDA GND
SRDB
V
GND
H
SPICS4 TOUT6 TOUT3 TOUT0
A20
NC
E
CCHQ
GND
PSTAT1 PSTAT2 SCKA SC0A SC2B
MOSI
V
SPICS1 TOUT7 TOUT2
A21
A19
A16
A11
A9
A18
A17
A15
A12
A7
GND
A
K
CCQ
SIZ1
CTS
PSTAT0
MUX_CTL
TEST
TDI
VCCK
SIZ0
PSTAT3
VCCE
RTS
SC1A STDB SCKB GNDQ
VCCH
TOUT5 TOUT1
VCCA
A13
C
D
E
F
SC2A SC1B
MISO
NC
SCK
SPICS3 TOUT4
A14
A10
A6
TxD
RxD
GND
TDO
SC0B
GND
SPICS0 SPICS2 GND
A8
TRST
DSP_DE
TCK
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D12
D11
D8
A5
A2
VCCA
G
TMS ROW6 VCCHQ ROW7 MCU_DE GND
A3
A4
GNDA
EB1
A0
ROW5 ROW4 VCCQ
VCCG
GNDG
GND
GND
VCCP
CKIL
EB0
A1
CKIH
GNDF
CKO
CS0
H
J
ROW3 ROW1 INT7 ROW2 GNDQ
GNDQ CKOH VCCHQ
VCCQ
VCCF
CS1
CS2
CS5
D2
K
ROW0 INT4
INT5
INT0
INT6
VCCG
GND
GNDB PWR_EN
VCCB SIMCLK
GND
GNDD
VCCD
D7
R/W
D5
D1
D4
D6
OE
VCCC
CS4
D0
RESET_
IN
INT3
INT2
INT1
NC
GNDG
PCAP
L
SIM
DATA
RESET_
OUT
M
COL7 COL5 COL1
VCCQ
D13
D15
GNDC
CS3
SIM
RESET
N
P
COL6 COL3 COL0 GNDP1
GNDQ
D10
D14
COL4 COL2
STO
MOD
GNDP SENSE VCCHQ
D9
D3
NC
AA1695
Figure 1-2 DSP56651 Plastic Ball Grid Array (PBGA), Bottom View
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Pin Description
Table 1-1 DSP56651 PBGA Signal Identification by Pin Number
Pin
Pin
Pin
Signal Name
Signal Name
Signal Name
No.
No.
No.
A1
Not Connected (NC),
reserved
B12 PSTAT2
D9
SC1B
A2
A3
A4
A5
A6
A7
A8
A9
A20
B13 PSTAT1
D10 SC2A
D11
D12 SIZ0
TOUT0
TOUT3
TOUT6
SPICS4
B14 GND
V
CCE
K
C1
C2
C3
C4
C5
C6
C7
C8
C9
V
CCA
A17
A19
D13 MUX_CTL
D14 CTS
GND
TOUT1
TOUT5
E1
E2
E3
E4
E5
E6
E7
E8
E9
A8
H
V
A12
CCHQ
DSP_IRQ
V
A11
CCH
A10 SRDB
A11 GND
GND
A10
Q
SCKB
STDB
GND
SPICS2
SPICS0
NC
E
A12 SRDA
A13 STDA
A14 NC
C10 SC1A
C11 PSTAT3
B1
B2
B3
B4
B5
B6
B7
B8
B9
GND
A18
C12
V
SC0B
A
CCK
C13 PSTAT0
C14 SIZ1
E10 GND
E11 RTS
E12 RxD
E13 TEST
E14 TxD
A21
TOUT2
TOUT7
SPICS1
D1
D2
D3
D4
D5
D6
D7
D8
A13
A15
A16
V
A14
F1
F2
F3
F4
F5
V
CCA
CCQ
MOSI
SC2B
TOUT4
SPICS3
SCK
A7
A9
A6
A5
B10 SC0A
B11 SCKA
MISO
Preliminary
DSP56651 Technical Data Sheet
1-4
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Pin Description
Table 1-1 DSP56651 PBGA Signal Identification by Pin Number (Continued)
Pin
Pin
Pin
Signal Name
Signal Name
Signal Name
No.
No.
No.
F6
GND
GND
GND
GND
H3
A1
J14
ROW3
CKO
F7
F8
F9
H4
H5
H6
H7
H8
H9
EB0
K1
K2
K3
K4
K5
K6
K7
K8
K9
CKIL
GND
GND
GND
GND
V
CCF
OE
F10 TDO
F11 TCK
R/ W
GND
D12
F12 DSP_DE
F13 TDI
H10 GND
PWR_EN
GND
G
F14 TRST
H11
H12
V
V
CCG
CCQ
B
G1
G2
G3
G4
G5
G6
G7
G8
G9
A0
V
CCP
GND
A4
H13 ROW4
H14 ROW5
K10 GND
K11 INT6
K12 INT5
K13 INT4
A
A3
J1
GND
F
A2
J2
V
V
CCQ
CCHQ
GND
GND
GND
GND
J3
K14 ROW0
J4
CKOH
L1
L2
L3
L4
L5
L6
L7
L8
L9
CS0
CS1
J5
GND
GND
GND
GND
GND
GND
Q
J6
V
CCC
G10 MCU_DE
G11 ROW7
J7
D5
J8
GND
D11
D
G12
V
J9
CCHQ
G13 ROW6
G14 TMS
J10
J11
J12
J13
SIMCLK
Q
ROW2
INT7
V
CCB
H1
H2
CKIH
EB1
PCAP
ROW1
L10 RESET_IN
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-5
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Pin Description
Table 1-1 DSP56651 PBGA Signal Identification by Pin Number (Continued)
Pin
Pin
Pin
Signal Name
Signal Name
Signal Name
No.
No.
No.
L11
V
M13 COL7
M14 INT2
P1
NC
D2
D3
D6
D9
D14
CCG
L12 INT0
L13 GND
L14 INT3
P2
P3
P4
P5
P6
P7
P8
P9
N1
N2
N3
N4
N5
N6
N7
N8
N9
CS3
CS5
D0
G
C
M1
M2
M3
M4
M5
M6
M7
M8
M9
GND
CS2
CS4
D1
D4
D7
V
CCHQ
D10
D15
GND
SENSE
GND
V
CCD
P
D8
P10 MOD
P11 STO
P12 COL2
P13 COL4
P14 NC
Q
D13
SIMRESET
V
N10 GND
P1
CCQ
SIMDATA
N11 COL0
N12 COL3
N13 COL6
N14 INT1
M10 RESET_OUT
M11 COL1
M12 COL5
Preliminary
1-6
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Pin Description
Table 1-2 DSP56651 PBGA Signal Identification by Name
Pin
Pin
Pin
Signal Name
Signal Name
Signal Name
No.
No.
No.
A0
A1
G1
H3
G5
G4
G3
F5
CKOH
COL0
COL1
COL2
COL3
COL4
COL5
COL6
COL7
CS0
CS1
CS2
CS3
CS4
CS5
CTS
D0
J4
N11
M11
P12
N12
P13
M12
N13
M13
L1
D9
D10
P5
N6
L6
A2
D11
A3
D12
K6
M7
P6
A4
D13
A5
D14
A6
F4
D15
N7
F12
A9
H4
H2
E10
E5
A7
F2
DSP_DE
DSP_IRQ
EB0
A8
E1
F3
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
CKIH
CKIL
CKO
E4
E3
E2
D1
D4
D2
D3
C2
B2
C3
A2
B3
H1
H5
K1
L2
EB1
M2
N1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M3
N2
F6
F7
D14
N3
F8
F9
D1
M4
P2
G6
G7
G8
G9
H6
H7
H8
H9
D2
D3
P3
D4
N4
D5
L4
D6
P4
D7
N5
D8
M6
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-7
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Pin Description
Table 1-2 DSP56651 PBGA Signal Identification by Name (Continued)
Pin
Pin
Pin
Signal Name
Signal Name
Signal Name
No.
No.
No.
GND
GND
GND
GND
GND
GND
J6
J7
INT2
INT3
M14
L14
K13
K12
K11
J12
RESET_OUT
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
RTS
M10
K14
J13
J8
INT4
J9
INT5
J11
K10
K5
B1
INT6
J14
INT7
H13
H14
G13
G11
E11
E12
B10
E9
GND
GND
GND
GND
GND
GND
MCU_DE
MISO
MOD
G10
D8
A
A
B
C
D
E
G2
K8
M1
L5
P10
B8
MOSI
MUX_CTL
NC
D13
A1
RxD
A11
J1
SC0A
GND
NC
A14
E8
SC0B
F
G
G
H
K
GND
GND
GND
GND
H10
L13
A7
B14
P9
NC
SC1A
C10
D9
NC
P1
SC1B
NC
P14
K3
SC2A
D10
B9
OE
SC2B
GND
PCAP
PSTAT0
PSTAT1
PSTAT2
PSTAT3
PWR_EN
R/ W
L9
SCK
D7
P
GND
N10
C7
J10
J5
C13
B13
B12
C11
K7
SCKA
SCKB
B11
C8
P1
GND
GND
GND
GND
Q
Q
Q
Q
SENSE
SIMCLK
SIMDATA
SIMRESET
SIZ0
P8
L7
N8
L12
N14
M9
N9
INT0
INT1
K4
RESET_IN
L10
D12
Preliminary
1-8
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Pin Description
Table 1-2 DSP56651 PBGA Signal Identification by Name (Continued)
Pin
Pin
Pin
Signal Name
Signal Name
Signal Name
No.
No.
No.
SIZ1
SPICS0
SPICS1
SPICS2
SPICS3
SPICS4
SRDA
SRDB
STDA
STDB
STO
C14
E7
TOUT0
TOUT1
TOUT2
TOUT3
TOUT4
TOUT5
TOUT6
TOUT7
TRST
A3
C4
B4
V
K2
H11
L11
C6
CCF
CCG
CCG
CCH
V
V
V
B6
E6
A4
D5
C5
A5
B5
D6
V
V
V
V
A8
G12
J3
CCHQ
CCHQ
CCHQ
CCHQ
A6
A12
A10
A13
C9
P7
F14
E14
C1
F1
V
C12
K9
CCK
TxD
V
CCP
CCQ
CCQ
CCQ
CCQ
P11
F11
F13
F10
E13
G14
V
V
V
B7
CCA
CCA
TCK
V
V
V
J2
TDI
V
L8
H12
M8
CCB
CCC
CCD
TDO
V
V
L3
TEST
TMS
M5
D11
V
CCE
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-9
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
DSP56651 SIGNAL DESCRIPTION
DSP56651 signals are organized into nineteen functional groups as summarized in
Table 1-3. Figure 1-3 is a diagram of DSP56651 signals by functional group.
Table 1-3 Signal Functional Group Allocations
Number
Detailed
Functional Group
of
Description
Signals
Power (V
)
20
17
20
5
Table 1-4
Table 1-5
CCX
Ground (GND )
X
Substrate ground (GND)
PLL and clocks
Address bus
Table 1-6
Table 1-7
Table 1-8
Table 1-9
Table 1-10
Table 1-11
Table 1-12
Table 1-13
Table 1-14
Table 1-15
Table 1-16
Table 1-17
Table 1-18
Table 1-19
Table 1-20
Table 1-21
Table 1-22
22
16
4
External
Interface
Module
(EIM)
Data bus
Bus control
Chip selects
6
Reset, mode, and multiplexer control
External interrupts
5
9
Timers
8
Keypad port
16
4
Serial data port (UART)
Serial control port (QSPI)
Smart Card port (SIM)
Serial audio codec port (SAP)
Baseband codec port
Emulation port
8
5
6
6
6
Develop-
ment
and Test
Debug control port
2
JTAG test access port (TAP)
6
Preliminary
DSP56651 Technical Data Sheet
1-10
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
6
DSP56651
Power Inputs:
Address Bus
Smart Card
Bus Control
Data Bus
INT0–INT5
Interrupts
Timers
INT6/STDA/DSR or TRST
INT7/SRDA/DTR/SCK or TMS
DSP_IRQ
2
V
V
V
V
CCA
CCB
CCC
CCD
8
TOUT0–TOUT7
V
CCE
Audio Codec
Clock Output
6
5
V
CCF
CCG
COL0–COL5
COL6/OC1
COL7/PWM
ROW0–ROW4
ROW5/IC2B
ROW6/SC2A/DCD or DSP_DE
ROW7/SCKA/RI or TCK
2
4
V
GPIO/Keypad/Int/JTAG/UART/STO
Baseband Codec/Timers/QSPI
Quiet Power High
Emulation Port
PLL
V
CCH
Keypad
Port
V
CCHQ
V
V
V
CCK
CCP
CCQ
4
2
Internal Logic (Quiet)
TxD or TDO
Grounds:
Address Bus
Smart Card
Bus Control
Data Bus
Audio Codec
Clock Output
GPIO/Keypad/Int/JTAG
Baseband Codec/Timers
Emulation Port
PLL
Serial
Data Port
(UART)
RxD/IC1 or TDI
RTS/IC2 or RESET_IN
CTS or MCU_DE
GND
GND
GND
GND
GND
GND
GND
GND
A
B
C
D
5
SPICS0–SPICS4
SCK
MISO
Queued
Serial
Port
E
F
2
G
MOSI
H
SIMCLK
SENSE
SIMDATA
SIMRESET
PWR_EN
GND
GND
GND
K
P
Smart
Card
Port
PLL
P1
4
GND
Internal Logic (Quiet)
Substrate Ground
Q
20
GND
CKIH
STDA
SRDA
SCKA
SC0A–SC2A
PLL and
Clocks
CKIL
CKO
CKOH
PCAP
Serial Audio
Codec Port
3
3
STDB
SRDB
SCKB
SC0B–SC2B
Baseband
Codec
Port
22
16
A0-A21
D0-D15
External Address Bus
External Data Bus
R/W
EB0
EB1
OE
Chip
External
Bus
Control
2
4
SIZ0–SIZ1
PSTAT0–PSTAT3
Emulation
Port
CS0
CS1–CS4
CS5
MCU_DE
DSP_DE
Debug Control
Port
4
Selects
TCK
TDI
TDO
TMS
TRST
TEST
RESET_IN
RESET_OUT
MOD
JTAG
Port
Reset,
Mode, and
Multiplexer
Control
MUX_CTL
STO
AA1690
Figure 1-3 Signals Identified by Functional Group
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-11
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Power
Table 1-4 Power
Power Names
Description
V
V
Address Bus power—These lines supply power to the address bus.
CCA
Smart Card interface power—This line supplies isolated power for Smart Card
CCB
Interface I/ O drivers.
V
V
V
V
Bus control power—This line supplies power to the bus control logic.
Data bus power—These lines supply power to the data bus.
CCC
CCD
CCE
CCF
Audio codec port power—This line supplies power to audio codec I/ O drivers.
Clock output power—This line supplies a quiet power source for the CKOUT
output. Ensure that the input voltage to this line is well-regulated and uses an
extremely low impedance path to tie to the V power rail. Use a 0.1 µF bypass
CC
capacitor located as close as possible to the chip package to connect between the
V
line and the GND line.
CCF
F
V
V
V
GPIO power—This line supplies power to the GPIO, keypad, data port, interrupts,
STO, and JTAG I/ O drivers.
CCG
Baseband codec and timer power—This line supplies power to the baseband codec,
timer and QSPI I/ O drivers.
CCH
Quiet power high—These lines supply a quiet power source to the pre-driver
CCHQ
voltage converters. This value should be greater than or equal to the maximum
value of the power supplies of the chip I/ O drivers (i.e., the maximum of V
,
CCA
V
, V
, V
, V
, V
, V
, V
, and V
).
CCB CCC
CCD
CCE
CCF
CCG
CCH
CCK
V
V
Emulation port power—This line supplies power to the emulation port I/ O drivers.
CCK
Analog PLL circuit power—This line is dedicated to the analog PLL circuits and
must remain noise-free to ensure stable PLL frequency and performance. Ensure
that the input voltage to this line is well-regulated and uses an extremely low
CCP
impedance path to tie to the V power rail. Use a 0.1 µF capacitor and a 0.01 µF
CC
capacitor located as close as possible to the chip package to connect between the
V
line and the GND and GND lines.
CCP
P P1
V
Quiet power—These lines supply a quiet power source to the internal logic circuits.
CCQ
Ensure that the input voltage to this line is well-regulated and uses an extremely low
impedance path to tie to the V power rail. Use a 0.1 µF bypass capacitor located as
CC
close as possible to the chip package to connect between the V
lines and the
CCQ
GND lines.
Q
Preliminary
1-12
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Ground
Table 1-5 Ground
Ground Names
Description
GND
GND
Address Bus ground—These lines connect system ground to the address bus.
A
B
Smart Card interface ground—These lines connect system ground to the Smart
Card bus.
GND
GND
GND
Bus control ground—This line connects ground to the bus control logic.
Data bus ground—These lines connect system ground to the data bus.
C
D
E
Audio codec port ground—These lines connect system ground to the audio codec
port.
GND
Clock output ground—This line supplies a quiet ground connection for the clock
output drivers. Ensure that this line connects through an extremely low impedance
path to ground. Use a 0.1 µF bypass capacitor located as close as possible to the chip
F
package to connect between the V
line and the GND line.
CCF
F
GND
GND
GND
GND
GPIO ground—These lines connect system ground to GPIO, keypad, data port,
interrupts, STO, and JTAG I/ O drivers.
G
H
K
P
Baseband codec and timer ground—These lines connect system ground to the
baseband codec, timer and QSPI I/ O drivers.
Emulation port ground—These lines connect system ground to the emulation port
I/ O drivers.
Analog PLL circuit ground—This line supplies a dedicated quiet ground connection
for the analog PLL circuits and must remain relatively noise-free to ensure stable
PLL frequency and performance. Ensure that this line connects through an
extremely low impedance path to ground. Use a 0.1 µF capacitor and a 0.01 µF
capacitor located as close as possible to the chip package to connect between the
V
line and the GND line.
CCP
P
GND
Analog PLL circuit ground—This line supplies a dedicated quiet ground connection
for the analog PLL circuits and must remain relatively noise-free to ensure stable
PLL frequency and performance. Ensure that this line connects through an
extremely low impedance path to ground. Use a 0.1 µF capacitor and a 0.01 µF
capacitor located as close as possible to the chip package to connect between the
P1
V
line and the GND line.
CCP
P
GND
GND
Quiet ground—These lines supply a quiet ground connection for the internal logic
circuits. Ensure that this line connects through an extremely low impedance path to
ground. Use a 0.1 µF bypass capacitor located as close as possible to the chip
Q
package to connect between the V
line and the GND line.
CCQ
Q
Substrate ground—These lines must be tied to ground.
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-13
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
PLL and Clock
Table 1-6 PLL and Clock Signals
State
Signal
Name
Signal
Type
during
Reset
Signal Description
CKIH
Input
Input
Input
High frequency clock input—This signal provides the high frequency
input clock. This clock may be other a CMOS square wave or sinusoid
input.
CKIL
CKO
Input
Low frequency clock input—This signal provides the low frequency
input clock and should be less than or equal to the frequency of CKIH.
This is the default input clock after reset.
Output Driven
low
DSP/MCU output clock—This signal provides an output clock
synchronized to the DSP or MCU core internal clock phases, according
the selected programming option. The choices of clock source and
enabling/ disabling the output signal are software selectable.
CKOH
PCAP
Output Driven
low
High frequency clock output—This signal provides an output clock
derived from the CKIH input. This signal can be enabled or disabled
by software.
Input/
Indeter-
PLL capacitor—This signal is used to connect the required external
Output minate
filter capacitor to the PLL filter. Connect one end of the capacitor to
PCAP and the other to V
. The value of the capacitor is specified in
CCP
Section 2 of this data sheet.
Address Bus
Table 1-7 Address Bus Signals
State
during
Reset
Signal
Names
Signal
Signal Description
Type
A0–A21
Output
Driven
low
Address bus—These signals specify the address for external
memory accesses. If there is no external bus activity, A0–A21
remain at their previous values to reduce power consumption.
Preliminary
1-14
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Data Bus
Table 1-8 Data Bus Signals
State
during
Reset
Signal
Names
Signal
Type
Signal Description
D0–D15
Input/
Output
Input
Data bus—These signals provide the bidirectional data bus for
external memory accesses. D0–D15 are held in the previous logic
state when there is no external bus activity and during hardware
reset. This is done with weak “keepers” inside the I/ O buffers.
Bus Control
Table 1-9 Bus Control Signals
State
Signal Signal
during
Reset
Signal Description
Name
Type
R/ W
Output Driven
high
Read/write—This signal indicates the bus access type. A high signal
indicates a bus read. A low signal indicates a write to the bus. When
accessing memory it can also be used as write enable (WE) signal. When
accessing a peripheral chip, the signal acts as a read/ write.
EB0
EB1
OE
Output Driven
high
Enable byte 0—When driven low, this signal indicates access to data
byte 0 (D8–D15) during a read or write cycle. This pin may also act as a
write byte enable, if so programmed. This output is used when accessing
16-bit wide SRAM.
Output Driven
high
Enable byte 1—When driven low, this signal indicates access to data
byte 1 (D0–D7) during a read or write cycle. This pin may also act as a
write byte enable, if so programmed. This output is used when accessing
16-bit wide SRAM.
Output Driven
high
Bus select—When driven low, this signal indicates that the current bus
access is a read cycle and enables slave devices to drive the data bus with
a read.
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-15
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Chip Selects
Table 1-10 Chip Select Signals
State
during
Reset
Signal
Type
Signal Name
Signal Description
CS0
Output Chip-
driven
Chip select 0—This signal is asserted low based on the decode of the
internal address bus bits A[31:24] and is typically used as the external
flash memory chip select. After reset, accesses using this CS have a
default of 15 wait states.
CS1–CS4
Output Driven
high
Chip select 1–chip select 4—These signals are asserted low based
on the decode of the internal address bus bits A[31:24] of the access
address.
When not selected as chip select signals, these signals become
general purpose outputs (GPOs). After reset, these signals are
GPOs that are driven high.
CS5
Output Driven
low
Chip select 5—This signal is asserted high based on the decode of
the internal address bus bits A[31:24] of the access address.
When not selected as a chip select signal, this signal becomes a
GPO. After reset, this signal is a GPO that is driven low.
Preliminary
1-16
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Reset, Mode, and Multiplexer Control
Table 1-11 Reset, Mode, and Multiplexer Control Signals
State
during
Reset
Signal
Type
Signal Name
Signal Description
RESET_IN
Input
Input
Reset input—This signal is an active low Schmitt trigger input
that provides a reset signal to the internal circuitry. The input is
valid if it is asserted for at least three CKIL clock cycles.
This pin has a 47kΩ pull-up resistor.
Note: If MUX_CTL is held high, the RTS signal of the serial data
port (UART) becomes the RESET_IN input line.
(See Table 1-15 on page 1-26.)
RESET_OUT
Output Pulled
low
Reset output—This signal is asserted low for at least seven CKIL
clock cycles under one of the following conditions:
•
•
•
RESET_IN is pulled low for at least three CKIL clock
cycles
The alternate RESET_IN signal is enabled by MUX_CTL
and is pulled low for at least three CKIL clock cycles
The watchdog count expires
This signal is asserted immediately after the qualifier detects a
valid RESET_IN signal, remains asserted during RESET_IN
assertion, and is stretched for at least seven more CKIL clock
cycles after RESET_IN is deasserted. Three CKIL clock cycles
before RESET_OUT is deasserted, the MCU boot mode is latched
from the MOD signal.
MOD
Input
Input
Mode select—This signal selects the MCU boot mode during
hardware reset. If MOD is driven low at least four CKIL clock
cycles before RESET_OUT is deasserted, then the internal MCU
ROM ignores the first access and the M• CORE fetches the first
word from the first location the external flash memory. If MOD is
driven high four CKIL clock cycles before RESET_OUT
deassertion, then the internal MCU ROM is enabled and the
M• CORE fetches the first word from the first location in the
internal ROM.
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-17
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Table 1-11 Reset, Mode, and Multiplexer Control Signals (Continued)
State
Signal
Signal Name
during
Reset
Signal Description
Type
MUX_CTL
Input
Input
Multiplexer control—This input allows the designer to select an
alternate set of pins to be used for RESET_IN, the debug control
port signals, and the JTAG signals as defined below:
Normal
(MUX_CTL low)
Alternate
(MUX_CTL high)
TRST
INT6/ STDA/ DSR
INT7/ SRDA/ DTR/ SCLK
Interrupt signals
(See Table 1-12)
TMS
Keypad signals ROW6/ SC2A/ DCD
DSP_DE
(See Table 1-14
on page 1-22)
ROW7/ SCKA/ RI
TCK
TxD
TDO
TDI
RESET_IN
MCU_DE
Serial Data Port
(UART) signals
(See Table 1-15
on page 1-26)
RxD/ IC1
RTS/ IC2A
CTS
If MUX_CTL is driven low, the normal functions are selected. If
MUX_CTL is driven high, the alternate functions are selection.
Note: The user is responsible to ensure that transition between
normal and alternate functions are made smoothly. No
provisions are made in the on-chip hardware to assure
such a smooth switch. The external command converter
uses to drive this signal must ensure that critical pins
(such as the JTAG TMS and TRST signals and RESET_IN)
are driven with inactive values during and after the
switch.
The MUX_CTL signal has an internal 100 kΩ pull-down resistor.
STO
Output Chip
driven
Soft turn off—This is a general purpose output pin. Its logic state
is not affected by reset.
For Reset, mode, and MUX control signals equipped with resistors, all pull-ups and
pull-downs are automatically disconnected when the pin is an output.
Preliminary
1-18
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Interrupts
Table 1-12 Interrupt Signals
State
during
Reset
Signal
Name
Signal
Type
Signal Description
INT0–INT3 Input or Input
Output
Interrupt 0–interrupt 3—These signals can be programmed as
interrupt inputs or GPIO signals. The signals have on-chip 100 kΩ
pull-up resistors.
As Schmitt trigger interrupt inputs the signals can be programmed
to be level sensitive, positive edge-triggered, or negative edge-
triggered. When edge-triggered, triggering occurs at a voltage level
and is not directly related to the fall time of the interrupt signal;
however, as signal fall time of the interrupt signal increases, the
probability of generating multiple interrupts due to this noise also
increases.
The signals are GPIOs when not programmed as interrupts. After
reset, the default state for these signals is general purpose input
(GPI).
INT4–INT5 Input or Input
Output
Interrupt 4–interrupt 5—These signals can be programmed as
interrupt inputs or GPIO signals, and have 10-27kΩ pull-up
resistors.
As Schmitt trigger interrupt inputs, the signals can be programmed
to be level sensitive, positive edge-triggered, or negative edge-
triggered. When edge-triggered, triggering occurs at a voltage level
and is not directly related to the fall time of the interrupt signal;
however, as signal fall time of the interrupt signal increases, the
probability of generating multiple interrupts due to this noise also
increases.
The signals are GPIOs when not programmed as interrupts. After
reset, the default state for these signals is GPI.
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-19
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Table 1-12 Interrupt Signals (Continued)
State
Signal
Name
Signal
Type
during
Reset
Signal Description
Normal:
MUX_CTL driven low
INT6
Input or Input
Output
Interrupt 6—When selected, this signal can be programmed as an
interrupt input or a GPIO signal, and has a 47kΩ pull-up resistor.
As a Schmitt trigger interrupt input, the signal can be programmed
to be level sensitive, positive edge-triggered, or negative edge-
triggered. When edge-triggered, triggering occurs at a voltage level
and is not directly related to the fall time of the interrupt signal;
however, as signal fall time of the interrupt signal increases, the
probability of generating multiple interrupts due to this noise also
increases.
STDA
DSR
Output
Output
Audio codec serial transmit data (alternate)—When programmed
as STDA, this signal transmits data from the serial transmit shift
register in the serial audio codec port.
Note: When this signal is used as STDA, the primary STDA signal
is disabled. (See Table 1-18 on page 1-31.)
Data set ready—When programmed as GPIO output, this signal can
be used as the DSR output for the serial data port. (See Table 1-15
on page 1-26)
The signal is a GPIO when not programmed as one of the above
functions. After reset, the default state for this signal is GPI.
Alternate:
MUX_CTL driven high
TRST
Input
Input
Test Reset—When selected, this signal acts as the TRST input for the
JTAG TAP controller. The signal is a Schmitt trigger input that
asynchronously initializes the JTAG test controller when asserted.
Note: When this signal is enabled, the primary TRST signal is
disconnected from the TAP controller. (See Table 1-22.)
Preliminary
1-20
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Table 1-12 Interrupt Signals (Continued)
State
Signal
Name
Signal
Type
during
Reset
Signal Description
Normal:
MUX_CTL driven low
INT7
Input or Input
Output
Interrupt 7—When selected, this signal can be programmed as an
interrupt input or a GPIO signal, and has a 47kΩ pull-up resistor.
As a Schmitt trigger interrupt input, the signal can be programmed
to be level sensitive, positive edge-triggered, or negative edge-
triggered. When edge-triggered, triggering occurs at a voltage level
and is not directly related to the fall time of the interrupt signal;
however, as signal fall time of the interrupt signal increases, the
probability of generating multiple interrupts due to this noise also
increases.
SRDA
Input
Audio codec serial receive data (alternate)—When programmed as
SRDA, this signal receives data into the serial receive shift register in
the serial audio codec port.
Note: When this signal is used as SRDA, the primary SRDA signal
is disabled. (See Table 1-18 on page 1-31.)
DTR
Input
Input
Data terminal ready—When programmed as GPIO, this signal is
used as the DTR positive and negative edge-triggered interrupt
input for the serial data port. (See Table 1-15 on page 1-26.)
SCLK
Serial clock–When so programmed, this signal provides the input
clock for the serial data port (UART). (See Table 1-15 on page 1-26.)
The signal is a GPIO when not programmed as one of the above
functions. After reset, the default state for this signal is GPI.
Alternate:
MUX_CTL driven high
TMS
Input
Input
Test mode select—When selected, this signal acts as the TMS input
for the JTAG TAP controller. The signal is used to sequence that
TAP controller state machine. The TMS is sampled on the rising
edge of TCK.
Note: When this signal is enabled, the primary TMS signal is
disconnected from the TAP controller. (See Table 1-22
on page 1-36.)
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-21
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Table 1-12 Interrupt Signals (Continued)
State
Signal
Name
Signal
Type
during
Reset
Signal Description
DSP_IRQ
Input
Input
DSP external interrupt request—This active low Schmitt trigger
input can be programmed as a level-sensitive or negative edge-
triggered maskable interrupt request input during normal
instruction processing. If the DSP is in the stop state and DSP_IRQ is
asserted, the DSP exits the stop state.
This signal has an on-chip 47 kΩ pull-up resistor.
For Interrupt signals equipped with resistors, all pull-ups and pull-downs are
automatically disconnected when the pin is an output.
Timers
Table 1-13 Timer Signals
State
Signal
Signal Name
during
Reset
Signal Description
Type
TOUT0–
TOUT7
Input or Input
Output
Timer output 0–7—These are timer output signals.
After reset, the default state for these signals is GPI.
Note: These signals are GPIOs when not used as timer outputs.
Keypad Port
Table 1-14 Keypad Port Signals
State
during
Reset
Signal
Type
Signal Name
Signal Description
COL0–COL5 Input or Input
Output
Column strobe 0–5—These signals function as keypad column
strobes that can be programmed as regular or open-drain outputs.
When not used as column strobe signals, these are GPIO signals.
After reset, the default state is GPI.
Preliminary
1-22
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Table 1-14 Keypad Port Signals (Continued)
State
during
Reset
Signal
Type
Signal Name
COL6
Signal Description
Input or Input
Output
Column strobe 6—This signal functions as a keypad column strobe
that can be programmed as a regular or open-drain output.
OC1
Output
MCU timer 1 output compare —When programmed as OC1, this is
the MCU Timer 1 output compare signal.
When not programmed as OC1 and not used as a column strobe
signal, this is a GPIO signal. After reset, the default state is GPI
COL7
PWM
Input or Input
Output
Column strobe 7—This signal functions as a keypad column strobe
that can be programmed as a regular or open-drain output.
Output
Pulse width modulator output—When so programmed, this is the
pulse width modulator output.
When not programmed as PWM and not used as a column strobe
signal, this is a GPIO signal. After reset, the default state is GPI
ROW0–
ROW4
Input or Input
Output
Row sense 0–4—These signals function as keypad row senses.
When not used as Row Sense signals, these are GPIO signals. After
reset, the default state is GPI. These signals have on-chip 22 kΩ pull-
up resistors.
ROW5
IC2B
Input or Input
Output
Row sense 5—This signal functions as a keypad row sense.
Input
MCU input compare 2 timer—When so programmed, this signal
can be the input capture for the MCU input compare 2 timer.
When not programmed as IC2B and not used as a row sense signal,
this is a GPIO signal. After reset, the default state is GPI.
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-23
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Table 1-14 Keypad Port Signals (Continued)
State
Signal
Type
Signal Name
during
Reset
Signal Description
Normal:
MUX_CTL driven low
ROW6
Input or Input
Output
Row sense 6—This signal functions as a keypad row sense and is
equipped with an on-chip 100kΩ pull-up resistor.
SC2A
Input or
Output
Audio codec serial control 2 (alternate)—When programmed as
SC2A, this signal provides I/ O frame synchronization for the serial
audio codec port. In synchronous mode, the signal provides the
frame sync for both the transmitter and receiver. In asynchronous
mode, the signal provides the frame sync for the transmitter only.
As SC2A, this pin has a 100kΩ pull-down resistor.
Note: When this signal is used as SC2A, the primary SC2A signal
is disabled. (See Table 1-18 on page 1-31.)
DCD
Output
Data Carrier Detect—When programmed as GPIO output, this
signal can be used as the DSR output for the serial data port. (See
Table 1-15 on page 1-26.) After reset, the default state is GPI.
Alternate:
MUX_CTL driven high
DSP_DE
Input
Input
Digital signal processor debug event—As an input signal, this
signal provides a means to enter the debug mode of operation from
an external command converter. An an output signal, it acknow-
ledges that the DSP has entered the debug mode. When program-
med as DSP_DE, this signal has an open-drain 100kΩ pull-up.
Output
When the DSP enters the debug mode due to a debug request or as
the result of meeting a breakpoint condition, it asserts DSP_DE as
an output signal for three clock cycles.
Note: When this signal is enabled, the primary DSP_DE signal is
disabled. (See Table 1-21 on page 1-35.)
Preliminary
1-24
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Table 1-14 Keypad Port Signals (Continued)
State
during
Reset
Signal
Type
Signal Name
Signal Description
Normal:
MUX_CTL driven low
ROW7
Input or Input
Output
Row sense 7—This signal functions as a keypad row sense.
Audio codec serial clock (alternate)—When programmed as SCKA,
this signal provides the serial bit rate clock for the serial audio codec
port. In synchronous mode, the signal provides the clock input or
output for both the transmitter and receiver. In asynchronous mode,
the signal provides the clock for the transmitter only.
SCKA
Input
Note: When this signal is used as SCKA, the primary SCKA signal
is disabled. (See Table 1-18 on page 1-31.)
Ring indicator—When programmed as GPIO output, this signal
can be used as the RI output for the serial data port. (See
Table 1-15.) After reset, the default state is GPI.
RI
Output
Alternate:
MUX_CTL driven high
TCK
Input
Input
Test clock—When selected, this signal provides the TCK input for
the JTAG TAP controller. The signal is used to synchronize the
JTAG test logic. This signal is equipped with a 47kΩ pull-up
resistor.
Note: When this signal is enabled, the primary TCK signal is
disconnected from the TAP controller. (See Table 1-22
on page 1-36.)
For keypad port signals equipped with resistors, all pull-ups and pull-downs are
automatically disconnected when the pin is an output.
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-25
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Serial Data Port (UART)
Table 1-15 Serial Data Port (UART) Signals
State
during
Reset
Signal
Type
Signal Name
Signal Description
Normal:
MUX_CTL driven low
TxD
Input or Input
Output
UART transmit—This signal transmits data from the UART.
The signal is a GPIO when not programmed as the TxD signal. After
reset, the default state for this signal is GPI.
Alternate:
MUX_CTL driven high
TDO
Output
Test data output—When selected, this signal provides the TDO
serial output for test instructions and data from the JTAG TAP
controller. TDO is a tri-state signal that is actively driven in the
shift-IR and shift-DR controller states.
Note: When this signal is enabled, the primary TDO signal is
disconnected from the TAP controller. (See Table 1-22
on page 1-36.)
Normal:
MUX_CTL driven low
RxD
Input or Input
Output
UART receive—This signal receives data into the UART.
IC1
Input
Input compare 1—When so programmed, the signal connects to an
input capture/ output compare timer used for autobaud mode
support.
The signal is a GPIO when not programmed as one of the above
functions. This signal has an on-chip 47 kΩ pull-up resistor. After
reset, the default state for this signal is GPI.
Alternate:
MUX_CTL driven high
TDI
Input
Input
Test data in—When selected, this signal provides the TDI serial
input for test instructions and data for the JTAG TAP controller. TDI
is sampled on the rising edge of TCK.
Note: When this signal is enabled, the primary TDI signal is
disconnected from the TAP controller. (See Table 1-22
on page 1-36.)
Preliminary
1-26
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Table 1-15 Serial Data Port (UART) Signals (Continued)
State
during
Reset
Signal
Type
Signal Name
Signal Description
Normal:
MUX_CTL driven low
RTS
Input or Input
Output
Request to send—This signal functions as the UART RTS signal.
IC2A
Input
Input compare 2 A—When so programmed, this signal connects to
an input capture timer channel.
The signal is a GPIO when not programmed as one of the above
functions. After reset, the default state for this signal is GPI.
Alternate:
MUX_CTL driven high
RESET_IN
Input
Input
Reset input—This signal is an active low Schmitt trigger input that
provides a reset signal to the internal circuitry. The input is valid if
it is asserted for at least three CKIL clock cycles.
Note: When this signal is enabled, the primary RESET_IN signal
is disabled. (See Table 1-11 on page 1-17.)
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-27
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Table 1-15 Serial Data Port (UART) Signals (Continued)
State
Signal
Type
Signal Name
during
Reset
Signal Description
Normal:
MUX_CTL driven low
CTS
Input or Input
Output
Clear to send—This signal functions as the UART CTS signal, and is
equipped with a 47kΩ pull-up.
After reset, the default state for this signal is GPI.
Note: The signal is a GPIO when not used as CTS.
Alternate:
MUX_CTL driven high
MCU_DE
Input
Input
Microcontroller debug event—As an input signal, this signal
provides a means to enter the debug mode of operation from an
external command converter. An an output signal, it acknowledges
that the MCU has entered the debug mode. The signal is equipped
with an open-drain 47kΩ pull-up resistor.
Output
When the MCU enters the debug mode due to a debug request or as
the result of meeting a breakpoint condition, it asserts MCU_DE as
an output signal for several clock cycles.
Note: When this signal is enabled, the primary MCU_DE signal is
disabled. (See Table 1-21.)
Note: There are four additional signals that support UART operation, provided as follows:
•
•
•
•
DSR—data set ready. This is an alternate function for the INT6 signal. (See Table 1-12
on page 1-19.)
DTR—data terminal ready. This is an alternate function for the INT7 signal. (See Table 1-12
on page 1-19.)
DCD—data carrier detect. This is an alternate function for the ROW6 signal. (See Table 1-14
on page 1-22.)
RI—ring indicator. This is an alternate function for the ROW7 signal. (See Table 1-14
on page 1-22.)
For serial data port (UART) signals equipped with resistors, all pull-ups and
pull-downs are automatically disconnected when the pin is an output.
Preliminary
1-28
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Serial Control Port
Table 1-16 Serial Control Port Signals
State
Signal
Signal Name
Type
during
Reset
Signal Description
SPICS0–
SPICS3
Output Input
Synchronous peripheral chip select 0–3—The output signals
provide chip select signals for the queued serial peripheral interface
(QSPI). The signals are programmable as active high or active low.
Each signal has an on-chip 100 kΩ pull-up resistor.
Input or
Output
These are GPIO signals when the chip select functions are not being
used. After reset, the default state for each signal is GPI.
SPICS4
Output Input
Synchronous peripheral chip select 4—This output signal provides
a chip select signal for the QSPI. This signal is programmable as
active high or active low. This signal has an on-chip 100 kΩ pull-
down resistor.
Input or
Output
This is a GPIO signal when the chip select function is not being
used. After reset, the default state is GPI.
SCK
Output Input
Serial clock — This output signal provides the serial clock from the
QSPI for the accessed peripherals. There is a programmable number
of clock cycles delay between the assertion of the chip select signal
and the first transmission of the serial clock. The polarity and phase
of SCK are programmable.
Input or
Output
This is a GPIO signal when the SCK function is not being used.
After reset, the default state is GPI.
MISO
MOSI
Input
Input
Synchronous master in slave out—This input signal provides serial
data input to the QSPI. Input data can be sampled on the rising or
falling edge of SCK and received in QSPI RAM MSB or LSB first.
This is a GPIO signal when the function is not being used. After
reset, the default state is GPI.
Input or
Output
Output Input
Synchronous master out slave in—This output signal provides
serial data from the QSPI. Output data can be sampled on the rising
or falling edge of SCK and transmitted MSB or LSB first.
This is a GPIO signal when the function is not being used. After
reset, the default state is GPI.
Input or
Output
For serial control port signals equipped with resistors, all pull-ups and pull-downs
are automatically disconnected when the pin is an output.
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-29
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Smart Card Port
After rest, the default state of all Smart Card port pins is GPI. For Smart Card port
signals equipped with resistors, all pull-ups and pull-downs are automatically
disconnected when the pin is an output.
Table 1-17 Smart Card Port Signals
State
Signal
Signal Name
during
Reset
Signal Description
Type
SIMCLK
Output Input
SIM clock—This signal is an output clock from the Smart Card port
to the Smart Card.
Input or
Output
This signal is a GPIO signal when the Smart Card Port is not being
used.
SENSE
Input
Input
Input
SIM sense—This signal is a Schmitt trigger input that signals when
a Smart Card is inserted or removed.
Input or
Output
This signal is a GPIO signal when the Smart Card port is not being
used. The signal has an on-chip 100 kΩ pull-down resistor.
SIMDATA
Input/
Output
SIM data—This bidirectional signal is used to transmit data to and
receive data from the Smart Card. In the output state, the signal is
open-drain.
Input or
Output
This signal is a GPIO signal when the Smart Card port is not being
used. The signal has an on-chip 47 kΩ pull-up resistor.
SIMRESET
PWR_EN
Output Input
SIM reset—This signal is an output reset signal from the Smart
Card port to the Smart Card. The Smart Card port can activate the
reset of an attached Smart Card by driving SIMRESET low.
Input or
Output
This signal is a GPIO signal when the Smart Card port is not being
used.
Output Input
SIM power enable—This active high output enables the external
device that supplies V to the Smart Card. If this pin is driven
CC
high, the external device supplies power to the Smart Card. Driving
the signal low cuts off power to card. This permits effective power
management and power sequencing for Smart Card enable/ disable.
Input or
Output
This signal is a GPIO signal when the Smart Card port is not being
used. This signal has an on-chip 100 kΩ pull-down resistor.
Preliminary
1-30
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Serial Audio Codec Port
After reset, the default state of all serial audio codec pins is Hi-Z. For serial audio
codec port signals equipped with resistors, all pull-ups and pull-downs are
automatically disconnected when the pin is an output.
Table 1-18 Serial Audio Codec Port Signals
State
Signal
Signal Name
during
Reset
Signal Description
Type
STDA
Input or Input
Output
Audio codec transmit data— This output signal transmits serial
data from the audio codec serial transmitter shift register. It is
equipped with a 100kΩ pull-up resistor.
This is a GPIO signal when STDA is not being used.
Note: This signal is disabled if the alternate STDA function on
INT6 is selected. (See Table 1-12 on page 1-19.)
SRDA
SCKA
Input or Input
Output
Audio codec receive data — This input signal receives serial data
and transfers the data to the audio codec receive shift register. It is
equipped with a 100kΩ pull-down resistor.
This is a GPIO signal when SRDA is not being used.
Note: This signal is disabled if the alternate SRDA function on
INT7 is selected. (See Table 1-12 on page 1-19.)
Input or Input
Output
Audio codec serial clock — This bidirectional signal provides the
serial bit rate clock when only one clock is being used or the TxD
clock otherwise. It is equipped with a 100kΩ pull-down resistor.
This is a GPIO signal when the serial audio codec port is not being
used.
Note: This signal is disabled if the alternate SCKA function on
ROW7 is selected. (See Table 1-14 on page 1-22.)
SC0A
SC1A
Input or Input
Output
Audio codec serial clock 0—This signal’s function is determined by
the SCLK mode.
•
•
Synchronous mode—serial I/ O flag 0
Asynchronous mode—receive clock I/ O
This is a GPIO signal when SC0A is not being used.
Input or Input
Output
Audio codec serial clock 1—This signal’s function is determined by
the SCLK mode.
•
•
Synchronous mode—serial I/ O flag 0
Asynchronous mode—receiver frame sync I/ O
This is a GPIO signal when SC1A is not being used.
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-31
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Table 1-18 Serial Audio Codec Port Signals (Continued)
State
Signal
Type
Signal Name
during
Reset
Signal Description
SC2A
Input or Input
Output
Audio codec serial clock 2—This signal’s function is determined by
the SCLK mode.
•
•
Synchronous mode—transmitter and receiver frame sync I/ O
Asynchronous mode—transmitter frame sync I/ O
It is equipped with a 100kΩ pull-down resistor.
This is a GPIO signal when SC2A is not being used.
Note: This signal is disabled if the alternate SC2A function on
ROW6 is selected. (See Table 1-14 on page 1-22.)
Baseband Codec Port
After reset, the default state of the baseband codec port pins is Hi-Z. For baseband
codec port signals equipped with resistors, all pull-ups and pull-downs are
automatically disconnected when the pin is an output.
Table 1-19 Baseband Codec Port Signals
State
Signal
Signal Name
during
Reset
Signal Description
Type
STDB
Output Input
Baseband codec transmit data— This output signal transmits serial
data from the baseband codec serial transmitter shift register. This
signal is equipped with a 100 pull-up resistor.
Input or
Output
This is a GPIO signal when STDB is not being used.
SRDB
SCKB
Input
Input
Baseband codec receive data — This input signal receives serial
data and transfers the data to the baseband codec receive shift
register. This signal is equipped with a 100kΩ pull-down resistor.
Input or
Output
This is a GPIO signal when SRDB is not being used.
Input or Input
Output
Baseband codec serial clock — This bidirectional signal provides
the serial bit rate clock when only one clock is being used or the TxD
clock otherwise. This signal is equipped with a 100kΩ pull-down
resistor. This is a GPIO signal when the serial baseband codec port
is not being used.
Preliminary
1-32
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Table 1-19 Baseband Codec Port Signals (Continued)
State
during
Reset
Signal
Type
Signal Name
Signal Description
SC0B
Input or Input
Output
Baseband codec serial clock 0—This signal’s function is determined
by the SCLK mode.
•
•
Synchronous mode—serial I/ O flag 0
Asynchronous mode—receive clock I/ O
This signal is equipped with a 100kΩ pull-down resistor.
This is a GPIO signal when SC0B is not being used.
SC1B
SC2B
Input or Input
Output
Baseband codec serial clock 1—This signal’s function is determined
by the SCLK mode.
•
•
Synchronous mode—serial I/ O flag 0
Asynchronous mode—receiver frame sync I/ O
This signal is equipped with a 100KkΩ pull-down resistor.
This is a GPIO signal when SC1B is not being used.
Input or Input
Output
Baseband codec serial clock 2—This signal’s function is determined
by the SCLK mode.
•
•
Synchronous mode—transmitter and receiver frame sync I/ O
Asynchronous mode—transmitter frame sync I/ O
This signal is equipped with a 100kΩ pull-down resistor.
This is a GPIO signal when SC2B is not being used.
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-33
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Emulation Port
After reset, the default state for the emulation port pins is GPI.
Table 1-20 Emulation Port Signals
State
Signal
Signal Name
during
Reset
Signal Description
Type
SIZ0–SIZ1
Input or Input
Output
Data size 0–1—These signals encode the data size for the current
MCU access.
When not programmed as data size signals, these are GPIO signals.
The signals have on-chip 100 kΩ pull-up resistors.
PSTAT0–
PSTAT3
Input or Input
Output
Pipeline state 0–3—These signals encode the internal MCU
execution unit status.
When not programmed as pipeline state signals, these are GPIO
signals. The signals have on-chip 100 kΩ pull-up resistors.
Preliminary
1-34
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
Debug Port Control
If the MUX_CTL signal is driven high, the alternate MCU_DE and DSP_DE signal locations
are selected, and this interface is disabled. For debug port control signals equipped with
resistors, all pull-ups and pull-downs are automatically disconnected when the pin is
an output
Table 1-21 Debug Port Control Signals
State
Signal
Signal Name
during
Reset
Signal Description
Type
MCU_DE
Input
Input
Microcontroller debug event—As an input signal, this signal
provides a means to enter the debug mode of operation from an
external command converter. An an output signal, it acknowledges
that the MCU has entered the debug mode. This signal is equipped
with an open-drain 47kΩ pull-up resistor.
Output
Input
When the MCU enters the debug mode due to a debug request or as
the result of meeting a breakpoint condition, it asserts MCU_DE
as an output signal for three clock cycles.
DSP_DE
Input
Digital signal processor debug event—As an input signal, this
signal provides a means to enter the debug mode of operation from
an external command converter. An an output signal, it acknow-
ledges that the DSP has entered the debug mode.This signal is
equipped with an open-drain 4kΩ K pull-up resistor.
Output
When the DSP enters the debug mode due to a debug request or as
the result of meeting a breakpoint condition, it asserts DSP_DE as
an output signal for three clock cycles.
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
1-35
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Pin and Signal Descriptions
DSP56651 Signal Description
JTAG Port
When the bottom connector pins are selected as a debug port by holding the
MUX_CTL pin at a logic high, the dedicated JTAG pins become inactive. That is, they
are disconnected from the JTAG TAP controller. For JTAG signals equipped with
resistors, all pull-ups and pull-downs are automatically disconnected when the pin is
an output.
Table 1-22 JTAG Port Signals
State
Signal
Signal Name
during
Reset
Signal Description
Type
TMS
Input
Input
Test mode select—TMS is an input signal used to sequence the test
controller’s state machine. TMS is sampled on the rising edge of
TCK and has an internal 47 kΩ pull-up resistor.
MUX_CTL high: INT7 is connected to the JTAG TAP controller and
functions as TMS, see Table 1-12 on page 1-19.)
TDI
Input
Input
Test data input—TDI is a serial test data input signal used for test
instructions and data. TDI is sampled on the rising edge of TCK and
has an internal 47 kΩ pull-up resistor.
MUX_CTL high: RxD is connected to the JTAG TAP controller and
functions as TDI, see Table 1-15 on page 1-26.)
TDO
Output Tri-
stated
Test data output—TDO is a test data serial output signal used for
test instructions and data. TDO is tri-statable and is actively driven
in the shift-IR and shift-DR controller states. TDO changes on the
falling edge of TCK.
MUX_CTL high: TxD is connected to the JTAG TAP controller and
functions as TDO, see Table 1-15 on page 1-26.)
TCK
Input
Input
Input
Input
Test clock—TCK is a test clock input signal used to synchronize the
JTAG test logic. It has an internal 47 kΩ pull-up resistor.
MUX_CTL high: ROW7 is connected to the JTAG TAP controller
and functions as TCK, see Table 1-14 on page 1-22.)
TRST
Test reset—TRST is an active-low Schmitt-trigger input signal used
to asynchronously initialize the test controller. TRST has an internal
47 kΩ pull-up resistor.
MUX_CTL high: INT6 is connected to the JTAG TAP controller and
functions as TRST, see Table 1-12 on page 1-19.)
TEST
Input
Input
Factory test mode—Selects factory test mode. Reserved. This pin
MUST be connected to ground.
Preliminary
1-36
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
SECTION 2
SPECIFICATIONS
GENERAL CHARACTERISTICS
The DSP56651 is fabricated in high-density CMOS. The DSP56651 specifications are
preliminary from design simulations and may not be fully tested or guaranteed at
this early stage of the product life cycle. Finalized specifications will be published
after full characterization and device qualifications are complete.
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting
against damage due to high static voltage or
electrical fields; however, normal precautions
should be taken to avoid exceeding maximum
voltage ratings. Reliability is enhanced if
unused inputs are tied to an appropriate logic
voltage level (e.g., either GND or V ).
CC
Note: In the calculation of timing requirements, adding a maximum value of one
specification to a minimum value of another specification does not yield a
reasonable sum. A maximum specification is calculated using a worst case
variation of process parameter values in one direction. The minimum
specification is calculated using the worst case for the same parameters in the
opposite direction. Therefore, a “maximum” value for a specification will
never occur in the same device that has a “minimum” value for another
specification; adding a maximum to a minimum represents a condition that
can never exist.
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
2-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
Thermal characteristics
Table 2-1 Absolute Maximum Ratings (GND = 0 V)
Rating
Symbol
Value
Unit
Internal supply voltage
External supply voltage
V
–0.3 to +2.75
–0.3 to +3.6
–40 to +85
V
V
CCI
V
CCE
Operating temperature range
Storage temperature
T
°C
°C
A
T
–55 to +125
STG
THERMAL CHARACTERISTICS
Table 2-2 Thermal Characteristics
3
Characteristic
Symbol
Unit
BGA Value
1
Junction-to-ambient thermal resistance
R
or θ
or θ
TBD
TBD
TBD
˚C/ W
˚C/ W
˚C/ W
θJA
JA
JC
2
Junction-to-case thermal resistance
R
θJC
Thermal characterization parameter
Ψ
JT
Notes: 1. Junction-to-ambient thermal resistance is based on measurements on a horizontal-
single-sided printed circuit board per SEMI G38-87 in natural convection.(SEMI is
Semiconductor Equipment and Materials International, 805 East Middlefield Rd.,
Mountain View, CA 94043, (415) 964-5111)
2. Junction-to-case thermal resistance is based on measurements using a cold plate per
SEMI G30-88, with the exception that the cold plate temperature is used for the case
temperature.
3. These are measured values; testing is not complete. Values were measured on a non-
standard four-layer thermal test board (two internal planes) at one watt in a horizontal
configuration.
Preliminary
2-2
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
DC Electrical Characteristics
DC ELECTRICAL CHARACTERISTICS
Table 2-3 DC Electrical Characteristics
Characteristics
Internal supply voltage
Symbol
Min
Typ
Max
Units
V
2.3
—
—
—
—
—
—
—
—
2.5
3.4
3.4
V
V
CCI
External supply voltage
I/ O predriver supply voltage
Input high voltage
V
V
CCI
CCE
V
V
V
CCHQ
CCE
V
0.7 × V
V + 0.2
CCE
V
IH
CCE
Input low voltage
V
–0.3
–10
0.2 × V
V
IL
CCE
Input leakage current
I
10
µA
V
IN
Output high voltage (I
= –400 µA)
V
0.75 × V
0
V
CCE
OH
OH
CCE
Output low voltage (I = 800 µA)
V
0.18 × V
CCE
V
OL
OL
Total stop mode (DSP and MCU stopped, PLL
powered down, timers disabled)
I
—
60
—
µA
CC_STOP
DSP run current at 58.8 MHz (MCU stopped,
timers disabled, DSP running algorithm from
internal memory, BBP and SAP active)
I
—
35
—
mA
CCDSP_RUN
PLL supply current (16.8 MHz input,
DSP freq = 58.8 MHz, MCU clock = 16.8 MHz)
I
—
—
1.6
4.5
—
—
mA
mA
CC_PLL
DSP wait current at 58.8 MHz (MCU stopped,
timers disabled, BBP and SAP active)
I
CC_DSP_WAIT
CC_MCU_RUN
MCU run current at 16.8 MHz (DSP and DSP PLL
stopped, timers disabled, MCU peripherals
active)
I
—
—
9
3
—
—
—
mA
mA
MCU doze current at 16.8 MHz (DSP and DSP
PLL stopped, timers disabled, MCU peripherals
active)
I
CC_MCU_DOZE
MCU wait current at 16.8 MHz (DSP and DSP
PLL stopped, timers disabled, MCU peripherals
active)
I
—
—
3
mA
CC_MCU_WAIT
Timer current (MCU and DSP stopped; 16.8 MHz
to timer)
I
500
—
µA
CC_TIMER
Input capacitance per pin
C
—
—
TBD
pF
—
IN
1
Pull-up resistor value
—
50%
100%
180%
Note:
1. Applies to 22 K and 47 K resistors.
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
2-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
Clock Requirements
CLOCK REQUIREMENTS
Table 2-4 Clock Requirements
Characteristics
CKIH input frequency
Symbol
Min
Typ
Max
Units
f
f
0
0
—
32.768
—
16.8
MHz
kHz
1
CKIL input frequency
MCU internal frequency
DSP internal frequency
CKIH input amplitude
CKIL input low voltage
CKIL input high voltage
CKIH input impedance
f
1
2
f
0
16.8
58.8
—
MHz
MHz
MCU-CLK
f
—
500
-0.3
—
DSP-CLK
V
—
mV
V
I-CKIH
IL-CKIL
IH-CKIL
PP
V
—
0.2xV
CCE
V
V
—
2.77
—
V
CCI
R
High TBD
—
MΩ
I-CKIH
EXTERNAL BUS INTERFACE REQUIREMENTS
When the MCU is operating at 16.8 MHz, the bus interface can access 100 ns access
time external memory with one wait state or 15 ns access time external memory with
no wait states.
AC ELECTRICAL CHARACTERISTICS
The characteristics listed in this section are given for V
with a capacitive load of 50 pF.
= 2.4 V and V
= 3.3 V
DDE
DDI
Preliminary
2-4
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
Internal Clocks
INTERNAL CLOCKS
For each occurrence of T , T , T , or I , substitute with the numbers in
DCYC
DH
DL DC
Table 2-6. DF, MF, and PDF are the DSP PLL division, multiplication, and pre-
division factors set in registers.
Table 2-5 DSP Clocks
Characteristics
DSP PLL input frequency
Symbol
Min
Max
Unit
EfD
0
16.8
MHz
DSP PLL input clock cycle time
• with PLL disabled
• with PLL enabled
ET
59.5
59.5
∞
ns
ns
DC
273100
Table 2-6 Internal DSP Clocks
Characteristics
Symbol
Expression
Internal DSP operation frequency with PLL enabled
fD
fD
(EfD × MF) / (PDF × DF)
Internal DSP operation frequency with PLL
disabled
EfD/ 2
Internal DSP clock high period
• with PLL disabled
ET
DC
• with PLL enabled and MF ≤ 4
(Min) 0.49 × ET × PDF × DF/ MF
(Max) 0.51 × ETDC × PDF × DF/ MF
DC
T
DH
• with PLL enabled and MF > 4
(Min) 0.47 × ET × PDF × DF/ MF
DC
(Max) 0.53 × ETDC × PDF × DF/ MF
Internal clock low period
• with PLL disabled
ET
DC
• with PLL enabled and MF ≤ 4
(Min) 0.49 × ET × PDF × DF/ MF
(Max) 0.51 × ETDC × PDF × DF/ MF
DC
T
DL
• with PLL enabled and MF > 4
(Min) 0.47 × ET × PDF × DF/ MF
DC
(Max) 0.53 × ETDC × PDF × DF/ MF
Internal clock cycle time with PLL enabled
Internal clock cycle time with PLL disabled
DSP instruction cycle time
T
T
ET × PDF × DF/ MF
DC
DC
2 × ET
DC
DC
I
T
DC
DCYC
Table 2-7 MCU Clocks
Characteristics
Symbol
Min
Max
Unit
Frequency of the internal MCU-CLK clock
Internal MCU-CLK clock cycle time
fM
0
16.8
MHz
ns
T
59.5
∞
MC
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
2-5
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
Phase-Locked Loop (PLL) Characteristics
PHASE-LOCKED LOOP (PLL) CHARACTERISTICS
Table 2-8 Phase-Locked Loop (PLL) Characteristics
Characteristics
Expression
Min
Max
Unit
1
VCO frequency when PLL enabled
MF × EfD × 2 / PDF
30
120
MHz
PLL external capacitor (PCAP pin to V
)
CCP
(680 • MF-120) recommended
(580 • MF-100) minimum
(780 • MF-140) maximum
•
MF ≤ 4
2
C
PCAP
pF
(1100 • MF) recommended
(830 • MF) minimum
•
MF > 4
(1470 • MF) maximum
Notes: 1. The VCO output is further divided by 2 when PLL is enabled. If the division factor (DF) is 1, the
VCO
-------------
2
operating frequency is
.
2.
C
is the value of the PLL capacitor (connected between PCAP pin and V
).
PCAP
CCP
(The recommended value for Cpcap is (680 × MF – 120) pF for MF ≤ 4 and (1100 × MF) pF for MF > 4.)
RESET, MODE SELECT, AND INTERRUPT TIMING
Table 2-9 Reset, Mode Select, and Interrupt Timing
MCU @16.8
MHz DSP
@58.8 MHz
Num
Characteristics
Expression
Unit
Min
Max
1
2
RESET_IN duration to guarantee reset
3 × T
+ 0.05
91.6
—
µs
µs
CKIL
Delay from RESET_IN assertion to RESET_OUT
assertion
min: 4.5 × T
max: 5.5 × T
137.33
CKIL
CKIL
167.85
—
3
4
Duration of RESET_OUT assertion
7 × T
213.62
137.33
µs
CKIL
Delay from RESET_IN assertion to all pins at Reset
Value (periodically sampled and not 100% tested)
min: 4.5 × T
max: 5.5 × T
µs
µs
CKIL
CKIL
167.85
—
5
6
7
MOD select setup time
MOD select hold time
3.5 × T
+ 0.02
107
0
µs
ns
ns
CKIL
—
—
Minimum edge-triggered DSP_IRQ assertion
width
—
10
—
8
Minimum edge-triggered DSP_IRQ deassertion
width
—
10
—
ns
Preliminary
2-6
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
RESET, Mode Select, and Interrupt Timing
Table 2-9 Reset, Mode Select, and Interrupt Timing (Continued)
MCU @16.8
MHz DSP
@58.8 MHz
Num
Characteristics
Expression
Unit
Min
Max
9
Minimum edge-triggered INTn width high
Minimum edge-triggered INTn width low
—
—
TBD
TBD
—
—
ns
ns
10
RESET_IN
1
RESET_OUT
3
2
All Pins
4
Reset Value
AA1679
Figure 2-1 Reset Timing
RESET_OUT
5
6
MOD
AA1680
Figure 2-2 Operating Mode Select Timing
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
2-7
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
RESET, Mode Select, and Interrupt Timing
DSP_IRQ
7
DSP_IRQ
8
AA1681
Figure 2-3 DSP External Interrupt Timing (Negative Edge-Triggered)
INTn
9
INTn
10
AA1682
Figure 2-4 INT0-INT7 External Interrupt Timing
Preliminary
2-8
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
External Interface Module (EIM) Timing
EXTERNAL INTERFACE MODULE (EIM) TIMING
The EIM provides the bus interface between the DSP56651 and external memory and
peripherals. It uses the external address bus, data bus, bus control signals, and the
chip select signals.
1
Table 2-10 EIM External Bus Output AC Timing Specifications
MCU @16.8 MHz
Num
Characteristics
Unit
Min
Max
2
11
12
13
14
15
MCU_CLK rise to address and R/ W valid
—
0
4
—
4
ns
ns
ns
ns
ns
MCU_CLK rise to address and R/ W invalid (output hold)
MCU_CLK rise to CS asserted
—
0
MCU_CLK rise to CS deasserted (output hold)
—
4
MCU_CLK fall to OE, EB asserted (read, OEA = 0),
—
3
EB asserted (write)
3
16
17
MCU_CLK rise to OE, EB asserted (read, OEA = 1)
—
0
4
—
—
—
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
MCU_CLK rise to OE, EB deasserted (output hold) (read)
MCU_CLK rise to EB deasserted (output hold) (write, WEN = 0)
MCU_CLK fall to EB deasserted (output hold) (write, WEN = 1)
0
18
19
0
3
MCU_CLK fall to OE, EB asserted (WSC = 0)
—
0
3
20
MCU_CLK rise to OE, EB deasserted (output hold) (WSC = 0)
—
—
—
4
21
Data-in valid to MCU_CLK rise (setup)
15
0
22
MCU_CLK rise to data-in invalid (hold)
23
MCU_CLK rise to data-out valid
—
0
24
MCU_CLK rise to data-out invalid (output hold)
MCU_CLK rise to data-out high impedance
MCU_CLK fall to data-out valid (WSC = 0)
MCU_CLK rise to data-out invalid (output hold) (WSC = 0)
MCU_CLK rise to data-out high impedance (WSC = 0)
1. The following notes apply to this table:
—
4
25
—
—
0
26
6
27
—
6
28
—
Note:
•
•
•
Output timing is measured at the pin. The specifications assume a capacitive load of 50 pF.
R/ W, EB, and CS deassertion to address change is 0 ns minimum.
MCU_CLK can be viewed on the CKO pin by programming the clock control register (CKCTL).
2. Address setup to R/ W and CS assertion is 0 ns minimum.
3. EB outputs are asserted for reads if the EBC bit in the corresponding CS control register is clear.
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
2-9
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
External Interface Module (EIM) Timing
MCU_CLK
11
ADDRESS
R/W
12
14
13
CS
15
OE, EB (OEA=0)
(READ)
17
16
(OEA=1)
OE, EB
(READ)
17
17
15
15
19
EB (WEN=0)
(WRITE)
EB (WEN=1)
(WRITE)
18
OE, EB (WSC=0)
20
22
21
DATA in
(READ)
23
25
DATA out
(WRITE)
24
28
26
(WSC=0)
DATA out
(WRITE)
27
AA1683
Figure 2-5 EIM Read/ Write Timing
Preliminary
2-10
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
Smart Card Timing
SMART CARD TIMING
Table 2-11 Smart Card Port to Smart Card AC Timing
CKIH @16.8 MHz
Num
Characteristics
Unit
Min
Max
31 SIMRESET low to SIMCLK low
32 SIMCLK deactivated to SIMDATA tri-state to low
1.18
1.18
200/ f
200/ f
200/ f
—
µs
µs
µs
ns
µs
33 SIMDATA low to PWR_EN low
34 SIMRESET low
1.18
40000/ f
57
35 SENSE high to SIMRESET low
76
Note: “f” is CKIH/ 4 (for 5 V sims) or CKIH/ 5 (for 3 V sims), as programmed in the Smart Card port.
SENSE
35
34
SIMRESET
31
SIMCLK
32
SIMDATA
33
PWR_EN
AA1684
Figure 2-6 Smart Card Interface Power Down AC Timing
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
2-11
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
QSPI Timing
QSPI TIMING
The QSPI uses the signals in the serial control port to select individual serial
peripherals (using the SPI chip select signals) and transfer data between peripherals
and the DSP56651.
Table 2-12 QSPI Timing
MCU_CLK
@ 16.8 MHz
Num
Characteristics
Symbol
Expression
Unit
Min
Max
301 Cycle time
T
—
—
—
—
—
—
—
—
—
—
—
1
—
1
504
252
∞
T
T
QCYC
MC
MC
302 Clock (SCK) high or low time
303 Chip-select lag time
304 Inter-queue transfer delay
305 Chip-select lead time
306 Data setup time (inputs)
307 Data hold time (inputs)
308 Data valid (after SCK edge)
309 Data hold time (outputs)
310 Rise time
T
SW
T
T
LAG
QCYC
QCYC
T
1
∞
T
T
TD
T
1
128
—
—
6
LEAD
QCYC
T
0
nS
SU
T
0.5
—
–2
—
—
T
HI
QCYC
T
nS
V
T
—
10
10
nS
nS
nS
HO
T
I
311 Fall time
T
F
305
303
PCS [4:0]
301
304
310
302
SCK (CSPOL = 0)
304
SCK (CSPOL = 1)
307
311
306
MISO
MOSI
MSB IN
DATA
LSB IN
MSB IN
309
308
LSB OUT
MSB OUT
DATA
MSB OUT
AA1685
Figure 2-7 QSPI Timings for CPHA = 0
Preliminary
2-12
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
Audio Serial Codec and Baseband Serial Codec Timing
303
305
PCS [4:0]
310
311
304
301
SCK (CSPOL = 0)
SCK (CSPOL = 1)
302
302
307
306
MISO
MOSI
MSB IN
DATA
LSB IN
MSB IN
308
309
LSB OUT
MSB OUT
DATA
MSB OUT
AA1686
Figure 2-8 QSPI Timings for CPHA = 1
AUDIO SERIAL CODEC AND BASEBAND SERIAL CODEC TIMING
The audio serial codec port (also called the serial audio port or SAP) and the
baseband serial codec port (also called the baseband port or BBP) have the same
timing specifications. The timing table uses the following acronyms to describe the
signal parameters:
tSSICC = BBP/ SAP clock cycle time
TXC (SCKA/ SCKB Pin) = Transmit clock
RXC (SC0A/ SC0B or SCKA/ SCKB Pin) = Receive clock
FST (SC2A/ SC2B Pin) = Transmit frame sync
FSR (SC1A/ SC1B or SC2A/ SC2B Pin) = Receive frame sync
ick = Internal clock
xck = External Clock
i ck a = Internal clock, asynchronous mode (asynchronous
implies that TXC and RXC are two different clocks)
i ck s = Internal clock, synchronous mode (synchronous implies
that TXC and RXC are the same clock)
bl = Bit length
wl = Word length
wr = Word length relative
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
2-13
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
Audio Serial Codec and Baseband Serial Codec Timing
Table 2-13 SAP and BBP Timing
DSP @ 58.8
MHz
Num
Characteristics
Symbol
Expression
Case Unit
Min Max
1
430 Clock cycle
t
4 × T
3 × T
68
51
—
—
i ck
x ck
ns
ns
DC
DC
SSICC
431 Clock high period
for internal clock
—
—
2 × T
1.5 × T
– 12.2 21.8
—
—
ick
xck
ns
ns
DC
for external clock
25.5
DC
432 Clock low period
for internal clock
2 × T
– 12.2 21.8
—
—
ick
xck
ns
ns
DC
for external clock
1.5 × T
25.5
DC
433 RXC rising edge to FSR out (bl) high
434 RXC rising edge to FSR out (bl) low
435 RXC rising edge to FSR out (wr) high
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
45.1 x ck
26.8 i ck a
ns
ns
—
—
—
—
—
—
—
—
—
—
—
—
—
—
45.1 x ck
26.8 i ck a
ns
ns
2
—
—
47.6 x ck
29.3 i ck a
ns
ns
2
436 RXC rising edge to FSR out (wr) low
437 RXC rising edge to FSR out (wl) high
438 RXC rising edge to FSR out (wl) low
439 Data in setup time before RXC
—
—
47.6 x ck
29.3 i ck a
ns
ns
—
—
45.9 x ck
25.6 i ck a
ns
ns
—
—
45.1 x ck
26.8 i ck a
ns
ns
0.0
23.2
—
—
x ck
i ck
ns
ns
(SCK in synchronous mode) falling edge
440 Data in hold time after RXC
falling edge
6.1
3.6
—
—
x ck
i ck
ns
ns
441 FSR input (bl, wr) high before RXC
1.2
28.0
—
—
x ck
i ck a
ns
ns
2
falling edge
442 FSR input (wl) high before RXC
falling edge
1.2
28.0
—
—
x ck
i ck a
ns
ns
443 FSR input hold time after RXC falling
edge
3.6
0.0
—
—
x ck
i ck a
ns
ns
444 Flags input setup before RXC
falling edge
0.0
23.2
—
—
x ck
i ck s
ns
ns
445 Flags input hold time after RXC
falling edge
7.3
0.0
—
—
x ck
i ck s
ns
ns
Preliminary
DSP56651 Technical Data Sheet
2-14
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
Audio Serial Codec and Baseband Serial Codec Timing
Table 2-13 SAP and BBP Timing (Continued)
DSP @ 58.8
MHz
Num
Characteristics
Symbol
Expression
Case Unit
Min Max
446 TXC rising edge to FST out (bl) high
447 TXC rising edge to FST out (bl) low
448 TXC rising edge to FST out (wr) high
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
35.4 x ck
18.3 i ck
ns
ns
—
—
37.8 x ck
20.7 i ck
ns
ns
2
—
—
37.8 x ck
20.7 i ck
ns
ns
2
449 TXC rising edge to FST out (wr) low
450 TXC rising edge to FST out (wl) high
451 TXC rising edge to FST out (wl) low
—
—
40.3 x ck
23.2 i ck
ns
ns
—
—
36.6 x ck
19.5 i ck
ns
ns
—
—
37.8 x ck
20.7 i ck
ns
ns
452 TXC rising edge to data out enable from
high impedance
—
—
37.8 x ck
20.7 i ck
ns
ns
454 TXC rising edge to data out valid
35 + 0.5 × T
—
—
43.5 x ck
25.6 i ck
ns
ns
DC
455 TXC rising edge to data out high
—
—
—
—
—
—
—
—
37.8 x ck
19.5 i ck
ns
ns
3
impedance
457 FST input (bl, wr) setup time before TXC
2.0
21.0
—
—
x ck
i ck
ns
ns
2
falling edge
458 FST input (wl) to data out enable from
—
32.9
—
ns
3
high impedance
460 FST input (wl) setup time before TXC
falling edge
2.0
21.0
—
—
x ck
i ck
ns
ns
461 FST input hold time after TXC falling
edge
4.0
0.0
—
—
x ck
i ck
ns
ns
462 Flag output valid after TXC rising edge
—
—
39.0 x ck
22.0 i ck
ns
ns
Note:
1. For internal clock, external clock cycle is defined by I
and BBP/ SAP control register.
CYC
2. Word relative frame sync signal wave form, relates to clock, as the bit length frame sync signal wave
form, but spreads from one serial clock before first bit clock (same as bit length frame sync signal),
until the one before last bit clock of the first word in frame.
3. Periodically sampled and not 100% tested.
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
2-15
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
Audio Serial Codec and Baseband Serial Codec Timing
430
431
TXC
432
(Input/Output)
447
446
FST (Bit)
Out
FST (Word)
Out
450
451
Data Out
455
452
455
457
FST (Bit) In
First Bit
Last Bit
460
461
FST (Word) In
Flags Out
458
461
460
462
AA1687
Note: In the network mode, output flag transitions can occur at the start of each time slot
within the frame. In the normal mode, the output flag state is asserted for the entire
frame period.
Figure 2-9 BBP and SAP Transmitter Timing
Preliminary
2-16
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
Audio Serial Codec and Baseband Serial Codec Timing
430
431
432
434
RXC
(Input/Output)
433
FSR (Bit)
Out
FSR (Word)
Out
437
438
Data In
440
439
443
FSR (Bit)
In
First Bit
Last Bit
441
FSR (Word)
In
Flags In
442
443
444
445
AA1688
Figure 2-10 BBP And SAP Receiver Timing
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
2-17
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
JTAG Port Timing
JTAG PORT TIMING
Table 2-14 JTAG Timing
DSP @ 58.8 MHz
Num
Characteristics
Expression
Unit
Min
Max
500
1/ (3 × T
—
)
0.0
45.0
20.0
0.0
19.6
—
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK frequency of operation
DC
501 TCK cycle time in crystal mode
502 TCK clock pulse width measured at 1.5 V
503 TCK rise and fall times
—
—
—
3.0
—
504 Boundary scan input data setup time
505 Boundary scan input data hold time
506 TCK low to output data valid
507 TCK low to output high impedance
508 TMS, TDI data setup time
—
5.0
—
24.0
0.0
—
—
40.0
40.0
—
—
0.0
—
5.0
509 TMS, TDI data hold time
—
25.0
0.0
—
510 TCK low to TDO data valid
511 TCK low to TDO high impedance
512 TRST assert time
—
44.0
44.0
—
—
0.0
—
100.0
40.0
513 TRST setup time to TCK low
—
—
501
502
502
V
M
V
M
V
TCK
(Input)
IH
V
IL
503
503
AA0496
Figure 2-11 Test Clock Input Timing Diagram
Preliminary
2-18
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
JTAG Port Timing
V
TCK
(Input)
IH
V
IL
504
505
Data
Inputs
Input Data Valid
506
507
506
Data
Output Data Valid
Outputs
Data
Outputs
Data
Outputs
Output Data Valid
AA0497
Figure 2-12 Boundary Scan (JTAG) Timing Diagram
TCK
(Input)
513
TRST
(Input)
AA1689
512
Figure 2-13 TRST Timing Diagram
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
2-19
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Specifications
JTAG Port Timing
V
IH
TCK
(Input)
V
IL
509
508
TDI
TMS
Input Data Valid
(Input)
510
TDO
(Output)
Output Data Valid
511
TDO
(Output)
510
TDO
(Output)
Output Data Valid
AA0498
Figure 2-14 Test Access Port Timing Diagram
Preliminary
2-20
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
SECTION 3
PACKAGING
PACKAGE INFORMATION
This section provides information about the available packages for this product. The
DSP56651 is available in a 196-pin plastic ball grid array (PBGA) package.
The DSP56651 part (RAM-based DSP program memory) is delivered in a 17-mm
(outline) PBGA package having a solder-ball footprint identical to that of the
15 mm PBGA. Compatibility between the footprints of the two packages is
maintained to minimize impact to the customer’s application board routing, such
that the same board can be used for both the DSP56651 and DSP56652.
196 PBGA (GT), 17 x 17 mm, with Footprint of 15-mm PBGA
The DSP56651 is offered in the non-JEDEC standard, 17-mm PBGA package. The
package is “non-standard” in that the single outermost row of solder balls in the
array is removed, leaving a 14 x 14 array (196) of solder balls. This package footprint
is identical to that of the JEDEC standard 15 mm (outline) 196 PBGA. The pitch of the
solder balls is 1 mm. Refer to the following table and figure for package drawing
and dimensions.
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
3-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Packaging
PBGA Package Dimensions
PBGA PACKAGE DIMENSIONS
Table 3-1 Dimensions for 196 PBGA (17-mm Outline)
MILLIMETERS
DIM
MIN
MAX
A
A1
A2
A3
b
1.32
0.27
0.30
0.75
0.35
1.75
0.47
0.40
0.88
0.65
D
17.00 BASIC
13.00 BASIC
D1
D2
E
TBD
17.00
17.00 BASIC
13.00 BASIC
E1
E2
e
TBD
1.00
—
17.00
BASIC
2.50
R1
Preliminary
3-2
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Packaging
PBGA Package Mechanical Drawing
PBGA PACKAGE MECHANICAL DRAWING
D
E
E2
2x R R1
D2
4X R R1
A2
D1
e/2
13x, e
A3
A1
P
N
M
L
A
K
J
H
E1
G
F
e/2
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14
196x, b
AA1696
Figure 3-1 DSP56651 Mechanical Drawing
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
3-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Packaging
Ordering Drawings
ORDERING DRAWINGS
Complete mechanical information regarding DSP56651 packaging is available by
facsimile through Motorola's Mfax system. Call the following number to obtain
information by facsimile:
(602) 244-6591
The Mfax automated system requests the following information:
•
The receiving facsimile telephone number including area code or country
code
•
The caller’s personal identification number (PIN)
Note: For first time callers, the system provides instructions for setting up a PIN,
which requires entry of a name and telephone number.
•
The type of information requested:
–
–
–
–
Instructions for using the system
A literature order form
Specific part technical information or data sheets
Other information described by the system messages
A total of three documents may be ordered per call.
The DSP56651 196-pin PBGA package mechanical drawing is referenced as Case
1128-01 Rev. D.
Preliminary
3-4
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
SECTION 4
DESIGN CONSIDERATIONS
HEAT DISSIPATION
An estimation of the chip junction temperature, T , in °C can be obtained from the
J
equation:
Equation 1: TJ = TA + (PD × RθJA
)
Where:
T = ambient temperature ˚C
A
R
= package junction-to-ambient thermal resistance ˚C/ W
θJA
P = power dissipation in package
D
Historically, thermal resistance has been expressed as the sum of a junction-to-case
thermal resistance and a case-to-ambient thermal resistance:
Equation 2: RθJA = RθJC + RθCA
Where:
R
R
R
= package junction-to-ambient thermal resistance ˚C/ W
= package junction-to-case thermal resistance ˚C/ W
= package case-to-ambient thermal resistance ˚C/ W
θJA
θJC
θCA
R
is device-related and cannot be influenced by the user. The user controls the
θJC
thermal environment to change the case-to-ambient thermal resistance, R
. For
θCA
example, the user can change the air flow around the device, add a heat sink, change
the mounting arrangement on the printed circuit board, or otherwise change the
thermal dissipation capability of the area surrounding the device on a printed circuit
board. This model is most useful for ceramic packages with heat sinks; Ninety
percent of the heat flow is dissipated through the case to the heat sink and out to the
ambient environment. For ceramic packages, in situations where the heat flow is split
between a path to the case and an alternate path through the printed circuit board,
analysis of the device thermal performance may need the additional modeling
capability of a system level thermal simulation tool.
The thermal performance of plastic packages is more dependent on the temperature
of the printed circuit board to which the package is mounted. Again, if the
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
4-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Design Considerations
Heat Dissipation
estimations obtained from R
do not satisfactorily answer whether the thermal
θJA
performance is adequate, a system level model may be appropriate.
A complicating factor is the existence of three common ways for determining the
junction-to-case thermal resistance in plastic packages:
•
•
•
To minimize temperature variation across the surface, the thermal resistance
is measured from the junction to the outside surface of the package (case)
closest to the chip mounting area when that surface has a proper heat sink.
To define a value approximately equal to a junction-to-board thermal
resistance, the thermal resistance is measured from the junction to where the
leads are attached to the case.
If the temperature of the package case (T ) as determined by a thermocouple,
T
the thermal resistance is computed using the value obtained by the equation
(T - T )/ P .
J
T
D
As noted above, the junction-to-case thermal resistances quoted in this data sheet are
determined using the first definition. From a practical standpoint, this value is also
suitable for determining the junction temperature from a case thermocouple reading
in forced convection environments. In natural convection, using the junction-to-case
thermal resistance to estimate junction temperature from a thermocouple reading on
the case of the package will estimate a junction temperature slightly hotter than
actual temperature. Hence, the new thermal metric, thermal characterization
parameter or Ψ , has been defined to be (T - T )/ P . This value gives a better
JT
J
T
D
estimate of the junction temperature in natural convection when using the surface
temperature of the package. Remember that surface temperature readings of
packages are subject to significant errors caused by inadequate attachment of the
sensor to the surface and to errors caused by heat loss to the sensor. The
recommended technique is to attach a 40-gauge thermocouple wire and bead to the
top center of the package with thermally conductive epoxy.
Note: Table 2-2 on page 2-2 of this document contains the package thermal values
for this chip.
Preliminary
4-2
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Design Considerations
Electrical Design Considerations
ELECTRICAL DESIGN CONSIDERATIONS
CAUTION
This device contains protective circuitry to
guard against damage due to high static
voltage or electrical fields. However, normal
precautions are advised to avoid application
of any voltages higher than maximum rated
voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage
level (e.g., either GND or V ).
CC
Use the following list of recommendations to assure correct DSP operation:
•
•
•
•
•
Provide a low-impedance path from the board power supply to each V pin
on the DSP and from the board ground to each GND pin.
CC
Use at least four 0.1 µF bypass capacitors positioned as close as possible to the
four sides of the package to connect the V power source to GND.
CC
Ensure that capacitor leads and associated printed circuit traces that connect
to the chip V and GND pins are less than 0.5 inch per capacitor lead.
CC
Use at least a four-layer printed circuit board (PCB) with two inner layers for
V
and GND.
CC
Because the DSP output signals have fast rise and fall times, PCB trace lengths
should be minimal. This recommendation particularly applies to the address
and data buses as well as the R/ W, DSP_IRQ, and INT0–INT7 signals.
•
Consider all device loads as well as parasitic capacitance due to PCB traces
when calculating capacitance. This is especially critical in systems with higher
capacitive loads that could create higher transient currents in the V and
CC
GND circuits.
•
•
All inputs must be terminated (i.e., not allowed to float) using CMOS levels.
Take special care to minimize noise levels on the PLL supply pins (both V
and GND).
CC
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
4-3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Design Considerations
Electrical Design Considerations
Preliminary
4-4
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
SECTION 5
ORDERING INFORMATION
Table 5-1 lists the pertinent information needed to place an order. Consult a Motorola
Semiconductor sales office or authorized distributor to determine availability and to
order parts.
Table 5-1 DSP56651 Ordering Information
Pin
Count
Part
Package Type
Order Number
DSP56651 Plastic ball grid array (PBGA)
196
PC56651GC
Preliminary
MOTOROLA
DSP56651 Technical Data Sheet
5-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Ordering information
Preliminary
5-2
DSP56651 Technical Data Sheet
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
M• CORE, Mfax, and OnCE are trademarks of Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may
be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights
of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support life, or for any other application in which the
failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer
purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,
damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent
regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA/Europe/Locations Not
Asia/Pacific:
Japan:
Listed:
Motorola Semiconductors H.K. Ltd.
8B Tai Ping Industrial Park
51 Ting Kok Road
Nippon Motorola Ltd.
SPD, Strategic Planning Office, 141
4-32-1, Nishi-Gotanda
Motorola Literature Distribution
P.O. Box 5405
Denver, Colorado 80217
1 (800) 441-2447 (within US)
1 (303) 675-2140 (outside US)
1 (303) 675-2150 (direct FAX)
Tai Po, N.T., Hong Kong
852-2662928
Shinagawa-ku, Tokyo, Japan
81-3-5487-8488
Technical Resource Center:
1 (800) 521-6274
Internet:
Mfax™:
RMFAX0@email.sps.mot.com
TOUCHTONE (602) 244-6609
www.motorola-dsp.com
DSP Helpline
dsphelp@dsp.sps.mot.com
For More Information On This Product,
Go to: www.freescale.com
相关型号：
PC56F8357MPY60
16-BIT, 240MHz, OTHER DSP, PQFP160, 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-160
MOTOROLA
©2020 ICPDF网 联系我们和版权申明