PCA2001U/10AB [NXP]
32 kHz watch circuit with programmable adaptive motor pulse; 32 kHz的时钟电路与可编程自适应电机脉冲
| 型号： | PCA2001U/10AB |
| 厂家： | 
NXP |
| 描述： | 32 kHz watch circuit with programmable adaptive motor pulse |
| 文件： | 总28页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA2000; PCA2001
32 kHz watch circuit with programmable adaptive motor pulse
Rev. 05 — 11 November 2008
Product data sheet
1. General description
The PCA2000 and PCA2001 are CMOS integrated circuits for battery operated wrist
watches with a 32 kHz quartz crystal as timing element and a bipolar 1 Hz stepping motor.
The quartz crystal oscillator and the frequency divider are optimized for minimum power
consumption. A timing accuracy of 1 ppm is achieved with a programmable, digital
frequency adjustment.
To obtain the minimum overall power consumption for the watch, an automatic motor
pulse adaptation function is provided. The circuit supplies only the minimum drive current,
which is necessary to ensure a correct motor step. Changing the drive current of the
motor is achieved by chopping the motor pulse with a variable duty cycle. The pulse width
and the range of the variable duty cycle can be programmed to suit different types of
motors. The automatic pulse adaptation scheme is based on a safe dynamic detection of
successful motor steps.
A pad RESET is provided (used for stopping the motor) for accurate time setting and for
accelerated testing of the watch.
The PCA2000 has a battery End Of Life (EOL) warning function. If the battery voltage
drops below the EOL threshold voltage (which can be programmed for silver oxide or
lithium batteries), the motor steps change from one pulse per second to a burst of four
pulses every 4 seconds.
The PCA2001 uses the same circuit as the PCA2000, but without the EOL function.
2. Features
I Amplitude-regulated 32 kHz quartz crystal oscillator, with excellent frequency stability
and high immunity to leakage currents
I Electrically programmable time calibration with 1 ppm resolution stored in One Time
Programmable (OTP) memory
I The quartz crystal is the only external component connected
I Very low power consumption, typical 90 nA
I One second output pulses for bipolar stepping motor
I Minimum power consumption for the entire watch, due to self adaptation of the motor
drive according to the required torque
I Reliable step detection circuit
I Motor pulse width, pulse modulation, and pulse adaptation range programmable in a
wide range, stored in OTP memory
I Stop function for accurate time setting and power saving during shelf life
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
I End Of Life (EOL) indication for silver oxide or lithium battery (only the PCA2000 has
the EOL feature)
I Test mode for accelerated testing of the mechanical parts of the watch and the IC
I Test bits for type recognition
3. Applications
I Driver circuits for bipolar stepping motors
I High immunity motor drive circuits
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Delivery form
Version
PCA2000U/AB
PCA2001U/AB
PCA200xU
wire bond die; 8 bonding pads;
1.16 × 0.86 × 0.22 mm
chip in tray
PCA200xU
PCA200xU
wire bond die; 8 bonding pads;
1.16 × 0.86 × 0.22 mm
chip in tray
PCA200xU
PCA200xU
PCA200xU
PCA200xCX
PCA200xCX
PCA2000U/10AB PCA200xU
PCA2001U/10AB PCA200xU
wire bond die; 8 bonding pads;
1.16 × 0.86 × 0.22 mm
chip on film frame carrier
chip on film frame carrier
wire bond die; 8 bonding pads;
1.16 × 0.86 × 0.22 mm
PCA2000CX8/5 PCA200xCX wafer level chip-size package; 8 bumps;
unsawn wafer with lead
free solder bumps
1.16 × 0.86 × 0.31 mm
PCA2001CX8/5 PCA200xCX wafer level chip-size package; 8 bumps;
unsawn wafer with lead
free solder bumps
1.16 × 0.86 × 0.31 mm
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
2 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
5. Block diagram
32 Hz
8 kHz
3
OSCIN
8
OSCILLATOR
DIVIDER
RESET
reset
÷4
RESET
4
OSCOUT
TIMING ADJUSTMENT,
INHIBITION
5
V
DD
VOLTAGE DETECTOR,
OTP-CONTROLLER
1 Hz
OTP-MEMORY
1
V
SS
MOTOR CONTROL WITH
ADAPTIVE PULSE MODULATION
EOL
PCA2000 only
2
STEP
DETECTION
i.c.
PCA2000
PCA2001
6
7
mgw567
MOT1
MOT2
Fig 1. Block diagram
6. Pinning information
6.1 Pinning
PCA200xCX
PCA200xU
V
1
2
8
7
RESET
MOT2
V
1
2
8
7
RESET
MOT2
SS
SS
i.c.
i.c.
x
x
0
0
y
0
0
y
OSCIN
3
4
6
MOT1
OSCIN
3
4
6
MOT1
OSCOUT
5
V
OSCOUT
5
V
DD
DD
001aai177
001aai176
Top view. For mechanical details, see
Figure 13.
Top view. For mechanical details, see
Figure 14.
Fig 2. Pad and bump configuration of PCA2000 and PCA2001
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
3 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
6.2 Pin description
Table 2.
Symbol
VSS
Pin description
Pin
1
Description
ground
i.c.
2
internally connected
oscillator input
oscillator output
supply voltage
motor 1 output
motor 2 output
reset input
OSCIN
OSCOUT
VDD
3
4
5
MOT1
MOT2
RESET
6
7
8
7. Functional description
7.1 Motor pulse
The motor output supplies pulses of different driving stages, depending on the torque
required to turn on the motor. The number of different stages can be selected between
three and six. With the exception of the highest driving stage, each motor pulse (tp in
Figure 3 and Figure 6) is followed by a detection phase during which the motor movement
is monitored, in order to check whether the motor has turned correctly or not.
1.96 ms
t
t
2t
p
detection phase
p
p
mgw350
0.98 ms
31.25 ms
31.25 ms
Fig 3. Correction sequence after failed motor step
If a missing step is detected, a correction sequence is generated (see Figure 3) and the
driving stage is switched to the next level. The correction sequence consists of two pulses:
first a short pulse in the opposite direction (0.98 ms, modulated with the maximum duty
cycle) to give the motor a defined position, followed by a motor pulse of the strongest
driving level. Every 4 minutes, the driving level is lowered again by one stage.
The motor pulse has a constant pulse width. The driving level is regulated by chopping the
driving pulse with a variable duty cycle. The driving level starts from the programmed
minimum value and increases by 6.25 % after each failed motor step. The strongest
driving stage, which is not followed by a detection phase, is programmed separately.
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
4 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
Therefore it is possible to program a larger energy gap between the pulses with step
detection and the strongest, not monitored, pulse. This might be necessary to ensure a
reliable and stable operation under adverse conditions (magnetic fields and vibrations). If
the watch works in the highest driving stage, the driving level jumps after the 4-minute
period directly to the lowest stage, and not just one stage lower.
To optimize the performance for different motors, the following parameters can be
programmed:
• Pulse width: 0.98 ms to 7.8 ms in steps of 0.98 ms
• Duty cycle of lowest driving level: 37.5 % to 56.25 % in steps of 6.25 %
• Number of driving levels (including the highest driving level): 3 to 6
• Duty cycle of the highest driving level: 75 % or 100 %
• Enlargement pulse for the highest driving level: on or off
The enlargement pulse has a duty cycle of 25 % and a pulse width which is twice the
programmed motor pulse width. The repetition period for the chopping pattern is 0.98 ms.
Figure 4 shows an example of a 3.9 ms pulse.
0.244 ms
0.122 ms
DUTY CYCLE
37.5 %
43.75 %
50 %
56.25 %
62.5 %
68.75 %
75 %
81.25 %
100 %
mgw351
0.98 ms
0.98 ms
0.98 ms
0.98 ms
Fig 4. Possible modulations for a 3.9 ms motor pulse
7.2 Step detection
Figure 5 shows a simplified diagram of the motor driving and step detection circuit, and
Figure 6 shows the step detection sequence and corresponding sampling current.
Between the motor driving pulses, the switches P1 and P2 are closed, which means the
motor is short-circuited. For a pulse in one direction, P1 and N2 are open, and P2 and N1
are closed with the appropriate duty cycle; for a pulse in the opposite direction, P2 and N1
are open, and P1 and N2 closed.
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
5 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
V
DD
R
D
D1
P2
N2
P1
N1
P3
MOTOR
P4
MOT1
MOT2
V
SS
mgw352
Fig 5. Simplified diagram of motor driving and step detection circuit
The step detection phase is initiated after the motor driving pulse. In phase 1 P1 and P2
are first closed for 0.98 ms and then in phase 2 all four drive switches (P1, N1, P2 and N2)
are opened for 0.98 ms. As a result, the energy stored in the motor inductance is reduced
as fast as possible.
The induced current caused by the residual motor movement is then sampled in phase 3
(closing P3 and P2) and in phase 4 (closing P1 and P4). For step detection in the opposite
direction P1 and P4 are closed during phase 3 and P2 and P3 during phase 4 (see
Figure 6).
I
motor
positive detection level
t
negative detection level
t
p
0.98 ms
(motor shorted)
programmable time limit
OTP C4 to C6
t
= 0.98 ms
sampling
d
sampling
voltage
t
sampling
voltage
positive detection
motor shorted
negative detection
sampling results
t
sampling
mgw569
61 µs
0.49 ms
Fig 6. Step detection sequence and corresponding sampling voltage
Rev. 05 — 11 November 2008
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
6 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
The condition for a successful motor step is a positive step detection pulse (current in the
same direction as in the driving phase) followed by a negative detection pulse within a
given time limit. This time limit can be programmed between 3.9 ms and 10.7 ms (in steps
of 0.98 ms) in order to ensure a safe and correct step detection under all conditions (for
instance magnetic fields). The step detection phase stops after the last 31.25 ms, after the
start of the motor driving pulse.
7.3 Time calibration
The quartz crystal oscillator has an integrated capacitance of 5.2 pF, which is lower than
the specified capacitance (CL) of 8.2 pF for the quartz crystal (see Table 10). Therefore,
the oscillator frequency is typically 60 ppm higher than 32.768 kHz. This positive
frequency offset is compensated by removing the appropriate number of 8192 Hz pulses
in the divider chain (maximum 127 pulses), every 1 or 2 minutes. The time correction is
given in Table 3.
Table 3.
Time calibration
Correction per step (n = 1)
Calibration
period
Correction per step (n = 127)
seconds per day ppm seconds per day
22.3
11.15
ppm
2.03
1 minute
0.176
0.088
258
129
2 minutes
1.017
After measuring the effective oscillator frequency, the number of correction pulses must
be calculated and stored together with the calibration period in the OTP memory (see
Section 7.8).
The oscillator frequency can be measured at pad RESET, where a square wave signal
1
1024
with the frequency of
× f
is provided.
-----------
osc
This frequency shows a jitter every minute or every two minutes, depending on the
programmed calibration period, which originates from the time calibration.
Details on how to measure the oscillator frequency and the programmed inhibition time
are given in Section 7.11.
7.4 Reset
1
At pad RESET an output signal with a frequency of
× f
= 32 Hz is provided.
osc
-----------
1024
Connecting pad RESET to VDD stops the motor drive and opens all four (P1, N1, P2 and
N2) driver switches (see Figure 5). Connecting pad RESET to VSS activates the test
mode. In this mode the motor output frequency is 32 Hz, which can be used to test the
mechanical function of the watch.
After releasing the pad RESET, the motor starts exactly one second later with the smallest
duty cycle and with the opposite polarity to the last pulse before stopping.
The debounce time for the RESET function is between 31 ms and 62 ms.
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
7 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
7.5 Programming possibilities
The programming data is stored in OTP cells (EPROM cells). At delivery, all memory cells
are in state 0. The cells can be programmed to the state 1, but then there is no more set
back to state 0.
The programming data is organized in an array of four 8-bit words: word A contains the
time calibration, words B and C contain the setting for the monitor pulses and word D
contains the type recognition (see Table 4).
Table 4.
Word
Words and bits
Bit
1
2
3
4
5
6
7
8
A
B
number of 8192 Hz pulses to be removed
calibration
period
lowest stage: duty
cycle
number of driving
stages
highest stage:
duty cycle and
stretching
factory test bits
C
D
pulse width
type
maximum time delay between EOL
factorytest
positive and negative
detection pulses
voltage bit
factory test bits
Table 5.
Bit
Description of word A bits
Value
Description
Inhibition time
1 to 7
-
adjust the number of the 8192 Hz pulses to be removed;
bit 1 is the MSB and bit 7 is the LSB
Calibration period
8
0
1
1 minute
2 minutes
Table 6.
Bit
Description of word B bits
Value
Description
Duty cycle lowest driving stage
1 to 2
00
01
10
11
37.5 %
43.75 %
50 %
56.25 %
Number of driving stages
3 to 4
00
01
10
11
3
4
5
6[1]
Duty cycle highest driving stage
5
0
1
75 %[2]
100 %
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
8 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
Table 6.
Description of word B bits …continued
Bit
Value
Description
Pulse stretching
6
0
1
no pulse stretching
pulse of 2 × tp and duty cycle of 25 % are added
Factory test bits
7 to 8
-
-
[1] Including the highest driving stage, which one has no motor step detection.
[2] If the maximum duty cycle of 75 % is selected, not all programming combinations are possible since the
second highest level must be smaller than the highest driving level.
Table 7.
Bit
Description of word C bits
Value
Description
Pulse width tp
1 to 3
000
001
010
011
100
101
110
111
0.98 ms
1.95 ms
2.90 ms
3.90 ms
4.90 ms
5.90 ms
6.80 ms
7.80 ms
[1]
Time delay td(max)
4 to 6
000
001
010
011
100
101
110
111
3.91 ms
4.88 ms
5.86 ms
6.84 ms
7.81 ms
8.79 ms
9.77 ms
10.74 ms
EOL voltage of the battery
7
0
1
1.38 V (silver-oxide)
2.5 V (lithium)
Factory test bit
8
-
-
[1] Between positive and negative detection pulses.
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
9 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
7.6 Type recognition
Byte D is read to determine which type of the PCA200X family is used in a particular
application.
Table 8.
Bit
Description of word D bits
Value
Description
Type recognition
1 to 4
0000
1000
0100
1100
PCA2002
PCA2000
PCA2001
PCA2003
7.7 Programming procedure
For a watch it is essential that the timing calibration can be made after the watch is fully
assembled. In this situation, the supply pads are often the only terminals which are still
accessible.
Writing to the OTP cells and performing the related functional checks is achieved in the
PCA2000 and PCA2001 by modulating the supply voltage. The necessary control circuit
consists basically of a voltage level detector, an instruction counter which determines the
function to be performed, and an 8-bit shift register which allows writing to the OTP cells of
an 8-bit word in one step and acts as a data pointer for checking the OTP content.
There are six different instruction states (state 3 and state 5 are handled as state 4):
• State 1: measurement of the quartz crystal oscillator frequency (divided by 1024)
• State 2: measurement of the inhibition time
• State 3: write/check word A
• State 4: write/check word B
• State 5: write/check word C
• State 6: check word D (type recognition)
Each instruction state is switched on with a pulse to VP(prog)(start). After this large pulse, an
initial waiting time of t0 is required. The programming instructions are then entered by
modulating the supply voltage with small pulses (amplitude VP(mod) and pulse width tmod).
The first small pulse defines the start time, the following pulses perform three different
functions, depending on the time delay (td) from the preceding pulse
(see Figure 7, Figure 8, Figure 11 and Figure 12):
• td = t1 (0.7 ms); increments the instruction counter
• td = t2 (1.7 ms); clocks the shift register with data = logic 0
• td = t3 (2.7 ms); clocks the shift register with data = logic 1
The programming procedure requires a stable oscillator. This means that a waiting time,
determined by the start-up time of the oscillator is necessary after power-up of the circuit.
After the VP(prog)(start) pulse, the instruction counter is in state 1 and the data shift register
is cleared.
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
10 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
The instruction state ends with a second pulse to VP(prog)(stop) or with a pulse to Vstore
.
In any case, the instruction states are terminated automatically 2 seconds after the last
supply modulation pulse.
7.8 Programming the memory cells
Applying the two-stage programming pulse (see Figure 7) transfers the stored data in the
shift register to the OTP cells.
Perform the following to program a memory word:
1. Starting with a VP(prog)(start) pulse wait for the time period t0 then set the instruction
counter to the word to be written (td = t1).
2. Enter the data to be stored in the shift register (td = t2 or t3). LSB first (bit 8) and the
MSB last (bit 1).
3. Applying the two-stage programming pulse Vprestore followed by Vstore stores the word.
The delay between the last data bit and the prestore pulse Vprestore is td = t4. Store the
word by raising the supply voltage to Vstore; the delay between the last data bit and the
store pulse is td.
The example shown in Figure 7 performs the following functions:
• Start
• Setting instruction counter to state 4 (word B)
• Entering data word 110101 into the shift register (sequence: LSB first and MSB last)
• Writing to the OTP cells for word B
t
w(prestore)
V
DD
V
store
t
p(start)
V
P(prog)(start)
V
prestore
t
t
t
t
t
t
t
t
t
t
t
t
w(store)
0
1
1
1
3
2
3
2
3
3
4
V
P(mod)
V
DD(nom)
V
SS
mgw356
The example shows the programming of B = 110101 (the sequence is LSB first and MSB last).
Fig 7. Supply voltage modulation for programming
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
11 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
7.9 Checking memory content
The stored data of the OTP array can be checked bit wise by measuring the supply
current. The array word is selected by the instruction state and the bit is addressed by the
shift register.
To read a word, the word is first selected (td = t1), and a logic 1 is written into the first cell
of the shift register (td = t3). This logic 1 is then shifted through the entire shift register
(td = t2), so that it points with each clock pulse to the next bit.
If the addressed OTP cell contains a logic 1, a 30 kΩ resistor is connected between VDD
and VSS, which increases the supply current accordingly.
Figure 8 shows the supply voltage modulation for reading word B, with the corresponding
supply current variation for word B = 110101 (sequence: first MSB and last LSB).
V
DD
t
p(start)
t
p(stop)
V
P(prog)(start)
V
P(prog)(stop)
t
t
t
t
t
t
t
t
t
t
2
0
1
1
1
3
2
2
2
2
V
P(mod)
V
DD(nom)
V
SS
I
DD
(1)
mgw357
VDD
(1) ∆IDD
=
---------------
30 kΩ
Fig 8. Supply voltage modulation and corresponding supply current variation for
reading word B
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
12 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
7.10 Frequency tuning of assembled watch
Figure 9 shows the test set-up for frequency tuning the assembled watch.
32 kHz
M
PCA200x
FREQUENCY
COUNTER
motor
PROGRAMMABLE
DC POWER SUPPLY
battery
PC INTERFACE
PC
mgw568
Fig 9. Frequency tuning at assembled watch
7.11 Measurement of oscillator frequency and inhibition time
The output of the two measuring states can either be monitored directly at pad RESET or
as a modulation of the supply voltage (a modulating resistor of 30 kΩ is connected
between VDD and VSS when the signal at pad RESET is at HIGH-level).
The supply voltage modulation must be followed as shown in Figure 10 in order to
guarantee the correct start-up of the circuit during production and testing.
V
DD
t
p(stop)
V
P(prog)(stop)
t
> 500 ms
d(start)
V
DD(nom)
V
SS
001aac503
Fig 10. Supply voltage at start-up during production and testing
Measuring states:
• State 1: quartz crystal oscillator frequency divided by 1024; state 1 starts with a pulse
to Vp and ends with a second pulse to Vp
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
13 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
• State 2: inhibition time has a value of n × 0.122 ms. A signal with periodicity of
31.25 ms + n × 0.122 ms appears at pad RESET and as current modulation at
pad VDD (see Figure 11 and Figure 12)
31.25 ms + inhibition time
V
DD
V
O(dif)
V
SS
mgw355
Fig 11. Output waveform at pad RESET for instruction state 2
V
DD
t
t
p(stop)
p(start)
V
V
P(prog)(stop)
P(prog)(start)
t
t
1
0
V
P(mod)
V
DD(nom)
V
SS
mgu719
Fig 12. Supply voltage modulation for starting and stopping of instruction state 2
7.12 Customer testing
Connecting pad RESET to VSS activates the test mode. In this test mode, the motor
output frequency is 8 Hz; the duty cycle reduction and battery check occurs every second,
instead of every 4 minutes. If the supply voltage drops below the EOL threshold voltage,
the motor output frequency is 32 Hz with the highest driving level.
7.13 EOL of battery
The supply voltage is checked every 4 minutes. If it drops below the EOL threshold
voltage (1.38 V for silver-oxide, 2.5 V for lithium batteries), the motor steps change from
one pulse per second to a burst of four pulses every 4 seconds. The step detection is
switched off, and the motor is driven with the highest pulse level.
Only the PCA2000 has an EOL function.
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
14 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
8. Limiting values
Table 9.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
VI
Parameter
Conditions
VSS = 0 V
Min
−1.8
−0.5
-
Max
Unit
V
[1][2]
supply voltage
+7.0
input voltage
on all supply pins
output
+7.5
V
tsc
short circuit duration time
ambient temperature
storage temperature
electrostatic discharge voltage
indefinite
+60
s
Tamb
Tstg
−10
−30
-
°C
°C
V
+100
±2000
±200
100
[3]
[4]
[5]
Vesd
HBM
MM
-
V
Ilu
latch-up current
-
mA
[1] When writing to the OTP cells, the supply voltage (VDD) can be raised to a maximum of 12 V for a period of 1 s.
[2] Connecting the battery with reversed polarity does not destroy the circuit, but in this condition a large current flows, which rapidly
discharges the battery.
[3] HBM: Human Body Model, according to JESD22-A114.
[4] MM: Machine Model, according to JESD22-A115.
[5] Latch-up testing, according to JESD78.
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
15 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
9. Characteristics
Table 10. Characteristics
VDD = 1.55 V; VSS = 0 V; fosc = 32.768 kHz; Tamb = 25 °C; quartz crystal: RS = 40 kΩ, C1 = 2 fF to 3 fF, CL = 8.2 pF; unless
otherwise specified.
Symbol
Supply
VDD
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
normal operating mode;
1.1
1.55
3.60
V
T
amb = −10 °C to +60 °C
∆VDD
supply voltage variation ∆V/∆t = 1 V/µs
-
-
-
-
0.25
120
180
V
IDD
supply current
between motor pulses
90
120
nA
nA
between motor pulses at
VDD = 3.5 V
Tamb = −10 °C to +60 °C
-
-
-
200
135
nA
nA
stop mode;
100
pad RESET connected to
VDD
Motor output
[1]
Vsat
saturation voltage
Rmotor = 2 kΩ;
-
-
150
200
200
300
mV
T
amb = −10 °C to +60 °C
between motor pulses;
motor < 1 mA
Zo(sc)
output impedance
(short circuit)
Ω
I
Oscillator
Vstart
start voltage
1.1
5
-
-
V
gm
transconductance
start-up time
V
i(osc) ≤ 50 mV(p-p)
10
-
µS
s
tstartup
∆f/f
-
0.3
0.05
5.2
0.9
0.20
6.3
frequency stability
∆VDD = 100 mV
-
ppm
pF
CL(itg)
integrated load
capacitance
4.3
Rpar
parasitic resistance
allowed resistance between
adjacent pads
20
-
-
MΩ
Voltage level detector
Vth(EOL) EOL threshold voltage silver-oxide battery
1.30
2.35
-
1.38
2.50
−0.07
1.46
2.65
-
V
lithium battery
V
TCEOL
EOL temperature
coefficient
%/°C
Pad RESET
fo
output frequency
-
32
-
-
-
Hz
V
[2]
VO(dif)
differential output
voltage
RL = 1 MΩ; CL = 10 pF
1.4
[2]
[2]
tr
rise time
RL = 1 MΩ; CL = 10 pF
RL = 1 MΩ; CL = 10 pF
pad RESET connected to
-
-
-
1
-
µs
µs
nA
tf
fall time
1
-
Ii(AV)
average input current
10
20
V
DD or VSS
[1] P1 + ... + P4 + N1 + N2 (see Section 7.2).
[2] RL and CL are a load resistor and load capacitor, externally connected to pad RESET.
PCA2000_2001_5
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Product data sheet
Rev. 05 — 11 November 2008
16 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
10. OTP programming characteristics
Table 11. Specifications for OTP programming
See Figure 7, Figure 8 and Figure 12.
Symbol
Parameter[1]
Conditions
Min
1.5
6.6
6.2
320
6.2
9.9
Typ
Max
3.0
Unit
V
VDD
supply voltage
during programming procedure
-
VP(prog)(start) programming supply voltage (start)
VP(prog)(stop) programming supply voltage (stop)
-
6.8
V
-
6.4
V
VP(mod)
Vprestore
Vstore
supply voltage modulation
prestore voltage
for entering instructions
for prestore pulse
350
-
380
6.4
mV
V
supply voltage for writing to the
OTP cells
10.0
10.1
V
Istore
store current
for writing to the OTP cells
-
-
10
mA
ms
ms
µs
tp(start)
tp(stop)
tmod
pulse width of start pulse
pulse width of stop pulse
modulation pulse width
prestore pulse width
store pulse width
time 0
8
10
-
12
0.05
25
0.05
95
20
0.6
0.5
40
30
-
tw(prestore)
tw(store)
t0
0.5
110
30
ms
ms
ms
ms
for writing to the OTP cells
waiting time after start pulse
100
-
t1
time 1
pulse distance for incrementing
the state counter
0.7
0.8
t2
time 2
pulse distance for clocking the
data register with data = logic 0
1.6
2.6
0.1
0.5
18
1.7
2.7
0.2
-
1.8
2.8
0.3
5.0
45
ms
ms
ms
V/µs
kΩ
t3
time 3
pulse distance for clocking the
data register with data = logic 1
t4
time 4
waiting time for writing to OTP
cells
SR
Rmod
slew rate
for modulation of the supply
voltage
modulation resistance
supply current modulation
read-out resistor
30
[1] Program each word once only.
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
17 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
11. Bare die outline
Wire bond die; 8 bonding pads; 1.16 x 0.86 x 0.22 mm
PCA200xU
A
D
P
P
1
2
e
1
e
2
E
P
P
3
4
detail X
X
e
D
DIMENSIONS (mm are the original dimensions)
UNIT
A
D
E
e
1
e
2
e
D
P
P
P
P
4
1
2
3
max 0.22
nom 0.20 1.16 0.86 0.17 0.32 0.96 0.096 0.086 0.096 0.086
min 0.18 0.093 0.083 0.093 0.083
0.099 0.089 0.099 0.089
0
0.5
1 mm
mm
scale
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
08-05-09
08-05-21
PCA200xU
Fig 13. Bare die outline PCA2000U and PCA2001U
PCA2000_2001_5
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Product data sheet
Rev. 05 — 11 November 2008
18 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
WLCSP8: wafer level chip-size package; 8 bumps; 1.16 x 0.86 x 0.31 mm
PCA200xCX
D
b
e
1
A
2
e
2
A
E
A
1
detail X
e
D
X
DIMENSIONS (mm are the original dimensions)
UNIT
max 0.310 0.090 0.22 0.12
A
A
1
A
2
b
D
E
e
1
e
2
e
D
0
0.5
scale
1 mm
mm
nom 0.275 0.075 0.20 0.10 1.16 0.86 0.17 0.32 0.96
min 0.240 0.060 0.18 0.08
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
08-05-09
08-05-21
PCA200xCX
Fig 14. Bare die outline PCA2000CX and PCA2001CX
Table 12. Bonding pad and solder bump locations
Symbol
Pad
Coordinates[1]
x
y
[2]
VSS
1
2
3
4
5
6
7
8
−480
+330
+160
−160
−330
−330
−160
+160
+330
i.c.[3]
−480
OSCIN
OSCOUT
VDD
−480
−480
+480
MOT1
MOT2
RESET
+480
+480
+480
[1] All coordinates are referenced, in µm, to the center of the die (see Figure 2, Figure 13 and Figure 14).
[2] The substrate (rear side of the chip) is connected to VSS. Therefore the die pad must be either floating or
connected to VSS
[3] Pad i.c. is used for factory tests; in normal operation it should be left open-circuit, and it has an internal
pull-down resistance to VSS
.
.
PCA2000_2001_5
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Product data sheet
Rev. 05 — 11 November 2008
19 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
12. Packing information
12.1 Tray information
A
x
G
C
H
y
1,1 2,1 3,1
1,2 2,2
1,3
x,1
D
B
F
x,y
1,y
A
A
E
M
J
SECTION A-A
mgu653
Fig 15. Tray details
mgu652
The orientation of the IC in a pocket is indicated by the position of the IC type name on the surface
of the die, with respect to the cut corner on the upper left of the tray.
Fig 16. Tray alignment
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
20 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
Table 13. Tray dimensions
Dimension
Description
Value
A
B
C
D
E
F
pocket pitch; x direction
pocket pitch; y direction
pocket width; x direction
pocket width; y direction
tray width; x direction
tray width; y direction
2.15 mm
2.43 mm
1.01 mm
1.39 mm
50.67 mm
50.67 mm
4.86 mm
G
distance from cut corner to pocket (1, 1)
center
H
distance from cut corner to pocket (1, 1)
center
4.66 mm
J
tray thickness
3.94 mm
0.61 mm
20
M
x
pocket depth
number of pockets in x direction
number of pockets in y direction
y
18
PCA2000_2001_5
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Product data sheet
Rev. 05 — 11 November 2008
21 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
12.2 Unsawn wafer information
(1)
(1)
~18 µm
~18 µm
84 µm
84 µm
(1)
~18 µm
Saw lane
Saw lane
84 µm
detail X
detail Y
(1)
1
8
1
8
4
1
5
8
4
1
5
8
Y
X
4
1
5
8
4
1
5
8
4
1
5
8
4
1
5
8
4
1
5
8
4
1
5
8
4
1
5
8
4
1
5
8
4
5
4
5
Straight edge of the wafer
001aai236
The die are grouped in arrays of 2 × 6 devices. Each array is edged with a metal path. All this metal
paths have to be cut while dicing.
Fig 17. Wafer layout of PCA2000CX and PCA2001CX
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
22 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCA2000_2001_5
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Product data sheet
Rev. 05 — 11 November 2008
23 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 18) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 14 and 15
Table 14. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 15. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 18.
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
24 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 18. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
25 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
14. Revision history
Table 16. Revision history
Document ID
Release date
20081111
Data sheet status
Change notice
Supersedes
PCA2000_2001_5
Modifications:
Product data sheet
-
PCA2000_2001_4
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of NXP
• Implemented new drawings and wafer information
• Added new bare die outline drawing
PCA2000_2001_4
PCA2000_2001_3
PCA2000_2001_2
PCA2000_2001_1
20050908
20031217
20030204
20020517
Product data sheet
-
-
-
-
PCA2000_2001_3
PCA2000_2001_2
PCA2000_2001_1
-
Product data sheet
Objective specification
Preliminary specification
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
26 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Bare die — All die are tested on compliance with their related technical
15.2 Definitions
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA2000_2001_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
27 of 28
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
17. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Motor pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Step detection. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Time calibration . . . . . . . . . . . . . . . . . . . . . . . . 7
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Programming possibilities. . . . . . . . . . . . . . . . . 8
Type recognition . . . . . . . . . . . . . . . . . . . . . . . 10
Programming procedure. . . . . . . . . . . . . . . . . 10
Programming the memory cells . . . . . . . . . . . 11
Checking memory content . . . . . . . . . . . . . . . 12
Frequency tuning of assembled watch . . . . . . 13
Measurement of oscillator frequency and
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
inhibition time . . . . . . . . . . . . . . . . . . . . . . . . . 13
Customer testing. . . . . . . . . . . . . . . . . . . . . . . 14
EOL of battery . . . . . . . . . . . . . . . . . . . . . . . . 14
7.12
7.13
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 16
OTP programming characteristics . . . . . . . . . 17
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 18
9
10
11
12
12.1
12.2
Packing information. . . . . . . . . . . . . . . . . . . . . 20
Tray information . . . . . . . . . . . . . . . . . . . . . . . 20
Unsawn wafer information . . . . . . . . . . . . . . . 22
13
Soldering of SMD packages . . . . . . . . . . . . . . 23
Introduction to soldering . . . . . . . . . . . . . . . . . 23
Wave and reflow soldering . . . . . . . . . . . . . . . 23
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 24
13.1
13.2
13.3
13.4
14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 26
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 27
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 27
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 November 2008
Document identifier: PCA2000_2001_5
相关型号：
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PCA2001U/10AC/1,00
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PCA2001U/AB/1,026
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