PCA85063ATTA_技术文档

PCA85063A

Automotive tiny Real-Time Clock/calendar with alarm function

and I²C-bus

Rev. 4 — 30 March 2018

Product data sheet

1. General description

The PCA85063A is a CMOS¹Real-Time Clock (RTC) and calendar optimized for low

power consumption. An offset register allows fine-tuning of the clock. All addresses and

data are transferred serially via the two-line bidirectional I²C-bus. Maximum data rate is

400 kbit/s. The register address is incremented automatically after each written or read

data byte.

For a selection of NXP Real-Time Clocks, see Table 45 on page 50

2. Features and benefits

 AEC-Q100 grade 2 compliant for

 High temperature operation range:

40 C to +105 C

automotive applications

 Provides year, month, day, weekday,

hours, minutes, and seconds based on a

32.768 kHz quartz crystal

 Clock operating voltage: 0.9 V to 5.5 V

 Low current; typical 0.25 A at

V_DD= 3.0 V and T_amb= 25 C

 400 kHz two-line I²C-bus interface

(at V_DD= 1.8 V to 5.5 V)

 Programmable clock output for

peripheral devices (32.768 kHz,

16.384 kHz, 8.192 kHz, 4.096 kHz,

2.048 kHz, 1.024 kHz, and 1 Hz)

 Selectable integrated oscillator load

capacitors for C_L= 7 pF or C_L= 12.5 pF

 Alarm function

 Countdown timer

 Minute and half minute interrupt

 Internal Power-On Reset (POR)

 Oscillator stop detection function

 Programmable offset register for

frequency adjustment

3. Applications

 Tracking time of the day

 Dashboard

 Accurate timing

 Infotainment unit

 Air condition

 Center stack

 Telematics

 Body control and battery management

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 22.

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

PCA85063ATT

TSSOP8

plastic thin shrink small outline package; SOT505-1

8 leads; body width 3 mm

4.1 Ordering options

Table 2.

Ordering options

Product type number Orderable part number Sales item

(12NC)

Delivery form

IC

revision

PCA85063ATT/A

PCA85063ATT/AJ

935305541118 tape and reel, 13 inch

1

5. Marking

Table 3.

Marking codes

Product type number

PCA85063ATT/A

Marking code

063Q

6. Block diagram

26&2

26&,

ꢀꢁꢂN+]

26&,//$725

&/.287

',9,'(5

&/2&.ꢂ287

&/2&.

&$/,%5$7,21

2))6(7

32:(5ꢃ21

5(6(7

9''

966

6<67(0

&21752/

,17(55837

&21752/

,17

6'$

6&/

ꢁ

O &ꢃ%86

5($/ꢃ7,0(

&/2&.

,17(5)$&(

$/$50ꢂ$1'

7,0(5

&21752/

3&$ꢀꢁꢂꢃꢄ$

DDDꢀꢁꢂꢃꢄꢂꢅ

Fig 1. Block diagram of PCA85063A

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

2 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

7. Pinning information

7.1 Pinning

26&, ꢄ

26&2 ꢁ

,17 ꢀ

ꢅ 9''

ꢆ &/.287

ꢇ 6&/

3&$ꢀꢁꢂꢃꢄ$77

966 ꢈ

ꢉ 6'$

DDDꢀꢁꢂꢃꢄꢂꢆ

For mechanical details, see Figure 30.

Fig 2. Pin configuration for TSSOP8 (PCA85063ATT)

7.2 Pin description

Table 4.

Pin description

Input or input/output pins must always be at a defined level (V_SSor V_DD) unless otherwise specified.

Symbol

Type

Description

PCA85063ATT

OSCI

1

2

3

4

5

6

7

8

input

oscillator input

OSCO

INT^[1]

output

supply

input/output

input

oscillator output

interrupt output (open-drain)

ground supply voltage

serial data line

VSS

SDA^[1]

SCL^[1]

CLKOUT

VDD

serial clock input

output

supply

clock output (push-pull)

supply voltage

[1] NXP recommends tying VDD of the device and VDD of all the external pull-up resistors to the same Power

Supply.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

3 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

8. Functional description

The PCA85063A contains 18 8-bit registers with an auto-incrementing register address,

an on-chip 32.768 kHz oscillator with integrated capacitors, a frequency divider which

provides the source clock for the Real-Time Clock (RTC) and calender, and an I²C-bus

interface with a maximum data rate of 400 kbit/s.

The built-in address register will increment automatically after each read or write of a data

byte up to the register 11h. After register 11h, the auto-incrementing will wrap around to

address 00h (see Figure 3).

DGGUHVVꢂUHJLVWHU

ꢊꢊK

ꢊꢄK

DXWRꢃLQFUHPHQW

ꢊꢁK

ꢊꢀK

ꢋꢋꢋ

ꢊ)K

ꢄꢊK

ꢄꢄK

ZUDSꢂDURXQG

DDDꢀꢁꢁꢆꢆꢃꢂ

Fig 3. Handling address registers

All registers (see Table 5) are designed as addressable 8-bit parallel registers although

not all bits are implemented. The first two registers (memory address 00h and 01h) are

used as control and status register. The register at address 02h is an offset register

allowing the fine-tuning of the clock; and at 03h is a free RAM byte. The addresses 04h

through 0Ah are used as counters for the clock function (seconds up to years counters).

Address locations 0Bh through 0Fh contain alarm registers which define the conditions for

an alarm. The registers at 10h and 11h are for the timer function.

The Seconds, Minutes, Hours, Days, Months, and Years as well as the corresponding

alarm registers are all coded in Binary Coded Decimal (BCD) format. When one of the

RTC registers is written or read, the contents of all time counters are frozen. Therefore,

faulty writing or reading of the clock and calendar during a carry condition is prevented.

For details on maximum access time, see Section 8.4 on page 23.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

4 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

8.2 Control registers

To ensure that all control registers will be set to their default values, the V_DDlevel must be

at zero volts at initial power-up. If this is not possible, a reset must be initiated with the

software reset command when power is stable. Refer to Section 8.2.1.3 for details.

8.2.1 Register Control_1

Table 6.

Control_1 - control and status register 1 (address 00h) bit description

Bit

Symbol

Value

Description

Reference

7

EXT_TEST

external clock test mode

normal mode

Section 8.2.1.1

0^[1]

1

external clock test mode

unused

6

5

-

0

-

STOP

STOP bit

Section 8.2.1.2

0^[1]

1

RTC clock runs

RTC clock is stopped; all RTC divider chain

flip-flops are asynchronously set logic 0

4

SR

software reset

Section 8.2.1.3

0^[1]

1

no software reset

initiate software reset^[2]; this bit always

returns a 0 when read

3

2

-

0

unused

-

CIE

correction interrupt enable

no correction interrupt generated

Section 8.2.3

0^[1]

1

interrupt pulses are generated at every

correction cycle

1

0

12_24

12 or 24-hour mode

Section 8.3.3

Section 8.5.3

0^[1]

1

24-hour mode is selected

12-hour mode is selected

CAP_SEL

internal oscillator capacitor selection for

quartz crystals with a corresponding load

capacitance

-

0^[1]

1

7 pF

12.5 pF

[1] Default value.

[2] For a software reset, 01011000 (58h) must be sent to register Control_1 (see Section 8.2.1.3).

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

6 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

8.2.1.1 EXT_TEST: external clock test mode

A test mode is available which allows for on-board testing. In this mode, it is possible to

set up test conditions and control the operation of the RTC.

The test mode is entered by setting bit EXT_TEST in register Control_1. Then

pin CLKOUT becomes an input. The test mode replaces the internal clock signal with the

signal applied to pin CLKOUT.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a

maximum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided

down to 1 Hz by a 2⁶divide chain called a prescaler. The prescaler can be set into a

known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0. (STOP

must be cleared before the prescaler can operate again.)

From a stop condition, the first 1 second increment will take place after 32 positive edges

on pin CLKOUT. Thereafter, every 64 positive edges cause a 1 second increment.

Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When

entering the test mode, no assumption as to the state of the prescaler can be made.

Operation example:

1. Set EXT_TEST test mode (register Control_1, bit EXT_TEST = 1).

2. Set STOP (register Control_1, bit STOP = 1).

3. Clear STOP (register Control_1, bit STOP = 0).

4. Set time registers to desired value.

5. Apply 32 clock pulses to pin CLKOUT.

6. Read time registers to see the first change.

7. Apply 64 clock pulses to pin CLKOUT.

8. Read time registers to see the second change.

Repeat 7 and 8 for additional increments.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

7 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

8.2.1.2 STOP: STOP bit function

The function of the STOP bit (see Figure 4) is to allow for accurate starting of the time

circuits. The STOP bit function causes the upper part of the prescaler (F₂to F₁₄) to be

held in reset and thus no 1 Hz ticks are generated. It also stops the output of clock

frequencies below 8 kHz on pin CLKOUT.

26&,//$725ꢂ6723

VHWWLQJꢂWKHꢂ26ꢂIODJ

'(7(&725

ꢀꢁꢆꢇꢅꢂ+]

)

ꢄꢇꢀꢅꢈꢂ+]

)

ꢅꢄꢌꢁꢂ+]

)

ꢈꢊꢌꢇꢂ+]

)

ꢁꢂ+]

)

ꢄꢈ

ꢊ

ꢄ

ꢁ

ꢄꢀ

26&,//$725

ꢄꢂ+]ꢂWLFN

5(6(7

6723

DDDꢀꢁꢁꢆꢆꢂꢇ

Fig 4. STOP bit functional diagram

The time circuits can then be set and do not increment until the STOP bit is released (see

Figure 5 and Table 7).

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

8 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

Table 7.

Bit

First increment of time circuits after STOP bit release

[1]

Prescaler bits

F₀F₁-F₂to F₁₄

1 Hz tick

Time

Comment

STOP

hh:mm:ss

Clock is running normally

0

01-0 0001 1101 0100

12:45:12

prescaler counting normally

STOP bit is activated by user. F₀F₁are not reset and values cannot be predicted externally

1

XX-0 0000 0000 0000

12:45:12

prescaler is reset; time circuits are frozen

New time is set by user

1

XX-0 0000 0000 0000

08:00:00

prescaler is reset; time circuits are frozen

STOP bit is released by user

0

XX-0 0000 0000 0000

XX-1 0000 0000 0000

XX-0 1000 0000 0000

XX-1 1000 0000 0000

:

08:00:00

:

prescaler is now running

-

ꢊꢋꢉꢊꢆꢅꢄꢀ

WR

ꢊꢋꢉꢊꢆꢌꢀꢉꢂV

-

:

11-1 1111 1111 1110

00-0 0000 0000 0001

10-0 0000 0000 0001

:

08:00:00

08:00:01

:

-

0 to 1 transition of F₁₄increments the time circuits

-

:

11-1 1111 1111 1111

00-0 0000 0000 0000

10-0 0000 0000 0000

:

08:00:01

:

-

ꢄꢋꢊꢊꢊꢊꢊꢊꢂV

-

:

11-1 1111 1111 1110

00-0 0000 0000 0001

08:00:01

08:00:02

-

0 to 1 transition of F₁₄increments the time circuits

DDDꢀꢁꢁꢆꢆꢂꢈ

[1] F₀is clocked at 32.768 kHz.

The lower two stages of the prescaler (F₀and F₁) are not reset. And because the I²C-bus

is asynchronous to the crystal oscillator, the accuracy of restarting the time circuits is

between zero and one 8.192 kHz cycle (see Figure 5).

ꢅꢄꢌꢁꢂ+]

VWRSꢂUHOHDVHG

ꢊꢂVꢂWRꢂꢄꢁꢁꢂV

DDDꢀꢁꢁꢆꢆꢂꢄ

Fig 5. STOP bit release timing

The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP

bit is released. The uncertainty is caused by the prescaler bits F₀and F₁not being reset

(see Table 7) and the unknown state of the 32 kHz clock.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

9 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

8.2.1.3 Software reset

A reset is automatically generated at power-on. There is a low probability that some

devices will have corruption of the registers after the automatic power-on reset if the

device is powered up with a residual V_DDlevel. It is required that the V_DDstarts at zero

volts at power up or upon power cycling to ensure that there is no corruption of the

registers. If this is not possible, a reset must be initiated after power-up (i.e. when power is

stable) with the software reset command. Software reset command means setting bits 6,

4, and 3 in register Control_1 (00h) logic 1 and all other bits logic 0 by sending the bit

sequence 01011000 (58h), see Figure 6.

VODYHꢂDGGUHVV

DGGUHVVꢂꢊꢊK

VRIWZDUHꢂUHVHWꢂꢉꢅK

5ꢍ:

ꢊ

V

ꢄ

ꢊ

ꢄ

ꢊ

ꢄ

$

ꢊ

$

ꢊ

ꢄ

ꢊ

ꢄ

ꢊ

$ 3ꢍ6

6'$

6&/

LQWHUQDO

UHVHWꢂVLJQDO

DDDꢀꢁꢁꢆꢆꢂꢉ

After sending the software reset command, it is recommended to re-initialize the interface by a STOP and START.

Fig 6. Software reset command

In reset state, all registers are set according to Table 8 and the address pointer returns to

address 00h.

Table 8.

Registers reset values

Address Register name

Bit

7

0

1

0

1

6

0

5

0

4

0

3

0

2

0

1

0

1

0

1

0

1

0

1

0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

Control_1

Control_2

Offset

RAM_byte

Seconds

Minutes

Hours

Days

Weekdays

Months

Years

Second_alarm

Minute_alarm

Hour_alarm

Day_alarm

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

10 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

Table 8.

Registers reset values …continued

Address Register name

Bit

7

6

0

5

0

4

0

1

3

0

1

2

0

1

0

0Fh

10h

11h

Weekday_alarm

Timer_value

1

0

Timer_mode

0

The PCA85063A resets to:

Time — 00:00:00

Date — 20000101

Weekday — Saturday

8.2.2 Register Control_2

Table 9.

Control_2 - control and status register 2 (address 01h) bit description

Bit

Symbol

Value

Description

Reference

7

AIE

alarm interrupt

disabled

Section 8.2.2.1

Section 8.5.6

0^[1]

1

enabled

6

AF

alarm flag

Section 8.2.2.1

Section 8.5.6

0^[1]

read: alarm flag inactive

write: alarm flag is cleared

read: alarm flag active

write: alarm flag remains unchanged

minute interrupt

disabled

1

5

4

3

MI

Section 8.2.2.2

Section 8.2.2.3

0^[1]

1

enabled

HMI

TF

half minute interrupt

disabled

Section 8.2.2.2

Section 8.2.2.3

0^[1]

1

enabled

timer flag

Section 8.2.2.1

Section 8.2.2.3

Section 8.6.3

0^[1]

no timer interrupt generated

flag set when timer interrupt generated

CLKOUT control

1

2 to 0 COF[2:0]

[1] Default value.

see Table 11

Section 8.2.2.4

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

11 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

8.2.2.1 Alarm interrupt

+0,

6(&21'6ꢂ&2817(5

0,187(6ꢂ&2817(5

+0,ꢍ0,

&/($5

+0, 0,

6(7

ꢊ

ꢄ

38/6(

*(1(5$725ꢂꢄ

0,

75,**(5

&/($5

IURPꢂLQWHUIDFHꢎ

FOHDUꢂ7)

7,B73

WRꢂLQWHUIDFHꢎ

UHDGꢂ7)

7,0(5ꢂ)/$*

7)

7,(

&2817'2:1ꢂ&2817(5

7(

6(7

ꢊ

ꢄ

38/6(

*(1(5$725ꢂꢁ

&/($5

,17ꢂꢂ

75,**(5

&/($5

WRꢂLQWHUIDFHꢎ

UHDGꢂ$)

$,(

&,(

$/$50ꢂ)/$*

$)

6(7

H[DPSOH

$,(

VHWꢂDODUP

IODJꢏꢂ$)

&/($5

ꢊ

ꢄ

IURPꢂLQWHUIDFHꢎ

FOHDUꢂ$)

38/6(

*(1(5$725ꢂꢀ

RIIVHWꢂFLUFXLWꢎ

DGGꢍVXEVWUDFW

SXOVH

75,**(5

&/($5

IURPꢂLQWHUIDFHꢎ

VHWꢂ&,(

DDDꢀꢁꢁꢆꢆꢃꢅ

Fig 7. Interrupt scheme

AIE: This bit activates or deactivates the generation of an interrupt when AF is asserted,

respectively.

AF: When an alarm occurs, AF is set logic 1. This bit maintains its value until overwritten

by command. To prevent one flag being overwritten while clearing another, a logic AND is

performed during a write access.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

12 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

8.2.2.2 MI and HMI: minute and half minute interrupt

The minute interrupt (bit MI) and half minute interrupt (bit HMI) are pre-defined timers for

generating interrupt pulses on pin INT; see Figure 8. The timers are running in sync with

the seconds counter (see Table 19 on page 19).

The minute and half minute interrupts must only be used when the frequency offset is set

to normal mode (MODE = 0), see Section 8.2.3. In normal mode, the interrupt pulses on

pin INT are ¹⁄₆₄s wide.

When starting MI, the first interrupt will be generated after 1 second to 59 seconds. When

starting HMI, the first interrupt will be generated after 1 second to 29 seconds.

Subsequent periods do not have such a delay. The timers can be enabled independently

from one another. However, a minute interrupt enabled on top of a half minute interrupt is

not distinguishable.

VHFRQGVꢂFRXQWHU

PLQXWHVꢂFRXQWHU

ꢉꢅ

ꢉꢌ

ꢄꢄ

ꢊꢊ

ꢄꢁ

ꢊꢊ

ꢊꢄ

,17ꢂZKHQꢂ0,ꢂHQDEOHG

7)ꢂZKHQꢂ0,ꢂHQDEOHG

DDDꢀꢁꢁꢆꢆꢂꢊ

In this example, the TF flag is not cleared after an interrupt.

Fig 8. INT example for MI

Table 10. Effect of bits MI and HMI on INT generation

Minute interrupt (bit MI)

Half minute interrupt (bit HMI)

Result

0

1

0

1

0

1

no interrupt generated

an interrupt every minute

an interrupt every 30 s

The duration of the timer is affected by the register Offset (see Section 8.2.3). Only when

OFFSET[6:0] has the value 00h the periods are consistent.

8.2.2.3 TF: timer flag

The timer flag (bit TF) is set logic 1 on the first trigger of MI, HMI, or the countdown timer.

The purpose of the flag is to allow the controlling system to interrogate what caused the

interrupt: timer or alarm. The flag can be read and cleared by command.

The status of the timer flag TF can affect the INT pulse generation depending on the

setting of TI_TP (see Section 8.6.2 “Register Timer_mode” on page 28):

• When TI_TP is set logic 1

– an INT pulse is generated independent of the status of the timer flag TF

– TF stays set until it is cleared

– TF does not affect INT

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

13 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

– the countdown timer runs in a repetitive loop and keeps generating timed periods

• When TI_TP is set logic 0

– the INT generation follows the TF flag

– TF stays set until it is cleared

– If TF is not cleared before the next coming interrupt, no INT is generated

– the countdown timer stops after the first countdown

8.2.2.4 COF[2:0]: Clock output frequency

A programmable square wave is available at pin CLKOUT. Operation is controlled by the

COF[2:0] bits in the register Control_2. Frequencies of 32.768 kHz (default) down to 1 Hz

can be generated for use as a system clock, microcontroller clock, input to a charge

pump, or for calibration of the oscillator.

Pin CLKOUT is a push-pull output and enabled at power-on. CLKOUT can be disabled by

setting COF[2:0] to 111. When disabled, the CLKOUT is LOW.

The duty cycle of the selected clock is not controlled. However, due to the nature of the

clock generation, all clock frequencies except 32.768 kHz have a duty cycle of 50 : 50.

The STOP bit function can also affect the CLKOUT signal, depending on the selected

frequency. When the STOP bit is set logic 1, the CLKOUT pin generates a continuous

LOW for those frequencies that can be stopped. For more details of the STOP bit function,

see Section 8.2.1.2.

Table 11. CLKOUT frequency selection

COF[2:0]

000^[2]

001

CLKOUT frequency (Hz) Typical duty cycle^[1]

Effect of STOP bit

no effect

32768

16384

8192

60 : 40 to 40 : 60

50 : 50

-

no effect

010

no effect

011

4096

CLKOUT = LOW

-

100

2048

101

1024

1^[3]

110

111

CLKOUT = LOW

[1] Duty cycle definition: % HIGH-level time : % LOW-level time.

[2] Default value.

[3] 1 Hz clock pulses are affected by offset correction pulses.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

14 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

8.2.3 Register Offset

The PCA85063A incorporates an offset register (address 02h) which can be used to

implement several functions, such as:

• Accuracy tuning

• Aging adjustment

• Temperature compensation

Table 12. Offset - offset register (address 02h) bit description

Bit

Symbol

Value

Description

offset mode

7

MODE

0^[1]

normal mode: offset is made once every two

hours

1

course mode: offset is made every 4 minutes

6 to 0 OFFSET[6:0]

[1] Default value.

see Table 13

offset value

For MODE = 0, each LSB introduces an offset of 4.34 ppm. For MODE = 1, each LSB

introduces an offset of 4.069 ppm. The offset value is coded in two’s complement giving a

range of +63 LSB to 64 LSB.

Table 13. Offset values

OFFSET[6:0]

Offset value in

decimal

Offset value in ppm

Normal mode

MODE = 0

Fast mode

MODE = 1

0111111

0111110

:

+63

+62

:

+273.420

+269.080

:

+256.347

+252.278

:

0000010

0000001

0000000^[1]

1111111

1111110

:

+2

+1

0

+8.680

+4.340

0^[1]

+8.138

+4.069

0^[1]

1

2

:

4.340

8.680

:

4.069

8.138

:

1000001

1000000

63

64

273.420

277.760

256.347

260.416

[1] Default value.

The correction is made by adding or subtracting clock correction pulses, thereby changing

the period of a single second but not by changing the oscillator frequency.

It is possible to monitor when correction pulses are applied. To enable correction interrupt

generation, bit CIE (register Control_1) has to be set logic 1. At every correction cycle, a

pulse is generated on pin INT. The pulse width depends on the correction mode. If

multiple correction pulses are applied, an interrupt pulse is generated for each correction

pulse applied.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

15 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

8.2.3.1 Correction when MODE = 0

The correction is triggered once every two hours and then correction pulses are applied

once per minute until the programmed correction values have been implemented.

Table 14. Correction pulses for MODE = 0

Correction value

Update every n^thhour Minute

Correction pulses on

INT per minute^[1]

+1 or 1

+2 or 2

+3 or 3

:

2

00

1

:

2

00 and 01

00, 01, and 02

:

2

:

+59 or 59

+60 or 60

+61 or 61

2

00 to 58

00 to 59

00

1

2

2nd and next hour

+62 or 62

+63 or 63

64

2

00 to 59

00 and 01

00 to 59

00, 01, and 02

00 to 59

00, 01, 02, and 03

2nd and next hour

02

2nd and next hour

02

2nd and next hour

[1] The correction pulses on pin INT are ¹

⁄₆₄s wide.

In MODE = 0, any timer or clock output using a frequency below 64 Hz is affected by the

clock correction (see Table 15).

Table 15. Effect of correction pulses on frequencies for MODE = 0

Frequency (Hz)

Effect of correction

CLKOUT

32768

no effect

affected

16384

8192

4096

2048

1024

1

Timer source clock

4096

64

no effect

affected

1

⁄

60

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

16 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

8.2.3.2 Correction when MODE = 1

The correction is triggered once every four minutes and then correction pulses are applied

once per second up to a maximum of 60 pulses. When correction values greater than 60

pulses are used, additional correction pulses are made in the 59^thsecond.

Clock correction is made more frequently in MODE = 1; however, this can result in higher

power consumption.

Table 16. Correction pulses for MODE = 1

Correction value

Update every n^th

minute

Second

Correction pulses on

INT per second^[1]

+1 or 1

+2 or 2

+3 or 3

:

2

:

00

1

:

00 and 01

00, 01, and 02

:

+59 or 59

+60 or 60

+61 or 61

2

00 to 58

00 to 59

00 to 58

59

1

2

1

3

1

4

1

5

+62 or 62

+63 or 63

64

00 to 58

59

00 to 58

59

00 to 58

59

[1] The correction pulses on pin INT are ¹

⁄₁₀₂₄s wide. For multiple pulses, they are repeated at an interval of

1

⁄₅₁₂s.

In MODE = 1, any timer source clock using a frequency below 1.024 kHz is also affected

by the clock correction (see Table 17).

Table 17. Effect of correction pulses on frequencies for MODE = 1

Frequency (Hz)

Effect of correction

CLKOUT

32768

no effect

affected

16384

8192

4096

2048

1024

1

Timer source clock

4096

64

no effect

affected

1

⁄

60

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

17 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

8.2.3.3 Offset calibration workflow

The calibration offset has to be calculated based on the time. Figure 9 shows the workflow

how the offset register values can be calculated:

VDPSOHꢂFDOFXODWLRQꢎ

0HDVXUHꢂWKHꢂIUHTXHQF\ꢂRQꢂSLQꢂ&/.287ꢎ

I

PHDV

ꢀꢁꢆꢇꢅꢋꢈꢅꢂ+]

ꢀꢊꢋꢉꢄꢆꢄꢀꢄꢂV

&RQYHUWꢂWRꢂWLPHꢎ

ꢂ ꢂꢄꢂꢍꢂI

W

PHDV

&DOFXODWHꢂWKHꢂGLIIHUHQFHꢂWRꢂWKHꢂLGHDO

SHULRGꢂRIꢂꢄꢂꢍꢂꢀꢁꢆꢇꢅꢋꢊꢊꢎꢂ

ꢊꢋꢊꢊꢊꢈꢈꢆꢂV

ꢄꢈꢋꢇꢈꢅꢂSSP

'

ꢂ ꢂꢄꢂꢍꢂꢀꢁꢆꢇꢅꢂꢃꢂW

PHDV

&DOFXODWHꢂWKHꢂSSPꢂGHYLDWLRQꢂFRPSDUHG

WRꢂWKHꢂPHDVXUHGꢂYDOXHꢎꢂ

(

ꢂ ꢂꢄꢊꢊꢊꢊꢊꢊꢂîꢂ'

ꢂꢂꢍꢂW

SSP

PHDV PHDV

&DOFXODWHꢂWKHꢂRIIVHWꢂUHJLVWHUꢂYDOXHꢎ

0RGHꢂ ꢂꢊꢂꢐORZꢂSRZHUꢑꢎ

2IIVHWꢂYDOXHꢂ ꢂ(

ꢂꢍꢂꢈꢋꢀꢈ

ꢀꢋꢀꢆꢉꢂ

ꢀꢋꢇꢊꢊꢂ

ꢀꢂFRUUHFWLRQꢂSXOVHV

SSP

DUHꢂQHHGHG

0RGHꢂ ꢂꢄꢂꢐIDVWꢂFRUUHFWLRQꢑ

2IIVHWꢂYDOXHꢂ ꢂ( ꢂꢍꢂꢈꢋꢊꢇꢌ

ꢈꢂFRUUHFWLRQꢂSXOVHV

DUHꢂQHHGHG

SSP

DDDꢀꢁꢁꢆꢃꢄꢇ

Fig 9. Offset calibration calculation workflow

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

18 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

ꢐꢁꢑ

ꢐꢄꢑ

ꢐꢀꢑ

ꢃꢇ

ꢃꢈ

ꢃꢁ

ꢊ

ꢁ

ꢈ

ꢇ

ꢅ

ꢄꢊ

ꢄꢁ

ꢄꢈ

ꢄꢇ

GHYLDWLRQꢂDIWHU

ꢂFRUUHFWLRQꢂLQꢂ

02'(ꢂ ꢂꢄ

GHYLDWLRQꢂDIWHU

ꢂFRUUHFWLRQꢂLQꢂ

02'(ꢂ ꢂꢊ

PHDVXUHGꢍFDOFXODWHG

GHYLDWLRQꢂꢂꢂꢄꢈꢋꢇꢈꢅꢂSSP

ꢂꢂꢃꢄꢋꢇꢁꢅꢂSSP

ꢂꢂꢂꢒꢄꢋꢇꢁꢅꢂSSP

DDDꢀꢁꢁꢆꢃꢄꢂ

With the offset calibration an accuracy of 2 ppm (0.5  offset per LSB) can be reached (see

Table 13).

1 ppm corresponds to a time deviation of 0.0864 seconds per day.

(1) 3 correction pulses in MODE = 0 correspond to 13.02 ppm.

(2) 4 correction pulses in MODE = 1 correspond to 16.276 ppm.

(3) Reachable accuracy zone.

Fig 10. Result of offset calibration

8.2.4 Register RAM_byte

The PCA85063A provides a free RAM byte, which can be used for any purpose, for

example, status byte of the system.

Table 18. RAM_byte - 8-bit RAM register (address 03h) bit description

Bit

Symbol

Value

Description

7 to 0 B[7:0]

00000000^[1]to RAM content

11111111

[1] Default value.

8.3 Time and date registers

Most of the registers are coded in the BCD format to simplify application use.

8.3.1 Register Seconds

Table 19. Seconds - seconds register (address 04h) bit description

Bit

Symbol

Value

Place value Description

oscillator stop

7

OS

0

1^[1]

-

clock integrity is guaranteed

clock integrity is not

guaranteed; oscillator has

stopped or has been

interrupted

6 to 4 SECONDS

3 to 0

0

^[1]to 5

0^[1]to 9

ten’s place actual seconds coded in BCD

format, see Table 20

unit place

[1] Default value.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

19 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

Table 20. Seconds coded in BCD format

Seconds value in Upper-digit (ten’s place)

Digit (unit place)

decimal

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00^[1]

01

02

:

0

:

0

:

0

:

0

:

0

:

0

1

:

0

1

0

:

09

10

:

0

:

0

:

0

1

:

1

0

:

0

:

0

:

1

0

:

58

59

1

0

1

0

1

[1] Default value.

8.3.1.1 OS: Oscillator stop

When the oscillator of the PCA85063A is stopped, the OS flag is set. The oscillator can be

stopped, for example, by connecting one of the oscillator pins OSCI or OSCO to ground.

The oscillator is considered to be stopped during the time between power-on and stable

crystal resonance. This time can be in the range of 200 ms to 2 s depending on crystal

type, temperature, and supply voltage.

The flag remains set until cleared by command (see Figure 11). If the flag cannot be

cleared, then the oscillator is not running. This method can be used to monitor the

oscillator and to determine if the supply voltage has reduced to the point where oscillation

fails.

26ꢂ ꢂꢄꢂDQGꢂIODJꢂFDQꢂQRWꢂEHꢂFOHDUHG

26ꢂ ꢂꢄꢂDQGꢂIODJꢂFDQꢂEHꢂFOHDUHG

9

''

RVFLOODWLRQ

26ꢂIODJ

26ꢂIODJꢂVHWꢂZKHQ

RVFLOODWLRQꢂVWRSV

26ꢂIODJꢂFOHDUHG

E\ꢂVRIWZDUH

W

RVFLOODWLRQꢂQRZꢂVWDEOH

DDDꢀꢁꢁꢆꢆꢅꢁ

Fig 11. OS flag

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

20 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

8.3.2 Register Minutes

Table 21. Minutes - minutes register (address 05h) bit description

Bit

Symbol

Value

Place value Description

- unused

7

-

0

6 to 4 MINUTES

3 to 0

0^[1]to 5

ten’s place actual minutes coded in BCD

format

0

^[1]to 9

unit place

[1] Default value.

8.3.3 Register Hours

Table 22. Hours - hours register (address 06h) bit description

Bit

Symbol

Value

Place value Description

7 to 6

-

00

-

unused

12-hour mode^[1]

5

AMPM

AM/PM indicator

0^[2]

1

-

AM

PM

4

HOURS

0

^[2]to 1

^[2]to 9

ten’s place actual hours in 12-hour mode

coded in BCD format

3 to 0

unit place

24-hour mode^[1]

5 to 4 HOURS

3 to 0

0^[2]to 2

^[2]to 9

ten’s place actual hours in 24-hour mode

coded in BCD format

0

unit place

[1] Hour mode is set by the 12_24 bit in register Control_1.

[2] Default value.

8.3.4 Register Days

Table 23. Days - days register (address 07h) bit description

Bit

Symbol

Value

Place value Description

- unused

7 to 6

-

00

5 to 4 DAYS^[1]

0^[2]to 3

ten’s place actual day coded in BCD format

3 to 0

0

^[3]to 9

unit place

[1] If the year counter contains a value, which is exactly divisible by 4 (including the year 00), the PCA85063A

compensates for leap years by adding a 29th day to February.

[2] Default value.

[3] Default value is 1.

8.3.5 Register Weekdays

Table 24. Weekdays - weekdays register (address 08h) bit description

Bit

Symbol

Value

00000

0 to 6

Description

7 to 3

-

unused

2 to 0 WEEKDAYS

actual weekday values, see Table 25

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

21 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

Table 25. Weekday assignments

Day^[1]

Bit

2

1

0

1

0

1

0

1

0

1

0

1

0

Sunday

Monday

Tuesday

0

Wednesday

0

Thursday

1

Friday

Saturday^[2]

1

[1] Definition may be reassigned by the user.

[2] Default value.

8.3.6 Register Months

Table 26. Months - months register (address 09h) bit description

Bit

Symbol

-

Value

000

Place value Description

- unused

7 to 5

4

MONTHS

0 to 1

0 to 9

ten’s place actual month coded in BCD

format, see Table 27

3 to 0

unit place

Table 27. Month assignments in BCD format

Month

Upper-digit

(ten’s place)

Digit (unit place)

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

0

Bit 0

1

January^[1]

February

March

0

1

0

1

April

0

1

0

May

0

1

0

1

June

0

1

0

July

0

1

August

September

October

November

December

0

1

0

1

0

1

0

1

0

1

0

1

0

[1] Default value.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

22 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

8.3.7 Register Years

Table 28. Years - years register (0Ah) bit description

Bit

Symbol

Value

Place value Description

ten’s place actual year coded in BCD format

unit place

7 to 4 YEARS

3 to 0

0^[1]to 9

0

^[1]to 9

[1] Default value.

8.4 Setting and reading the time

Figure 12 shows the data flow and data dependencies starting from the 1 Hz clock tick.

ꢄꢂ+]ꢂWLFN

6(&21'6

0,187(6

ꢄꢁBꢁꢈꢂKRXUꢂPRGH

+2856

'$<6

/($3ꢂ<($5

&$/&8/$7,21

:((.'$<

0217+6

<($56

DDDꢀꢁꢁꢆꢆꢅꢂ

Fig 12. Data flow for the time function

During read/write operations, the time counting circuits (memory locations 04h through

0Ah) are blocked.

The blocking prevents

• Faulty reading of the clock and calendar during a carry condition

• Incrementing the time registers during the read cycle

After this read/write access is completed, the time circuit is released again and any

pending request to increment the time counters that occurred during the read/write access

is serviced. A maximum of 1 request can be stored; therefore, all accesses must be

completed within 1 second (see Figure 13).

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

23 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

WꢂꢓꢂꢄꢂV

67$57

6/$9(ꢂ$''5(66

'$7$

6723

DDDꢀꢁꢁꢆꢆꢅꢅ

Fig 13. Access time for read/write operations

Because of this method, it is very important to make a read or write access in one go, that

is, setting or reading seconds through to years should be made in one single access.

Failing to comply with this method could result in the time becoming corrupted.

As an example, if the time (seconds through to hours) is set in one access and then in a

second access the date is set, it is possible that the time will increment between the two

accesses. A similar problem exists when reading. A roll-over may occur between reads

thus giving the minutes from one moment and the hours from the next.

Recommended method for reading the time:

1. Send a START condition and the slave address (see Table 39 on page 33) for write

(A2h)

2. Set the address pointer to 4 (Seconds) by sending 04h

3. Send a RESTART condition or STOP followed by START

4. Send the slave address for read (A3h)

5. Read Seconds

6. Read Minutes

7. Read Hours

8. Read Days

9. Read Weekdays

10. Read Months

11. Read Years

12. Send a STOP condition

8.5 Alarm registers

8.5.1 Register Second_alarm

Table 29. Second_alarm - second alarm register (address 0Bh) bit description

Bit

Symbol

Value

Place value Description

second alarm

7

AEN_S

0

1^[1]

-

enabled

disabled

6 to 4 SECOND_ALARM

3 to 0

0

^[1]to 5

^[1]to 9

ten’s place second alarm information

coded in BCD format

unit place

[1] Default value.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

24 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

8.5.2 Register Minute_alarm

Table 30. Minute_alarm - minute alarm register (address 0Ch) bit description

Bit

Symbol

Value

Place value Description

minute alarm

7

AEN_M

0

1^[1]

-

enabled

disabled

6 to 4 MINUTE_ALARM

3 to 0

0

^[1]to 5

^[1]to 9

ten’s place minute alarm information coded

in BCD format

unit place

[1] Default value.

8.5.3 Register Hour_alarm

Table 31. Hour_alarm - hour alarm register (address 0Dh) bit description

Bit

Symbol

Value

Place value Description

hour alarm

7

AEN_H

0

1^[1]

-

enabled

disabled

6

-

0

unused

12-hour mode^[2]

5

AMPM

AM/PM indicator

0^[1]

1

-

AM

PM

4

HOUR_ALARM

0

^[1]to 1

^[1]to 9

ten’s place hour alarm information in

12-hour mode coded in BCD

3 to 0

unit place

format

24-hour mode^[2]

5 to 4 HOUR_ALARM

3 to 0

0^[1]to 2

^[1]to 9

ten’s place hour alarm information in

24-hour mode coded in BCD

0

unit place

format

[1] Default value.

[2] Hour mode is set by the 12_24 bit in register Control_1.

8.5.4 Register Day_alarm

Table 32. Day_alarm - day alarm register (address 0Eh) bit description

Bit

Symbol

Value

Place value Description

day alarm

7

AEN_D

0

1^[1]

-

enabled

disabled

6

-

0

unused

5 to 4 DAY_ALARM

3 to 0

0

^[1]to 3

^[1]to 9

ten’s place day alarm information coded in

BCD format

unit place

[1] Default value.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

25 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

8.5.5 Register Weekday_alarm

Table 33. Weekday_alarm - weekday alarm register (address 0Fh) bit description

Bit

Symbol

Value

Description

weekday alarm

enabled

7

AEN_W

0

1^[1]

disabled

6 to 3

-

0

unused

2 to 0 WEEKDAY_ALARM

0

^[1]to 6

weekday alarm information coded in BCD

format

[1] Default value.

8.5.6 Alarm function

By clearing the alarm enable bit (AEN_x) of one or more of the alarm registers, the

corresponding alarm condition(s) are active. When an alarm occurs, AF is set logic 1. The

asserted AF can be used to generate an interrupt (INT). The AF is cleared by command.

The registers at addresses 0Bh through 0Fh contain alarm information. When one or

more of these registers is loaded with second, minute, hour, day or weekday, and its

corresponding AEN_x is logic 0, then that information is compared with the current

second, minute, hour, day, and weekday. When all enabled comparisons first match, the

alarm flag (AF in register Control_2) is set logic 1.

The generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is

enabled, the INT pin follows the condition of bit AF. AF remains set until cleared by

command. Once AF has been cleared, it will only be set again when the time increments

to match the alarm condition once more. Alarm registers which have their AEN_x bit at

logic 1 are ignored.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

26 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

H[DPSOH

FKHFNꢂQRZꢂVLJQDO

$(1B6

$(1B6ꢂ ꢂꢄ

6(&21'ꢂ$/$50

ꢄ

ꢊ

6(&21'ꢂ7,0(

$(1B0

0,187(ꢂ$/$50

0,187(ꢂ7,0(

$(1B+

+285ꢂ$/$50

ꢐꢄꢑ

VHWꢂDODUPꢂIODJꢂ$)ꢂ

+285ꢂ7,0(

$(1B'

$(1B:

'$<ꢂ$/$50

'$<ꢂ7,0(

:((.'$<ꢂ$/$50

:((.'$<ꢂ7,0(

DDDꢀꢁꢁꢆꢆꢃꢃ

(1) Only when all enabled alarm settings are matching.

It is only on increment to a matched case that the alarm flag is set.

Fig 14. Alarm function block diagram

8.6 Timer registers

The 8-bit countdown timer at address 10h is controlled by the register Timer_mode at

address 11h.

8.6.1 Register Timer_value

Table 34. Timer_value - timer value register (address 10h) bit description

Bit

Symbol

Value

Description

countdown timer value^[2]

7 to 0 T[7:0]

0h^[1]to

FFh

[1] Default value.

T

[2] Countdown period in seconds: CountdownPeriod =

where T is the

--------------------------------------------------------------

SourceClockFrequency

countdown value.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

27 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

8.6.2 Register Timer_mode

Table 35. Timer_mode - timer control register (address 11h) bit description

Bit

Symbol

Value

Description

7 to 5

-

000

unused

4 to 3 TCF[1:0]

timer clock frequency

4.096 kHz timer source clock

64 Hz timer source clock

00

01

10

1 Hz timer source clock

1

11^[1]

⁄₆₀Hz timer source clock

2

1

0

TE

timer enable

0^[1]

1

timer is disabled

timer is enabled

TIE

timer interrupt enable

no interrupt generated from timer

interrupt generated from timer

timer interrupt mode

interrupt follows timer flag

interrupt generates a pulse

0^[1]

1

TI_TP^[2]

0^[1]

1

[1] Default value.

[2] How the setting of TI_TP and the timer flag TF can affect the INT pulse generation is explained in

Section 8.2.2.3 on page 13.

8.6.3 Timer functions

The timer has four selectable source clocks allowing for countdown periods in the range

from 244 s to 4 hours 15 min. For periods longer than 4 hours, the alarm function can be

used.

Table 36. Timer clock frequency and timer durations

TCF[1:0] Timer source clock Delay

frequency^[1]

Minimum timer duration

T = 1

Maximum timer duration

T = 255

00

01

10

11

4.096 kHz

64 Hz

1 Hz^[2]

244 s

15.625 ms

1 s

62.256 ms

3.984 s

255 s

1

⁄

₆₀Hz^[2]

60 s

4 hours 15 min

[1] When not in use, TCF[1:0] must be set to ¹

⁄₆₀Hz for power saving.

[2] Time periods can be affected by correction pulses.

Remark: Note that all timings which are generated from the 32.768 kHz oscillator are

based on the assumption that there is 0 ppm deviation. Deviation in oscillator frequency

results in deviation in timings. This is not applicable to interface timing.

The timer counts down from a software-loaded 8-bit binary value, T[7:0], in register

Timer_value. Loading the counter with 0 stops the timer. Values from 1 to 255 are valid.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

28 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

When the counter decrements from 1, the timer flag (bit TF in register Control_2) is set

and the counter automatically re-loads and starts the next timer period.

FRXQWGRZQꢂYDOXHꢏꢂ7

[[

ꢊꢀ

WLPHUꢂVRXUFHꢂFORFN

FRXQWGRZQꢂFRXQWHU

[[

ꢊꢀ

ꢊꢁ

ꢊꢄ

ꢊꢀ

ꢊꢁ

ꢊꢄ

ꢊꢀ

ꢊꢁ

ꢊꢄ

ꢊꢀ

7(

7)

,17

7

GXUDWLRQꢂRIꢂILUVWꢂWLPHUꢂSHULRGꢂDIWHU

HQDEOHꢂPD\ꢂUDQJHꢂIURPꢂ7ꢂꢃꢂꢄꢂWRꢂ7ꢂꢒꢂꢄ

DDDꢀꢁꢁꢆꢆꢃꢆ

In this example, it is assumed that the timer flag is cleared before the next countdown period

expires and that the pin INT is set to pulsed mode.

Fig 15. General countdown timer behavior

If a new value of T is written before the end of the current timer period, then this value

takes immediate effect. NXP does not recommend changing T without first disabling the

counter by setting bit TE logic 0. The update of T is asynchronous to the timer clock.

Therefore changing it without setting bit TE logic 0 may result in a corrupted value loaded

into the countdown counter. This results in an undetermined countdown period for the first

period. The countdown value T will, however, be correctly stored and correctly loaded on

subsequent timer periods.

When the TIE flag is set, an interrupt signal on INT is generated if this mode is enabled.

See Section 8.2.2 for details on how the interrupt can be controlled.

When starting the timer for the first time, the first period has an uncertainty. The

uncertainty is a result of the enable instruction being generated from the interface clock

which is asynchronous from the timer source clock. Subsequent timer periods do not have

such delay. The amount of delay for the first timer period depends on the chosen source

clock, see Table 37.

Table 37. First period delay for timer counter value T

Timer source clock

4.096 kHz

64 Hz

Minimum timer period

Maximum timer period

T

T + 1

1 Hz

1

T – 1 +

T +

--------------

64 Hz

1

⁄₆₀Hz

1

--------------

64 Hz

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

29 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

At the end of every countdown, the timer sets the countdown timer flag (bit TF in register

Control_2). Bit TF can only be cleared by command. The asserted bit TF can be used to

generate an interrupt at pin INT. The interrupt may be generated as a pulsed signal every

countdown period or as a permanently active signal which follows the condition of bit TF.

Bit TI_TP is used to control this mode selection and the interrupt output may be disabled

with bit TIE, see Table 35 and Figure 15.

When reading the timer, the current countdown value is returned and not the initial

value T. Since it is not possible to freeze the countdown timer counter during read back, it

is recommended to read the register twice and check for consistent results.

Timer source clock frequency selection of 1 Hz and ¹⁄₆₀Hz is affected by the Offset

register. The duration of a program period varies according to when the offset is initiated.

For example, if a 100 s timer is set using the 1 Hz clock as source, then some 100 s

periods will contain correction pulses and therefore be longer or shorter depending on the

setting of the Offset register. See Section 8.2.3 to understand the operation of the Offset

register.

8.6.3.1 Countdown timer interrupts

The pulse generator for the countdown timer interrupt uses an internal clock and is

dependent on the selected source clock for the countdown timer and on the countdown

value T. As a consequence, the width of the interrupt pulse varies (see Table 38).

Table 38. INT operation

TF and INT become active simultaneously.

Source clock (Hz)

INT period (s)

T = 1^[1]

T > 1^[1]

1

4096

64

⁄

8192

4096

1

⁄

128

64

1

⁄

64

1

⁄

60

64

[1] T = loaded countdown value. Timer stops when T = 0.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

30 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

9. Characteristics of the I²C-bus interface

The I²C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse, as changes in the data line at this time

are interpreted as a control signal (see Figure 16).

6'$

6&/

GDWDꢂOLQHꢂ

VWDEOHꢔꢂ

FKDQJHꢂ

RIꢂGDWDꢂ

DOORZHG

GDWDꢂYDOLG

PEFꢈꢅꢂ

Fig 16. Bit transfer

9.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START

condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P (see Figure 17).

6'$

6&/

6'$

6&/

6

3

67$57ꢂFRQGLWLRQ

6723ꢂFRQGLWLRQ

PEFꢈꢅꢅ

Fig 17. Definition of START and STOP conditions

9.3 System configuration

A device generating a message is a transmitter; a device receiving a message is a

receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves (see Figure 18).

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

31 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

0$67(5ꢂ

75$160,77(5ꢍꢂ

5(&(,9(5

0$67(5ꢂ

75$160,77(5ꢍꢂ

5(&(,9(5

6/$9(ꢂ

75$160,77(5ꢍꢂ

5(&(,9(5

6/$9(ꢂ

5(&(,9(5

0$67(5ꢂ

75$160,77(5

6'$

6&/

PJDꢉꢁꢄ

Fig 18. System configuration

9.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge

cycle.

• A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte

• Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered)

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition

Acknowledgement on the I²C-bus is shown in Figure 19.

GDWDꢂRXWSXWꢂ

E\ꢂWUDQVPLWWHU

QRWꢂDFNQRZOHGJH

GDWDꢂRXWSXWꢂ

E\ꢂUHFHLYHU

DFNQRZOHGJH

6&/ꢂIURPꢂ

PDVWHU

ꢄ

ꢁ

ꢅ

ꢌ

6

FORFNꢂSXOVHꢂIRUꢂ

67$57ꢂ

FRQGLWLRQ

DFNQRZOHGJHPHQW

PEFꢈꢁꢅ

Fig 19. Acknowledgement on the I²C-bus

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

32 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

9.5 I²C-bus protocol

9.5.1 Addressing

One I²C-bus slave address (1010001) is reserved for the PCA85063A. The entire I²C-bus

slave address byte is shown in Table 39.

Table 39. I²C slave address byte

Slave address

Bit

7

6

5

4

3

2

1

0

MSB

LSB

R/W

1

0

1

0

1

After a START condition, the I²C slave address has to be sent to the PCA85063A device.

The R/W bit defines the direction of the following single or multiple byte data transfer

(R/W = 0 for writing, R/W = 1 for reading). For the format and the timing of the START

condition (S), the STOP condition (P) and the acknowledge bit (A) refer to the I²C-bus

characteristics (see Ref. 12 “UM10204”). In the write mode, a data transfer is terminated

by sending either the STOP condition or the START condition of the next data transfer.

9.5.2 Clock and calendar READ or WRITE cycles

The I²C-bus configuration for the different PCA85063A READ and WRITE cycles is

shown in Figure 20 and Figure 21. The register address is a 5-bit value that defines which

register is to be accessed next. The upper 3 bits of the register address are not used.

DFNQRZOHGJH

IURPꢂ3&$ꢅꢉꢊꢇꢀ$

DFNQRZOHGJH

IURPꢂ3&$ꢅꢉꢊꢇꢀ$

DFNQRZOHGJH

IURPꢂ3&$ꢅꢉꢊꢇꢀ$

6

ꢄ

ꢊ

ꢄ

ꢊ

ꢄ

ꢊ

$

3ꢍ6

VODYHꢂDGGUHVV

ZULWHꢂELW

UHJLVWHUꢂDGGUHVV

ꢊꢊKꢂWRꢂꢄꢄK

ꢊꢂWRꢂQ

GDWDꢂE\WHV

67$57ꢍ

6723

DDDꢀꢁꢂꢃꢄꢂꢈ

Fig 20. Master transmits to slave receiver (WRITE mode)

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

33 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

DFNQRZOHGJH

IURPꢂ3&$ꢅꢉꢊꢇꢀ$

DFNQRZOHGJH

IURPꢂ3&$ꢅꢉꢊꢇꢀ$

VHWꢂUHJLVWHU

DGGUHVV

6

ꢄ

ꢊ

ꢄ

ꢊ

ꢄ

ꢊ

$

3

VODYHꢂDGGUHVV

ZULWHꢂELW

UHJLVWHUꢂDGGUHVV

ꢊꢊKꢂWRꢂꢄꢄK

6723

DFNQRZOHGJH

IURPꢂ3&$ꢅꢉꢊꢇꢀ$

DFNQRZOHGJH

IURPꢂPDVWHU

QRꢂDFNQRZOHGJH

/$67ꢂ'$7$ꢂ%<7(

UHDGꢂUHJLVWHU

GDWD

6

ꢄ

ꢊ

ꢄ

ꢊ

ꢄ

$

'$7$ꢂ%<7(

$

3

VODYHꢂDGGUHVV

UHDGꢂELW

ꢊꢂWRꢂQꢂGDWDꢂE\WHV

DXWRꢂLQFUHPHQW

PHPRU\ꢂUHJLVWHUꢂDGGUHVV

DXWRꢂLQFUHPHQW

PHPRU\ꢂUHJLVWHUꢂDGGUHVV

DDDꢀꢁꢂꢃꢄꢂꢄ

For multimaster configurations and to fasten the communication, the STOP-START sequence can be replaced by a repeated

START (Sr).

Fig 21. Master reads after setting register address (write register address; READ data)

9.5.3 I²C-bus error recovery technique

Slave devices like the PCA85063A use a state machine to implement the I²C protocol and

expect a certain sequence of events to occur to function properly. Unexpected events at

the I²C master can wreak havoc with the slaves connected on the bus. However, it is

usually possible to recover deterministically to a known bus state with careful protocol

manipulation.

A deterministic method to clear this situation if SDA is stuck LOW (it effectively blocks any

other I2C-bus transaction, once the master recognizes a ‘stuck bus’ state), is for the

master to blindly transmit nine clocks on SCL. If the slave was transmitting data or

acknowledging, nine or more clocks ensures the slave state machine returns to a known,

idle state since the protocol calls for eight data bits and one ACK bit. It does not matter

when the slave state machine finishes its transmission; extra clocks are recognized as

STOP conditions.

With careful design of the bus master error recovery firmware, many I²C-bus protocol

problems can be avoided.

S/W considerations: NXP recommends customers allow for S/W reset capability to enable

the bus error recovery technique. The 9-clock pulse method as described above involves

a bus-master capable of providing such a signal.

Further comments/additional information are available in Ref. 13 “UM10301” and Ref. 12

“UM10204”.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

34 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

10. Internal circuitry

3&$ꢀꢁꢂꢃꢄ$

9''

26&,

&/.287

26&2

6&/

6'$

,17

966

DDDꢀꢁꢂꢃꢄꢂꢉ

Fig 22. Device diode protection diagram of PCA85063A

11. Safety notes

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling

electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or

equivalent standards.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

35 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

12. Limiting values

Table 40. Limiting values^[1]

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

I_DD

Parameter

Conditions

Min

0.5

50

0.5

10

-

Max

+6.5

+50

Unit

V

supply voltage

supply current

input voltage

mA

V

V_I

on pins SCL, SDA, OSCI

+6.5

+10

V_O

output voltage

input current

V

I_I

at any input

mA

mW

V

I_O

output current

total power dissipation

at any output

+10

P_tot

V_ESD

300

[2]

[3]

[4]

[5]

electrostatic

discharge voltage

HBM

CDM

-

5000

2000

200

-

V

I_lu

latch-up current

-

mA

C

T_stg

T_amb

storage temperature

65

40

+150

+105

ambient temperature operating device

[1] Remark: The PCA85063A part is not guaranteed (nor characterized) above the operating range as denoted in the datasheet. NXP

recommends not to bias the PCA85063A device during reflow (e.g. if utilizing a 'coin' type battery in the assembly). If customer so

chooses to continue to use this assembly method, there must be the allowance for a full `0 V' level Power supply `reset' to re-enable the

device. Without a proper POR, the device may remain in an indeterminate state.

[2] Pass level; Human Body Model (HBM) according to Ref. 7 “JESD22-A114”.

[3] Pass level; Charged-Device Model (CDM), according to Ref. 8 “JESD22-C101”.

[4] Pass level; latch-up testing, according to Ref. 9 “JESD78” at maximum ambient temperature (T_amb(max)).

[5] According to the store and transport requirements (see Ref. 14 “UM10569”) the devices have to be stored at a temperature of +8 C to

+45 C and a humidity of 25 % to 75 %.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

36 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

13. Characteristics

Table 41. Static characteristics

V_DD= 0.9 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +105 C; f_osc= 32.768 kHz; quartz R_s= 60 k; C_L= 7 pF; unless otherwise

specified.

Symbol

Supplies

V_DD

Parameter

Conditions

Min

Typ

Max

Unit

[1]

[2]

supply voltage

supply current

interface inactive; f_SCL= 0 Hz

interface active; f_SCL= 400 kHz

0.9

1.8

-

5.5

V

I_DD

CLKOUT disabled;

V_DD= 5 V

interface inactive; f_SCL= 0 Hz

T_amb= 25 C

-

250

550

900

35

450

750

1800

50

nA

A

T_amb= 85 C

T_amb= 105 C

interface active;

f_SCL= 400 kHz

Inputs^[3]

V_I

input voltage

V_SS

-

5.5

V

V_IL

LOW-level input

voltage

0.3V_DD

V_IH

I_LI

HIGH-level input

voltage

0.7V_DD

-

V_DD

V

input leakage current V_I= V_SSor V_DD

post ESD event

-

0

-

A

pF

0.15

+0.15

7

[4]

C_i

input capacitance

-

Outputs

V_OH

HIGH-level output

voltage

on pin CLKOUT

0.8V_DD

V_SS

1

-

V_DD

V

V_OL

I_OH

LOW-level output

voltage

on pins SDA, INT, CLKOUT

-

0.2V_DD

-

V

HIGH-level output

current

output source current;

V_OH= 4.6 V;

3

mA

V_DD= 5 V;

on pin CLKOUT

I_OL

LOW-level output

current

output sink current; V_OL= 0.4 V;

V_DD= 5 V

on pin SDA

3

2

1

8.5

6

-

mA

on pin INT

on pin CLKOUT

3

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

37 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

Table 41. Static characteristics …continued

V_DD= 0.9 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +105 C; f_osc= 32.768 kHz; quartz R_s= 60 k; C_L= 7 pF; unless otherwise

specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Oscillator

f_osc/f_osc

relative oscillator

frequency variation

V_DD= 200 mV; T_amb= 25 C

-

0.075

-

ppm

[5]

C_L(itg)

integrated load

capacitance

on pins OSCO, OSCI

C_L= 7 pF

4.2

7.5

-

7

9.8

pF

k

C_L= 12.5 pF

12.5

-

17.5

100

R_s

series resistance

[1] For reliable oscillator start-up at power-on use V_DDgreater than 1.2 V. If powered up at 0.9 V the oscillator will start but it might be a bit

slow, especially if at high temperature. Normally the power supply is not 0.9 V at start-up and only comes at the end of battery

discharge. V_DDmin of 0.9 V is specified so that the customer can calculate how large a battery or capacitor they need for their

application. V_DDmin of 1.2 V or greater is needed to ensure speedy oscillator start-up time. For a restart condition, NXP recommends a

full '0 V' V_DDvalue upon re-biasing.

[2] Timer source clock = ¹

⁄₆₀Hz, level of pins SCL and SDA is V_DDor V_SS.

[3] The I²C-bus interface of PCA85063A is 5 V tolerant.

[4] Implicit by design.

C_OSCI C_OSCO



[5] Integrated load capacitance, C_L(itg), is a calculation of C_OSCIand C_OSCOin series: C_Litg

=

.

-------------------------------------------

C_OSCI+ C_OSCO



DDDꢀꢁꢁꢇꢄꢆꢁ

ꢉꢊ

,

''

ꢐ$ꢑ

ꢈꢊ

ꢀꢊ

ꢁꢊ

ꢄꢊ

ꢊ

ꢐꢄꢑ

ꢐꢁꢑ

ꢊ

ꢄꢊꢊ

ꢁꢊꢊ

ꢀꢊꢊ

ꢈꢊꢊ

ꢉꢊꢊ

I

ꢂꢐN+]ꢑ

6&/

T_amb= 25 C; CLKOUT disabled.

(1) V_DD= 5.0 V.

(2) _DD= 3.3 V.

V

Fig 23. Typical I_DDwith respect to f_SCL

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

38 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

DDDꢀꢁꢂꢄꢃꢄꢈ

ꢄꢁꢊꢊ

,

''

ꢐQ$ꢑ

ꢄꢊꢊꢊ

ꢅꢊꢊ

ꢇꢊꢊ

ꢈꢊꢊ

ꢁꢊꢊ

ꢊ

ꢐꢄꢑ

ꢐꢁꢑ

ꢃꢉꢊ

ꢃꢄꢊ

ꢀꢊ

ꢆꢊ

ꢄꢄꢊ

7

DPE

ꢂꢐ&ꢑ

C_L(itg)= 7 pF; CLKOUT disabled.

(1) V_DD= 5.5 V.

(2) V_DD= 3.3 V.

DDDꢀꢁꢂꢄꢃꢉꢂ

ꢄꢁꢊꢊ

,

''

ꢐQ$ꢑ

ꢄꢊꢊꢊ

ꢅꢊꢊ

ꢇꢊꢊ

ꢈꢊꢊ

ꢁꢊꢊ

ꢊ

ꢐꢄꢑ

ꢐꢁꢑ

ꢃꢉꢊ

ꢃꢄꢊ

ꢀꢊ

ꢆꢊ

ꢄꢄꢊ

7

DPE

ꢂꢐ&ꢑ

C_L(itg)= 12.5 pF; CLKOUT disabled.

(1) V_DD= 5.5 V.

(2) _DD= 3.3 V.

V

Fig 24. Typical I_DDas a function of temperature

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

39 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

DDDꢀꢁꢁꢇꢄꢃꢊ

ꢄꢁ

ꢄꢊ

ꢅ

,

''

ꢐ$ꢑ

ꢐꢄꢑ

ꢐꢁꢑ

ꢐꢄꢑ

ꢐꢁꢑ

ꢇ

ꢈ

ꢁ

ꢊ

ꢄ

ꢁ

ꢀ

ꢈ

ꢉ

ꢇ

9

ꢂꢐ9ꢑ

''

T_amb= 25 C; f_CLKOUT= 32768 Hz.

(1) 47 pF CLKOUT load.

(2) 22 pF CLKOUT load.

DDDꢀꢁꢁꢇꢄꢆꢂ

ꢉꢊꢊ

,

''

ꢐQ$ꢑ

ꢈꢊꢊ

ꢀꢊꢊ

ꢁꢊꢊ

ꢄꢊꢊ

ꢊ

ꢐꢄꢑ

ꢐꢁꢑ

ꢊ

ꢄ

ꢁ

ꢀ

ꢈ

ꢉ

ꢇ

9

ꢂꢐ9ꢑ

''

T_amb= 25 C; CLKOUT disabled.

(1) C_L(itg)= 12.5 pF.

(2)

C_L(itg)= 7 pF.

Fig 25. Typical I_DDwith respect to V_DD

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

40 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

DDDꢀꢁꢁꢇꢉꢆꢂ

ꢅꢊꢊ

,

''

ꢐQ$ꢑ

ꢐꢄꢑ

ꢇꢊꢊ

ꢐꢁꢑ

ꢈꢊꢊ

ꢁꢊꢊ

ꢊ

ꢐꢀꢑ

ꢐꢈꢑ

ꢁꢊ

ꢀꢊ

ꢈꢊ

ꢉꢊ

ꢇꢊ

ꢆꢊ

ꢅꢊ

ꢌꢊ

5 ꢂꢐNꢑ

ꢄꢊꢊ

6

V_DD= 5 V; CLKOUT disabled.

(1) C_L(itg)= 12.5 pF; 50 C; maximum value.

(2) C_L(itg)= 7 pF; 50 C; maximum value.

(3)

C_L(itg)= 12.5 pF; 25 C; typical value.

(4) C_L(itg)= 7 pF; 25 C; typical value.

Fig 26. I_DDwith respect to quartz R_S

DDDꢀꢁꢁꢇꢄꢆꢃ

ꢀ

ǻI

RVF

ꢐSSPꢑ

ꢄꢋꢉ

ꢊ

ꢃꢄꢋꢉ

ꢃꢀ

ꢐꢄꢑ

ꢐꢁꢑ

ꢊ

ꢄ

ꢁ

ꢀ

ꢈ

ꢉ

ꢇ

9

ꢂꢐ9ꢑ

''

T_amb= 40 C to +105 C.

_L(itg)= 7 pF.

(2) C_L(itg)= 12.5 pF.

(1)

C

Fig 27. Oscillator frequency variation with respect to V_DD

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

41 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

Table 42. I²C-bus characteristics

V

_DD= 1.8 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +105 C; f_osc= 32.768 kHz; quartz R_s= 60 k; C_L= 7 pF; unless otherwise

specified. All timing values are valid within the operating supply voltage and temperature range and referenced to V_ILand V_IH

[1]

with an input voltage swing of V_SSto V_DD

.

Symbol

Parameter

Conditions

Min

Max

Unit

C_b

capacitive load for

each bus line

-

400

pF

[2]

f_SCL

SCL clock frequency

0

400

-

kHz

t_HD;STA

hold time (repeated)

START condition

0.6

s

t_SU;STA

set-up time for a

repeated START

condition

0.6

-

s

t_LOW

t_HIGH

t_r

LOW period of the

SCL clock

1.3

0.6

20

-

s

ns

s

HIGH period of the

SCL clock

-

rise time of both SDA

and SCL signals

300

[3][4]

t_f

fall time of both SDA

and SCL signals

20  (V_DD/ 5.5 V) 300

t_BUF

bus free time between

a STOP and START

condition

1.3

-

t_SU;DAT

t_HD;DAT

t_SU;STO

data set-up time

data hold time

100

0

-

ns

s

set-up time for STOP

condition

0.6

t_VD;DAT

t_VD;ACK

data valid time

0

0.9

s

data valid

acknowledge time

t_SP

pulse width of spikes

that must be

0

50

ns

suppressed by the

input filter

[1] A detailed description of the I²C-bus specification is given in Ref. 12 “UM10204”.

[2] I²C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.

[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V_IH(min)of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

[4] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t_fis specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified t_f.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

42 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

67$57ꢂ

FRQGLWLRQꢂ

ꢐ6ꢑ

ELWꢂꢆꢂ

06%ꢂ

ꢐ$ꢆꢑ

6723ꢂ

FRQGLWLRQꢂ

ꢐ3ꢑ

ELWꢂꢇꢂ

ꢐ$ꢇꢑ

ELWꢂꢊꢂ DFNQRZOHGJHꢂ

ꢐ5ꢍ:ꢑ ꢐ$ꢑ

SURWRFRO

W

+,*+

68ꢔ67$

/2:

ꢄ

ꢍI

6&/

6'$

W

%8)

I

W

U

W

+'ꢔ'$7

9'ꢔ$&.

9'ꢔ'$7

68ꢔ672

ꢋꢁꢂꢃDDDꢆꢂꢄ

68ꢔ'$7

+'ꢔ67$

Fig 28. I²C-bus timing diagram; rise and fall times refer to 30 % and 70 %

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

43 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

14. Application information

(2)

DD

V

(3)

TP

SDA

SCL

(1)

R1

MASTER

TRANSMITTER/

RECEIVER

1 F

100 nF

VDD

CLKOUT

INT

SCL

OSCI

(2)

V

DD

PCA85063A

OSCO

SDA

R

R: pull-up resistor

VSS

t

r

R =

C

b

SDA SCL

2

(I C-bus)

aaa-013719

A 1 farad super capacitor combined with a low V_Fdiode can be used as a standby or back-up

supply. With the RTC in its minimum power configuration that is, timer off and CLKOUT off, the

RTC may operate for weeks.

(1) R1 limits the inrush current to the super capacitor at power-on.

(2) NXP recommends tying V_DDof the device and V_DDof all the external pull-up resistors to the same

Power Supply.

(3) NXP also recommends the customer place accessible 'Pads/TP-test point' on the layout so as to

enable a 'hard'' grounding of the power supply V_DDin the event a full discharge cannot be attained.

Fig 29. Application diagram for PCA85063A

15. Test information

15.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated

circuits, and is suitable for use in automotive applications.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

44 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

16. Package outline

76623ꢀꢋꢅSODVWLFꢅWKLQꢅVKULQNꢅVPDOOꢅRXWOLQHꢅSDFNDJHꢌꢅꢀꢅOHDGVꢌꢅERG\ꢅZLGWKꢅꢄꢅPPꢅ

627ꢁꢂꢁꢍꢆꢅ

'ꢂ

(ꢂ

$ꢂ

;ꢂ

Fꢂ

\ꢂ

+

Yꢂ 0ꢂ

$ꢂ

(ꢂ

=ꢂ

ꢉꢂ

ꢅꢂ

$

ꢐ$ ꢑꢂ

ꢁꢂ

$ꢂ

ꢀ

$

ꢄꢂ

SLQꢂꢄꢂLQGH[ꢂ

șꢂ

/

Sꢂ

/ꢂ

GHWDLOꢂ;ꢂ

ꢄꢂ

ꢈꢂ

Hꢂ

Zꢂ 0ꢂ

E

Sꢂ

ꢊꢂ

ꢁꢋꢉꢂ

ꢉꢂPPꢂ

VFDOHꢂ

',0(16,216ꢅꢉPPꢅDUHꢅWKHꢅRULJLQDOꢅGLPHQVLRQVꢊꢅ

$ꢅ

ꢉꢆꢊꢅ

ꢉꢈꢊꢅ

ꢉꢆꢊꢅ

$

E

Fꢅ

'

(

Hꢅ

+

/ꢅ

/

81,7ꢅ

PPꢂ

Yꢅ

Zꢅ

\ꢅ

=

șꢂ

ꢆꢅ

ꢈꢅ

ꢄꢅ

Sꢅ

(ꢅ

Sꢅ

PD[ꢇꢅ

ꢊꢋꢄꢉꢂ ꢊꢋꢌꢉꢂ

ꢊꢋꢊꢉꢂ ꢊꢋꢅꢊꢂ

ꢊꢋꢈꢉꢂ ꢊꢋꢁꢅꢂ

ꢊꢋꢁꢉꢂ ꢊꢋꢄꢉꢂ

ꢀꢋꢄꢂ

ꢁꢋꢌꢂ

ꢀꢋꢄꢂ

ꢁꢋꢌꢂ

ꢉꢋꢄꢂ

ꢈꢋꢆꢂ

ꢊꢋꢆꢂ

ꢊꢋꢈꢂ

ꢊꢋꢆꢊꢂ

ꢊꢋꢀꢉꢂ

ꢇꢂ

ꢊꢂ

ꢄꢋꢄꢂ

ꢊꢋꢇꢉꢂ

ꢊꢋꢌꢈꢂ

ꢊꢋꢄꢂ

ꢊꢋꢁꢉꢂ

1RWHVꢅ

ꢄꢋꢂ3ODVWLFꢂRUꢂPHWDOꢂSURWUXVLRQVꢂRIꢂꢊꢋꢄꢉꢂPPꢂPD[LPXPꢂSHUꢂVLGHꢂDUHꢂQRWꢂLQFOXGHGꢋꢂ

ꢁꢋꢂ3ODVWLFꢂRUꢂPHWDOꢂSURWUXVLRQVꢂRIꢂꢊꢋꢁꢉꢂPPꢂPD[LPXPꢂSHUꢂVLGHꢂDUHꢂQRWꢂLQFOXGHGꢋꢂ

ꢅ5()(5(1&(6ꢅ

ꢅ-('(&ꢅ ꢅ-(,7$ꢅ

287/,1(ꢅ

9(56,21ꢅ

(8523($1ꢅ

352-(&7,21ꢅ

,668(ꢅ'$7(ꢅ

ꢅ,(&ꢅ

ꢌꢌꢃꢊꢈꢃꢊꢌꢂ

ꢊꢀꢃꢊꢁꢃꢄꢅꢂ

ꢂ627ꢉꢊꢉꢃꢄꢂ

ꢂ

Fig 30. Package outline SOT505-1 (TSSOP8) of PCA85063ATT

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

45 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

17. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent

standards.

18. Packing information

18.1 Tape and reel information

For tape and reel packing information, please see Ref. 11 “SOT505-1_118”.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

46 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

19. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

19.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

19.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

19.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

47 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

19.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 31) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 43 and 44

Table 43. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 44. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 31.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

48 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 31. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

20. Footprint information

ꢀꢋꢇꢊꢊ

ꢁꢋꢌꢉꢊ

ꢊꢋꢆꢁꢉ

ꢊꢋꢄꢁꢉ

ꢉꢋꢆꢉꢊ ꢀꢋꢇꢊꢊ

ꢀꢋꢁꢊꢊ ꢉꢋꢉꢊꢊ

ꢄꢋꢄꢉꢊ

ꢊꢋꢇꢊꢊ

ꢊꢋꢈꢉꢊ

ꢊꢋꢇꢉꢊ

VRWꢇꢁꢇꢀꢂBIU

VROGHUꢂODQGV

RFFXSLHGꢂDUHD

'LPHQVLRQVꢂLQꢂPP

Fig 32. Footprint information for reflow soldering of SOT505-1 (TSSOP8) of

PCA85063ATT

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

49 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

22. Abbreviations

Table 46. Abbreviations

Acronym

Description

BCD

CMOS

ESD

HBM

I²C

Binary Coded Decimal

Complementary Metal Oxide Semiconductor

ElectroStatic Discharge

Human Body Model

Inter-Integrated Circuit

Integrated Circuit

IC

LSB

MSB

MSL

PCB

POR

RTC

SCL

SDA

SMD

Least Significant Bit

Most Significant Bit

Moisture Sensitivity Level

Printed-Circuit Board

Power-On Reset

Real-Time Clock

Serial CLock line

Serial DAta line

Surface Mount Device

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

52 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

23. References

[1] AN10365 — Surface mount reflow soldering description

[2] AN10366 — HVQFN application information

[3] AN11247 — Improved timekeeping accuracy with PCF85063, PCF8523 and

PCF2123 using an external temperature sensor

[4] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[6] IPC/JEDEC J-STD-020 — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices

[7] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[8] JESD22-C101 — Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[9] JESD78 — IC Latch-Up Test

[10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[11] SOT505-1_118 — TSSOP8; Reel pack; SMD, 13", packing information

[12] UM10204 — I²C-bus specification and user manual

[13] UM10301 — User Manual for NXP Real Time Clocks PCF85x3, PCA8565 and

PCF2123, PCA2125

[14] UM10569 — Store and transport requirements

[15] UM10788 — User manual for I²C-bus RTC demo board OM13515

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

53 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

24. Revision history

Table 47. Revision history

Document ID

PCA85063A v.4

Modifications:

Release date

20180330

Data sheet status

Change notice

Supersedes

Product data sheet

201801008I

PCA85063A v.3

• Table 4 “Pin description”: Added Table note 1 to INT, SDA, and SCL

• Added Section 9.5.3 “I²C-bus error recovery technique”

• Table 41 “Static characteristics”: Updated Table note 1

• Updated Figure 29 “Application diagram for PCA85063A”; added Figure note 2 and Figure

note 3

• Table 40 “Limiting values^[1]”: Added Table note 1

PCA85063A v.3

Modifications:

20160420

Product data sheet

-

PCA85063A v.2

• Clarified reset information in Section 8.2 and Section 8.2.1.3.

PCA85063A v.2

PCA85063A v.1

20150601

20150407

Product data sheet

Objective data sheet

-

PCA85063A v.1

-

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

54 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

25. Legal information

25.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

25.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

25.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

55 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

25.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

26. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

56 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

27. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .3

Table 5. Registers overview . . . . . . . . . . . . . . . . . . . . . .5

Table 6. Control_1 - control and status register 1

(address 00h) bit description . . . . . . . . . . . . . . .6

Table 7. First increment of time circuits after STOP bit

release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 8. Registers reset values . . . . . . . . . . . . . . . . . . .10

Table 9. Control_2 - control and status register 2

(address 01h) bit description . . . . . . . . . . . . . .11

Table 10. Effect of bits MI and HMI on INT generation . .13

Table 11. CLKOUT frequency selection . . . . . . . . . . . . .14

Table 12. Offset - offset register (address 02h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 13. Offset values . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 14. Correction pulses for MODE = 0 . . . . . . . . . . .16

Table 15. Effect of correction pulses on frequencies for

MODE = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 16. Correction pulses for MODE = 1 . . . . . . . . . . .17

Table 17. Effect of correction pulses on frequencies for

MODE = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 18. RAM_byte - 8-bit RAM register (address 03h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 19. Seconds - seconds register (address 04h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 20. Seconds coded in BCD format . . . . . . . . . . . .20

Table 21. Minutes - minutes register (address 05h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 22. Hours - hours register (address 06h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 23. Days - days register (address 07h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 24. Weekdays - weekdays register (address 08h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 25. Weekday assignments . . . . . . . . . . . . . . . . . . .22

Table 26. Months - months register (address 09h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 27. Month assignments in BCD format. . . . . . . . . .22

Table 28. Years - years register (0Ah) bit description. . . .23

Table 29. Second_alarm - second alarm register

(address 0Bh) bit description . . . . . . . . . . . . . .24

Table 30. Minute_alarm - minute alarm register

Table 37. First period delay for timer counter value T . . 29

Table 38. INT operation . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 39. I²C slave address byte. . . . . . . . . . . . . . . . . . . 33

Table 40. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 41. Static characteristics . . . . . . . . . . . . . . . . . . . . 37

Table 42. I²C-bus characteristics. . . . . . . . . . . . . . . . . . . 42

Table 43. SnPb eutectic process (from J-STD-020D) . . . 48

Table 44. Lead-free process (from J-STD-020D) . . . . . . 48

Table 45. Selection of Real-Time Clocks . . . . . . . . . . . . 50

Table 46. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 47. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 54

(address 0Ch) bit description . . . . . . . . . . . . . .25

Table 31. Hour_alarm - hour alarm register

(address 0Dh) bit description . . . . . . . . . . . . . .25

Table 32. Day_alarm - day alarm register (address 0Eh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 33. Weekday_alarm - weekday alarm register

(address 0Fh) bit description . . . . . . . . . . . . . .26

Table 34. Timer_value - timer value register

(address 10h) bit description . . . . . . . . . . . . . .27

Table 35. Timer_mode - timer control register

(address 11h) bit description . . . . . . . . . . . . . .28

Table 36. Timer clock frequency and timer durations. . . .28

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

57 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

28. Figures

Fig 1. Block diagram of PCA85063A . . . . . . . . . . . . . . . .2

Fig 2. Pin configuration for TSSOP8 (PCA85063ATT) . .3

Fig 3. Handling address registers . . . . . . . . . . . . . . . . . .4

Fig 4. STOP bit functional diagram . . . . . . . . . . . . . . . . .8

Fig 5. STOP bit release timing. . . . . . . . . . . . . . . . . . . . .9

Fig 6. Software reset command. . . . . . . . . . . . . . . . . . .10

Fig 7. Interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . .12

Fig 8. INT example for MI . . . . . . . . . . . . . . . . . . . . . . .13

Fig 9. Offset calibration calculation workflow. . . . . . . . .18

Fig 10. Result of offset calibration . . . . . . . . . . . . . . . . . .19

Fig 11. OS flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Fig 12. Data flow for the time function . . . . . . . . . . . . . . .23

Fig 13. Access time for read/write operations . . . . . . . . .24

Fig 14. Alarm function block diagram. . . . . . . . . . . . . . . .27

Fig 15. General countdown timer behavior . . . . . . . . . . .29

Fig 16. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Fig 17. Definition of START and STOP conditions. . . . . .31

Fig 18. System configuration . . . . . . . . . . . . . . . . . . . . . .32

Fig 19. Acknowledgement on the I²C-bus . . . . . . . . . . . .32

Fig 20. Master transmits to slave receiver

(WRITE mode). . . . . . . . . . . . . . . . . . . . . . . . . . .33

Fig 21. Master reads after setting register address

(write register address; READ data) . . . . . . . . . .34

Fig 22. Device diode protection diagram of PCA85063A.35

Fig 23. Typical I_DDwith respect to f_SCL. . . . . . . . . . . . . .38

Fig 24. Typical I_DDas a function of temperature . . . . . . .39

Fig 25. Typical I_DDwith respect to V_DD. . . . . . . . . . . . . .40

Fig 26. I_DDwith respect to quartz R_S. . . . . . . . . . . . . . . .41

Fig 27. Oscillator frequency variation with respect

to V_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Fig 28. I²C-bus timing diagram; rise and fall times refer

to 30 % and 70 % . . . . . . . . . . . . . . . . . . . . . . . .43

Fig 29. Application diagram for PCA85063A . . . . . . . . . .44

Fig 30. Package outline SOT505-1 (TSSOP8) of

PCA85063ATT. . . . . . . . . . . . . . . . . . . . . . . . . . .45

Fig 31. Temperature profiles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Fig 32. Footprint information for reflow soldering of

SOT505-1 (TSSOP8) of PCA85063ATT . . . . . . .49

PCA85063A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 30 March 2018

58 of 59

PCA85063A

NXP Semiconductors

Automotive Real-Time Clock/calendar with alarm function and I²C-bus

29. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

8.6.2

8.6.3

8.6.3.1

Register Timer_mode. . . . . . . . . . . . . . . . . . . 28

Timer functions. . . . . . . . . . . . . . . . . . . . . . . . 28

Countdown timer interrupts . . . . . . . . . . . . . . 30

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3

9

Characteristics of the I²C-bus interface . . . . 31

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

START and STOP conditions. . . . . . . . . . . . . 31

System configuration . . . . . . . . . . . . . . . . . . . 31

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 32

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 33

Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Clock and calendar READ or WRITE cycles . 33

4

4.1

5

9.1

9.2

9.3

9.4

9.5

9.5.1

9.5.2

6

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

8

8.1

8.2

Functional description . . . . . . . . . . . . . . . . . . . 4

Registers organization . . . . . . . . . . . . . . . . . . . 5

Control registers . . . . . . . . . . . . . . . . . . . . . . . . 6

Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 6

EXT_TEST: external clock test mode. . . . . . . . 7

STOP: STOP bit function . . . . . . . . . . . . . . . . . 8

Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 10

Register Control_2 . . . . . . . . . . . . . . . . . . . . . 11

Alarm interrupt . . . . . . . . . . . . . . . . . . . . . . . . 12

MI and HMI: minute and half minute interrupt. 13

TF: timer flag . . . . . . . . . . . . . . . . . . . . . . . . . 13

COF[2:0]: Clock output frequency . . . . . . . . . 14

Register Offset . . . . . . . . . . . . . . . . . . . . . . . . 15

Correction when MODE = 0 . . . . . . . . . . . . . . 16

Correction when MODE = 1 . . . . . . . . . . . . . . 17

Offset calibration workflow . . . . . . . . . . . . . . . 18

Register RAM_byte . . . . . . . . . . . . . . . . . . . . 19

Time and date registers . . . . . . . . . . . . . . . . . 19

Register Seconds . . . . . . . . . . . . . . . . . . . . . . 19

OS: Oscillator stop . . . . . . . . . . . . . . . . . . . . . 20

Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 21

Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 21

Register Days. . . . . . . . . . . . . . . . . . . . . . . . . 21

Register Weekdays. . . . . . . . . . . . . . . . . . . . . 21

Register Months . . . . . . . . . . . . . . . . . . . . . . . 22

Register Years . . . . . . . . . . . . . . . . . . . . . . . . 23

Setting and reading the time. . . . . . . . . . . . . . 23

Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 24

Register Second_alarm . . . . . . . . . . . . . . . . . 24

Register Minute_alarm . . . . . . . . . . . . . . . . . . 25

Register Hour_alarm . . . . . . . . . . . . . . . . . . . 25

Register Day_alarm . . . . . . . . . . . . . . . . . . . . 25

Register Weekday_alarm . . . . . . . . . . . . . . . . 26

Alarm function. . . . . . . . . . . . . . . . . . . . . . . . . 26

Timer registers . . . . . . . . . . . . . . . . . . . . . . . . 27

Register Timer_value . . . . . . . . . . . . . . . . . . . 27

10

Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 35

Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 36

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37

Application information . . . . . . . . . . . . . . . . . 44

Test information . . . . . . . . . . . . . . . . . . . . . . . 44

Quality information. . . . . . . . . . . . . . . . . . . . . 44

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 45

Handling information . . . . . . . . . . . . . . . . . . . 46

Packing information . . . . . . . . . . . . . . . . . . . . 46

Tape and reel information . . . . . . . . . . . . . . . 46

11

12

8.2.1

8.2.1.1

8.2.1.2

8.2.1.3

8.2.2

8.2.2.1

8.2.2.2

8.2.2.3

8.2.2.4

8.2.3

8.2.3.1

8.2.3.2

8.2.3.3

8.2.4

8.3

8.3.1

8.3.1.1

8.3.2

8.3.3

8.3.4

8.3.5

8.3.6

8.3.7

8.4

13

14

15

15.1

16

17

18

18.1

19

Soldering of SMD packages. . . . . . . . . . . . . . 47

Introduction to soldering. . . . . . . . . . . . . . . . . 47

Wave and reflow soldering. . . . . . . . . . . . . . . 47

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 47

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 48

19.1

19.2

19.3

19.4

20

Footprint information . . . . . . . . . . . . . . . . . . . 49

Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Real-Time Clock selection . . . . . . . . . . . . . . . 50

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 52

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Revision history . . . . . . . . . . . . . . . . . . . . . . . 54

21

21.1

22

23

24

25

Legal information . . . . . . . . . . . . . . . . . . . . . . 55

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 55

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 56

25.1

25.2

25.3

25.4

8.5

8.5.1

8.5.2

8.5.3

8.5.4

8.5.5

8.5.6

8.6

26

27

28

29

Contact information . . . . . . . . . . . . . . . . . . . . 56

Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

8.6.1

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 30 March 2018

Document identifier: PCA85063A


型号：	PCA85063ATTA
厂家：	NXP
描述：	Automotive tiny Real-Time Clock/calendar with alarm function and I2C-bus
文件：	总59页 (文件大小：677K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCA85063ATTA [NXP]

相关型号：

PCA85063ATTAJ

PCA85073A

PCA85073ADP/Q900Z

PCA8510

PCA8510P

PCA85132

PCA85132U

PCA85132U/2DA/Q1

PCA85132U/2DA/Q1,0

PCA85132U/2DB/Q1,0

PCA85133

PCA85133U