PCA85262_技术文档

PCA85262

Automotive 32 x 4 LCD driver for low multiplex rates

Rev. 3 — 12 November 2018

Product data sheet

1. General description

The PCA85262 is a peripheral device which interfaces to almost any Liquid Crystal

Display (LCD)¹with low multiplex rates. It generates the drive signals for any static or

multiplexed LCD containing up to four backplanes and up to 32 segments. It can be easily

cascaded for larger LCD applications. The PCA85262 is compatible with most

microcontrollers and communicates via the two-line bidirectional I²C-bus. Communication

overheads are minimized by a display RAM with auto-incremented addressing, by

hardware subaddressing, and by display memory switching (static and duplex drive

modes).

For a selection of NXP LCD segment drivers, see Table 23 on page 46

2. Features and benefits

 AEC-Q100 grade 2 compliant for automotive applications

 Single chip LCD controller and driver

 Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing

 Selectable display bias configuration: static, ¹⁄₂, or ¹⁄₃

 Internal LCD bias generation with voltage-follower buffers

 32 segment drives:

 Up to 16 7-segment numeric characters

 Up to 8 14-segment alphanumeric characters

 Any graphics of up to 128 segments/elements

 32  4-bit RAM for display data storage

 Display memory bank switching in static and duplex drive modes

 Versatile blinking modes

 Independent supplies possible for LCD and logic voltages

 Wide power supply range: from 1.8 V to 5.5 V

 Wide logic LCD supply range:

 From 2.5 V for low-threshold LCDs

 Up to 8.0 V for guest-host LCDs and high-threshold twisted nematic LCDs

 Low power consumption

 Extended temperature range up to 105 C

 400 kHz I²C-bus interface

 No external components required

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21.

PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

3. Ordering information

Table 1.

Ordering information

Type number

Topside

marking

Package

Name

Description

Version

PCA85262ATT/A PCA85262TT TSSOP48 plastic thin shrink small outline package; 48 leads; body

width 6.1 mm

SOT362-1

3.1 Ordering options

Table 2.

Ordering options

Type number

Orderable

part number

Package

Packing method

Minimum

order quantity

Temperature

T_amb= 40 C to +105 C

PCA85262ATT/A PCA85262ATT/AJ

TSSOP48

REEL 13" Q1 NDP

2000

4. Block diagram

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Fig 1. Block diagram of PCA85262

PCA85262

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

5. Pinning information

5.1 Pinning

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Top view. For mechanical details, see Figure 28.

Fig 2. Pinning diagram for PCA85262ATT (TSSOP48)

PCA85262

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Product data sheet

Rev. 3 — 12 November 2018

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

5.2 Pin description

Table 3.

Pin description of PCA85262ATT (TSSOP48)

Input or input/output pins must always be at a defined level (V_SSor V_DD) unless otherwise specified.

Symbol

SDA

10

11

Type

Description

input/output

input

I²C-bus serial data line

I²C-bus serial clock

SCL

SYNC

12

input/output

cascade synchronization input or

output; if not used it must be left open

CLK

V_DD

13

input/output

supply

input

clock line

14

supply voltage

OSC

A0, A1

T1

15

internal oscillator enable

subaddress inputs

16, 17

18

input

dedicated testing pin; to be tied to V_SS

in application mode

SA0

19

input

I²C-bus address input

ground supply voltage

LCD supply voltage

V_SS

20

supply

output

V_LCD

21

BP0 to BP3

22 to 25

LCD backplane outputs

LCD segment outputs

S0 to S22,

S23 to S31

26 to 48,

1 to 9

PCA85262

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

6. Functional description

The PCA85262 is a versatile peripheral device designed to interface between any

microcontroller to a wide variety of LCD segment or dot-matrix displays. It can directly

drive any static or multiplexed LCD containing up to four backplanes and up to

32 segments.

6.1 Commands of PCA85262

The commands available to the PCA85262 are defined in Table 4.

Table 4.

Definition of the PCA85262 commands

Bit position labeled as - is not used.

Command

Bit

Operation code

Reference

7

6

1

0

1

5

0

1

4

3

2

1

0

mode-set

C

-

E

B

M[1:0]

Table 6

Table 7

Table 8

Table 9

Table 10

load-data-pointer

device-select

bank-select

blink-select

P[4:0]

0

1

0

1

0

A[1:0]

I

0

O

AB

BF[1:0]

All available commands carry a continuation bit C in their most significant bit position as

shown in Figure 21. When this bit is set logic 1, it indicates that the next byte of the

transfer to arrive will also represent a command. If this bit is set logic 0, it indicates that

the command byte is the last in the transfer. Further bytes are regarded as display data

(see Table 5).

Table 5.

C bit description

Bit

Symbol Value

Description

continue bit

7

C

0

last control byte in the transfer; next byte will be regarded

as display data

1

control bytes continue; next byte will be a command too

6.1.1 Command: mode-set

The mode-set command allows configuring the multiplex mode, the bias levels and

enabling or disabling the display.

Table 6.

Mode-set command bit description

Bit

Symbol Value

Description

see Table 5

fixed value

7

C

-

0, 1

10

-

6 to 5

4

3

-

unused

E

display status^[1]

disabled (blank)^[2]

enabled

0

1

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

Table 6.

Mode-set command bit description …continued

Bit

Symbol Value

Description

2

B

LCD bias configuration^[3]

¹⁄₃bias

0

1

¹⁄₂bias

1 to 0

M[1:0]

01

10

11

00

LCD drive mode selection

static; BP0

1:2 multiplex; BP0, BP1

1:3 multiplex; BP0, BP1, BP2

1:4 multiplex; BP0, BP1, BP2, BP3

[1] The possibility to disable the display allows implementation of blinking under external control.

[2] The display is disabled by setting all backplane and segment outputs to V_LCD

.

[3] Not applicable for static drive mode.

6.1.2 Command: load-data-pointer

The load-data-pointer command defines the display RAM address where the following

display data are sent to.

Table 7.

Load-data-pointer command bit description

See Section 6.3.1.

Bit

Symbol Value

Description

see Table 5

fixed value

7

C

0, 1

00

6 to 5

4 to 0

-

P[4:0]

00000 to

11111

5-bit binary value, 0 to 31; transferred to the data pointer to

define one of 32 display RAM addresses

6.1.3 Command: device-select

The device-select command allows defining the subaddress counter value.

Table 8.

Device-select command bit description

See Section 6.3.2.

Bit

Symbol Value

Description

see Table 5

fixed value

7

C

0, 1

6 to 2

1 to 0

-

11000

00 to 11

A[1:0]

2-bit binary value, 0 to 3; transferred to the subaddress

counter to define one of four hardware subaddresses

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

6.1.4 Command: bank-select

The bank-select command controls where data is written to RAM and where it is displayed

from.

Table 9.

Bank-select command bit description

See Section 6.3.5.

Bit

Symbol Value

Description

Static

1:2 multiplex^[1]

7

C

-

0, 1

see Table 5

fixed value

6 to 2

1

11110

I

input bank selection; storage of arriving display data

0

1

RAM row 0

RAM row 2

RAM rows 0 and 1

RAM rows 2 and 3

0

O

output bank selection; retrieval of LCD display data

0

1

RAM row 0

RAM row 2

RAM rows 0 and 1

RAM rows 2 and 3

[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.

6.1.5 Command: blink-select

The blink-select command allows configuring the blink mode and the blink frequency.

Table 10. Blink-select command bit description

See Section 6.1.5.1.

Bit

7

Symbol Value

Description

C

0, 1

see Table 5

6 to 3

2

-

1110

fixed value

AB

blink mode selection

0

1

normal blinking^[1]

alternate RAM bank blinking^[2]

1 to 0

BF[1:0]

blink frequency selection

00

01

10

11

off

1

2

3

[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.

[2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.

6.1.5.1 Blinking

The display blinking capabilities of the PCA85262 are very versatile. The whole display

can blink at frequencies selected by the blink-select command (see Table 10). The blink

frequencies are derived from the clock frequency. The ratio between the clock and blink

frequencies depends on the blink mode selected (see Table 11).

PCA85262

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

An additional feature is for an arbitrary selection of LCD segments/elements to blink. This

applies to the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. With the output bank selector, the displayed RAM banks are

exchanged with alternate RAM banks at the blink frequency. This mode can also be

specified by the blink-select command.

In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of

LCD segments/elements can blink by selectively changing the display RAM data at fixed

time intervals.

The entire display can blink at a frequency other than the nominal blink frequency. This

can be effectively performed by resetting and setting the display enable bit E at the

required rate using the mode-set command (see Table 6).

Table 11. Blink frequencies

Blink mode

Blink frequency equation^[1]

off

1

-

f_clk

f_blink

=

---------

768

2

3

f_clk

------------

1536

f_clk

------------

3072

[1] The blink frequency is proportional to the clock frequency (f_clk). For the range of the clock frequency, see

Table 19.

6.2 Clock and frame frequency

6.2.1 Internal clock

The internal logic of the PCA85262 and its LCD drive signals are timed either by its

internal oscillator or by an external clock. The internal oscillator is enabled by connecting

pin OSC to pin V_SS. If the internal oscillator is used, the output from pin CLK can be used

as the clock signal for several PCA85262 in the system that are connected in cascade.

6.2.2 External clock

Pin CLK is enabled as an external clock input by connecting pin OSC to V_DD. The LCD

frame frequency is determined by the clock frequency (f_clk).

Remark: A clock signal must always be supplied to the device; removing the clock may

freeze the LCD in a DC state, which is not suitable for the liquid crystal.

6.2.3 Timing

The PCA85262 timing controls the internal data flow of the device. This includes the

transfer of display data from the display RAM to the display segment outputs. In cascaded

applications, the correct timing relationship between each PCA85262 in the system is

maintained by the synchronization signal at pin SYNC. The timing also generates the LCD

frame frequency signal. The frame frequency signal is a fixed division of the clock

f_clk

frequency from either the internal or an external clock: f_fr

=

-------

24

PCA85262

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

6.3 Display RAM

The display RAM is a static 32  4-bit RAM which stores LCD data.

There is a one-to-one correspondence between

• the bits in the RAM bitmap and the LCD segments/elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;

similarly, a logic 0 indicates the off-state.

The display RAM bitmap, Figure 3, shows the rows 0 to 3 which correspond with the

backplane outputs BP0 to BP3, and the columns 0 to 31 which correspond with the

segment outputs S0 to S31. In multiplexed LCD applications the segment data of the first,

second, third, and fourth row of the display RAM are time-multiplexed with BP0, BP1,

BP2, and BP3 respectively.

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The display RAM bitmap shows the direct relationship between the display RAM column and the

segment outputs; and between the bits in a RAM row and the backplane outputs.

Fig 3. Display RAM bitmap

When display data is transmitted to the PCA85262, the display bytes received are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and depending on the current multiplex drive mode the bits are stored singularly,

in pairs, triples or quadruples. To illustrate the filling order, an example of a 7-segment

numeric display showing all drive modes is given in Figure 4; the RAM filling organization

depicted applies equally to other LCD types.

• In static drive mode the eight transmitted data bits are placed into row 0 as one byte

• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into

row 0 and 1 as four successive 2-bit RAM words

• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as

three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difficult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address, but

care should be taken to avoid overwriting adjacent data because always full bytes are

transmitted (see Section 6.3.4)

• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples

into row 0, 1, 2, and 3 as two successive 4-bit RAM words

PCA85262

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

6.3.1 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte, or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer command (see Table 7). Following this command, an

arriving data byte is stored at the display RAM address indicated by the data pointer. The

filling order is shown in Figure 4.

After each byte is stored, the content of the data pointer is automatically incremented by a

value dependent on the selected LCD drive mode:

• In static drive mode by eight

• In 1:2 multiplex drive mode by four

• In 1:3 multiplex drive mode by three

• In 1:4 multiplex drive mode by two

If an I²C-bus data access terminates early, then the state of the data pointer is unknown.

Consequently, the data pointer must be rewritten prior to further RAM accesses.

6.3.2 Subaddress counter

The storage of display data is determined by the contents of the subaddress counter.

Storage is allowed only when the content of the subaddress counter matches with the

hardware subaddress applied to A0 and A1. The subaddress counter value is defined by

the device-select command (see Table 8). If the content of the subaddress counter and

the hardware subaddress do not match, then data storage is inhibited but the data pointer

is incremented as if data storage had taken place. The subaddress counter is also

incremented when the data pointer overflows.

6.3.3 RAM addressing in cascaded applications

In cascaded applications each PCA85262 in the cascade must be addressed separately.

Initially, the first PCA85262 is selected by sending the device-select command matching

the first device's hardware subaddress. Then the data pointer is set to the preferred

display RAM address by sending the load-data-pointer command.

Once the display RAM of the first PCA85262 has been written, the second PCA85262 is

selected by sending the device-select command again. This time however the command

matches the second device's hardware subaddress. Next the load-data-pointer command

is sent to select the preferred display RAM address of the second PCA85262.

This last step is very important because during writing data to the first PCA85262, the data

pointer of the second PCA85262 is incremented. In addition, the hardware subaddress

should not be changed while the device is being accessed on the I²C-bus interface.

PCA85262

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

6.3.4 RAM writing in 1:3 multiplex drive mode

In 1:3 multiplex drive mode, the RAM is written as shown in Table 12 (see Figure 4 as

well).

Table 12. Standard RAM filling in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any segments/elements on the

display.

Display RAM

bits (rows)/

backplane

Display RAM addresses (columns)/segment outputs (Sn)

0

1

2

3

4

5

6

7

8

9

:

outputs (BPn)

0

1

2

3

a7

a6

a5

-

a4

a3

a2

-

a1

a0

-

b7

b6

b5

-

b4

b3

b2

-

b1

b0

-

c7

c6

c5

-

c4

c3

c2

-

c1

c0

-

d7

d6

d5

-

:

-

If the bit at position BP2/S2 would be written by a second byte transmitted, then the

mapping of the segment bits would change as illustrated in Table 13.

Table 13. Entire RAM filling by rewriting in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to segments/elements on the display.

Display RAM

bits (rows)/

backplane

Display RAM addresses (columns)/segment outputs (Sn)

0

1

2

3

4

5

6

7

8

9

:

outputs (BPn)

0

1

2

3

a7

a6

a5

-

a4

a3

a2

-

a1/b7 b4

a0/b6 b3

b1/c7 c4

b0/c6 c3

c1/d7 d4

c0/d6 d3

d1/e7 e4

d0/e6 e3

:

b5

-

b2

-

c5

-

c2

-

d5

-

d2

-

e5

-

e2

-

In the case described in Table 13 the RAM has to be written entirely and BP2/S2, BP2/S5,

BP2/S8 etc. have to be connected to segments/elements on the display. This can be

achieved by a combination of writing and rewriting the RAM like follows:

• In the first write to the RAM, bits a7 to a0 are written

• The data-pointer (see Section 6.3.1 on page 11) has to be set to the address of bit a1

• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7

and b6

• The data-pointer has to be set to the address of bit b1

• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and

c6

Depending on the method of writing to the RAM (standard or entire filling by rewriting),

some segments/elements remain unused or can be used, but it has to be considered in

the module layout process as well as in the driver software design.

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

6.3.5 Bank selection

6.3.5.1 Output bank selector

The output bank selector (see Table 9) selects one of the four rows per display RAM

address for transfer to the display register. The actual row selected depends on the

particular LCD drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by

the contents of row 1, 2, and then 3

• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially

• In 1:2 multiplex mode, rows 0 and 1 are selected

• In static mode, row 0 is selected

6.3.5.2 Input bank selector

The input bank selector loads display data into the display RAM in accordance with the

selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode

or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see

Table 9). The input bank selector functions independently to the output bank selector.

6.3.5.3 RAM bank switching

The PCA85262 includes a RAM bank switching feature in the static and 1:2 multiplex

drive modes. A bank can be thought of as one RAM row or a collection of RAM rows (see

Figure 5). The RAM bank switching gives the provision for preparing display information in

an alternative bank and to be able to switch to it once it is complete.

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Fig 5. RAM banks in static and multiplex driving mode 1:2

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PCA85262

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Automotive 32 x 4 LCD driver for low multiplex rates

There are two banks; bank 0 and bank 1. Figure 5 shows the location of these banks

relative to the RAM map. Input and output banks can be set independently from one

another with the Bank-select command (see Table 9 on page 7). Figure 6 shows the

concept.

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Fig 6. Bank selection

In the static drive mode, the bank-select command may request the contents of row 2 to

be selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the

contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the

provision for preparing display information in an alternative bank and to be able to switch

to it once it is assembled.

In Figure 7 an example is shown for 1:2 multiplex drive mode where the displayed data is

read from the first two rows of the memory (bank 0), while the transmitted data is stored in

the second two rows of the memory (bank 1).

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6.4 Initialization

At power-on the status of the I²C-bus and the registers of the PCA85262 is undefined.

Therefore the PCA85262 should be initialized as quickly as possible after power-on to

ensure a proper bus communication and to avoid display artifacts. The following

instructions should be accomplished for initialization:

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PCA85262

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6.4.1 Device initialization

At power-on the status of the I²C-bus communication interface is undefined since this

device doesn’t have POR which was removed to improve the ESD performance. A START

and STOP condition with dummy byte in-between must be sent after every power reset to

set up the I²C-bus communication interface.

• I²C-bus (see Section 7) initialization

– generating a START condition

– sending 0h (1 byte) and ignoring the acknowledge – Note, this is not the device

address but just a dummy byte of all zeros

– generating a STOP condition

6.4.2 Device setup

At power-on the status of the display and configuration registers are undefined and need

to be set up to properly display information on the LCD display. After the I²C-bus interface

is initialized as discussed in Section 6.4.1 set up the device using these register settings

• Mode-set command (see Table 6), setting

– bit E = 0

– bit B to the required LCD bias configuration

– bits M[1:0] to the required LCD drive mode

• Load-data-pointer command (see Table 7), setting

– bits P[4:0] to 0h (or any other required address)

• Device-select command (see Table 8), setting

– bits A[1:0] to the required hardware subaddress (for example, 0h)

• Bank-select command (see Table 9), setting

– bit I to 0

– bit O to 0

• Blink-select command (see Table 10), setting

– bit AB to 0 or 1

– bits BF[1:0] to 00 (or to a desired blinking mode)

• writing meaningful information (for example, a logo) into the display RAM

• After the initialization, the display can be switched on by setting bit E = 1 with the

mode-set command or left off (blank) with bit E = 0.

6.5 Possible display configurations

The possible display configurations of the PCA85262 depend on the number of active

backplane outputs required. A selection of display configurations is shown in Table 14. All

of these configurations can be implemented in the typical system shown in Figure 9.

PCA85262

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Product data sheet

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PCA85262

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Automotive 32 x 4 LCD driver for low multiplex rates

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Fig 8. Example of displays suitable for PCA85262

Table 14. Selection of possible display configurations

Number of

Backplanes

Icons

Digits/Characters

7-segment^[1]

Dot matrix:

segments/

elements

14-segment^[2]

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3

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32 dots (1  32)

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Fig 9. Typical system configuration

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The host microcontroller maintains the 2-line I²C-bus communication channel with the

PCA85262. The internal oscillator is enabled by connecting pin OSC to pin V_SS. The

appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.

The only other connections required to complete the system are the power supplies (V_DD

,

V

_SS, and V_LCD) and the LCD panel chosen for the application.

6.6 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of

three impedances connected in series between V_LCDand V_SS. The center impedance is

bypassed by switch if the ¹⁄₂bias voltage level for the 1:2 multiplex drive mode

configuration is selected. The LCD voltage can be temperature compensated externally,

using the supply to pin V_LCD

.

6.7 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

mode-set command from the command decoder. The biasing configurations that apply to

the preferred modes of operation, together with the biasing characteristics as functions of

V

_LCDand the resulting discrimination ratios (D) are given in Table 15.

Discrimination is a term which is defined as the ratio of the on and off RMS voltage across

a segment. It can be thought of as a measurement of contrast.

Table 15. Biasing characteristics

LCD drive

mode

Number of:

LCD bias

configuration

V_offRMSV_onRMS

------------------------ ----------------------- D = ------------------------

V_LCDV_LCDV_offRMS

V_onRMS

Backplanes Levels

static

1

2

3

4

2

3

4

static

0

1



1

⁄

1:2 multiplex

1:3 multiplex

1:4 multiplex

0.354

0.333

0.791

0.745

0.638

0.577

2.236

1.915

1.732

2

1

⁄

3

1

⁄

3

1

⁄

3

A practical value for V_LCDis determined by equating V_off(RMS)with a defined LCD

threshold voltage (V_th(off)), typically when the LCD exhibits approximately 10 % contrast. In

the static drive mode, a suitable choice is V_LCD> 3V_th(off)

.

Multiplex drive modes of 1:3 and 1:4 with ¹⁄₂bias are possible but the discrimination and

hence the contrast ratios are smaller.

1

Bias is calculated by ------------ , where the values for a are

1 + a

a = 1 for ¹⁄₂bias

a = 2 for ¹⁄₃bias

The RMS on-state voltage (V_on(RMS)) for the LCD is calculated with Equation 1:

a²+ 2a + n

n  1 + a²

V_onRMS

=

-----------------------------

(1)

V

LCD

where the values for n are

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

n = 1 for static drive mode

n = 2 for 1:2 multiplex drive mode

n = 3 for 1:3 multiplex drive mode

n = 4 for 1:4 multiplex drive mode

The RMS off-state voltage (V_off(RMS)) for the LCD is calculated with Equation 2:

a²– 2a + n

n  1 + a²

V_offRMS

=

-----------------------------

(2)

(3)

V

LCD

Discrimination is the ratio of V_on(RMS)to V_off(RMS)and is determined from Equation 3:

a²+ 2a + n

V_onRMS

D =

=

---------------------------

----------------------

a²– 2a + n

V_offRMS

Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with

¹⁄₂bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with

21

¹⁄₂bias is ---------- = 1.528 .

3

The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V_LCD

as follows:

• 1:3 multiplex (¹⁄₂bias): V_LCD

• 1:4 multiplex (¹⁄₂bias): V_LCD

=

6  V_offRMS= 2.449V_offRMS

4  3

---------------------

= 2.309V_offRMS

3

These compare with V_LCD= 3V_offRMSwhen ¹⁄₃bias is used.

V_LCDis sometimes referred as the LCD operating voltage.

6.7.1 Electro-optical performance

Suitable values for V_on(RMS)and V_off(RMS)are dependent on the LCD liquid used. The

RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of

the pixel.

For any given liquid, there are two threshold values defined. One point is at 10 % relative

transmission (at V_th(off)) and the other at 90 % relative transmission (at V_th(on)), see

Figure 10. For a good contrast performance, the following rules should be followed:

V

_onRMS V_thon

_offRMS V_thoff

(4)

(5)

V_on(RMS)and V_off(RMS)are properties of the display driver and are affected by the selection

of a, n (see Equation 1 to Equation 3) and the V_LCDvoltage.

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PCA85262

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V_th(off)and V_th(on)are properties of the LCD liquid and can be provided by the module

manufacturer. V_th(off)is sometimes just named V_th. V_th(on)is sometimes named saturation

voltage V_sat

.

It is important to match the module properties to those of the driver in order to achieve

optimum performance.

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PCA85262

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6.8 LCD drive mode waveforms

6.8.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD. The

backplane (BPn) and segment (Sn) drive waveforms for this mode are shown in

Figure 11.

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V_state2(t) = V_{(Sn + 1)}(t)  V_BP0(t).

V_off(RMS)= 0 V.

Fig 11. Static drive mode waveforms

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PCA85262

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6.8.2 1:2 Multiplex drive mode

When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The

PCA85262 allows the use of ¹⁄₂bias or ¹⁄₃bias in this mode as shown in Figure 12 and

Figure 13.

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V_state2(t) = V_Sn(t)  V_BP1(t).

V_off(RMS)= 0.354V_LCD

.

Fig 12. Waveforms for the 1:2 multiplex drive mode with ¹⁄₂bias

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

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V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= 0.745V_LCD

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V_off(RMS)= 0.333V_LCD

.

Fig 13. Waveforms for the 1:2 multiplex drive mode with ¹⁄₃bias

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PCA85262

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6.8.3 1:3 Multiplex drive mode

When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as

shown in Figure 14.

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V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= 0.638V_LCD

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V_off(RMS)= 0.333V_LCD

.

Fig 14. Waveforms for the 1:3 multiplex drive mode with ¹⁄₃bias

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PCA85262

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6.8.4 1:4 Multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as

shown in Figure 15.

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V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= 0.577V_LCD

V_state2(t) = V_Sn(t)  V_BP1(t).

V_off(RMS)= 0.333V_LCD

.

Fig 15. Waveforms for the 1:4 multiplex drive mode with ¹⁄₃bias

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6.9 Backplane and segment outputs

6.9.1 Backplane outputs

The LCD drive section includes four backplane outputs BP0 to BP3 which must be

connected directly to the LCD. The backplane output signals are generated in accordance

with the selected LCD drive mode. If less than four backplane outputs are required, the

unused outputs can be left open-circuit.

• In 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities

• In 1:2 multiplex drive mode, BP0 and BP2, respectively, BP1 and BP3 carry the same

signals and may also be paired to increase the drive capabilities

• In static drive mode, the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements

6.9.2 Segment outputs

The LCD drive section includes 32 segment outputs (S0 to S31) which should be

connected directly to the LCD. The segment output signals are generated in accordance

with the multiplexed backplane signals and with data residing in the display register. When

less than 32 segment outputs are required, the unused segment outputs should be left

open-circuit.

PCA85262

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Product data sheet

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25 of 55

PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

7. Characteristics of the I²C-bus

The I²C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

7.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 16).

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Fig 16. Bit transfer

7.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START

condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P.

The START and STOP conditions are illustrated in Figure 17.

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Fig 17. Definition of START and STOP conditions

7.3 System configuration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves. The system configuration is shown in Figure 18.

PCA85262

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Product data sheet

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26 of 55

PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

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Fig 18. System configuration

7.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

• A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte

• A master receiver must generate an acknowledge after the reception of each byte that

has been clocked out of the slave transmitter

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered)

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition

Acknowledgement on the I²C-bus is illustrated in Figure 19.

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Fig 19. Acknowledgement of the I²C-bus

PCA85262

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Product data sheet

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PCA85262

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Automotive 32 x 4 LCD driver for low multiplex rates

7.5 I²C-bus controller

The PCA85262 acts as an I²C-bus slave receiver. It does not initiate I²C-bus transfers or

transmit data to an I²C-bus master receiver. The only data output from the PCA85262 are

the acknowledge signals of the selected devices. Device selection depends on the

I²C-bus slave address, on the transferred command data and on the hardware

subaddress.

In single device applications, the hardware subaddress inputs A0 and A1 are normally tied

to V_SSwhich defines the hardware subaddress 0. In multiple device applications A0

and A1 are tied to V_SSor V_DDusing a binary coding scheme, so that no two devices with a

common I²C-bus slave address have the same hardware subaddress.

7.6 Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

7.7 I²C-bus protocol

Two I²C-bus slave addresses (0111 000 and 0111 001) are used to address the

PCA85262. The entire I²C-bus slave address byte is shown in Table 16.

Table 16. I²C slave address byte

Slave address

Bit

7

6

5

4

3

2

1

0

MSB

LSB

R/W

0

1

0

SA0

The PCA85262 is a write-only device and will not respond to a read access, therefore bit 0

should always be logic 0. Bit 1 of the slave address byte that a PCA85262 responds to, is

defined by the level tied to its SA0 input (V_SSfor logic 0 and V_DDfor logic 1).

Having two reserved slave addresses allows the following on the same I²C-bus:

• Up to 8 PCA85262 for very large LCD applications

• The use of two types of LCD multiplex drive modes

The I²C-bus protocol is shown in Figure 20. The sequence is initiated with a START

condition (S) from the I²C-bus master which is followed by one of the two possible

PCA85262 slave addresses available. All PCA85262 whose SA0 inputs correspond to

bit 0 of the slave address respond by asserting an acknowledge in parallel. This I²C-bus

transfer is ignored by all PCA85262 whose SA0 inputs are set to the alternative level.

PCA85262

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

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Fig 20. I²C-bus protocol

After an acknowledgement, one or more command bytes follow that define the status of

each addressed PCA85262.

The last command byte sent is identified by resetting its most significant bit, continuation

bit C (see Figure 21). The command bytes are also acknowledged by all addressed

PCA85262 on the bus.

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Fig 21. Format of command byte

After the last command byte, one or more display data bytes may follow. Display data

bytes are stored in the display RAM at the address specified by the data pointer and the

subaddress counter. Both data pointer and subaddress counter are automatically updated

and the data directed to the intended PCA85262 device.

An acknowledgement after each byte is asserted only by the PCA85262 that are

addressed via address lines A0 and A1. After the last display byte, the I²C-bus master

asserts a STOP condition (P). Alternately a START may be asserted to restart an I²C-bus

access.

PCA85262

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

8. Internal circuitry

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Fig 22. Device protection circuits

PCA85262

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Product data sheet

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30 of 55

PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

9. Safety notes

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling

electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or

equivalent standards.

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(V_LCD) is on while the IC supply voltage (V_DD) is off, or vice versa. This may cause unwanted

display artifacts. To avoid such artifacts, V_LCDand V_DDmust be applied or removed together.

10. Limiting values

Table 17. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

Parameter

Conditions

Min

0.5

Max

+6.5

+9.0

+6.5

Unit

V

supply voltage

LCD supply voltage

input voltage

V_LCD

V_I

V

on each of the pins CLK,

SDA, SCL, SYNC, SA0,

OSC, A0, A1, T1

V

V_O

output voltage

on each of the pins S0 to

S31, BP0 to BP3

0.5

+9.0

V

I_I

input current

10

50

-

+10

mA

mW

V

I_O

output current

+10

I_DD

supply current

+50

I_DD(LCD)

I_SS

LCD supply current

ground supply current

total power dissipation

output power

+50

P_tot

P_o

400

-

100

[1]

[2]

[3]

[4]

V_ESD

electrostatic discharge

voltage

HBM

-

5000

1500

200

CDM

-

V

I_lu

latch-up current

V_LU= 11.5 V

-

mA

C

T_stg

T_amb

storage temperature

ambient temperature

65

40

+150

+105

operating device

C

[1] Pass level; Human Body Model (HBM), according to Ref. 8 “JESD22-A114”.

[2] Pass level; Charged-Device Model (CDM), according to Ref. 9 “JESD22-C101”.

[3] Pass level; latch-up testing according to Ref. 10 “JESD78” at maximum ambient temperature (T_amb(max)).

[4] According to the store and transport requirements (see Ref. 14 “UM10569”) the devices have to be stored at a temperature of +8 C to

+45 C and a humidity of 25 % to 75 %.

PCA85262

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Product data sheet

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PCA85262

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Automotive 32 x 4 LCD driver for low multiplex rates

11. Static characteristics

Table 18. Static characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 8.0 V; T_amb= 40 C to +105 C; unless otherwise specified.

Symbol

Supplies

V_DD

Parameter

Conditions

Min

Typ

Max

Unit

supply voltage

LCD supply voltage

supply current

V_LCD 6.5 V

1.8

2.5

-

5.5

6.5

8.0

7

V

V_LCD> 6.5 V

-

V

V_LCD

V_DD< 2.5 V

-

V

V_DD 2.5 V

-

V

[1][2]

[1]

I_DD

f_clk(ext)= 1536 Hz

V_DD= 3.0 V; T_amb= 25 C

f_clk(ext)= 1536 Hz

3.5

2.7

23

13

A

-

I_DD(LCD)

LCD supply current

-

32

-

V_LCD= 3.0 V;

-

T_amb= 25 C

Logic^[3]

V_IL

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

on pins CLK, SYNC, OSC,

A0, A1, T1, SA0, SCL, SDA

V_SS

-

0.3V_DD

V_DD

V

[4][5]

V_IH

I_OL

on pins CLK, SYNC, OSC,

A0, A1, T1, SA0, SCL, SDA

0.7V_DD

output sink current;

V_OL= 0.4 V; V_DD= 5 V

on pins CLK and SYNC

on pin SDA

1

3

1

-

mA

I_OH(CLK)

I_L

HIGH-level output current output source current;

on pin CLK

V_OH= 4.6 V; V_DD= 5 V

leakage current

V_I= V_DDor V_SS

;

1

-

+1

A

on pins CLK, SCL, SDA, A0,

A1, T1, and SA0

I_L(OSC)

C_I

leakage current on pin

OSC

V_I= V_DD

1

-

+1

7

A

[6]

[7]

input capacitance

-

pF

LCD outputs

V_O

output voltage variation

on pins BP0 to BP3 and

S0 to S31

100

-

+100

mV

R_O

output resistance

V_LCD= 5 V

on pins BP0 to BP3

on pins S0 to S31

-

1.5

6.0

-

k

[1] LCD outputs are open-circuit; inputs at V_SSor V_DD; external clock with 50 % duty factor; I²C-bus inactive.

[2] For typical values, see Figure 23.

[3] The I²C-bus interface of PCA85262 is 5 V tolerant.

[4] When tested, I²C pins SCL and SDA have no diode to V_DDand may be driven to the V_Ilimiting values given in Table 17 (see Figure 22

as well).

[5] Propagation delay of driver between clock (CLK) and LCD driving signals.

[6] Periodically sampled, not 100 % tested.

[7] Outputs measured one at a time.

PCA85262

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Product data sheet

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32 of 55

PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

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logic 1; no display connected; I²C-bus inactive.

Fig 23. Typical I_DDwith respect to V_DD

PCA85262

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

12. Dynamic characteristics

Table 19. Dynamic characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 8.0 V; T_amb= 40 C to +105 C; unless otherwise specified.

Symbol

Clock

f_clk(int)

f_clk(ext)

f_fr

Parameter

Conditions

Min

Typ

Max

Unit

[1]

internal clock frequency

external clock frequency

frame frequency

3505

960

146

40

4800

6240

6720

260

280

-

Hz

s

-

internal clock

external clock

200

-

t_clk(H)

t_clk(L)

HIGH-level clock time

LOW-level clock time

60

-

Synchronization

t_{PD(SYNC_N)}SYNC propagation delay

-

30

-

ns

s

t_{SYNC_NL}

t_PD(drv)

I²C-bus^[3]

Pin SCL

f_SCL

SYNC LOW time

1

-

[2]

driver propagation delay

V_LCD= 5 V

-

30

SCL clock frequency

-

400

-

kHz

t_LOW

LOW period of the SCL

clock

1.3

s

t_HIGH

HIGH period of the SCL

clock

0.6

-

s

Pin SDA

t_SU;DAT

t_HD;DAT

data set-up time

data hold time

100

0

-

ns

Pins SCL and SDA

t_BUF

bus free time between a

1.3

-

s

STOP and START

condition

t_SU;STO

t_HD;STA

t_SU;STA

t_r

set-up time for STOP

condition

0.6

-

s

hold time (repeated)

START condition

set-up time for a repeated

START condition

rise time of both SDA and f_SCL= 400 kHz

SCL signals

-

0.3

1.0

0.3

s

f_SCL< 125 kHz

t_f

fall time of both SDA and

SCL signals

C_b

capacitive load for each

bus line

-

400

50

pF

ns

t_w(spike)

spike pulse width

on the I²C-bus

[1] Typical output duty factor: 50 % measured at the CLK output pin.

[2] Not tested in production.

PCA85262

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Product data sheet

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PCA85262

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Automotive 32 x 4 LCD driver for low multiplex rates

[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V_ILand V_IHwith an

input voltage swing of V_SSto V_DD

.

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Fig 25. I²C-bus timing waveforms

PCA85262

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

13. Application information

13.1 Cascaded operation

Large display configurations of up to 8 PCA85262 can be recognized on the same I²C-bus

by using the 2-bit hardware subaddress (A0 and A1) and the programmable I²C-bus slave

address (SA0).

Table 20. Addressing cascaded PCA85262

Cluster

Bit SA0

Pin A1

Pin A0

Device

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

2

1

When cascaded PCA85262 are synchronized, they can share the backplane signals from

one of the devices in the cascade. Such an arrangement is cost-effective in large LCD

applications since the backplane outputs of only one device need to be through-plated to

the backplane electrodes of the display. The other PCA85262 of the cascade contribute

additional segment outputs. The backplanes can either be connected together to enhance

the drive capability or some can be left open-circuit (such as the ones from the slave in

Figure 26) or just some of the master and some of the slave can be taken to facilitate the

layout of the display.

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCA85262. Synchronization is guaranteed after a power-on and initialization. The only

time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by

noise in adverse electrical environments or by defining a multiplex drive mode when

PCA85262 with different SA0 levels are cascaded).

PCA85262

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Product data sheet

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36 of 55

PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

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(1) Is master (OSC connected to V_SS).

(2) Is slave (OSC connected to V_DD).

Fig 26. Cascaded PCA85262 configuration

SYNC is organized as an input/output pin. The output selection is realized as an

open-drain driver with an internal pull-up resistor. A PCA85262 asserts the SYNC line at

the onset of its last active backplane signal and monitors the SYNC line at all other times.

If synchronization in the cascade is lost, it is restored by the first PCA85262 to assert

SYNC. The timing relationship between the backplane waveforms and the SYNC signal

for the various drive modes of the PCA85262 are shown in Figure 27.

The PCA85262 can always be cascaded with other devices of the same type or

conditionally with other devices of the same family. This allows optimal drive selection for

a given number of pixels to display. Figure 27 shows the timing of the synchronization

signals.

PCA85262

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Product data sheet

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37 of 55

PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

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Fig 27. Synchronization of the cascade for the various PCA85262 drive modes

Only one master but multiple slaves are allowed in a cascade. All devices in the cascade

have to use the same clock whether it is supplied externally or provided by the master.

If an external clock source is used, all PCA85262 in the cascade must be configured such

as to receive the clock from that external source (pin OSC connected to V_DD). Thereby it

must be ensured that the clock tree is designed such that on all PCA85262 the clock

propagation delay from the clock source to all PCA85262 in the cascade is as equal as

possible since otherwise synchronization artifacts may occur.

In mixed cascading configurations, care has to be taken that the specifications of the

individual cascaded devices are always met.

PCA85262

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Product data sheet

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PCA85262

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14. Test information

14.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated

circuits, and is suitable for use in automotive applications.

PCA85262

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Product data sheet

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PCA85262

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Automotive 32 x 4 LCD driver for low multiplex rates

15. Package outline

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Fig 28. Package outline SOT362-1 (TSSOP48) of PCA85262ATT

PCA85262

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PCA85262

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Automotive 32 x 4 LCD driver for low multiplex rates

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent

standards.

PCA85262

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PCA85262

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Automotive 32 x 4 LCD driver for low multiplex rates

17. Packing information

17.1 Tape and reel information

For tape and reel packing information, please see Ref. 12 “SOT362-1_118” on page 49.

18. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

18.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

PCA85262

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

18.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 29) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 21 and 22

Table 21. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 22. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 29.

PCA85262

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 29. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

19. Footprint information

PCA85262

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

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PCA85262

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

21. Abbreviations

Table 24. Abbreviations

Acronym

AEC

CMOS

CDM

DC

Description

Automotive Electronics Council

Complementary Metal-Oxide Semiconductor

Charged Device Model

Direct Current

HBM

I²C

Human Body Model

Inter-Integrated Circuit

Integrated Circuit

IC

LCD

LSB

Liquid Crystal Display

Least Significant Bit

MSB

MSL

PCB

RAM

RC

Most Significant Bit

Moisture Sensitivity Level

Printed-Circuit Board

Random Access Memory

Resistance and Capacitance

Root Mean Square

RMS

SCL

SDA

SMD

Serial CLock line

Serial DAta Line

Surface-Mount Device

PCA85262

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

22. References

[1] AN10365 — Surface mount reflow soldering description

[2] AN10853 — ESD and EMC sensitivity of IC

[3] AN11267 — EMC and system level ESD design guidelines for LCD drivers

[4] AN11494 — Cascading NXP LCD segment drivers

[5] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[6] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[7] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices

[8] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[9] JESD22-C101 — Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[10] JESD78 — IC Latch-Up Test

[11] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[12] SOT362-1_118 — TSSOP48; Reel pack; SMD, 13", Packing information

[13] UM10204 — I²C-bus specification and user manual

[14] UM10569 — Store and transport requirements

PCA85262

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Product data sheet

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PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

23. Revision history

Table 25. Revision history

Document ID

PCA85262 v.3

Modifications:

Release date

20181112

Data sheet status

Change notice

Supersedes

Product data sheet

201810014I

PCA85262 v.2

• Updated Section 6.4 “Initialization”

• Updated layout of Section 3 “Ordering information”

20150410 Product data sheet

PCA85262 v.2

Modifications:

-

PCA85262 v.1

• The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Changed pin configuration due to redesign

• Enhanced SYNC pin description in Table 3

• Changed typical value of I_DDand I_DD(LCD)in Table 18

• Adjusted description of initialization (Section 6.4)

PCA85262 v.1

20140211

Product data sheet

-

PCA85262

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Automotive 32 x 4 LCD driver for low multiplex rates

24. Legal information

24.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

24.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

24.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

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PCA85262

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Automotive 32 x 4 LCD driver for low multiplex rates

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

24.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

25. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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PCA85262

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Automotive 32 x 4 LCD driver for low multiplex rates

26. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4. Pin description of PCA85262ATT (TSSOP48) . .5

Table 5. Definition of the PCA85262 commands . . . . . . .6

Table 6. C bit description . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 7. Mode-set command bit description . . . . . . . . . .6

Table 8. Load-data-pointer command bit description . . . .7

Table 9. Device-select command bit description . . . . . . .7

Table 10. Bank-select command bit description . . . . . . . .8

Table 11. Blink-select command bit description . . . . . . . .8

Table 12. Blink frequencies . . . . . . . . . . . . . . . . . . . . . . . .9

Table 13. Standard RAM filling in 1:3 multiplex drive mode .

13

Table 14. Entire RAM filling by rewriting in 1:3 multiplex

drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 15. Selection of possible display configurations . . .17

Table 16. Biasing characteristics . . . . . . . . . . . . . . . . . . .18

Table 17. I²C slave address byte . . . . . . . . . . . . . . . . . . .29

Table 18. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 19. Static characteristics . . . . . . . . . . . . . . . . . . . .33

Table 20. Dynamic characteristics . . . . . . . . . . . . . . . . . .35

Table 21. Addressing cascaded PCA85262 . . . . . . . . . .37

Table 22. SnPb eutectic process (from J-STD-020D) . . .44

Table 23. Lead-free process (from J-STD-020D) . . . . . .44

Table 24. Selection of LCD segment drivers . . . . . . . . . .47

Table 25. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 26. Revision history . . . . . . . . . . . . . . . . . . . . . . . .51

PCA85262

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PCA85262

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Automotive 32 x 4 LCD driver for low multiplex rates

27. Figures

Fig 1. Block diagram of PCA85262 . . . . . . . . . . . . . . . . .3

Fig 2. Pinning diagram for PCA85262ATT (TSSOP48) . .4

Fig 3. Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . .10

Fig 4. Relationship between LCD layout, drive mode,

display RAM filling order, and display data

transmitted over the I²C-bus . . . . . . . . . . . . . . . .11

Fig 5. RAM banks in static and multiplex driving mode 1:2

14

Fig 6. Bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Fig 7. Example of the Bank-select command with multiplex

drive mode 1:2. . . . . . . . . . . . . . . . . . . . . . . . . . .15

Fig 8. Example of displays suitable for PCA85262 . . . .17

Fig 9. Typical system configuration . . . . . . . . . . . . . . . .17

Fig 10. Electro-optical characteristic: relative transmission

curve of the liquid. . . . . . . . . . . . . . . . . . . . . . . . .20

Fig 11. Static drive mode waveforms. . . . . . . . . . . . . . . .21

Fig 12. Waveforms for the 1:2 multiplex drive mode with ¹⁄₂

bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Fig 13. Waveforms for the 1:2 multiplex drive mode with ¹⁄₃

bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 14. Waveforms for the 1:3 multiplex drive mode with ¹⁄₃

bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Fig 15. Waveforms for the 1:4 multiplex drive mode with ¹⁄₃

bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Fig 16. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Fig 17. Definition of START and STOP conditions. . . . . .27

Fig 18. System configuration . . . . . . . . . . . . . . . . . . . . . .28

Fig 19. Acknowledgement of the I²C-bus . . . . . . . . . . . .28

Fig 20. I²C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . . . .30

Fig 21. Format of command byte. . . . . . . . . . . . . . . . . . .30

Fig 22. Device protection circuits. . . . . . . . . . . . . . . . . . .31

Fig 23. Typical I_DDwith respect to V_DD. . . . . . . . . . . . . .34

Fig 24. Driver timing waveforms . . . . . . . . . . . . . . . . . . .36

Fig 25. I²C-bus timing waveforms . . . . . . . . . . . . . . . . . .36

Fig 26. Cascaded PCA85262 configuration. . . . . . . . . . .38

Fig 27. Synchronization of the cascade for the various

PCA85262 drive modes. . . . . . . . . . . . . . . . . . . .39

Fig 28. Package outline SOT362-1 (TSSOP48) of

PCA85262ATT. . . . . . . . . . . . . . . . . . . . . . . . . . .41

Fig 29. Temperature profiles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Fig 30. Footprint information for reflow soldering of

SOT362-1 (TSSOP48) of PCA85262ATT . . . . . .46

PCA85262

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 November 2018

54 of 55

PCA85262

NXP Semiconductors

Automotive 32 x 4 LCD driver for low multiplex rates

28. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

8.1

8.2

8.3

8.4

8.5

8.6

8.7

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

START and STOP conditions. . . . . . . . . . . . . 27

System configuration . . . . . . . . . . . . . . . . . . . 27

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 28

I²C-bus controller . . . . . . . . . . . . . . . . . . . . . . 29

Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 29

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3

3.1

4

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

9

Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 31

Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 32

Static characteristics . . . . . . . . . . . . . . . . . . . 33

Dynamic characteristics. . . . . . . . . . . . . . . . . 35

Application information . . . . . . . . . . . . . . . . . 37

Cascaded operation. . . . . . . . . . . . . . . . . . . . 37

Test information . . . . . . . . . . . . . . . . . . . . . . . 40

Quality information. . . . . . . . . . . . . . . . . . . . . 40

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 41

Handling information . . . . . . . . . . . . . . . . . . . 42

Packing information . . . . . . . . . . . . . . . . . . . . 43

Tape and reel information . . . . . . . . . . . . . . . 43

10

11

7

7.1

Functional description . . . . . . . . . . . . . . . . . . . 6

Commands of PCA85262. . . . . . . . . . . . . . . . . 6

Command: mode-set . . . . . . . . . . . . . . . . . . . . 6

Command: load-data-pointer . . . . . . . . . . . . . . 7

Command: device-select . . . . . . . . . . . . . . . . . 7

Command: bank-select. . . . . . . . . . . . . . . . . . . 8

Command: blink-select. . . . . . . . . . . . . . . . . . . 8

Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Clock and frame frequency. . . . . . . . . . . . . . . . 9

Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . 9

External clock . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Subaddress counter . . . . . . . . . . . . . . . . . . . . 12

RAM addressing in cascaded applications. . . 12

RAM writing in 1:3 multiplex drive mode. . . . . 13

Bank selection . . . . . . . . . . . . . . . . . . . . . . . . 14

Output bank selector . . . . . . . . . . . . . . . . . . . 14

Input bank selector . . . . . . . . . . . . . . . . . . . . . 14

RAM bank switching. . . . . . . . . . . . . . . . . . . . 14

Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Device initialization. . . . . . . . . . . . . . . . . . . . . 16

Device setup. . . . . . . . . . . . . . . . . . . . . . . . . . 16

Possible display configurations . . . . . . . . . . . 16

LCD bias generator . . . . . . . . . . . . . . . . . . . . 18

LCD voltage selector . . . . . . . . . . . . . . . . . . . 18

Electro-optical performance . . . . . . . . . . . . . . 19

LCD drive mode waveforms . . . . . . . . . . . . . . 21

Static drive mode . . . . . . . . . . . . . . . . . . . . . . 21

1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 22

1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 24

1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 25

Backplane and segment outputs . . . . . . . . . . 26

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 26

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 26

12

13

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.1.5.1

7.2

7.2.1

7.2.2

7.2.3

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.3.5.1

7.3.5.2

7.3.5.3

7.4

14

14.1

15

15.1

16

17

18

18.1

19

Soldering of SMD packages. . . . . . . . . . . . . . 43

Introduction to soldering. . . . . . . . . . . . . . . . . 43

Wave and reflow soldering. . . . . . . . . . . . . . . 43

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 43

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 44

19.1

19.2

19.3

19.4

20

Footprint information . . . . . . . . . . . . . . . . . . . 45

Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

LCD segment driver selection . . . . . . . . . . . . 47

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 49

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Revision history . . . . . . . . . . . . . . . . . . . . . . . 51

21

21.1

22

23

7.4.1

7.4.2

7.5

7.6

7.7

24

25

Legal information . . . . . . . . . . . . . . . . . . . . . . 52

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 52

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 53

25.1

25.2

25.3

25.4

7.7.1

7.8

7.8.1

7.8.2

7.8.3

7.8.4

7.9

26

27

28

29

Contact information . . . . . . . . . . . . . . . . . . . . 53

Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.9.1

7.9.2

8

Characteristics of the I²C-bus . . . . . . . . . . . . 27

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 12 November 2018

Document identifier: PCA85262


型号：	PCA85262
厂家：	NXP
描述：	Automotive 32 x 4 LCD driver for low multiplex rates CD
文件：	总55页 (文件大小：495K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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