PCA8576FUG/2DA/Q1_技术文档

PCA8576F

Automotive 40 × 4 LCD driver

Rev. 3 — 3 December 2014

Product data sheet

1. General description

The PCA8576F is a peripheral device which interfaces to almost any Liquid Crystal

Display (LCD)¹with low multiplex rates. It generates the drive signals for any static or

multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily

cascaded for larger LCD applications. The PCA8576F is compatible with most

microcontrollers and communicates via the two-line bidirectional I²C-bus. Communication

overheads are minimized by a display RAM with auto-incremented addressing, by

hardware subaddressing and by display memory switching (static and duplex drive

modes).

For a selection of NXP LCD segment drivers, see Table 28 on page 46.

2. Features and benefits

 AEC-Q100 grade 2 compliant for automotive applications

 Single chip LCD controller and driver

 Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing

 Selectable display bias configuration: static, ¹⁄₂, or ¹⁄₃

 Internal LCD bias generation with voltage-follower buffers

 40 segment drives:

 Up to 20 7-segment numeric characters

 Up to 10 14-segment alphanumeric characters

 Any graphics of up to 160 segments/elements

 40  4-bit RAM for display data storage

 Auto-incremented display data loading across device subaddress boundaries

 Display memory bank switching in static and duplex drive modes

 Versatile blinking modes

 Independent supplies possible for LCD and logic voltages

 Wide power supply range: from 1.8 V to 5.5 V

 Wide LCD supply range:

 From 2.5 V for low-threshold LCDs

 Up to 8.0 V for high-threshold twisted nematic LCDs

 Low power consumption

 400 kHz I²C-bus interface

 May be cascaded for large LCD applications (up to 1280 segments/elements possible)

 No external components required

 Compatible with chip-on-glass and chip-on-board technology

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19.

PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

PCA8576FUG

bare die

59 bumps

PCA8576FUG

3.1 Ordering options

Table 2.

Ordering options

Product type number

Sales item (12NC)

Orderable part number

IC

Delivery form

revision

PCA8576FUG/2DA/Q1

935302565026

PCA8576FUG/2DA/QKP

1

chips in tray

4. Marking

Table 3.

Product type number

PCA8576FUG/2DA/Q1

Marking codes

Marking code

PC8576F-1

5. Block diagram

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Fig 1. Block diagram of PCA8576F

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

2 of 54

PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

6. Pinning information

6.1 Pinning

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Viewed from active side. C1 and C2 are alignment marks. For mechanical details, see Figure 31.

Fig 2. Pinning diagram for PCA8576FUG (bare die)

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

6.2 Pin description

Table 4.

Pin description

Input or input/output pins must always be at a defined level (V_SSor V_DD) unless otherwise specified.

Symbol

SDA

Description

1, 58, 59

I²C-bus serial data input and output

I²C-bus serial clock input

external clock input or output

supply voltage

SCL

2, 3

5

CLK

V_DD

6

SYNC

4

cascade synchronization input or output; if not used it

must be left open

OSC

A0, A1

T1

7

internal oscillator enable input

subaddress inputs

8, 9

10

dedicated testing pin; to be tied to V_SSin application

mode

SA0

V_SS

11

12^[1]

I²C-bus address input; bit 0

ground supply voltage

LCD supply voltage

V_LCD

13

BP0, BP2, BP1, 14 to 17

BP3

LCD backplane outputs

S0 to S39

18 to 57

LCD segment outputs

[1] The substrate (rear side of the die) is at V_SSpotential and must not be connected.

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

4 of 54

PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

7. Functional description

7.1 Commands of PCA8576F

The commands available to the PCA8576F are defined in Table 5.

Table 5.

Definition of PCA8576F commands

Operation code

Command

Bit

Reference

7

6

1

0

1

5

4

3

2

1

0

[1]

mode-set

C

0

-

E

B

M[1:0]

Table 7

Table 8

Table 9

Table 10

Table 11

load-data-pointer

device-select

bank-select

blink-select

P[5:0]

1

0

1

0

1

0

A[1:0]

I

0

O

AB

BF[1:0]

[1] Not used.

All available commands carry a continuation bit C in their most significant bit position as

shown in Figure 3.

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Fig 3. Format of command byte

When this bit is set logic 1, it indicates that the next byte of the transfer to arrive will also

represent a command. If this bit is set logic 0, it indicates that the command byte is the

last in the transfer. Further bytes will be regarded as display data (see Table 6).

Table 6.

C bit description

Bit

Symbol Value

Description

continue bit

7

C

0

last control byte in the transfer; next byte will be regarded

as display data

1

control bytes continue; next byte will be a command too

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

7.1.1 Command: mode-set

Table 7.

Mode-set command bit description

Bit

7

Symbol Value

Description

C

-

0, 1

10

-

see Table 6

6, 5

4

fixed value

-

unused

3

E

display status^[1]

disabled (blank)^[2]

enabled

0

1

2

B

LCD bias configuration^[3]

¹⁄₃bias

¹⁄₂bias

0

1

1 to 0

M[1:0]

LCD drive mode selection

static; BP0

01

10

11

00

1:2 multiplex; BP0, BP1

1:3 multiplex; BP0, BP1, BP2

1:4 multiplex; BP0, BP1, BP2, BP3

[1] The possibility to disable the display allows implementation of blinking under external control.

[2] The display is disabled by setting all backplane and segment outputs to V_LCD

.

[3] Not applicable for static drive mode.

7.1.2 Command: load-data-pointer

Table 8.

Load-data-pointer command bit description

See Section 7.3.5.

Bit

7

Symbol Value

Description

see Table 6

fixed value

C

0, 1

0

6

-

5 to 0

P[5:0]

000000 to

100111

6 bit binary value, 0 to 39; transferred to the data pointer to

define one of forty display RAM addresses

7.1.3 Command: device-select

Table 9.

Device-select command bit description

See Section 7.3.6.

Bit

Symbol Value

Description

see Table 6

fixed value

7

C

0, 1

6 to 2

1 to 0

-

11000

00 to 11

A[1:0]

2-bit binary value, 0 to 3; transferred to the subaddress

counter to define one of four hardware subaddresses

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

7.1.4 Command: bank-select

Table 10. Bank-select command bit description

See Section 7.3.8.2 and Section 7.3.8.3.

Bit

Symbol Value

Description

Static

1:2 multiplex^[1]

7

C

-

0, 1

see Table 6

fixed value

6 to 2

1

11110

I

input bank selection; storage of arriving display data

0

1

RAM row 0

RAM row 2

RAM rows 0 and 1

RAM rows 2 and 3

0

O

output bank selection; retrieval of LCD display data

0

1

RAM row 0

RAM row 2

RAM rows 0 and 1

RAM rows 2 and 3

[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.

7.1.5 Command: blink-select

Table 11. Blink-select command bit description

See Section 7.2.4.

Bit

7

Symbol Value

Description

C

0, 1

see Table 6

6 to 3

2

-

1110

fixed value

AB

blink mode selection

0

1

normal blinking^[1]

alternate RAM bank blinking^[2]

1 to 0

BF[1:0]

blink frequency selection

00

01

10

11

off

1

2

3

[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.

[2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.

7.2 Clock and frame frequency

7.2.1 Internal clock

The internal logic of the PCA8576F and its LCD drive signals are timed either by its

internal oscillator or by an external clock. The internal oscillator is enabled by connecting

pin OSC to pin V_SS. If the internal oscillator is used, the output from pin CLK can be used

as the clock signal for several PCA8576Fs in the system that are connected in cascade.

7.2.2 External clock

Pin CLK is enabled as an external clock input by connecting pin OSC to V_DD. The LCD

frame signal frequency is determined by the clock frequency (f_clk).

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

Remark: A clock signal must always be supplied to the device; removing the clock may

freeze the LCD in a DC state, which is not suitable for the liquid crystal.

7.2.3 Timing and frame frequency

The PCA8576F timing controls the internal data flow of the device. This includes the

transfer of display data from the display RAM to the display segment outputs. In cascaded

applications, the correct timing relationship between each PCA8576F in the system is

maintained by the synchronization signal at pin SYNC. The timing also generates the LCD

frame signal whose frequency is derived from the clock frequency. The frame signal

frequency is a fixed division of the clock frequency from either the internal or an external

f_clk

clock: f_fr

=

.

-------

24

7.2.4 Blinking

The display blinking capabilities of the PCA8576F are very versatile. The whole display

can blink at frequencies selected by the blink-select command (see Table 11). The blink

frequencies are derived from the clock frequency. The ratio between the clock and blink

frequencies depends on the blink mode selected (see Table 11).

An additional feature is for an arbitrary selection of LCD segments/elements to blink. This

applies to the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. By means of the output bank selector, the displayed RAM

banks are exchanged with alternate RAM banks at the blink frequency. This mode can

also be specified by the blink-select command.

In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of

LCD segments/elements can blink by selectively changing the display RAM data at fixed

time intervals.

The entire display can blink at a frequency other than the nominal blink frequency. This

can be effectively performed by resetting and setting the display enable bit E at the

required rate using the mode-set command (see Table 7).

Table 12. Blinking frequencies

Blink mode

Normal operating mode ratio

Nominal blink frequency^[1]

Unit

Hz

off

1

-

blinking off

6.2

Hz

f_clk

---------

768

2

3

3.1

1.6

Hz

f_clk

------------

1536

f_clk

------------

3072

[1] Blink modes 1, 2 and 3 and the nominal blink frequencies correspond to an oscillator frequency (f_clk) of

4800 Hz (see Section 13).

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

7.3 Display RAM

The display RAM is a static 40  4-bit RAM which stores LCD data.

There is a one-to-one correspondence between

• the bits in the RAM bitmap and the LCD segments/elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;

similarly, a logic 0 indicates the off-state.

The display RAM bit map, Figure 4, shows the rows 0 to 3 which correspond with the

backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the

segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,

second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2,

and BP3 respectively.

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The display RAM bitmap shows the direct relationship between the display RAM column and the

segment outputs; and between the bits in a RAM row and the backplane outputs.

Fig 4. Display RAM bit map

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

When display data is transmitted to the PCA8576F, the received display bytes are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and depending on the current multiplex drive mode the bits are stored singularly,

in pairs, triples, or quadruples. To illustrate the filling order, an example of a 7-segment

display showing all drive modes is given in Figure 5; the RAM filling organization depicted

applies equally to other LCD types, see Section 7.3.1 to Section 7.3.4.

7.3.1 RAM filling in static drive mode

In the static drive mode the eight transmitted data bits are placed in eight successive

display RAM columns in row 0 (see Figure 6).

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Fig 6. Display RAM filling order in static drive mode

7.3.2 RAM filling in 1:2 multiplex drive mode

In the 1:2 multiplex drive mode the eight transmitted data bits are placed in four

successive display RAM columns of two rows (see Figure 7).

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Fig 7. Display RAM filling order in 1:2 multiplex drive mode

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

7.3.3 RAM filling in 1:3 multiplex drive mode

In 1:3 multiplex drive mode, the RAM is written as shown in Table 13 (see Figure 5 as

well).

Table 13. Standard RAM filling in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any segments/elements on the

display.

Display RAM

bits (rows)/

backplane

Display RAM addresses (columns)/segment outputs (Sn)

0

1

2

3

4

5

6

7

8

9

:

outputs (BPn)

0

1

2

3

a7

a6

a5

-

a4

a3

a2

-

a1

a0

-

b7

b6

b5

-

b4

b3

b2

-

b1

b0

-

c7

c6

c5

-

c4

c3

c2

-

c1

c0

-

d7

d6

d5

-

:

-

If the bit at position BP2/S2 would be written by a second byte transmitted, then the

mapping of the segment bits would change as illustrated in Table 14.

Table 14. Entire RAM filling by rewriting in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to segments/elements on the display.

Display RAM

bits (rows)/

backplane

Display RAM addresses (columns)/segment outputs (Sn)

0

1

2

3

4

5

6

7

8

9

:

outputs (BPn)

0

1

2

3

a7

a6

a5

-

a4

a3

a2

-

a1/b7 b4

a0/b6 b3

b1/c7 c4

b0/c6 c3

c1/d7 d4

c0/d6 d3

d1/e7 e4

d0/e6 e3

:

b5

-

b2

-

c5

-

c2

-

d5

-

d2

-

e5

-

e2

-

In the case described in Table 14 the RAM has to be written entirely and BP2/S2, BP2/S5,

BP2/S8 etc. have to be connected to segments/elements on the display. This can be

achieved by a combination of writing and rewriting the RAM like follows:

• In the first write to the RAM, bits a7 to a0 are written.

• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7

and b6.

• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and

c6.

Depending on the method of writing to the RAM (standard or entire filling by rewriting),

some segments/elements remain unused or can be used, but it has to be considered in

the module layout process as well as in the driver software design.

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Product data sheet

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

7.3.4 RAM filling in 1:4 multiplex drive mode

In the 1:4 multiplex drive mode the eight transmitted data bits are placed in two

successive display RAM columns of four rows (see Figure 8).

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Fig 8. Display RAM filling order in 1:4 multiplex drive mode

7.3.5 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte, or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer command (see Table 8). Following this command, an

arriving data byte is stored at the display RAM address indicated by the data pointer. The

filling order is shown in Figure 5. After each byte is stored, the content of the data pointer

is automatically incremented by a value dependent on the selected LCD drive mode:

• In static drive mode by eight.

• In 1:2 multiplex drive mode by four.

• In 1:3 multiplex drive mode by three.

• In 1:4 multiplex drive mode by two.

If an I²C-bus data access terminates early then the state of the data pointer is unknown.

Consequently, the data pointer must be rewritten prior to further RAM accesses.

7.3.6 Subaddress counter

The storage of display data is determined by the contents of the subaddress counter.

Storage is allowed only when the content of the subaddress counter match with the

hardware subaddress applied to A0 and A1. The subaddress counter value is defined by

the device-select command (see Table 9). If the content of the subaddress counter and

the hardware subaddress do not match then data storage is inhibited but the data pointer

is incremented as if data storage had taken place. The subaddress counter is also

incremented when the data pointer overflows.

PCA8576F

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Product data sheet

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

The storage arrangements described lead to extremely efficient data loading in cascaded

applications. When a series of display bytes are sent to the display RAM, automatic

wrap-over to the next PCA8576F occurs when the last RAM address is exceeded.

Subaddressing across device boundaries is successful even if the change to the next

device in the cascade occurs within a transmitted character.

The hardware subaddress must not be changed while the device is being accessed on the

I²C-bus interface.

7.3.7 Writing over the RAM address boundary

In all multiplex drive modes, depending on the setting of the data pointer, it is possible to

fill the RAM over the RAM address boundary. If the PCA8576F is part of a cascade the

additional bits fall into the next device that also generates the acknowledge signal. If the

PCA8576F is a single device or the last device in a cascade the additional bits will be

discarded and no acknowledge signal will be generated.

7.3.8 Bank selection

7.3.8.1 RAM bank switching

The PCA8576F includes a RAM bank switching feature in the static and 1:2 multiplex

drive modes. A bank can be thought of as one RAM row or a collection of RAM rows (see

Figure 9). The RAM bank switching gives the provision for preparing display information in

an alternative bank and to be able to switch to it once it is complete.

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Fig 9. RAM banks in static and multiplex driving mode 1:2

There are two banks; bank 0 and bank 1. Figure 9 shows the location of these banks

relative to the RAM map. Input and output banks can be set independently from one

another with the Bank-select command (see Table 10 on page 7). Figure 10 shows the

concept.

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

14 of 54

PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

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Fig 10. Bank selection

In the static drive mode, the bank-select command may request the contents of row 2 to

be selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the

contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the

provision for preparing display information in an alternative bank and to be able to switch

to it once it is assembled.

In Figure 11 an example is shown for 1:2 multiplex drive mode where the displayed data is

read from the first two rows of the memory (bank 0), while the transmitted data is stored in

the second two rows of the memory (bank 1).

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Fig 11. Example of the Bank-select command with multiplex drive mode 1:2

7.3.8.2 Output bank selector

The output bank selector (see Table 10) selects one of the four rows per display RAM

address for transfer to the display register. The actual row selected depends on the

selected LCD drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by

the contents of row 1, 2, and then 3

• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially

• In 1:2 multiplex mode, rows 0 and 1 are selected

• In static mode, row 0 is selected

7.3.8.3 Input bank selector

The input bank selector loads display data into the display RAM in accordance with the

selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode

or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see

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PCA8576F

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Automotive 40 × 4 LCD driver

Table 10). The input bank selector functions independently to the output bank selector.

7.4 Initialization

At power-on the status of the I²C-bus and the registers of the PCA8576F is undefined.

Therefore the PCA8576F should be initialized as quickly as possible after power-on to

ensure a proper bus communication and to avoid display artifacts. The following

instructions should be accomplished for initialization:

• I²C-bus initialization. For information about the I²C-bus, see Section 8.

– generating a START condition

– sending 0h and ignoring the acknowledge

– generating a STOP condition

• Mode-set command (see Table 7), setting

– bit E = 0

– bit B to the required LCD bias configuration

– bits M[1:0] to the required LCD drive mode

• Load-data-pointer command (see Table 8), setting

– bits P[5:0] to 0h (or any other required address)

• Device-select command (see Table 9), setting

– bits A[1:0] to the required hardware subaddress (for example, 0h)

• Bank-select command (see Table 10), setting

– bit I to 0

– bit O to 0

• Blink-select command (see Table 11), setting

– bit AB to 0 or 1

– bits BF[1:0] to 00 (or to a desired blinking mode)

• writing meaningful information (for example, a logo) into the display RAM

After the initialization, the display can be switched on by setting bit E = 1 with the

mode-set command.

7.5 Possible display configurations

The possible display configurations of the PCA8576F depend on the number of active

backplane outputs required. A selection of display configurations is shown in Table 15. All

of these configurations can be implemented in the typical system shown in Figure 13.

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

16 of 54

PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

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Fig 12. Example of displays suitable for PCA8576F

Table 15. Selection of possible display configurations

Number of

Backplanes

Icons

Digits/Characters

7-segment^[1]

Dot matrix:

segments/

elements

14-segment^[2]

4

3

2

1

160

120

80

20

15

10

5

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120 (3  40)

80 (2  40)

40 (1  40)

5

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The resistance of the power lines must be kept to a minimum.

For chip-on-glass applications, due to the Indium Tin Oxide (ITO) track resistance, each supply line

must be routed separately between the chip and the connector.

Fig 13. Typical system configuration

PCA8576F

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Product data sheet

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

The host microcontroller maintains the 2-line I²C-bus communication channel with the

PCA8576F. The internal oscillator is enabled by connecting pin OSC to pin V_SS. The

appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.

The only other connections required to complete the system are to the power supplies

(V_DD, V_SS, and V_LCD) and the LCD panel chosen for the application.

7.6 LCD voltage

7.6.1 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider of three

impedances connected between pins V_LCDand V_SS. The center impedance is bypassed

by switch if the ¹⁄₂bias voltage level for the 1:2 multiplex drive mode configuration is

selected. The LCD voltage can be temperature compensated externally using the supply

to pin V_LCD

.

7.6.2 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

mode-set command from the command decoder. The biasing configurations that apply to

the preferred modes of operation, together with the biasing characteristics as functions of

V

_LCDand the resulting discrimination ratios (D) are given in Table 16.

Discrimination is a term which is defined as the ratio of the on and off RMS voltage across

a segment. It can be thought of as a measurement of contrast.

Table 16. Biasing characteristics

LCD drive

mode

Number of:

LCD bias

configuration

V_offRMSV_onRMS

------------------------ ----------------------- D = ------------------------

V_LCDV_LCDV_offRMS

V_onRMS

Backplanes Levels

static

1

2

3

4

2

3

4

static

0

1



1

⁄

1:2 multiplex

1:3 multiplex

1:4 multiplex

0.354

0.333

0.791

0.745

0.638

0.577

2.236

1.915

1.732

2

1

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3

1

⁄

3

1

⁄

3

A practical value for V_LCDis determined by equating V_off(RMS)with a defined LCD

threshold voltage (V_th(off)), typically when the LCD exhibits approximately 10 % contrast. In

the static drive mode a suitable choice is V_LCD> 3V_th(off)

.

Multiplex drive modes of 1:3 and 1:4 with ¹⁄₂bias are possible but the discrimination and

hence the contrast ratios are smaller.

1

Bias is calculated by ------------ , where the values for a are

1 + a

a = 1 for ¹⁄₂bias

a = 2 for ¹⁄₃bias

The RMS on-state voltage (V_on(RMS)) for the LCD is calculated with Equation 1:

a²+ 2a + n

n  1 + a²

V_onRMS

=

-----------------------------

(1)

V

LCD

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Product data sheet

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PCA8576F

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Automotive 40 × 4 LCD driver

where the values for n are

n = 1 for static drive mode

n = 2 for 1:2 multiplex drive mode

n = 3 for 1:3 multiplex drive mode

n = 4 for 1:4 multiplex drive mode

The RMS off-state voltage (V_off(RMS)) for the LCD is calculated with Equation 2:

a²– 2a + n

n  1 + a²

V_offRMS

=

-----------------------------

(2)

(3)

V

LCD

Discrimination is the ratio of V_on(RMS)to V_off(RMS)and is determined from Equation 3:

a²+ 2a + n

V_onRMS

D =

=

---------------------------

----------------------

a²– 2a + n

V_offRMS

Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with

¹⁄₂bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with

21

¹⁄₂bias is ---------- = 1.528 .

3

The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V_LCD

as follows:

• 1:3 multiplex (¹⁄₂bias): V_LCD

• 1:4 multiplex (¹⁄₂bias): V_LCD

=

6  V_offRMS= 2.449V_offRMS

4  3

---------------------

= 2.309V_offRMS

3

These compare with V_LCD= 3V_offRMSwhen ¹⁄₃bias is used.

_LCDis sometimes referred as the LCD operating voltage.

V

7.6.2.1 Electro-optical performance

Suitable values for V_on(RMS)and V_off(RMS)are dependent on the LCD liquid used. The

RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of

the pixel.

For any given liquid, there are two threshold values defined. One point is at 10 % relative

transmission (at V_th(off)) and the other at 90 % relative transmission (at V_th(on)), see

Figure 14. For a good contrast performance, the following rules should be followed:

V

_onRMS V_thon

_offRMS V_thoff

(4)

(5)

V

_on(RMS)and V_off(RMS)are properties of the display driver and are affected by the selection

of a, n (see Equation 1 to Equation 3) and the V_LCDvoltage.

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Product data sheet

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PCA8576F

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Automotive 40 × 4 LCD driver

V_th(off)and V_th(on)are properties of the LCD liquid and can be provided by the module

manufacturer. V_th(off)is sometimes named V_th. V_th(on)is sometimes named saturation

voltage V_sat

.

It is important to match the module properties to those of the driver in order to achieve

optimum performance.

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PCA8576F

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PCA8576F

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Automotive 40 × 4 LCD driver

7.6.3 LCD drive mode waveforms

7.6.3.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD. The

backplane (BPn) and segment drive (S_n) waveforms for this mode are shown in Figure 15.

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(2) V_on(RMS)= V_LCD

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(4) V_off(RMS)= 0 V.

.

V

Fig 15. Static drive mode waveforms

PCA8576F

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PCA8576F

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Automotive 40 × 4 LCD driver

7.6.3.2 1:2 Multiplex drive mode

The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This

mode allows fractional LCD bias voltages of ¹⁄₂bias or ¹⁄₃bias as shown in Figure 16 and

Figure 17.

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(1) V_state1(t) = V_Sn(t)  V_BP0(t).

(2) V_on(RMS)= 0.791V_LCD

(3) _state2(t) = V_Sn+1(t)  V_BP1(t).

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Fig 16. Waveforms for the 1:2 multiplex drive mode with ¹⁄₂bias

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

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(1) V_state1(t) = V_Sn(t)  V_BP0(t).

(2) V_on(RMS)= 0.745V_LCD

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.

Fig 17. Waveforms for the 1:2 multiplex drive mode with ¹⁄₃bias

PCA8576F

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

7.6.3.3 1:3 Multiplex drive mode

When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies

(see Figure 18).

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(1) V_state1(t) = V_Sn(t)  V_BP0(t).

(2) _on(RMS)= 0.638V_LCD

(3) V_state2(t) = V_Sn+1(t)  V_BP1(t).

(4) V_off(RMS)= 0.333V_LCD

V

.

Fig 18. Waveforms for the 1:3 multiplex drive mode with ¹⁄₃bias

PCA8576F

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

7.6.3.4 1:4 Multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies (see

Figure 19).

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(1) V_state1(t) = V_Sn(t)  V_BP0(t).

(2) _on(RMS)= 0.577V_LCD

(3) V_state2(t) = V_Sn+1(t)  V_BP1(t).

(4) V_off(RMS)= 0.333V_LCD

V

.

Fig 19. Waveforms for the 1:4 multiplex drive mode with ¹⁄₃bias

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

25 of 54

PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

7.6.4 Backplane outputs

The LCD drive section includes four backplane outputs BP0 to BP3 which must be

connected directly to the LCD. The backplane output signals are generated in accordance

with the selected LCD drive mode. If less than four backplane outputs are required, the

unused outputs can be left open-circuit.

Table 17 describes which outputs are active for each of the multiplex drive modes and

what signal is generated.

Table 17. Mapping of output pins and corresponding output signals with respect to the

multiplex driving mode

Multiplex drive

mode

Output pin

BP0

BP1

BP2

BP3

Signal

BP0

1:4

BP1

BP2

BP3

1:3

BP0

BP1

BP2

BP1^[1]

BP0^[1]

1:2

BP0

BP1

BP0^[1]

static

BP0

[1] These pins may optionally be connected to the display to improve drive strength. Connect only with the

corresponding output pin carrying the same signal. If not required, they can be left open-circuit.

7.6.5 Segment outputs

The LCD drive section includes 40 segment outputs S0 to S39 which should be

connected directly to the LCD. The segment output signals are generated in accordance

with the multiplexed backplane signals and with data residing in the display latch. When

less than 40 segment outputs are required, the unused segment outputs should be left

open-circuit.

PCA8576F

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Product data sheet

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

8. Characteristics of the I²C-bus

The I²C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 20).

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Fig 20. Bit transfer

8.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START

condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P.

The START and STOP conditions are illustrated in Figure 21.

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Fig 21. Definition of START and STOP conditions

8.3 System configuration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves. The system configuration is shown in Figure 22.

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

27 of 54

PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

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Fig 22. System configuration

8.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

• A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte.

• A master receiver must generate an acknowledge after the reception of each byte that

has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I²C-bus is illustrated in Figure 23.

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Fig 23. Acknowledgement of the I²C-bus

PCA8576F

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Product data sheet

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

8.5 I²C-bus controller

The PCA8576F acts as an I²C-bus slave receiver. It does not initiate I²C-bus transfers or

transmit data to an I²C-bus master receiver. The only data output from the PCA8576F are

the acknowledge signals of the selected devices. Device selection depends on the

I²C-bus slave address, on the transferred command data and on the hardware

subaddress.

In single device applications, the hardware subaddress inputs A0 and A1 are normally

tied to V_SSwhich defines the hardware subaddress 0. In multiple device applications A0

and A1 are tied to V_SSor V_DDusing a binary coding scheme, so that no two devices with a

common I²C-bus slave address have the same hardware subaddress.

8.6 Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

8.7 I²C-bus protocol

Two I²C-bus slave addresses (0111 000 and 0111 001) are used to address the

PCA8576F. The entire I²C-bus slave address byte is shown in Table 18.

Table 18. I²C slave address byte

Slave address

Bit

7

6

5

4

3

2

1

0

MSB

LSB

R/W

0

1

0

SA0

The PCA8576F is a write-only device and will not respond to a read access, therefore bit

0 should always be logic 0. Bit 1 of the slave address byte that a PCA8576F will respond

to, is defined by the level tied to its SA0 input (V_SSfor logic 0 and V_DDfor logic 1).

Having two reserved slave addresses allows the following on the same I²C-bus:

• Up to 8 PCA8576F for very large LCD applications

• The use of two types of LCD multiplex drive

The I²C-bus protocol is shown in Figure 24. The sequence is initiated with a START

condition (S) from the I²C-bus master which is followed by one of two possible PCA8576F

slave addresses available. All PCA8576Fs whose SA0 inputs correspond to bit 0 of the

slave address respond by asserting an acknowledge in parallel. This I²C-bus transfer is

ignored by all PCA8576Fs whose SA0 inputs are set to the alternative level.

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

29 of 54

PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

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Fig 24. I²C-bus protocol

After an acknowledgement, one or more command bytes follow, that define the status of

each addressed PCA8576F.

The last command byte sent is identified by resetting its most significant bit, continuation

bit C, (see Section 7.1). The command bytes are also acknowledged by all addressed

PCA8576F on the bus.

After the last command byte, one or more display data bytes may follow. Display data

bytes are stored in the display RAM at the address specified by the data pointer and the

subaddress counter. Both data pointer and subaddress counter are automatically updated

and the data directed to the intended PCA8576F device.

An acknowledgement after each byte is asserted only by the PCA8576Fs that are

addressed via address lines A0 and A1. After the last display byte, the I²C-bus master

asserts a STOP condition (P). Alternately a START may be asserted to restart an I²C-bus

access.

PCA8576F

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Product data sheet

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

9. Internal circuitry

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Fig 25. Device protection circuits

PCA8576F

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Product data sheet

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31 of 54

PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

10. Safety notes

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling

electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or

equivalent standards.

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(V_LCD) is on while the IC supply voltage (V_DD) is off, or vice versa. This may cause unwanted

display artifacts. To avoid such artifacts, V_LCDand V_DDmust be applied or removed together.

Semiconductors are light sensitive. Exposure to light sources can cause the IC to

malfunction. The IC must be protected against light. The protection must be applied to all

sides of the IC.

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

32 of 54

PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

11. Limiting values

Table 19. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

Parameter

Conditions

Min

0.5

Max

+6.5

+9.0

+6.5

Unit

V

supply voltage

LCD supply voltage

input voltage

V_LCD

V_I

V

on each of the pins CLK,

SDA, SCL, SYNC, SA0,

OSC, A0, A1, T1

V

V_O

output voltage

on each of the pins S0 to

S39, BP0 to BP3

0.5

+9.0

V

I_I

input current

10

50

-

+10

+50

400

100

5000

mA

mW

V

I_O

output current

I_DD

supply current

I_DD(LCD)

I_SS

LCD supply current

ground supply current

total power dissipation

output power

P_tot

P_o

-

[1]

V_ESD

electrostatic discharge

voltage

HBM

-

[2]

[3]

I_lu

latch-up current

V_LU(VLCD)= 11.5 V

-

200

mA

C

T_stg

T_amb

storage temperature

ambient temperature

65

40

+150

+105

operating device

C

[1] Pass level; Human Body Model (HBM) according to Ref. 10 “JESD22-A114”.

[2] Pass level; latch-up testing according to Ref. 11 “JESD78” at maximum ambient temperature (T_amb(max)).

[3] According to the store and transport requirements (see Ref. 14 “UM10569”) the devices have to be stored at a temperature of +8 C to

+45 C and a humidity of 25 % to 75 %.

PCA8576F

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Product data sheet

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33 of 54

PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

12. Static characteristics

Table 20. Static characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 8.0 V; T_amb= 40 C to +105 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supplies

V_DD

supply voltage

LCD supply voltage

supply current

V_LCD 6.5 V

1.8

2.5

-

5.5

6.5

8.0

20

-

V

V_LCD> 6.5 V

-

V

V_LCD

V_DD< 2.5 V

-

V

V_DD 2.5 V

-

V

[1][2]

[1]

I_DD

f_clk(ext)= 1536 Hz

V_DD= 3.0 V; T_amb= 25 C

f_clk(ext)= 1536 Hz

6

A

-

2.7

18

17.5

I_DD(LCD)

LCD supply current

-

30

-

V_DD(LCD)= 3.0 V;

-

T_amb= 25 C

Logic^[3]

V_IL

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

on pins CLK, SYNC, OSC,

A0, A1, T1, SA0, SCL, SDA

V_SS

-

0.3V_DD

V_DD

V

[4][5]

V_IH

I_OL

on pins CLK, SYNC, OSC,

A0, A1, T1, SA0, SCL, SDA

0.7V_DD

output sink current;

V_OL= 0.4 V; V_DD= 5 V

on pins CLK and SYNC

on pin SDA

1

3

1

-

mA

I_OH(CLK)

I_L

HIGH-level output current output source current;

on pin CLK

V_OH= 4.6 V; V_DD= 5 V

leakage current

V_I= V_DDor V_SS

;

1

-

+1

A

on pins CLK, SCL, SDA, A0,

A1, T1, SA0

I_L(OSC)

C_I

leakage current on pin

OSC

V_I= V_DD

1

-

+1

7

A

[6]

[7]

input capacitance

-

pF

LCD outputs

V_O

output voltage variation

on pins BP0 to BP3 and

S0 to S39

100

-

+100

mV

R_O

output resistance

V_LCD= 5 V

on pins BP0 to BP3

on pins S0 to S39

-

1.5

6.0

-

k

[1] LCD outputs are open-circuit; inputs at V_SSor V_DD; external clock with 50 % duty factor; I²C-bus inactive.

[2] For typical values, see Figure 26.

[3] The I²C-bus interface of PCA8576F is 5 V tolerant.

[4] When tested, I²C pins SCL and SDA have no diode to V_DDand may be driven to the V_Ilimiting values given in Table 19 (see Figure 25

as well).

[5] Propagation delay of driver between clock (CLK) and LCD driving signals.

[6] Periodically sampled, not 100 % tested.

[7] Outputs measured one at a time.

PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

34 of 54

PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

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logic 1; no display connected; I²C-bus inactive.

Fig 26. Typical I_DDwith respect to V_DD

PCA8576F

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Product data sheet

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

13. Dynamic characteristics

Table 21. Dynamic characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 8.0 V; T_amb= 40 C to +105 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Clock

f_clk(int)

f_clk(ext)

f_fr

[1]

internal clock frequency

external clock frequency

frame frequency

3505

960

146

40

4800

6240

6720

260

280

-

Hz

s

-

internal clock

external clock

200

-

t_clk(H)

t_clk(L)

HIGH-level clock time

LOW-level clock time

60

-

Synchronization

t_{PD(SYNC_N)}SYNC propagation delay

-

30

-

ns

s

t_{SYNC_NL}

t_PD(drv)

I²C-bus^[3]

Pin SCL

f_SCL

SYNC LOW time

1

-

[2]

driver propagation delay

V_LCD= 5 V

-

30

SCL clock frequency

-

400

-

kHz

t_LOW

LOW period of the SCL

clock

1.3

s

t_HIGH

HIGH period of the SCL

clock

0.6

-

s

Pin SDA

t_SU;DAT

t_HD;DAT

data set-up time

data hold time

100

0

-

ns

Pins SCL and SDA

t_BUF

bus free time between a

1.3

-

s

STOP and START

condition

t_SU;STO

t_HD;STA

t_SU;STA

t_r

set-up time for STOP

condition

0.6

-

s

hold time (repeated)

START condition

set-up time for a repeated

START condition

rise time of both SDA and f_SCL= 400 kHz

SCL signals

-

0.3

1.0

0.3

s

f_SCL< 125 kHz

t_f

fall time of both SDA and

SCL signals

C_b

capacitive load for each

bus line

-

400

50

pF

ns

t_w(spike)

spike pulse width

on the I²C-bus

[1] Typical output duty factor: 50 % measured at the CLK output pin.

[2] Not tested in production.

PCA8576F

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Product data sheet

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V_ILand V_IHwith an

input voltage swing of V_SSto V_DD

.

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PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

37 of 54

PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

14. Application information

14.1 Cascaded operation

In large display configurations, up to 8 PCA8576Fs can be differentiated on the same

I²C-bus by using the 2-bit hardware subaddresses (A0 and A1) and the programmable

I²C-bus slave address (SA0).

Table 22. Addressing cascaded PCA8576F

Cluster

Bit SA0

Pin A1

Pin A0

Device

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

2

1

PCA8576Fs connected in cascade are synchronized to allow the backplane signals from

only one device in the cascade to be shared. This arrangement is cost-effective in large

LCD applications since the backplane outputs of only one device need to be

through-plated to the backplane electrodes of the display. The other PCA8576F of the

cascade contribute additional segment outputs. The backplanes can either be connected

together to enhance the drive capability or some can be left open-circuit (such as the ones

from the slave in Figure 29) or just some of the master and some of the slave will be taken

to facilitate the layout of the display.

All PCA8576Fs connected in cascade are correctly synchronized by the automatically

generated SYNC signal. The only time that SYNC is likely to be needed is if

synchronization is lost accidentally, for example, by noise in adverse electrical

environments, or if the LCD multiplex drive mode is changed in an application using

several cascaded PCA8576Fs, as the drive mode cannot be changed on all of the

cascaded devices simultaneously. SYNC can be either an input or an output signal; a

SYNC output is implemented as an open-drain driver with an internal pull-up resistor.

The PCA8576F asserts SYNC at the start of its last active backplane signal and monitors

the SYNC line at all other times. If cascade synchronization is lost, it is restored by the first

PCA8576F to assert SYNC. The timing relationship between the backplane waveforms

and the SYNC signal for each LCD drive mode is shown in Figure 30.

The contact resistance between the SYNC on each cascaded device must be controlled.

If the resistance is too high, the device is not able to synchronize properly; this is

particularly applicable to chip-on-glass applications. The maximum SYNC contact

resistance allowed for the number of devices in cascade is given in Table 23.

Table 23. SYNC contact resistance

Number of devices

Maximum contact resistance

2

6 k

3 to 5

6 to 8

2.2 k

1.2 k

PCA8576F

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Figure 30 shows the timing of the synchronization signals.

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PCA8576F

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PCA8576F

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Automotive 40 × 4 LCD driver

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Fig 30. Synchronization of the cascade for the various PCA8576F drive modes

PCA8576F

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Automotive 40 × 4 LCD driver

15. Bare die outline

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Fig 31. Bare die outline PCA8576FUG (for dimensions see Table 24)

PCA8576F

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PCA8576F

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Automotive 40 × 4 LCD driver

Table 24. Dimensions of PCA8576FUG

Original dimensions are in mm.

Unit (mm)

max

A

A₁

A₂

b

D

-

E

-

e^[1]

L

-

0.012

0.015

0.018

-

nom

0.40

-

0.381

-

0.052

-

2.2

-

2.0

-

0.077

-

min

0.072

[1] Dimension not drawn to scale.

Table 25. Bump location for PCA8576FUG

All x/y coordinates represent the position of the center of each pad with respect to the center

(x/y = 0) of the chip (see Figure 2, and Figure 31).

Symbol

SDA

SCL

SYNC

CLK

V_DD

OSC

A0

Pad

1

X (m)

34.38

109.53

181.53

365.58

469.08

577.08

740.88

835.83

1005.48

347.22

263.97

180.72

97.47

Y (m)

876.6

630.9

513.9

396.9

221.4

10.71

Description

I²C-bus serial data input/output

I²C-bus serial clock input

2

3

4

cascade synchronization input/output

external clock input/output

supply voltage

5

6

7

internal oscillator enable input

subaddress inputs

8

A1

9

T1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

test pin

SA0

V_SS

V_LCD

BP0

BP2

BP1

BP3

S0

I²C-bus address input; bit 0

ground supply voltage

LCD supply voltage

LCD backplane outputs

156.51

232.74

308.97

385.2

493.2

LCD segment outputs

S1

565.2

S2

637.2

S3

709.2

S4

876.6

S5

876.6

S6

876.6

S7

876.6

S8

14.22

876.6

S9

69.03

152.28

235.53

318.78

402.03

876.6

S10

S11

S12

S13

876.6

PCA8576F

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PCA8576F

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Automotive 40 × 4 LCD driver

Table 25. Bump location for PCA8576FUG …continued

All x/y coordinates represent the position of the center of each pad with respect to the center

(x/y = 0) of the chip (see Figure 2, and Figure 31).

Symbol

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

S35

S36

S37

S38

S39

SDA

Pad

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

X (m)

Y (m)

876.6

Description

485.28

568.53

651.78

735.03

1005.5

735.03

663.03

591.03

519.03

447.03

375.03

196.38

106.38

LCD segment outputs

876.6

625.59

541.62

458.19

374.76

291.33

207.9

124.47

41.04

42.39

125.8

209.3

292.7

376.1

459.5

543

625.6

876.6

I²C-bus serial data input/output

Table 26. Alignment marks

All x/y coordinates represent the position of the center of each alignment mark with respect to the

center (x/y = 0) of the chip (see Figure 2, and Figure 31).

Symbol

Location

X (m)

Dimension

Y (m)

870.3

Diameter (m)

C1

C2

930.42

72

829.98

PCA8576F

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Automotive 40 × 4 LCD driver

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent

standards.

17. Packing information

17.1 Tray information

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PCA8576F

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PCA8576F

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Automotive 40 × 4 LCD driver

Table 27. Description of tray details

Tray details are shown in Figure 32.

Tray details

Dimensions

A

B

C

D

E

F

G

H

J

K

L

M

N

Unit

mm

3.6

2.36

2.11

50.8

45.72 39.6

5.6

39.6

3.96

2.18

2.49

Number of pockets

x direction

12

y direction

12

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PCA8576F

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PCA8576F

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Automotive 40 × 4 LCD driver

19. Abbreviations

Table 29. Abbreviations

Acronym

CDM

CMOS

HBM

ITO

Description

Charged-Device Model

Complementary Metal-Oxide Semiconductor

Human Body Model

Indium Tin Oxide

LCD

Liquid Crystal Display

Least Significant Bit

Machine Model

LSB

MM

MSB

MSL

PCB

RAM

RMS

SCL

Most Significant Bit

Moisture Sensitivity Level

Printed Circuit Board

Random Access Memory

Root Mean Square

Serial CLock line

SDA

SMD

Serial DAta line

Surface Mount Device

20. References

[1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD

drivers

[2] AN10365 — Surface mount reflow soldering description

[3] AN10706 — Handling bare die

[4] AN10853 — ESD and EMC sensitivity of IC

[5] AN11267 — EMC and system level ESD design guidelines for LCD drivers

[6] AN11494 — Cascading NXP LCD segment drivers

[7] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[8] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[9] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices

[10] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[11] JESD78 — IC Latch-Up Test

[12] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[13] UM10204 — I²C-bus specification and user manual

[14] UM10569 — Store and transport requirements

PCA8576F

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PCA8576F

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21. Revision history

Table 30. Revision history

Document ID

PCA8576F v.3

PCA8576F v.2

PCA8576F v.1

Release date

Data sheet status

Product data sheet

Change notice

Supersedes

PCA8576F v.2

PCA8576F v.1

-

20141203

20141010

20131122

-

PCA8576F

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PCA8576F

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22. Legal information

22.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

22.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

22.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

PCA8576F

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

NXP Semiconductors has no control of third party procedures in the sawing,

handling, packing or assembly of the die. Accordingly, NXP Semiconductors

assumes no liability for device functionality or performance of the die or

systems after third party sawing, handling, packing or assembly of the die. It

is the responsibility of the customer to test and qualify their application in

which the die is used.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

All die sales are conditioned upon and subject to the customer entering into a

written die sale agreement with NXP Semiconductors through its legal

department.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Bare die — All die are tested on compliance with their related technical

specifications as stated in this data sheet up to the point of wafer sawing and

are handled in accordance with the NXP Semiconductors storage and

transportation conditions. If there are data sheet limits not guaranteed, these

will be separately indicated in the data sheet. There are no post-packing tests

performed on individual die or wafers.

22.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP Semiconductors N.V.

23. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCA8576F

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

24. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4

Table 5. Definition of PCA8576F commands . . . . . . . . . .5

Table 6. C bit description . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 7. Mode-set command bit description . . . . . . . . . .6

Table 8. Load-data-pointer command bit description . . . .6

Table 9. Device-select command bit description . . . . . . .6

Table 10. Bank-select command bit description . . . . . . . .7

Table 11. Blink-select command bit description . . . . . . . . .7

Table 12. Blinking frequencies . . . . . . . . . . . . . . . . . . . . . .8

Table 13. Standard RAM filling in 1:3 multiplex drive

mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 14. Entire RAM filling by rewriting in 1:3 multiplex

drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 15. Selection of possible display configurations . . .17

Table 16. Biasing characteristics . . . . . . . . . . . . . . . . . . .18

Table 17. Mapping of output pins and corresponding

output signals with respect to the multiplex

driving mode . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 18. I²C slave address byte . . . . . . . . . . . . . . . . . . .29

Table 19. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 20. Static characteristics . . . . . . . . . . . . . . . . . . . .34

Table 21. Dynamic characteristics . . . . . . . . . . . . . . . . . .36

Table 22. Addressing cascaded PCA8576F . . . . . . . . . .38

Table 23. SYNC contact resistance . . . . . . . . . . . . . . . . .38

Table 24. Dimensions of PCA8576FUG. . . . . . . . . . . . . .42

Table 25. Bump location for PCA8576FUG . . . . . . . . . . .42

Table 26. Alignment marks. . . . . . . . . . . . . . . . . . . . . . . .43

Table 27. Description of tray details . . . . . . . . . . . . . . . . .45

Table 28. Selection of LCD segment drivers . . . . . . . . . .46

Table 29. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 30. Revision history . . . . . . . . . . . . . . . . . . . . . . . .49

PCA8576F

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Product data sheet

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PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

25. Figures

Fig 1. Block diagram of PCA8576F . . . . . . . . . . . . . . . . .2

Fig 2. Pinning diagram for PCA8576FUG (bare die) . . . .3

Fig 3. Format of command byte. . . . . . . . . . . . . . . . . . . .5

Fig 4. Display RAM bit map . . . . . . . . . . . . . . . . . . . . . . .9

Fig 5. Relationship between LCD layout, drive mode,

display RAM filling order and display data

transmitted over the I²C-bus . . . . . . . . . . . . . . . .10

Fig 6. Display RAM filling order in static drive mode . . .11

Fig 7. Display RAM filling order in 1:2 multiplex drive

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Fig 8. Display RAM filling order in 1:4 multiplex drive

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Fig 9. RAM banks in static and multiplex driving

mode 1:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Fig 10. Bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Fig 11. Example of the Bank-select command with

multiplex drive mode 1:2 . . . . . . . . . . . . . . . . . . .15

Fig 12. Example of displays suitable for PCA8576F . . . .17

Fig 13. Typical system configuration . . . . . . . . . . . . . . . .17

Fig 14. Electro-optical characteristic: relative

transmission curve of the liquid . . . . . . . . . . . . . .20

Fig 15. Static drive mode waveforms. . . . . . . . . . . . . . . .21

Fig 16. Waveforms for the 1:2 multiplex drive mode

with ¹⁄₂bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Fig 17. Waveforms for the 1:2 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 18. Waveforms for the 1:3 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Fig 19. Waveforms for the 1:4 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Fig 20. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Fig 21. Definition of START and STOP conditions. . . . . .27

Fig 22. System configuration . . . . . . . . . . . . . . . . . . . . . .28

Fig 23. Acknowledgement of the I²C-bus . . . . . . . . . . . .28

Fig 24. I²C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . . . .30

Fig 25. Device protection circuits. . . . . . . . . . . . . . . . . . .31

Fig 26. Typical I_DDwith respect to V_DD. . . . . . . . . . . . . .35

Fig 27. Driver timing waveforms . . . . . . . . . . . . . . . . . . .37

Fig 28. I²C-bus timing waveforms . . . . . . . . . . . . . . . . . .37

Fig 29. Cascaded PCA8576F configuration . . . . . . . . . .39

Fig 30. Synchronization of the cascade for the various

PCA8576F drive modes. . . . . . . . . . . . . . . . . . . .40

Fig 31. Bare die outline PCA8576FUG (for dimensions

see Table 24) . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Fig 32. Tray details . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Fig 33. Tray alignment . . . . . . . . . . . . . . . . . . . . . . . . . . .45

PCA8576F

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 3 December 2014

53 of 54

PCA8576F

NXP Semiconductors

Automotive 40 × 4 LCD driver

26. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

8

Characteristics of the I²C-bus . . . . . . . . . . . . 27

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

START and STOP conditions. . . . . . . . . . . . . 27

System configuration . . . . . . . . . . . . . . . . . . . 27

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 28

I²C-bus controller . . . . . . . . . . . . . . . . . . . . . . 29

Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 29

8.1

8.2

8.3

8.4

8.5

8.6

8.7

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3

3.1

4

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

9

Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 31

Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 33

Static characteristics . . . . . . . . . . . . . . . . . . . 34

Dynamic characteristics. . . . . . . . . . . . . . . . . 36

Application information . . . . . . . . . . . . . . . . . 38

Cascaded operation. . . . . . . . . . . . . . . . . . . . 38

Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 41

Handling information . . . . . . . . . . . . . . . . . . . 44

Packing information . . . . . . . . . . . . . . . . . . . . 44

Tray information . . . . . . . . . . . . . . . . . . . . . . . 44

Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

LCD segment driver selection . . . . . . . . . . . . 46

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 48

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Revision history . . . . . . . . . . . . . . . . . . . . . . . 49

10

7

7.1

Functional description . . . . . . . . . . . . . . . . . . . 5

Commands of PCA8576F. . . . . . . . . . . . . . . . . 5

Command: mode-set . . . . . . . . . . . . . . . . . . . . 6

Command: load-data-pointer . . . . . . . . . . . . . . 6

Command: device-select . . . . . . . . . . . . . . . . . 6

Command: bank-select. . . . . . . . . . . . . . . . . . . 7

Command: blink-select. . . . . . . . . . . . . . . . . . . 7

Clock and frame frequency. . . . . . . . . . . . . . . . 7

Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . 7

External clock . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Timing and frame frequency. . . . . . . . . . . . . . . 8

Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . 9

RAM filling in static drive mode. . . . . . . . . . . . 11

RAM filling in 1:2 multiplex drive mode. . . . . . 11

RAM filling in 1:3 multiplex drive mode. . . . . . 12

RAM filling in 1:4 multiplex drive mode. . . . . . 13

Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Subaddress counter . . . . . . . . . . . . . . . . . . . . 13

Writing over the RAM address boundary . . . . 14

Bank selection . . . . . . . . . . . . . . . . . . . . . . . . 14

RAM bank switching. . . . . . . . . . . . . . . . . . . . 14

Output bank selector . . . . . . . . . . . . . . . . . . . 15

Input bank selector . . . . . . . . . . . . . . . . . . . . . 16

Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Possible display configurations . . . . . . . . . . . 16

LCD voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 18

LCD bias generator . . . . . . . . . . . . . . . . . . . . 18

LCD voltage selector . . . . . . . . . . . . . . . . . . . 18

Electro-optical performance . . . . . . . . . . . . . . 19

LCD drive mode waveforms . . . . . . . . . . . . . . 21

Static drive mode . . . . . . . . . . . . . . . . . . . . . . 21

1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 22

1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 24

1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 25

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 26

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 26

11

12

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.2

7.2.1

7.2.2

7.2.3

7.2.4

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.3.6

7.3.7

7.3.8

7.3.8.1

7.3.8.2

7.3.8.3

7.4

13

14

14.1

15

16

17

17.1

18

18.1

19

20

21

22

Legal information . . . . . . . . . . . . . . . . . . . . . . 50

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 50

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 51

22.1

22.2

22.3

22.4

23

24

25

26

Contact information . . . . . . . . . . . . . . . . . . . . 51

Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.5

7.6

7.6.1

7.6.2

7.6.2.1

7.6.3

7.6.3.1

7.6.3.2

7.6.3.3

7.6.3.4

7.6.4

7.6.5

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 3 December 2014

Document identifier: PCA8576F


型号：	PCA8576FUG/2DA/Q1
厂家：	NXP
描述：	Automotive 40 Ã 4 LCD driver CD
文件：	总54页 (文件大小：428K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCA8576FUG/2DA/Q1 [NXP]

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