PCA9450B_技术文档

PCA9450

Power management IC for i.MX 8M application processor

family

Rev. 1.0 — 19 November 2019

Product data sheet

1 General description

The PCA9450 is a single chip Power Management IC (PMIC) specifically designed to

support i.MX 8M family processor in both 1 cell Li-Ion and Li-polymer battery portable

application and 5 V adapter non-portable applications. It supports various memory types

(DDR4/LPDDR4/DDR3L, etc.) via system UBOOT configuration, which does not require

hardware change.

The device provides six high efficiency step-down regulators, five LDOs, one 400 mA

load switch, 2-channel level translator and 32.768 kHz crystal oscillator driver.

Three buck regulators support Dynamic Voltage Scaling (DVS) feature along with

programmable ramping up and down time and those buck regulators support remote

sense to compensate IR drop to load from buck regulator. This device is characterized

across -40 °C to 105 °C ambient temperature range.

Six step-down regulators are designed to provide power for i.MX 8M application

processor and DRAM memory. Two LDOs, LDO1 and LDO2, feature very low quiescent

current to provide power for Secure Non-Volatile Storage (SNVS) since these LDOs are

always ON when input voltage is valid.

PCA9450 integrates logic translator which is a 2-bit, dual supply translating transceiver

with auto direction sensing. It enables bidirectional voltage level translation. It can be

used as I²C level translator. 400 mA load switch is to supply 3.3 V power supply to SD

card, which has internal discharge resistor.

PCA9450 has three versions: PCA9450A is companion PMIC for (i.MX 8M Mini),

PCA9450B is companion PMIC for i.MX 8M Nano and PCA9450C is companion PMIC

for i.MX 8M Plus.

The PCA9450 is offered in 56-pin HVQFN package, 7 mm x 7 mm, 0.4 mm pitch.

2 Features and benefits

• Six high-efficiency step-down regulators

– Three 3 A buck regulators with DVS feature and remote sense

– PCA9450A – Three 3 A buck regulators

– PCA9450B – Two 3 A buck regulators

– PCA9450C – 6 A dual-phase buck regulator and 3 A buck regulator

• One 3 A buck regulator

• Two 2 A buck regulators

• Five linear regulators

– Two 10 mA LDOs

– One 150 mA LDO

– One 200 mA LDO

– One 300 mA LDO

NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

• Support various memory types: DDR4/LPDDR4/DDR3L via system UBOOT

configuration, no hardware change required

• 400 mA load switch with built-in active discharge resistor

• 32.768 kHz crystal oscillator driver and buffer output

• Two channel logic level translator

• Power control IO

– Power ON/OFF control

– Standby/run mode control

• Fm+ 1 MHz I²C-bus interface

• ESD protection

– Human Body Model (HBM) : +/- 2000 V

– Charged Device Model (CDM) : +/-500 V

• 7 mm x 7 mm, 56 pin HVQFN with 0.4 mm pitch

3 Applications

• IoT Devices

• Tablet

• Electronic Point of Sale (ePOS)

• Industrial application

4 Ordering information

Table 1.ꢀOrdering information

Topside

AP platform

Package

Name

Type number

marking

Description

Version

PCA9450AHN

PCA9450A

i.MX 8M Mini

HVQFN56

thermal enhanced very thin quad flat

package; no leads; 56 terminals; 0.4 mm

pitch, 7 mm x 7 mm x 0.85 mm body

SOT949-6

PCA9450BHN

PCA9450CHN

PCA9450B

PCA9450C

i.MX 8M Nano

i.MX 8M Plus

HVQFN56

thermal enhanced very thin quad flat

package; no leads; 56 terminals; 0.4 mm

pitch, 7 mm x 7 mm x 0.85 mm body

SOT949-6

thermal enhanced very thin quad flat

package; no leads; 56 terminals; 0.4 mm

pitch, 7 mm x 7 mm x 0.85 mm body

Table 2.ꢀOrdering options

Type number

Orderable part

number

Package

Packing method Minimum order Temperature range

quantity

PCA9450AHN

PCA9450BHN

PCA9450CHN

PCA9450AHNY

PCA9450BHNY

PCA9450CHNY

HVQFN56

REEL 13" Q1 DP 2000

-40 °C to +105 °C

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

5 Block diagram

VSYS

SYS

PCA9450

INB26

DVS

VSYS

0.47 µH

22 µF

1 µF

SBIAS, REF,

UVLO,

TSHDN

10 µF

LX2

VINT

1 µF

INT LDO

VDD_ARM

BUCK2

0.85 V

3 A

LDO1

PGND

PMIC_RST_B

PMIC_ON_REQ

PMIC_STBY_REQ

WDOG_B

R_SNSP2

INB13

10 µF

VSYS

0.47 µH

22 µF

LX1

VDD_SOC

LDO1

NVCC_SNVS

LDO1

BUCK1

0.85 V

3 A

100 kΩ

RTC_RESET_B

R_SNSP1

INB13

DUAL

PHASE

CONFIG

IN

POR_B

NVCC_1V8

BUCK5

VSYS

PCA9450C

10 µF

LX3

VDD_V/GPU

VDD_DRAM

4.7 kΩ

100 kΩ

SCL

0.47 µH

22 µF

l2C

INTERFACE

BUCK3

0.85 V

3 A

SDA

IRQ_B

R_SNSP3_CFG

INB45

NVCC_1V8

BUCK5

VINT

SWIN

4.7 kΩ

VSYS

SCLL

SDAL

10 µF

LX4

l2C LEVEL

TRANSLATOR

0.47 µH

NVCC_3V3

ON/OFF

CONTROL

AND

BUCK4

3.3 V

3 A

3V3 V

22 µF

BUCK4

4.7 kΩ

I2C

REGISTER

SDAH

SCLH

BUCK4FB

INB45

XTAL_IN

32.768 kHz

X-TAL DRIVER

VSYS

X-tal

XTAL_OUT

4.7 µF

LX5

0.47 µH

NVCC_1V8

22 µF

LDO1

BUCK5

1.8 V

2 A

CLK_32K_OUT

INL1

MUX

SYS

4.7 µF

LDO1

BUCK5FB

INB26

LDO1

1.8 V

10 mA

NVCC_SNVS

VDD_SNVS

VDDA_1V8

1 µF

VSYS

4.7 µF

LX6

LDO2

0.85 V

10 mA

0.47 µH

LDO2

NVCC_DRAM

22 µF

BUCK6

1.1 V

2 A

1 µF

LDO3

1.8 V

300 mA

LDO3

BUCK6FB

SWIN

22 µF

LDO4

0.9 V

200 mA

BUCK 4

VDD_PHY_0V9

NVCC_SD2

LDO4

1 µF

LOAD SW

DRIVER

1 µF

SWOUT

SW_EN

SD_CARD

1 µF

LDO5

3.3 V/1.8 V

150 mA

LDO5

1 µF

SD_VSEL

AGND

EP

aaa-035069

Figure 1.ꢀBlock diagram

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

6 Pinning information

6.1 Pinning

PCA9450

LDO4

LDO2

1

2

42

41

40

39

38

37

36

35

34

33

32

31

30

29

SDA

SCL

3

LDO1

PMIC_STBY_REQ

PMIC_ON_REQ

R_SNSP1

LX1

4

VINT

5

AGND

6

RTC_RESET_B

CLK_32K_OUT

PMIC_RST_B

POR_B

7

LX1

EP

8

INB13

9

INB13

10

11

12

13

14

XTAL_IN

XTAL_OUT

SW_EN

INB13

LX3

R_SNSP3_CFG

SD_VSEL

IRQ_B

BUCK5FB

aaa-035701

Figure 2.ꢀPCA9450 pin map – Top View

6.2 Pin description

Table 3.ꢀPin description

Pin description

Symbol

LDO4

LDO2

LDO1

1

Type

Description

P

LDO4 output. Bypass with a 1 µF to Ground.

LDO2 output. Bypass with a 1 µF to Ground.

LDO1 output. Bypass with a 1 µF to Ground.

2

3

Internal Power supply output pin. Bypass with 1 µF to

Ground.

VINT

4

5

P

Analog ground pin. It should be connected to ground

plane through Via. Do not short to EP directly on top

layer

AGND

GND

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

Pin description

Symbol

6

Type

DO

DI

Description

Reset output pin. It is High-Z after both LDO1 and

LDO2 voltage are good. It is internally pulled up with

LDO1 power rail

RTC_RESET_B

CLK_32K_OUT

PMIC_RST_B

7

32.768 kHz clock CMOS output with LDO1 power rail.

PMIC reset input pin. It is internally pulled up with

LDO1 power rail. Once it is asserted low, PMIC

performs reset.

8

Power On reset output pin. Open drain output requiring

external pull up resistor.

POR_B

XTAL_IN

XTAL_OUT

SW_EN

IRQ_B

BUCK5FB

LX5

9

DO

AI

32.768 kHz crystal oscillator input, tie to GND if X-tal is

not used

10

11

12

13

14

15

32.768 kHz crystal oscillator output, leave floating if X-

tal is not used

AO

DI

Load switch enable input pin. It has internal 1.5 MΩ pull

down resistor.

Open drain output to indicate Interrupt issued. It

requires external pull up resistor.

DO

AI

BUCK5 output voltage sensing pin. If BUCK5 is not

used, tie to INB45.

BUCK5 switching node. If BUCK5 is not used, leave it

floating.

P

BUCK4 / BUCK5 Input pins. Bypass with 10 µF and

4.7 μF to Ground

INB45

16,17,18 P

BUCK4 switching node. If BUCK4 is not used, leave

them floating.

LX4

19,20

21

P

BUCK4 output voltage sensing pin. If BUCK4 is not

used, tie to INB45.

BUCK4FB

SWIN

AI

Load switch input pin, Bypass with a 1 µF to Ground.

Leave it floating if not used.

22

P

Load switch output pin, Bypass with a 1 µF to Ground.

Leave it floating if not used.

SWOUT

SDAH

23

P

Level translator high voltage IO pin, SDA referenced to

SWIN, 3.3 V

24

DIO

DO

DIO

DO

DI

Level translator high voltage IO pin, SCL referenced to

SWIN, 3.3 V

SCLH

25

Level translator low voltage IO pin, SDA referenced to

VINT, 1.8 V

SDAL

26

Level translator low voltage IO pin, SCL referenced to

VINT, 1.8 V

SCLL

27

Active low watchdog reset input pin from application

processor.

WDOG_B

28

LDO5 voltage selection input pin. LDO5 output is 3.3 V

when it is driven low and 1.8 V when driven high. VSEL

pin should be tied low or high. Do not leave it floating.

SD_VSEL

29

DI

PCA9450

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PCA9450

Power management IC for i.MX 8M application processor family

Pin description

Symbol

Type

Description

BUCK3 output voltage remote sense pin in PCA9450A.

Logic input pin in PCA9450B/C. This pin should be tied

to SYS in PCA9450B, where BUCK3 is disabled. This

pin is tied to GND in PCA9450C, where BUCK1 and

BUCK3 are configured as dual phase buck regulator.

R_SNSP3_CFG

30

AI

BUCK3 switching node

LX3

31,32

P

If BUCK3 is not used by shorting R_SNSP3_CFG to

VSYS, leave LX3 pins floating.

BUCK1 / BUCK3 Input. Bypass with two 10 µF to

Ground

INB13

LX1

33,34,35 P

36,37

38

P

BUCK1 switching node. Leave it floating if not used.

BUCK1 output voltage remote sensing pin. Tie to

INB13 if not used.

R_SNSP1

AI

PMIC ON input from Application processor. When it is

asserted high, the device starts power on sequence.

PMIC_ON_REQ

39

DI

Standby mode input from Application processor. When

it is asserted high, device enters STANDBY mode.

PMIC_STBY_REQ 40

SCL

SDA

41

42

DI

I2C serial clock pin

I2C serial data pin

DIO

Buck reference GND for BUCK1,2,3. It should be

connected to ground plane through Via. Do not short to

EP directly on top layer

BUCK_AGND

43

GND

BUCK2 output voltage remote sensing pin. Tie to

INB26 if not used.

R_SNSP2

LX2

44

AI

P

BUCK2 switching node. Leave them floating if not

used.

45,46

BUCK2 / BUCK6 Input. Bypass with 10 µF and 4.7 µF

to Ground

INB26

LX6

47,48,49 P

50,51

52

P

BUCK6 switching node. Leave it floating if not used.

BUCK6 output voltage sensing pin. Tie to INB26 if not

used.

BUCK6FB

AI

VSYS

LDO3

LDO5

53

54

55

P

Internal power input. Bypass with a 1 µF to Ground

LDO3 output. Bypass with a 2.2 µF to Ground.

LDO5 output. Bypass with a 1 µF to Ground.

Power input pin for LDO1, LDO2, LDO3, LDO4 and

LDO5. Bypass with a 4.7 µF to Ground.

INL1

EP

56

P

Exposed PAD. All buck PGNDs are internally

connected.

GND

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

7 Functional description

7.1 Features

The PCA9450 is a power management integrated circuit (PMIC) designed to be the

primary power management for NXP application processors, i.MX 8M Mini, Nano and

Plus.

• Buck regulators

– BUCK1, BUCK2, BUCK3 : 0.6 V to 2.1875 V, 12.5 mV step, 3000 mA

– BUCK4 : 0.6 V to 3.4 V, 25 mV step, 3000 mA

– BUCK5, BUCK6 : 0.6 V to 3.4 V, 25 mV step, 2000 mA

– Dynamic Voltage scaling on BUCK1, BUCK2 and BUCK3

– Support remote sensing on BUCK1, BUCK2 and BUCK3

– BUCK1-BUCK3 configurable as a 6 A dual phase regulator (PCA9450C)

– Monitor fault condition

• LDO regulators

– LDO1, 1.6 V to 1.9 V, 3.0 V to 3.3 V 100 mV step, 10 mA

– LDO2, 0.8 V to 1.15 V with 50 mV step,10 mA

– LDO3, 0.8 V to 3.3 V with 100 mV step, 300 mA

– LDO4, 0.8 V to 3.3 V with 100 mV step, 200 mA

– LDO5, 0.8 V to 3.3 V with 100 mV step, 150 mA, Voltage selection through SD_VSEL

– Monitor fault condition

• Support various memory types: DDR4/LPDDR4/DDR3L via system UBOOT

configuration, no hardware change required

• 400 mA Load switch for SD card

– Built-in OCP protection

– GPIO/I2C control

– Built-in Active discharge resistor

• Two Channel logic level translator

• 32.768 kHz Crystal Oscillator driver

– Mux output with internal 32 kHz output

• Protection and Monitoring: Soft start, Power Rails Fault detection, UVLO, Thermal

Shutdown

• Configurable reset behavior from WDOGB, PMIC_RST_B and SW_RST Register

• Power control IO

– PMIC_ON_REQ, PMIC_STBY_REQ

• Fm+ 1 MHz I²C-bus interface

• Type3 PCB applicable

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

7.2 Functional diagram

PCA9450 Functional Internal Block diagram

32 kHz buffer

Regulators

32 kHz Osc driver / Buffer

Linear Regulator

Switching Regulator

Bias / Timing

Internal Bias

BUCK1

(0.6 V to 2.1875 V,

12.5 mV Step)

3000 mA, 0.85 V

DVS

LDO1

(1.6 V-1.9 V, 3.0 V-3.3 V,

100 mV Step)

10 mA

Power on sequence / Timing

LDO2

(0.85 V to 1.15 V,

50 mV Step)

10 mA

BUCK2

(0.6 V to 2.1875 V,

12.5 mV Step)

3000 mA, 0.85 V

DVS

Logic Control

AP logic control

LDO3

BUCK3

(0.6 V to 2.1875 V,

12.5 mV Step)

3000 mA, 0.85 V

DVS

2

I C communication

(0.8 V to 3.3 V,

100 mV Step)

300 mA

I²C Level Translator

LDO4

2

I C Level Translator

BUCK4

(0.6 V to 3.4 V,

25 mV Step)

(0.8 V to 3.3 V,

100 mV Step)

200 mA

Protection

3000 mA, 3.3 V

LDO5

(1.8 V to 3.3 V,

100 mV Step)

150 mA

Thermal Warning / Protection

BUCK5

(0.6 V to 3.4 V,

25 mV Step)

UVLO

Current limit

2000 mA, 1.8 V

BUCK6

(0.6 V to 3.4 V,

25 mV Step)

2000 mA, 1.1 V

Load Switch

400 mA load switch

aaa-035702

Figure 3.ꢀPCA9450 functional block diagram

The PCA9450 is a single chip Power Management IC (PMIC) specifically designed to

support i.MX 8M family processor in both 1 cell Li-Ion and Li-polymer battery portable

application and 5 V adapter non-portable applications.

PCA9450 is provided in three versions: PCA9450A, PCA9450B and PCA9450C

depending on target application processor. Table 4 shows the selection guide.

Table 4.ꢀPCA9450 selection guide

Part number AP Platform

BUCK1

BUCK3

LDO4

R_SNSP3_CFG

3 A for VPU/GPU/

DRAM

3 A for SOC

0.9 V for VDDA

(ON by default)

R_SNSP3_CFG is feedback

of BUCK 3

PCA9450A

PCA9450B

i.MX 8M Mini

i.MX 8M Nano

i.MX 8M Plus

(ON by default)

3 A for SOC /

VPU/GPU/DRAM

Disabled

OFF by default

R_SNSP3_CFG = VSYS

R_SNSP3_CFG = GND

(ON by default)

6 A Dual phase for SOC/VPU/GPU/

DRAM

PCA9450C

(ON by default)

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

7.3 Power modes

PCA9450 has eight power modes: OFF, READY, SNVS, RUN, STADNBY, PWRDN,

PWRUP and FAULT_SD. Figure 4 shows the state transition diagram showing the

conditions to enter and exit each state.

VSYS_POR = 1

Any

State

OFF

VSYS_UVLO = 1

VSYS_POR = 0

VSYS_POR = 1

VSYS_UVLO = 1

THSD = 0 or LDO1/2 FLT Clear

Ready

VSYS_UVLO = 0

VR_FLT Clear

SNVS

PMIC_ON_REQ = H

VR_FLT

PWRDN Seq

PWRUP Seq

FAULT_SD

PMIC_ON_REQ = L

Or Cold Reset

Run

PMIC_STBY_REQ = H

PMIC_STBY_REQ = L

VR_FLT

STANDBY

PMIC_ON_REQ = L

Or Cold reset

aaa-035703

Figure 4.ꢀPower States Diagram

7.3.1 Off mode

PCA9450 enters OFF mode from any state when VSYS falls below V_{SYS_POR}threshold.

All regulators are off and all registers get reset in this mode.

7.3.2 READY mode

PCA9450 enters READY mode from OFF mode when VSYS is higher than V_{SYS_POR}

.

Internal LDO VINT is enabled and loads Multiple Time Program (MTP) data to registers.

Once MTP loading is done, it is ready to transition to SNVS mode.

7.3.3 SNVS mode

PCA9450 enters Secure Non-Volatile Storage mode (SNVS) when VSYS exceeds

V_{SYS_UVLO}threshold. LDO1 and LDO2 are powered up and 32.768 kHz buffer starts

running. RTC_RESET_B is pulled high in t_{RTC_RST}after both LDO1 and LDO2 voltage

come up.

PMIC_ON_REQ input is masked until RTC_RESET_B is released. PCA9450 starts

power up sequence if PMIC_ON_REQ is asserted high in this mode.

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

UVLO

POR

VSYS

VINT

t

SNVS_PU

LDO1 NVCC_SNVS

t

STEP

LDO2 VDD_SNVS

Int RC Osc

X-tal Osc

t

RTC_RST

RTC_RESET_B

CLK_32K_OUT

t

RTC_Tran

t

32K_EN

Mode

OFF

Ready

SNVS

OFF

aaa-035704

Figure 5.ꢀSNVS mode ON/OFF sequence

Table 5.ꢀSNVS mode

Time

Description

Value

t_{SNVS_PU}

t_STEP

Time to LDO1 turn on from VSYS UVLO detected

Time to LDO2 ON from LDO1 POK

20 ms

2 ms

t_{RTC_RST}

T_{32K_EN}

t_{RTC_Tran}

Time to RTC_RESET_B release from LDO2 POK

Time to 32k buffer Enable from LDO2 POK

20 ms

10 ms

1 sec

Time to transition to Xtal output from RC osc after

RTC_RESET_B release

7.3.4 PWRUP mode

After RTC_RESET_B is released in SNVS mode, it starts power up with pre-defined

sequence when PMIC_ON_REQ is asserted high for longer than debounce time,

t_{ON_DEB}, which is programmable in PWR_CTRL reg. BUCK1 begins turning ON at first

and then each power rail is followed with t_stepafter POK of predecessor power rail.

During PWRUP mode, PMIC_STBY_REQ signal is masked until POR_B is released. The

PWRUP mode ends up releasing POR_B and PCA9450 is transitioned to RUN mode.

Figure 6 shows Power on sequence of PCA9450A.

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

Masked

PMIC_STBY_REQ

PMIC_ON_REQ

t

OFF_DEB

t

ON_DEB

POK

step

BUCK1

BUCK3

VDD_SOC

t

OFF_Step

VDD_DRAM

VDD_G/VPU

t

POK

t

OFF_Step

t

step

POK

step

PHY_0P9

LDO4

t

OFF_Step

t

VDD_ARM

BUCK2

POK

t

OFF_Step

VDDA_1P8

VDDA_DRAM

t

step

POK

step

LDO3

t

OFF_Step

t

POK

BUCK5

NVCC_1V8

t

OFF_Step

t

step

POK

step

BUCK6

BUCK4

NVCC_DRAM

NVCC_3V3

t

OFF_Step

t

POK

t

OFF_Step

t

step

POK

LDO5

NVCC_SD2

t

OFF_Step

t

POR_B

Mode

SNVS

PWRUP

RUN

PWRDN

SNVS

aaa-035706

LDO4/BUCK3 is MTP programmable to be selected in power up/down sequence.

Figure 6.ꢀPCA9450A power ON/OFF sequence

BUCK3 and LDO4 are OFF by default in PCA9450B and PCA9450C. Those regulators

are removed in the power up sequence, shown in Figure 7.

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

Masked

PMIC_STBY_REQ

t

OFF_DEB

PMIC_ON_REQ

VDD_SOC

t

ON_DEB

POK

BUCK1

BUCK2

LDO3

VDD_DRAM

VDD_G/VPU

t

OFF_Step

t

step

VDD_ARM

POK

step

t

OFF_Step

t

VDDA_1P8

VDDA_DRAM

POK

t

OFF_Step

t

step

POK

step

BUCK5

NVCC_1V8

NVCC_DRAM

NVCC_3V3

t

OFF_Step

t

POK

BUCK6

BUCK4

t

OFF_Step

t

step

POK

step

t

OFF_Step

t

POK

LDO5

NVCC_SD2

POR_B

t

OFF_Step

t

POR_B

SNVS

PWRUP

PWRDN

SNVS

Mode

RUN

aaa-035707

LDO4/BUCK3 is MTP programmable to be selected in power up/down sequence.

Figure 7.ꢀPCA9450B/C power ON/OFF sequence

Table 6.ꢀPWRUP mode

Time

Description

Value

20 ms

2 ms

t_{ON_DEB}

t_STEP

Time to power-on start from PMIC_ON_REQ high

Time to next power rail ON from prev rail POK

Time to POR_B release from the last rail POK

Time to next power rail off from prev rail off

Time to POR_B low from PMIC_ON_REQ falling

t_PORB

20 ms

8 ms

t_{OFF_STEP}

t_{OFF_DEB}

120 μs

If any of regulators doesn’t generate POK within t_{FLT_SH_PU}after receiving digital enable

during PWRUP mode, it is transitioned to Fault_SD mode.

7.3.5 PWRDN mode

When PMIC_ON_REQ is low for t_{OFF_DEB}in RUN or STANDBY mode, PCA9450 enters

PWRDN mode. It starts with pulling down POR_B and then turning off each power rail in

t_{OFF_STEP}and transitions to SNVS mode.

7.3.6 RUN mode

PCA9450 operates in RUN mode when PMIC_ON_REQ is driven high and

PMIC_STBY_REQ is driven low. BUCK1, BUCK2 and BUCK3 output voltage are set

to BUCK1OUT_DVS0, BUCK2OUT_DVS0 and BUCK3OUT_DVS0 register value,

respectively, when PRESET_EN bit in DVS123_DVS register is set to “0”. When

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PMIC_STBY_REQ is asserted high in this mode, it is transitioned to STANDBY mode.

PMIC_ON_REQ is asserted low, it moves to PWRDN mode.

7.3.7 STANDBY mode

PCA9450 is transitioned to STANDBY mode from RUN mode when both

PMIC_ON_REQ and PMIC_STBY_REQ are driven high. BUCK1 and BUCK2 output

voltage is set to BUCK1OUT_DVS1 and BUCK2OUT_DVS1 and BUCK3 are turned off

when DVS_CTRL bit in each BUCKx_CTRL register is configured to 1.

If PMIC_ON_REQ is asserted low, then it transitions to PWRDN mode. If

PMIC_STBY_REQ is driven low, then it transitions to RUN mode.

PMIC_STBY_REQ

PMIC_ON_REQ

t

OFF_DEB

DVS0

DVS1

BUCK1

VDD_SOC

t

OFF_Step

VDD_DRAM

VDD_G/VPU

BUCK3

t

OFF_Step

LDO4

BUCK2

LDO3

PHY_0P9

t

OFF_Step

DVS0

t

OFF_Step

VDD_ARM

DVS1 = OFF

VDDA_1P8

t

VDDA_DRAM

OFF_Step

BUCK5

NVCC_1V8

t

OFF_Step

BUCK6 NVCC_DRAM

t

OFF_Step

NVCC_3V3

NVCC_SD2

BUCK4

LDO5

t

OFF_Step

t

OFF_Step

POR_B

Mode

RUN

STANDBY

RUN

STANDBY

PWRDN

SNVS

aaa-035708

Figure 8.ꢀPCA9450A mode transition

Table 7.ꢀPower modes summary

X : Don’t care

Power mode

OFF

VSYS

PMIC_ON_REQ

PMIC_STBY_REQ

VSYS < V_{SYS_POR}

VSYS > V_{SYS_POR}

X

READY

SNVS

X

VSYS > V_{SYS_UVLO}Low

VSYS > V_{SYS_UVLO}High

X

STANDBY

High

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Power mode

VSYS

PMIC_ON_REQ

PMIC_STBY_REQ

RUN

VSYS > V_{SYS_UVLO}High

Low

7.3.8 FAULT_SD

PCA9450 has three types of fault sources.

1. Thermal shutdown : Transition to SNVS mode or READY mode after FAULT_SD

mode.

When junction temperature reaches T_JSHDN, it enters FAULT_SD mode after t_{FLT_THSD}

where regulators are turned off simultaneously. It stays at FAULT_SD until junction

temperature falls below T_JSHDN. If the temperature drops below T_JSHDN, then it moves

to READY state if any of LDO1 and LDO2 fault is triggered when thermal shutdown

happens, and it moves to SNVS mode if neither LDO1 or LDO2 fault is triggered when

thermal shutdown happens.

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Tj < T

JSHDN

Thermal

Shutdown

Event

t

FLT_THSD

VSYS

NOTE1

LDO1

LDO2

NVCC_SNVS

VDD_SNVS

Int RC Osc

X-tal Osc

NOTE1

RTC_RESET_B

CLK_32K_OUT

BUCK1

BUCK3

VDD_SOC

VDD_DRAM

VDD_G/VPU

PHY_0P9

LDO4

VDD_ARM

BUCK2

VDDA_1P8

VDDA_DRAM

LDO3

BUCK5

BUCK6

NVCC_1V8

NVCC_DRAM

NVCC_3V3

NVCC_SD2

POR_B

BUCK4

LDO5

Mode

Any state

FAULT_SD

SNVS

aaa-035710

Note 1 : If LDO1/LDO2 triggers fault condition when junction temperature reaches thermal shutdown

threshold, LDO1/LDO2/RTC_RESETB/CLK_32K_OUT is turned off. Otherwise, they are kept on.

Figure 9.ꢀPCA9450 FAULT_SD from Thermal shutdown

Table 8.ꢀt_{FLT_THSD}

Time

Description

Value

t_{FLT_THSD}

Time to reset released from Fault event

120 μs

2. Voltage regulator fault during power up: Transition to READY mode after

FAULT_SD mode.

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Any POK of voltage regulators doesn’t come up within t_{FLT_SD_PU}after regulator is

enabled during power up sequence. It stops power-up sequence and then moves to

FAULT_SD where all regulators are turned off. It stays at FAULT_SD for t_{FLT_SD_STAY}

and transitions to READY state.

3. Voltage regulator fault in STANDBY and RUN MODE: Move to FAULT_SD mode in

t_{FLT_SD_WAIT}after Fault is detected. Transition to SNVS mode or READY mode from

FAULT_SD mode when fault is removed.

During RUN and STANDBY mode, VR Fault status bit in VRFLT1_STS and

VRFLT2_STS registers is latched to “1” when corresponding regulator voltage falls

below POK threshold for t_{DEB_POKB}, or POK doesn’t go high within t_{FLT_POK_MSK}after

regulator is enabled.

If the fault status bit is masked in VRFLT1_MASK and VRFLT2_MASK registers,

it doesn’t enter FAULT_SD mode. Instead, PCA9450 stays at current mode. If the

fault register bit is unmasked, it starts t_{FLT_SD_WAIT}timer. Application processor can

determine to enter FAULT_SD mode or not, by masking the VR Fault status bit in

VRFLTx_MASK registers before the timer expires. PCA9450 enters FAULT_SD mode

when the timer expires. PCA9450 stays in FAULT_SD mode for t_{FLT_SD_STAY}

.

t

starts

FLT_SD_WAIT

FAULT EVENT

AP receives

INT

Unmask fault register bit or Clear

the status bit when fault is cleared

INT

Mode

RUN/STANDBY

t

starts

FLT_SD_WAIT

FAULT EVENT

AP receives

INT

AP doesn't take an action until

timer is expired

INT

Mode

FAULT_SD

RUN/STANDBY

aaa-035711

Figure 10.ꢀPCA9450 Fault event

PCA9450 moves to READY mode after FAULT_SD mode if the regulator fault is caused

by LDO1 or LDO2. Otherwise, it moves to SNVS mode after FAULT_SD.

If either LDO1 or LDO2 has fault in SNVS mode, then it enters FAULT_SD mode

regardless of VRFLT1 Mask bit.

PCA9450 doesn’t enter FAULT_SD mode from load switch overcurrent fault.

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t

FLT_SD_STAY

VR_FLT event

VSYS

VR_FLT Clear

t

FLT_SD_WAIT

NOTE1

LDO1

LDO2

NVCC_SNVS

VDD_SNVS

Int RC Osc

X-tal Osc

NOTE1

RTC_RESET_B

CLK_32K_OUT

BUCK1

BUCK3

VDD_SOC

VDD_DRAM

VDD_G/VPU

PHY_0P9

LDO4

VDD_ARM

BUCK2

VDDA_1P8

VDDA_DRAM

LDO3

BUCK5

BUCK6

NVCC_1V8

NVCC_DRAM

NVCC_3V3

NVCC_SD2

POR_B

BUCK4

LDO5

Mode

Any state

FAULT_SD

SNVS

aaa-035712

Note 1 : If VR fault is caused by LDO1 or LDO2, then LDO1/LDO2/

RCT_REST_B/CLK_32K_OUT is turned OFF, otherwise, they are kept on.

Figure 11.ꢀPCA9450 FAULT_SD from VR Fault except LDO1/LDO2 in RUN/STANDBY

Table 9.ꢀt_{FLT_SD_WAIT}

Time

Description

Value

t_{FLT_SD_WAIT}

Time to reset released from Fault event

100 ms

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7.4 PMIC reset

PCA9450 has three reset input sources: WDOG_B pin, PMIC_RST_B pin and I2C reset

bit.

The reset behavior is configured in RESET_CTRL register for WDOG_B pin and

PMIC_RST_B pin. I2C reset behavior is configured in SW_RST register.

Table 10.ꢀ0x08 – RESET_CTRL

0x08 – RESET_CTRL

Bit Name

Reset Type

S

Type

Reset Description

When WDOG_B is asserted to L, PMIC behavior

00b = WDOG_B reset is disabled

01b = Warm Reset, POR_B pin is asserted low for 20 ms

7:6 WDOG_B_CFG

R/W

00

10

10b = Cold Reset, All voltage regulators are recycled except LDO1/

LDO2

11b = Cold Reset, All voltage regulators are recycled

When PMIC_RST_B is asserted to L, PMIC behavior

00b = PMIC_RST_B reset is disabled

01b = Warm Reset, POR_B pin is asserted low for 20 ms

5:4 PMIC_RST_CFG

R/W

10b = Cold Reset, All voltage regulators are recycled except

LDO1/LDO2

11b = Reserved

Table 11.ꢀ0x06 – SW_RST

0x06 – SW_RST

Reset Type

Reset Description

O

Bit

Name

Type

Software reset register. This register read back to “0x00” right after

writing the value.

0x00 = No action

0x05 = Reset all registers to default value

7:0 SW_RST

R/W

0x00 0x14 = Cold reset (Power recycle all regulators except LDO1, LDO2

and CLK_32K_OUT)

0x35 = Warm Reset (Toggle POR_B for 20 ms)

0x64 = Cold reset (Power recycle all regulators)

Others = No action

WDOG_B is asserted low, and gets reset depending on WDOG_B_CFG bit

configuration. When the bits are set to 2b00, the reset by WDOG_B pin is disabled. If the

bits are set to 2b01, warm reset is performed, where POR_B is pulled low for 20 ms and

resets I2C O type registers to default value keeping power rails remaining ON. If the bits

are set to 2b11, it performs Cold reset, where all voltage regulators except LDO1 and

LDO2 are power recycled and I2C O type registers get reset to default value.

When PMIC_RST_B is asserted low, it also gets reset depending on PMIC_RST_CFG

bits configuration. When the bits are set to 2b00, any reset by PMIC_RST_B pin is

disabled. If the bits are set to 2b01, warm reset is performed, in which pulling POR_B low

for 20 ms and reset I2C O type registers to default value keeping power rails remaining

ON.

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Cold reset event is generated by either of I2C reset, WDOG_B falling edge or

PMIC_RST_B falling edge after debounce time. Once it is detected, POR_B is pulled

low and takes power down sequence. For cold reset from WDOG_B and I2C reset,

PCA9450 stays at RESET for t_RESTARTand then starts power on sequence even though

WDOG_B pin is still low. For cold reset from PMIC_RST_B, t_RESTARTtimer starts after

PMIC_RST_B is asserted high; in other words, PCA9450 starts power on sequence in

t_RESTARTafter PMIC_RST_B pin is released high.

Cold Reset

Sources

LDO1/2

BUCK1

t

RESTART

POK

VDD_SOC

t

OFF_Step

VDD_DRAM

VDD_G/VPU

POK

BUCK3

LDO4

t

OFF_Step

t

POK

step

PHY_0P9

t

OFF_Step

POK

t

step

VDD_ARM

BUCK2

LDO3

t

OFF_Step

VDDA_1P8

VDDA_DRAM

t

POK

step

t

OFF_Step

t

step

POK

NVCC_1V8

BUCK5

t

OFF_Step

t

step

POK

BUCK6 NVCC_DRAM

t

OFF_Step

t

step

POK

BUCK4

LDO5

NVCC_3V3

NVCC_SD2

t

OFF_Step

t

POK

t

step

t

OFF_Step

t

step

POR_B

Mode

RUN/

STANDBY

RUN/

STANDBY

PWRDN

RESET

PWRUP

aaa-035713

Note: BUCK3 and LDO4 are removed in Power ON/OFF sequence in PCA9450B/C

Figure 12.ꢀPCA9450A Cold reset

Table 12.ꢀt_RESTART

Time

Description

Value

t_RESTART

Time to power ON seq from end of power OFF seq

during cold reset

250 ms

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Warm Reset

source

All regulator output

goes to default voltage

BUCK1

BUCK3

VDD_SOC

VDD_DRAM

VDD_G/VPU

LDO4

PHY_0P9

VDD_ARM

BUCK2

VDDA_1P8

LDO3

VDDA_DRAM

NVCC_1V8

BUCK5

BUCK6

BUCK4

NVCC_DRAM

NVCC_3V3

NVCC_SD2

LDO5

t

RESET

Reset

POR_B

Mode

RUN/

STANDBY

RUN/

STANDBY

aaa-035715

Figure 13.ꢀWarm reset

Table 13.ꢀt_RESET

Time

Description

POR_B low time at Warm reset

Value

20 ms

t_RESET

7.5 Regulator control in each power mode

Table 14 shows PCA9450A regulator ON/OFF control in each power mode by default. It

can be reconfigured through I2C registers.

Table 14.ꢀPCA9450A Regulator Control summary

Power Rail

LDO1

Default Voltage

1.8 V

OFF

SNVS

ON

STANDBY

ON

RUN

ON

NVCC_SNVS

VDD_SNVS

VDD_SOC

LDO2

0.85 V

ON

BUCK1

0.85 V

OFF

ON

VDD_DRAM

BUCK3

VDD_GPU VDD_ 0.85 V

VPU

OFF

ON

LDO4

PHY_0P9

0.9 V

ON

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Power Rail

Default Voltage

0.85 V

OFF

SNVS

OFF

STANDBY

OFF

ON

RUN

ON

BUCK2

LDO3

VDD_ARM

VDDA_1P8

NVCC_1V8

NVCC_DRAM

NVCC_3V3

NVCC_SD2

1.8 V

BUCK5

BUCK6

BUCK4

LDO5

1.8 V

ON

1.1 V

ON

3.3 V

ON

3.3 V / 1.8 V

ON

Table 15 shows PCA9450B/PCA9450C regulator ON/OFF control in each power mode

by default. It can be reconfigured through I2C registers.

Table 15.ꢀPCA9450B/PCA9450C Regulator Control summary

Power Rail

LDO1

Default Voltage

1.8 V

OFF

SNVS

ON

STANDBY

ON

RUN

ON

NVCC_SNVS

VDD_SNVS

LDO2

0.85 V

ON

VDD_SOC VDD_

BUCK1

DRAM VDD_GPU 0.85 V

VDD_VPU

OFF

ON

LDO4

0.9 V

OFF

ON

OFF

ON

BUCK2

LDO3

VDD_ARM

VDDA_1P8

NVCC_1V8

NVCC_DRAM

NVCC_3V3

NVCC_SD2

0.85 V

1.8 V

BUCK5

BUCK6

BUCK4

LDO5

1.8 V

1.1 V

3.3 V

3.3 V / 1.8 V

7.6 Regulator summary

The PCA9450 features six buck regulators, five linear regulators and one load switch to

supply voltage rails powering the application processor and peripheral devices. The buck

regulators are supplied directly from the main input supply. The input to all of the buck

regulators must be tied to VSYS, whether they are powered on or off.

7.6.1 BUCK regulator

The PCA9450A has six high-efficiency low Iq buck regulators. Each buck regulator

features soft start and overcurrent protection. Buck regulator operates in two modes:

PFM and PWM mode. It automatically transitions from PFM to PWM mode when FPWM

bit is set to “0”. Internal active discharge resistor is installed in each buck regulator output

to discharge voltage on output capacitors when regulator is off. It is configurable through

I2C register. Table 16 shows buck regulator summary.

BUCK1 and BUCK3 are configured as dual-phase buck regulator in PCA9450C and

provide up to 6 A. Table 17 shows PCA9450C buck summary.

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Table 16.ꢀPCA9450A Buck Summary

Default VOUT

[V]

Step size

[mV]

Default ON/

OFF

Current rating

[mA]

BUCK#

INPUT PIN

VOUT range [V]

BUCK1

BUCK2

BUCK3

BUCK4

BUCK5

BUCK6

INB13

INB26

INB13

INB45

INB26

0.85

3.3

0.6 - 2.1875

0.6 - 3.4

12.5

25

ON

3000

2000

1.8

0.6 - 3.4

25

1.1

0.6 - 3.4

25

Table 17.ꢀPCA9450C Buck Summary

Default VOUT

[V]

Step size

[mV]

Default ON/

OFF

Current rating

[mA]

Buck#

INPUT PIN

VOUT range [V]

BUCK1

BUCK2

BUCK4

BUCK5

BUCK6

INB13

INB26

INB45

INB26

0.85

3.3

0.6 - 2.1875

0.6 - 3.4

12.5

25

ON

6000

3000

2000

1.8

0.6 - 3.4

25

1.1

0.6 - 3.4

25

7.6.1.1 Dynamic voltage scaling

BUCK1, BUCK2 and BUCK3 support DVS (Dynamic Voltage Scaling). If PRESET_EN bit

in BUCK123_DVS register is set to 1, BUCK1/BUCK2/BUCK3 outputs are controlled by

Bx_DVS_PRESET bits in BUCK123_DVS. It enables those buck outputs to be controlled

by writing one register at a time.

If PRESET_EN bit is set to 0, those buck regulators outputs are determined by

BUCKxOUT_DVS0 and BUCKxOUT_DVS1 depending on PMIC_STBY_REQ

pin. When PMIC_STBY_REQ is asserted low, each buck output voltage is

determined by BUCKxOUT_DVS0 register, if the PMIC_STBY_REQ is asserted high,

BUCKxOUT_DVS1 register is selected as each buck output voltage. Figure 14 shows the

DVS voltage section diagram.

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Bx_DVS_PRESET

1

0x0C Reg

Min

Selection

BUCKx Output

BUCK1, 2, 3

BUCKxOUT_DVS0

L

I2C

0

programmable

BUCKxOUT_LIMIT

BUCK1, 2, 3

BUCKxOUT_DVS1

H

PRESET_EN

In 0x0C Reg

PMIC_STBY_REQ

DVS0 : PMIC_STBY_REQ = L

DVS1 : PMIC_STBY_REQ = H

aaa-035716

Figure 14.ꢀDVS functional diagram

The programmable voltage ramp-up and ramp-down are applied during the DVS voltage

transition. The ramp rate is configured by RAMP[7:6] bits in each BUCKxCTRL registers.

PMIC_STBY_REQ

DVS0

BUCKx

Internal

control with

RAMP[7:6]

DVS1

RAMP[7:6]

BUCK output

depending on Load

10us

aaa-035718

Figure 15.ꢀDVS timing

7.6.1.2 BUCK output voltage limiting

Application processor may accidentally write higher voltage than absolute maximum

voltage rating of its power input, which may cause significant damage on application

processor. PCA9450 has registers to limit the maximum voltage to prevent such an

incident.

BUCK1, BUCK2 and BUCK3 maximum output are limited by BUCKxOUT_LIMIT,

respectively. Even if buck output is configured to higher than the limit voltage configured

in BUCKxOUT_LIMIT register, the actual buck output is clamped to the limiting voltage

set by BUCKxOUT_LIMIT register.

7.6.1.3 Dual-phase configuration

BUCK1 and BUCK3 are configured as dual phase buck in PCA9450C by connecting

R_SNSP3_CFG pin to GND, where this dual phase buck regulator is controlled

through BUCK1 registers. All BUCK3 registers are not responsive under dual-phase

configuration.

When R_SNSP3_CFG pin is tied to INB13 in PCA9450B, BUCK3 is disabled. BUCK1

supplies VDD_SOC/VDD_VPU/VDD_GPU/VDD_DRAM in i.MX 8M Nano application

processor.

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PCA9450B

PCA9450C

INB13

VDD_SOC

VDD_VPU

VDD_GPU

VDD_DRAM

VDD_SOC

VDD_VPU

VDD_GPU

VDD_DRAM

SYS

F

SYS

DVS

10

22

10

22

F

0.47

H

0.47

H

LX1

BUCK1

3A

BUCK1

3A

F

R_SNSP1

EN

Dual

Phase

Ctrl

Dual

Phase

Ctrl

i.MX8

Nano

i.MX8

Plus

INB13

LX3

INB13

SYS

22

DVS

0.47

H

LX3

BUCK3

3A

BUCK3

3A

F

EN

R_SNSP3_CFG

aaa-035719

Figure 16.ꢀBUCK1/3 configuration

7.6.2 LDO and load switch

The PCA9450 has five LDOs and one load switch. LDO1 and LDO2 are supposed to

supply SNVS core in application processor. These two LDOs feature ultra-low quiescent

current, 2 μA typical, since they are always ON when VSYS is valid.

For all LDO and the load switch, each has designated active discharge resistor

configurable through I2C.

Table 18.ꢀLDO summary

Default VOUT

[V]

Step size

[mV]

Default ON/

OFF

Current rating

[mA]

LDO#

INPUT PIN

VOUT range [V]

LDO1

LDO2

LDO3

LDO4

LDO5

SW

INL1

SWIN

1.8

1.6-1.9, 3.0-3.3

0.8 – 1.15

0.8 - 3.3

1.8 - 3.3

-

100

50

ON

10

0.85

1.8

ON

10

100

-

ON

ON ^[1]

300

200

150

400

0.9

3.3/1.8

-

ON

OFF

[1] ON by default in PCA9450A, OFF by default in PCA9450B and PCA9450C

7.7 32 kHz Crystal Oscillator Driver

The PCA9450 consists of a crystal oscillator driver with an external load capacitor

and CLK_32K_OUT buffer referenced to LDO1 voltage. When VSYS exceeds POR

threshold and internal power VINT is good, internal 32 kHz oscillator and 32.768 kHz

crystal oscillator start oscillating. Crystal oscillator typically takes few seconds to be

stabilized. PCA9450 outputs the internal 32 kHz RC oscillator initially, while internal

counter counts crystal oscillator output in t_{RTC_Tran}after RTC_RESET_B is released. If

the counter reaches 100, then CLK_32K_OUT buffer input is switched to the external

crystal oscillator from internal 32 kHz oscillator. Clock stretch is applied during this clock

source transition to prevent unwanted glitch. If external 32.768 kHz crystal oscillator is

not populated, CLK_32K_OUT pin outputs 32 kHz clock from internal 32 kHz oscillator.

For more detailed information on selecting crystal oscillator and load capacitance, refer to

Section 9.2.2.

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XTAL_IN

VINT

32K Osc

32.768K Xtal

XTAL_OUT

t

RTC_RESET_B

LDO1

MUX

RTC_Tran

COUNT

CLK_32K_OUT

CLOCK

STRETCH

aaa-035720

Figure 17.ꢀ32 kHz Crystal oscillator driver block diagram

7.8 Load switch

PCA9450 integrates 400 mA load switch which is used to supply SD card VDD. SWIN

is connected to BUCK4 output, 3.3 V, in this application. It is enabled by SW_EN pin

or SW_EN[1:0] bits in LOADSW_CTRL register. It has soft start feature to reduce

inrush current during turn-on. This load switch has overcurrent protection and short

circuit protection by monitoring voltage difference between SWIN and SWOUT. When

the switch current exceeds overcurrent threshold (I_OC) for overcurrent debounce time

(t_{OC_DEB}), SW_OCP bit in VRFLT1_STS register is set to 1 and the fault behavior is

determined by SW_OC[1:0] configuration in LOADSW_CTRL register. When the switch

current exceeds short-circuit current threshold (I_SC), SW_OCP bit in VRFLT1_STS

register is set to 1 and switch is turned off right away.

SW_OC

SW_SC

from Buck4

3.3 V

SWOUT

SWIN

F

80

DRIVER

SW_EN

I2C

aaa-035721

Figure 18.ꢀLoad switch internal block diagram

7.9 I²C level translator

PCA9450 I²C level translator is a "switch" type voltage translator, and employs two key

circuits to enable voltage translation:

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1. A pass-gate transistor (N-channel) that ties the ports together.

2. An output edge-rate accelerator that detects and accelerates rising edges on the I/O

pins.

The gate bias voltage of the pass gate transistor (T3) is set at approximately one

threshold voltage above the VCC level of the low-voltage side. During a LOW-to-HIGH

transition the output one-shot accelerates the output transition by switching on the PMOS

transistors (T1, T2) bypassing the 10 kΩ pull-up resistors and increasing current drive

capability. The one-shot is activated once the input transition reaches approximately

VCCI/2; it is de-activated approximately 50 ns after the output reaches VCCO/2. During

the acceleration time the driver output resistance is between approximately 50 Ω and

70 Ω. To avoid signal contention and minimize dynamic ICC, the user should wait for

the one-shot circuit to turn off before applying a signal in the opposite direction. Pull-up

resistors are included in the device for DC current sourcing capability.

VCCA

(VINT)

VCCB

(SWIN)

T1

T2

ONE

SHOT

10 kΩ

GATE BIAS

T3

A

B

(SCLL)

(SCLH)

aaa-035722

Figure 19.ꢀArchitecture of I2C Level translator (One channel)

Each A port I/O has an internal 10 kΩ pull-up resistor to VCCA, and each B port I/O

has an internal 10 kΩ pull-up resistor to VCCB. If a smaller value of pull-up resistor is

required, an external resistor must be added parallel to the internal 10 kΩ, affecting the

VOL level. When Level translator is disabled through I2C, the internal pull up resistors

are disconnected.

PCA9450 I2C Level translator is controlled by I2C register, CONFIG2 Reg. When it

is configured to disabled, all I/Os assume the high-impedance OFF-state. The enable

time (ten) indicates the amount of time the user must allow for one one-shot circuitry to

become operational after it is enabled.

7.10 Interrupt management

The IRQ_B pin is an interface to the software-controlled system that indicates any

interrupt bit status change of INT1 register. The IRQ_B pin is pulled low when any

unmasked interrupt bit status is changed and it is released high once application

processor reads INT1 register.

The INT1 bits are latched to 1 whenever corresponding STATUS1 bits are changed

and the latch is cleared when the INT1 register is read. The INT1_MASK bits are used

to enable or disable individual interrupt bits of INT1 register. The STATUS1 register

indicates the current status and is not latched.

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VRFLT1_MASK

VRFLT1_STS

SW_OCP

RSVD

INT1 MASK

INT1

STATUS1

PWRONS

PWRONI

Deb

PMIC_ON_REQ

WDOG_B

BUCK6_FLT_M

BUCK5_FLT_M

BUCK6_FLT

BUCK5_FLT

WDOGBI

RSVD

WDOG_BS

RSVD

BUCK4_FLT_M

BUCK3_FLT_M

BUCK2_FLT_M

BUCK1_FLT_M

BUCK4_FLT

BUCK3_FLT

BUCK2_FLT

BUCK1_FLT

VR_FLT1_S

VR_FLT1I

VR_FLT2I

VRFLT2_MASK

RSVD

VRFLT2_STS

RSVD

INT

VR_FLT2_S

LOWVSYS_S

THERM_105S

THERM_125S

RSVD

VSYS

RSVD

LOWVSYSI

THERM_105I

THERM_125I

LDO5_FLT_M

LDO4_FLT_M

LDO3_FLT_M

LDO2_FLT_M

LDO1_FLT_M

LDO5_FLT

LDO4_FLT

LDO3_FLT

LDO2_FLT

LDO1_FLT

VSYS UVLO + Delta

105°C

Die

Temp

125°C

aaa-035723

Figure 20.ꢀInterrupt diagram

8 Software interface

PCA9450 implements I2C-bus slave interface and it interfaces with the host system.

The host processor can issue commands, monitor status and receive response through

this bus. A detailed description of the I2C-bus specification, with applications, is given in

UM10204, “I2C-bus specification and user manual” [Ref. 4]. PCA9450 supports I2C-bus

data transfers in Standard-mode (100 kbit/s), Fast-mode (400 kbit/s) and Fast-mode plus

(1 Mbit/s).

The I2C address at Power-On Reset is shown in Table 19

Table 19.ꢀPCA9450 I2C Slave Address

7-bit Slave Address

8-bit Write Address

8-bit Read Address

0x25, 0b 010 0101

0x4A, 0b 0100 1010

0x4B, 0b 0100 1011

I2C register reset type

Type S1 : Reset condition = VSYS < V_{SYS_POR}

Type S : Reset condition = VSYS < V_{SYS_UVLO}

Type O : Reset condition = (VSYS < V_{SYS_UVLO}) || (Cold Reset) || (Warm Reset) ||

(Falling edge of PMIC_ON_REQ) || (SW_RST) || (FAULT_SD)

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8.2 Register details

8.2.1 0x00 Device_ID

The device identification code stores a unique identifier for each version and/or revision

of a PCA9450, so that the connected processor recognizes it automatically.

Table 21.ꢀ0x00 Device_ID

0x00 – Device_ID

Bit Name

Reset Type

Reset Description

Chip ID

S

Type

R

7:4 CHIP_ID

3:0 RSVD

0001

0001b = PCA9450A

0011b = PCA9450B, PCA9450C

R

0000

Reserved

8.2.2 0x01 INT1

Interrupt source register. Either of unmasked register bits is set to 1, IRQ_B pin is pulled

low. This register is Read and Clear.

Table 22.ꢀ0x01 INT1

0x01 – INT1

Reset Type

S

Bit

Name

Type

Reset Description

PWRON interrupt bit

7

PWRONI

R/C

0

0b = PWRONS bit has not been changed

1b = PWRONS bit has been changed

WDOGB interrupt bit

6

5

4

WDOGBI

RSVD

R/C

0

0b = WDOG_BS bit has not been changed

1b = WDOG_BS bit has been changed

Reserved

Voltage regulator Group1 Fault interrupt

0b = VR_FLT1S bit has not been changed

1b = VR_FLT1S bit has been changed

VR_FLT1I

Voltage regulator Group2 Fault interrupt

0b = VR_FLT2S bit has not been changed

1b = VR_FLT2S bit has been changed

3

2

1

0

VR_FLT2I

R/C

0

Low-SYS Voltage interrupt bit

LOWVSYSI

THERM_105I

THERM_125I

0b = LOWVSYSS bit has not been changed

1b = LOWVSYSS bit has been changed

Die temperature 105 °C interrupt

0b = THERM_105S bit has not been changed

1b = THERM_105S bit has been changed

Die temperature 125 °C interrupt

0b = THERM_125S bit has not been changed

1b = THERM_125S bit has been changed

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8.2.3 0x02 INT1_MSK

The INT1_MSK register enables the masking (disabling) of the different interrupt signals

of register INT1. When unmasked, interrupt events trigger the IRQB pin to be pulled low

when the matching flag bit in the register INT1 is set.

Table 23.ꢀ0x02 INT1_MSK

0x02 – INT1_MSK

Reset Type

S

Bit

Name

Type

Reset Description

PWRONI interrupt mask bit

7

PWRON_M

R/W

1

0b = Enable PWRONI interrupt

1b = Mask PWRONI interrupt

WDOGBI interrupt mask bit

0b = Enable WDOGBI interrupt

1b = Mask WDOGBI interrupt

6

5

4

WDOGB_M

RSVD

R/W

1

Reserved

VR_FLT1I interrupt mask bit

0b = Enable VR_FLT1I interrupt

1b = Mask VR_FLT1I interrupt

VR_FLT1_M

VR_FLT2I interrupt mask bit

0b = Enable VR_FLT2I interrupt

1b = Mask VR_FLT2I interrupt

3

2

1

0

VR_FLT2_M

R/W

1

LOWVINI interrupt mask bit

0b = Enable LOWVINI interrupt

1b = Mask LOWVINI interrupt

LOWVSYS_M

THERM_105_M

THERM_125_M

THERM_105 interrupt mask bit

0b = Enable THERM_105 interrupt

1b = Mask THERM_105 interrupt

THERM_125 interrupt mask bit

0b = Enable THERM_125 interrupt

1b = Mask THERM_125 interrupt

8.2.4 0x03 STATUS1

STATUS1 register show current status. Any status bit change set corresponding interrupt

bit to 1.

Table 24.ꢀ0x03 STATUS1

0x03 – STATUS1

Reset Type

S

Bit

Name

Type

Reset Description

PMIC_ON_REQ pin status after debounce time

0b = PMIC_ON_REQ pin is low

7

PWRONS

R

0

1b = PMIC_ON_REQ pin is high

WDOG_B pin status

6

WDOG_BS

RSVD

R

0

0b = WDOG_B pin is low

1b = WDOG_B pin is high

5

Reserved

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0x03 – STATUS1

Reset Type

S

Bit

Name

Type

Reset Description

Voltage Regulator Fault status, See 0x2B Register.

0b = All voltage regulators are OK

4

VR_FLT1S

R

0

1b = Either of voltage regulators is in Fault state

Voltage Regulator POK status, See 0x2C Registers.

0b = All voltage regulators are OK

3

2

1

0

VR_FLT2S

R

1b = Either of voltage regulators is in Fault state

VSYS low voltage status

LOWVSYSS

THERM_105S

THERM_125S

0b = VSYS > Low VSYS threshold

1b = VSYS ≤ Low VSYS threshold

Die temperature 105 °C status

0b = Die temperature is below 105 °C

1b = Die temperature is above 105 °C

Die temperature 125 °C status

0b = Die temperature is below 125 °C

1b = Die temperature is above 125 °C

8.2.5 0x04 STATUS2

STATUS2 register shows current PCA9450 power status.

Table 25.ꢀ0x04 STATUS2

0x04 – STATUS2

Reset Type

S1

Bit

Name

Type

Reset Description

7:4 RSVD

R

0000

Reserved

Current PCA9450 power status

0000b = OFF

0001b = READY

0010b = SNVS

0011b = PWRUP

0100b = RUN

3:0 POWER_STATUS

R

0101b = STANDBY

0110b = PWRDN

0111b = WARM RESET

1000b = COLD RESET

1001b = FAULT Shutdown

1010b – 1111b = Reserved

8.2.6 0x05 PWRON_STAT

Power ON source register. It is latched to 1 until the bit is read back.

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Table 26.ꢀ0x05 PWRON_STAT

0x05 – PWRON_STAT

Reset Type

S

Bit

Name

Type

Reset Description

1b = Power ON triggered by PMIC_ON_REQ. This bit will be set right

after completing power up sequence.

7

PWRON

R/C

0

6

5

4

3

2

1

0

WDOG

SW_RST

PMIC_RST

RSVD

R/C

0

1b = This bit is set after cold reset by WDOGB pin

1b = This bit is set after cold reset by SW_RST bit

1b = This bit is set after cold reset by PMIC_RST_B

Reserved

RSVD

8.2.7 0x06 SW_RST

Software reset register through I2C.

Table 27.ꢀ0x06 SW_RST

0x06 – SW_RST

Reset Type

O

Bit

Name

Type

Reset Description

Software reset register. This register is read back to “0x00” right after

writing the value.

0x00 = No action

0x05 = Reset all registers to default value

7:0 SW_RST

R/W

0x00

0x14 = Cold reset (Power recycle all regulators except LDO1, LDO2

and CLK_32K_OUT)

0x35 = Warm Reset (Toggle POR_B for 20 ms)

0x64 = Cold reset (Power recycle all regulators)

Others = No action

8.2.8 0x07 PWR_CTRL

Debounce timer configuration register

Table 28.ꢀ0x07 PWR_CTRL

0x07 – PWR_CTRL

Reset Type

S

Bit

Name

Type

Reset Description

Debounce time for PMIC_ON_REQ high.

00b = 120 μs

7:6 Ton_Deb

R/W

01

0

01b = 20 ms

10b = 100 ms

11b = 750 ms

Debounce time for PMIC_ON_REQ is asserted low

5

Toff_Deb

R/W

0b = 120 μs

1b = 2 ms

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0x07 – PWR_CTRL

Reset Type

S

Bit

Name

Type

Reset Description

Time step configuration during power on sequence

00b = 1 ms

01b = 2 ms

10b = 4 ms

11b = 8 ms

4:3 Tstep

R/W

01

Time step configuration during power down sequence

00b = 2 ms

01b = 4 ms

10b = 8 ms

11b = 16 ms

2:1 Toff_step

R/W

10

0

Time to stay regulators off during Cold reset

0b = 250 ms

0

Trestart

1b = 500 ms

8.2.9 0x08 RESET_CTRL

Reset behavior configuration register through WDOG_B and PMIC_RST_B pin.

Table 29.ꢀ0x08 RESET_CTRL

0x08 – RESET_CTRL

Reset Type

S

Bit

Name

Type

Reset Description

When WDOG_B is asserted to low, PMIC reset behavior

00b = WDOG_B reset is disabled

01b = Warm Reset, POR_B pin is asserted low for 20 ms

7:6 WDOG_B_CFG

R/W

00

10b = Cold Reset, All voltage regulators are recycled except LDO1/

LDO2

11b = Cold Reset, All voltage regulators are recycled

When PMIC_RST_B is asserted to low, PMIC reset behavior

00b = PMIC_RST_B reset is disabled

01b = Warm Reset, POR_B pin is asserted low for 20 ms

5:4 PMIC_RST_CFG

R/W

10

0

10b = Cold Reset, All voltage regulators are recycled except

LDO1/LDO2

11b = Cold Reset, All voltage regulators are recycled

3

RSVD

Reserved

PMIC_RST_B debounce time

000b = 10 ms

001b = 50 ms

010b = 100 ms

011b = 500 ms

100b = 1 sec

2:0 T_PMIC_RST_DEB

R/W

001

101b = 2 sec

110b = 4 sec

111b = 8 sec

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8.2.10 0x09 CONFIG1

VSYS_UVLO and LOW VSYS configuration register

Table 30.ꢀ0x09 CONFIG1

0x09 – CONFIG1

Reset Type

S1

Bit

Name

Type

Reset Description

Low VSYS threshold above V_{SYS_UVLO}

00b = 100 mV

7:6

LOW_VSYS

R/W

01

01b = 200 mV

10b = 300 mV

11b = 400 mV

VSYS UVLO Rising threshold

00b = 2.85 V

5:4

VSYS_UVLO

R/W

01b = 3.0 V

10b = 3.15 V

11b = 3.3 V

3:2

1

RSVD

R/W

00

0

Reserved

Wait time for AP action when regulator fault occurs

tFLT_SD_WAIT

0b = 100 ms

1b = 120 μs

Thermal shutdown disable bit

0b = Enable Thermal shutdown

1b = Disable Thermal shutdown

0

THERM_SD_DIS

R/W

0

8.2.11 0x0A CONFIG2

I2C Level translator control register

Table 31.ꢀ0x0A CONFIG2

0x0A – CONFIG2

Reset Type

O

Bit

Name

Type

R/W

Reset Description

7

RSVD

0

Reserved

6:4 RSVD

3:2 RSVD

000

00

I2C level translator enable

00b = Forced Disable

1:0 I2C_LT_EN

R/W

00

01b = Enable only when STANDBY and RUN mode

10b = Enable only when RUN mode

11b = Forced enable

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8.2.12 0x0C BUCK123_DVS

BUCK1, BUCK2, BUCK3 DVS control register with preset value

Table 32.ꢀ0x0C BUCK123_DVS

0x0C – BUCK123_DVS

Reset Type

O

Bit

Name

Type

Reset Description

BUCK123 output voltage selection

0b = BUCK voltage is determined by each BUCKxOUT_DVS0 or

BUCKxOUT_DVS1.

7

PRESET_EN

R/W

1

1b = BUCK voltage is determined by Bx_DVS_PRESET bits.

BUCK3 (VPU/GPU) Preset voltage option, only for PCA9450A.

00b = 0.8 V

01b = 0.85 V

10b = 0.9 V

11b = 0.95 V

6:5

4:3

B3_DVS_PRESET

B1_DVS_PRESET

R/W

01

BUCK1 (SOC) Preset voltage option

00b = 0.8 V

01

01b = 0.85 V

10b = 0.9 V

11b = 0.95 V

BUCK2 (ARM) Preset voltage option

000b = 0.8 V

001b = 0.85 V

2:0

B2_DVS_PRESET

R/W

001

010b = 0.9 V

011b = 0.95 V

100b – 111b = 1.0 V

8.2.13 0x0D BUCK1OUT_LIMIT

BUCK1 output voltage limit register

Table 33.ꢀ0x0D BUCK1OUT_LIMIT

0x0D – BUCK1OUT_LIMIT

Reset Type

O

Bit

Name

Type

Reset Description

7

RSVD

R/W

0

Reserved

BUCK1 output voltage limit

001

1100

6:0 B1_LIMIT

R/W

Programmable from 0.60 V to 2.1875 V in 12.5 mV step

Default = 0.95 V

8.2.14 0x0E BUCK2OUT_LIMIT

BUCK2 output voltage limit register

Table 34.ꢀ0x0E BUCK2OUT_LIMIT

0x0E – BUCK2OUT_LIMIT

Reset Type

O

Bit

Name

Type

Reset Description

7

RSVD

R/W

0

Reserved

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0x0E – BUCK2OUT_LIMIT

Reset Type

O

Bit

Name

Type

Reset Description

BUCK2 output voltage limit

010

0000

6:0 B2_LIMIT

R/W

Programmable from 0.60 V to 2.1875 V in 12.5 mV step

Default = 1.00 V

8.2.15 0x0F BUCK3OUT_LIMIT

BUCK3 output voltage limit register. This register is only for PCA9450A

Table 35.ꢀ0x0F BUCK3OUT_LIMIT

0x0F – BUCK3OUT_LIMIT

Reset Type

O

Bit

Name

Type

Reset Description

7

RSVD

R/W

0

Reserved

BUCK3 output voltage limit

001

1100

6:0 B3_LIMIT

R/W

Programmable from 0.60 V to 2.1875 V in 12.5 mV step

Default = 0.95 V

8.2.16 0x10 BUCK1CTRL

BUCK1 control register for Ramp, DVS control, Active discharge, FPWM and Enable.

Table 36.ꢀ0x10 BUCK1CTRL

0x10 – BUCK1CTRL

Bit Name

Reset Type

O

Type

Reset Description

BUCK1 DVS speed

00b = 25 mV / 1 μs

01b = 25 mV / 2 μs

10b = 25 mV / 4 μs

11b = 25 mV / 8 μs

7:6 RAMP

R/W

01

5

4

RSVD

R/W

0

Reserved

DVS Control configuration

0b = BUCK voltage is determined by BUCK1VOUT_DVS0 register

regardless of PMIC_STBY_REQ

DVS_CTRL

1b = DVS control through PMIC_STBY_REQ

BUCK1 Active discharge

3

2

BUCK1AD

FPWM

R/W

1

0

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

Forced PWM mode

0b = Automatic PFM and PWM mode transition

1b = Forced PWM mode

BUCK1 enable mode

00b = OFF

1:0 B1_ENMODE

R/W

01

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

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8.2.17 0x11 BUCK1OUT_DVS0

BUCK1 DVS output voltage at PMIC_STBY_REQ = L

Table 37.ꢀ0x11 BUCK1OUT_DVS0

0x11 – BUCK1OUT_DVS0

Reset Type

O

Bit

Name

Type

Reset Description

7

RSVD

R/W

0

Reserved

BUCK1 DVS0 Output voltage

001

0100

6:0 B1_DVS0

R/W

Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 12

Default = 0.85 V

8.2.18 0x12 BUCK1OUT_DVS1

BUCK1 DVS output voltage at PMIC_STBY_REQ = H

Table 38.ꢀ0x12 BUCK1OUT_DVS1

0x12 – BUCK1OUT_DVS1

Reset Type

O

Bit

Name

Type

Reset Description

7

RSVD

R/W

0

Reserved

BUCK1 DVS1 Output voltage

001

0100

6:0 B1_DVS1

R/W

Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 12

Default = 0.85 V

8.2.19 0x13 BUCK2CTRL

BUCK2 control register for Ramp, DVS control, Active discharge, FPWM and Enable.

Table 39.ꢀ0x13 BUCK2CTRL

0x13 – BUCK2CTRL

Bit Name

Reset Type

O

Type

Reset Description

BUCK2 DVS speed

00b = 25 mV / 1 μs

01b = 25 mV / 2 μs

10b = 25 mV / 4 μs

11b = 25 mV / 8 μs

7:6 RAMP

R/W

01

5

4

RSVD

R/W

0

Reserved

DVS Control configuration

0b = BUCK voltage is determined by BUCK2VOUT_DVS0 register

regardless of PMIC_STBY_REQ

DVS_CTRL

1b = DVS control through PMIC_STBY_REQ

BUCK2 Active discharge

3

BUCK2AD

FPWM

R/W

1

0

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

Forced PWM mode

2

0b = Automatic PFM and PWM mode transition

1b = Forced PWM mode

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0x13 – BUCK2CTRL

Reset Type

O

Bit

Name

Type

Reset Description

BUCK2 enable mode

00b = OFF

1:0 B2_ENMODE

R/W

10

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

8.2.20 0x14 BUCK2OUT_DVS0

BUCK2 DVS output voltage at PMIC_STBY_REQ = L

Table 40.ꢀ0x14 BUCK2OUT_DVS0

0x14 – BUCK2OUT_DVS0

Reset Type

O

Bit

Name

Type

Reset Description

7

RSVD

R/W

0

Reserved

BUCK2 DVS0 Output voltage

001

0100

6:0 B2_DVS0

R/W

Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 45

Default = 0.85 V

8.2.21 0x15 BUCK2OUT_DVS1

BUCK2 DVS output voltage at PMIC_STBY_REQ = H

Table 41.ꢀ0x15 BUCK2OUT_DVS1

0x15 – BUCK2OUT_DVS1

Reset Type

O

Bit

Name

Type

Reset Description

7

RSVD

R/W

0

Reserved

BUCK2 DVS1 Output voltage

001

0100

6:0 B2_DVS1

R/W

Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 45

Default = 0.85 V

8.2.22 0x16 BUCK3CTRL

BUCK3 control register for Ramp, DVS control, Active discharge, FPWM and Enable.

The registers related to BUCK3 are only for PCA9450A.

Table 42.ꢀ0x16 BUCK3CTRL

0x16 – BUCK3CTRL

Bit Name

Reset Type

O

Type

R/W

Reset Description

BUCK3 DVS speed

00b = 25 mV / 1 μs

01b = 25 mV / 2 μs

10b = 25 mV / 4 μs

11b = 25 mV / 8 μs

7:6 RAMP

01

0

5

RSVD

Reserved

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

0x16 – BUCK3CTRL

Reset Type

O

Bit

Name

Type

Reset Description

DVS Control configuration

0b = BUCK voltage is determined by BUCK3VOUT_DVS0 register

regardless of PMIC_STBY_REQ

4

DVS_CTRL

R/W

0

1b = DVS control through PMIC_STBY_REQ

BUCK3 Active discharge

3

2

BUCK3AD

FPWM

R/W

1

0

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

Forced PWM mode

0b = Automatic PFM and PWM mode transition

1b = Forced PWM mode

BUCK3 enable mode

00b = OFF

1:0 B3_ENMODE

R/W

01

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

8.2.23 0x17 BUCK3OUT_DVS0

BUCK3 DVS output voltage at PMIC_STBY_REQ = L

Table 43.ꢀ0x17 BUCK3OUT_DVS0

0x17 – BUCK3OUT_DVS0

Reset Type

O

Bit

Name

Type

Reset Description

7

RSVD

R/W

0

Reserved

BUCK3 DVS0 Output voltage

001

0100

6:0 B3_DVS0

R/W

Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 45

Default = 0.85 V

8.2.24 0x18 BUCK3OUT_DVS1

BUCK3 DVS output voltage a PMIC_STBY_REQ = H

Table 44.ꢀ0x18 BUCK3OUT_DVS1

0x18 – BUCK3OUT_DVS1

Reset Type

O

Bit

Name

Type

Reset Description

7

RSVD

R/W

0

Reserved

BUCK3 DVS1 Output voltage

001

0100

6:0 B3_DVS1

R/W

Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 45

Default = 0.85 V

Table 45.ꢀBUCK1, BUCK2, BUCK3 Output voltage table

Code

Voltage

Code

Voltage

Code

Voltage

Code

Voltage

0x00

0.6000 V

0x20

1.0000 V

0x40

1.4000 V

0x60

1.8000 V

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

Code

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

Voltage

0.6125 V

0.6250 V

0.6375 V

0.6500 V

0.6625 V

0.6750 V

0.6875 V

0.7000 V

0.7125 V

0.7250 V

0.7375 V

0.7500 V

0.7625 V

0.7750 V

0.7875 V

0.8000 V

0.8125 V

0.8250 V

0.8375 V

0.8500 V

0.8625 V

0.8750 V

0.8875 V

0.9000 V

0.9125 V

0.9250 V

0.9375 V

0.9500 V

0.9625 V

0.9750 V

0.9875 V

Code

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

Voltage

1.0125 V

1.0250 V

1.0375 V

1.0500 V

1.0625 V

1.0750 V

1.0875 V

1.1000 V

1.1125 V

1.1250 V

1.1375 V

1.1500 V

1.1625 V

1.1750 V

1.1875 V

1.2000 V

1.2125 V

1.2250 V

1.2375 V

1.2500 V

1.2625 V

1.2750 V

1.2875 V

1.3000 V

1.3125 V

1.3250 V

1.3375 V

1.3500 V

1.3625 V

1.3750 V

1.3875 V

Code

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

Voltage

1.4125 V

1.4250 V

1.4375 V

1.4500 V

1.4625 V

1.4750 V

1.4875 V

1.5000 V

1.5125 V

1.5250 V

1.5375 V

1.5500 V

1.5625 V

1.5750 V

1.5875 V

1.6000 V

1.6125 V

1.6250 V

1.6375 V

1.6500 V

1.6625 V

1.6750 V

1.6875 V

1.7000 V

1.7125 V

1.7250 V

1.7375 V

1.7500 V

1.7625 V

1.7750 V

1.7875 V

Code

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

Voltage

1.8125 V

1.8250 V

1.8375 V

1.8500 V

1.8625 V

1.8750 V

1.8875 V

1.9000 V

1.9125 V

1.9250 V

1.9375 V

1.9500 V

1.9625 V

1.9750 V

1.9875 V

2.0000 V

2.0125 V

2.0250 V

2.0375 V

2.0500 V

2.0625 V

2.0750 V

2.0875 V

2.1000 V

2.1125 V

2.1250 V

2.1375 V

2.1500 V

2.1625 V

2.1750 V

2.1875 V

8.2.25 0x19 BUCK4CTRL

BUCK4 control register for Active discharge, FPWM and Enable.

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

Table 46.ꢀ0x19 BUCK4CTRL

0x19 – BUCK4CTRL

Reset Type

O

Bit

Name

Type

Reset Description

7:4 RSVD

R/W

0000

Reserved

BUCK4 Active discharge

3

2

BUCK4AD

R/W

1

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

Forced PWM mode

FPWM

0

0b = Automatic PFM and PWM mode transition

1b = Forced PWM mode

BUCK4 enable mode

00b = OFF

1:0 B4_ENMODE

R/W

01

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

8.2.26 0x1A BUCK4OUT

BUCK4 output voltage configuration register

Table 47.ꢀ0x1A BUCK4OUT

0x1A – BUCK4OUT

Reset Type

O

Bit

Name

Type

Reset Description

7

RSVD

R/W

0

Reserved

BUCK4 Output voltage

110

1100

6:0 B4_OUT

R/W

Programmable from 0.60 V to 3.40 V in 25 mV step. Table 52

Default = 3.3 V

8.2.27 0x1B BUCK5CTRL

BUCK5 control register for Active discharge, FPWM and Enable.

Table 48.ꢀ0x1B BUCK5CTRL

0x1B – BUCK5CTRL

Bit Name

7:4 RSVD

Reset Type

O

Type

Reset Description

R/W

0000

Reserved

BUCK5 Active discharge

3

2

BUCK5AD

R/W

1

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

Forced PWM mode

FPWM

0

0b = Automatic PFM and PWM mode transition

1b = Forced PWM mode

BUCK5 enable mode

00b = OFF

1:0 B5_ENMODE

R/W

01

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

8.2.28 0x1C BUCK5OUT

BUCK5 output voltage configuration register

Table 49.ꢀ0x1C BUCK5OUT

0x1C – BUCK5OUT

Reset Type

O

Bit

Name

Type

Reset Description

7

RSVD

R/W

0

Reserved

BUCK5 Output voltage

011

0000

6:0 B5_OUT

R/W

Programmable from 0.60 V to 3.40 V in 25 mV step. Table 52

Default = 1.8 V

8.2.29 0x1D BUCK6CTRL

BUCK6 control register for Active discharge, FPWM and Enable.

Table 50.ꢀ0x1D BUCK6CTRL

0x1D – BUCK6OUT

Bit Name

7:4 RSVD

Reset Type

O

Type

Reset Description

R/W

0000

Reserved

BUCK6 Active discharge

3

2

BUCK6AD

R/W

1

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

Forced PWM mode

FPWM

0

0b = Automatic PFM and PWM mode transition

1b = Forced PWM mode

BUCK6 enable mode

00b = OFF

1:0 B6_ENMODE

R/W

01

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

8.2.30 0x1E BUCK6OUT

BUCK6 output voltage configuration register

Table 51.ꢀ0x1E BUCK6OUT

0x1E – BUCK6CTRL

Reset Type

O

Bit

Name

Type

Reset Description

7

RSVD

R/W

0

Reserved

BUCK6 Output voltage

001

0100

6:0 B6_OUT

R/W

Programmable from 0.60 V to 3.40 V in 25 mV step. Table 52

Default = 1.1 V

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

Table 52.ꢀBUCK4, BUCK5, BUCK6 Output voltage table

Code

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

Voltage

0.600 V

0.625 V

0.650 V

0.675 V

0.700 V

0.725 V

0.750 V

0.775 V

0.800 V

0.825 V

0.850 V

0.875 V

0.900 V

0.925 V

0.950 V

0.975 V

1.000 V

1.025 V

1.050 V

1.075 V

1.100 V

1.125 V

1.150 V

1.175 V

1.200 V

1.225 V

1.250 V

1.275 V

1.300 V

1.325 V

1.350 V

1.375 V

Code

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

Voltage

1.400 V

1.425 V

1.450 V

1.475 V

1.500 V

1.525 V

1.550 V

1.575 V

1.600 V

1.625 V

1.650 V

1.675 V

1.700 V

1.725 V

1.750 V

1.775 V

1.800 V

1.825 V

1.850 V

1.875 V

1.900 V

1.925 V

1.950 V

1.975 V

2.000 V

2.025 V

2.050 V

2.075 V

2.100 V

2.125 V

2.150 V

2.175 V

Code

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

Voltage

2.200 V

2.225 V

2.250 V

2.275 V

2.300 V

2.325 V

2.350 V

2.375 V

2.400 V

2.425 V

2.450 V

2.475 V

2.500 V

2.525 V

2.550 V

2.575 V

2.600 V

2.625 V

2.650 V

2.675 V

2.700 V

2.725 V

2.750 V

2.775 V

2.800 V

2.825 V

2.850 V

2.875 V

2.900 V

2.925 V

2.950 V

2.975 V

Code

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

Voltage

3.000 V

3.025 V

3.050 V

3.075 V

3.100 V

3.125 V

3.150 V

3.175 V

3.200 V

3.225 V

3.250 V

3.275 V

3.300 V

3.325 V

3.350 V

3.375 V

3.400 V

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

8.2.31 0x20 LDO_AD_CTRL

LDO active discharge resistor configuration register

Table 53.ꢀ0x20 LDO_AD_CTRL

0x20 – LDO_AD_CTRL

Reset Type

O

Bit

Name

Type

Reset Description

LDO1 Active discharge enable

7

LDO1_AD

R/W

1

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

LDO2 Active discharge enable

6

5

4

3

LDO2_AD

LDO3_AD

LDO4_AD

LDO5_AD

R/W

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

LDO3 Active discharge enable

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

LDO4 Active discharge enable

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

LDO5 Active discharge enable

0b = Always disable Active discharge resistor

1b = Enable Active discharge resistor when regulator is OFF

2

1

0

RSVD

R/W

0

Reserved

8.2.32 0x21 LDO1CTRL

LDO1 control register for enable and voltage

Table 54.ꢀ0x21 LDO1CTRL

0x21 – LDO1CTRL

Reset Type

O

Bit

Name

Type

R/W

Reset Description

LDO1 Enable mode

00b = OFF

01b = ON by PMIC_ON_REQ = H

7:6 ENMODE

5:3 RSVD

11

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

* When LDO1 is turned off, PCA9450/A transitions to READY mode

000

Reserved

PCA9450

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

0x21 – LDO1CTRL

Reset Type

O

Bit

Name

Type

Reset Description

LDO1 output voltage

Programmable from 1.6 V – 1.9 V, 3.0 V – 3.3 V in 100 mV step

000b = 1.6 V

001b = 1.7 V

010b = 1.8 V

011b = 1.9 V

100b = 3.0 V

101b = 3.1 V

110b = 3.2 V

111b = 3.3 V

2:0 L1_OUT

R/W

010

8.2.33 0x22 LDO2CTRL

LDO2 control register for enable and voltage

Table 55.ꢀ0x22 LDO2CTRL

0x22 – LDO2CTRL

Reset Type

O

Bit

Name

Type

R/W

Reset Description

LDO2 Enable mode

00b = OFF

01b = ON by PMIC_ON_REQ = H

7:6 ENMODE

5:3 RSVD

11

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

* When LDO2 is turned off, PCA9450/A transitions to READY mode

000

Reserved

LDO2 output voltage

Programmable from 0.8 V to 1.15 V in 50 mV step

000b = 0.8 V

001b = 0.85 V

010b = 0.9 V

2:0 L2_OUT

R/W

001

011b = 0.95 V

100b = 1.0 V

101b = 1.05 V

110b = 1.1 V

111b = 1.15 V

8.2.34 0x23 LDO3CTRL

LDO3 control register for enable and voltage

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

Table 56.ꢀ0x23 LDO3CTRL

0x23 – LDO3CTRL

Reset Type

O

Bit

Name

Type

Reset Description

LDO3 Enable mode

00b = OFF

7:6 ENMODE

R/W

01

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

5

RSVD

R/W

0

Reserved

LDO3 output voltage

4:0 L3_OUT

0 1010

Programmable from 0.8 V to 3.3 V in 100 mV step, see Table 57

Table 57.ꢀLDO3 output voltage

0x00 : 0.80 V

0x01 : 0.90 V

0x02 : 1.00 V

0x03 : 1.10 V

0x04 : 1.20 V

0x05 : 1.30 V

0x06 : 1.40 V

0x07 : 1.50 V

0x8 : 1.60 V

0x10 : 2.40 V

0x11 : 2.50 V

0x12 : 2.60 V

0x13 : 2.70 V

0x14 : 2.80 V

0x15 : 2.90 V

0x16 : 3.00 V

0x17 : 3.10 V

0x18 : 3.20 V

0x19 : 3.30 V

0x1A : 3.30 V

0x1B : 3.30 V

0x1C : 3.30 V

0x1D : 3.30 V

0x1E : 3.30 V

0x1F : 3.30 V

0x9 : 1.70 V

0xA : 1.80 V

0xB : 1.90 V

0xC : 2.00 V

0xD : 2.10 V

0xE : 2.20 V

0xF : 2.30 V

8.2.35 0x24 LDO4CTRL

LDO4 control register for enable and voltage

Table 58.ꢀ0x24 LDO4CTRL

0x24 – LDO4CTRL

Reset Type

O

Bit

Name

Type

Reset Description

LDO4 Enable mode

00b = OFF (PCA9450B/PCA9450C)

7:6 ENMODE

R/W

01

01b = ON by PMIC_ON_REQ = H (PCA9450A)

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

5

RSVD

R/W

0

Reserved

LDO4 output voltage

4:0 L4_OUT

0 0001

Programmable from 0.8 V to 3.3 V in 100 mV step, see Table 59

Table 59.ꢀLDO4 output voltage

0x00 : 0.80 V

0x01 : 0.90 V

0x02 : 1.00 V

0x8 : 1.60 V

0x10 : 2.40 V

0x11 : 2.50 V

0x12 : 2.60 V

0x18 : 3.20 V

0x19 : 3.30 V

0x1A : 3.30 V

0x9 : 1.70 V

0xA : 1.80 V

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

0x03 : 1.10 V

0x04 : 1.20 V

0x05 : 1.30 V

0x06 : 1.40 V

0x07 : 1.50 V

0xB : 1.90 V

0xC : 2.00 V

0xD : 2.10 V

0xE : 2.20 V

0xF : 2.30 V

0x13 : 2.70 V

0x14 : 2.80 V

0x15 : 2.90 V

0x16 : 3.00 V

0x17 : 3.10 V

0x1B : 3.30 V

0x1C : 3.30 V

0x1D : 3.30 V

0x1E : 3.30 V

0x1F : 3.30 V

8.2.36 0x25 LDO5CTRL_L

LDO5 control register for enable and voltage when SD_VSEL is low

Table 60.ꢀ0x25 LDO5CTRL_L

0x25 – LDO5CTRL_L

Bit Name

Reset Type

O

Type

Reset Description

LDO5 Enable mode

00b = OFF

7:6 ENMODE

R/W

01

01b = ON by PMIC_ON_REQ = H

10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L

11b = Always ON

5:4 RSVD

R/W

00

Reserved

LDO5 output voltage when SD_VSEL = Low

3:0 L5_OUT_L

1111

Programmable from 1.8 V to 3.3 V in 100 mV step, see Table 61

Table 61.ꢀLDO5 output voltage when SD_VSEL = Low

0x00 : 1.80 V

0x01 : 1.90 V

0x02 : 2.00 V

0x03 : 2.10 V

0x4 : 2.20 V

0x5 : 2.30 V

0x6 : 2.40 V

0x7 : 2.50 V

0x8 : 2.60 V

0x9 : 2.70 V

0xA : 2.80 V

0xB : 2.90 V

0xC : 3.00 V

0xD : 3.10 V

0xE : 3.20 V

0xF : 3.30 V

8.2.37 0x26 LDO5CTRL_H

LDO5 control register for enable and voltage when SD_VSEL is High

Table 62.ꢀ0x26 LDO5CTRL_H

0x26 – LDO5CTRL_H

Bit Name

Reset Type

O

Type

R/W

Reset Description

7:6 RSVD

5:4 RSVD

00

Reserved

LDO5 output voltage when SD_VSEL = High

Programmable from 1.8 V to 3.3 V in 100 mV step, see Table 63

3:0 L5_OUT_H

R/W

0000

Table 63.ꢀLDO5 output voltage when SD_VSEL = High

0x00 : 1.80 V 0x4 : 2.20 V 0x8 : 2.60 V

0xC : 3.00 V

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0x01 : 1.90 V

0x02 : 2.00 V

0x03 : 2.10 V

0x5 : 2.30 V

0x6 : 2.40 V

0x7 : 2.50 V

0x9 : 2.70 V

0xA : 2.80 V

0xB : 2.90 V

0xD : 3.10 V

0xE : 3.20 V

0xF : 3.30 V

8.2.38 0x2A LOADSW_CTRL

Load switch control register for active discharge, short/over current and enable

Table 64.ꢀ0x2A LOADSW_CTRL

0x2A – LOADSW_CTRL

Reset Type

O

Bit

Name

Type

R/W

Reset Description

Load switch active discharge

7

SW_AD

1

0b = Always disable active discharge resistor

1b = Enable active discharge resistor when it is OFF

6:5 RSVD

00

0

Reserved

When switch detects short circuit current

4

SW_SC

0b = Turned OFF and set SWEN[1:0] are set to 00b automatically

1b = Turned off and restart in 100 ms

When load switch detects over current

00b = Turned OFF and set SWEN[1:0] are set to 00b automatically

01b = Turned off and restart in 100 ms

10b, 11b = stay ON

3:2 SW_OC

1:0 SWEN

R/W

01

SW Enable control

00b = Forced OFF

01b = Enabled by SW_EN pin

10b = Forced ON

11b = Forced ON

8.2.39 0x2B VRFLT1_STS

Voltage regulator fault status register. It is latched to 1 once corresponding regulator

detects fault. If the bit is overwritten to 1, the corresponding bit is newly updated by

current status.

Table 65.ꢀ0x2B VRFLT1_STS

0x2B – VRFLT1_STS

Reset Type

S

Bit Name

Type

Reset Description

Load SW OCP status, deglitched with t_{DEB_POKB_SW}

0 = Load SW doesn’t exceed current limit or is OFF

1 = Load SW exceeded current limit

7

6

5

SW_OCP

RSVD

R/W/C

0

Reserved

BUCK6 Fault status, deglitched with t_{DEB_POKB}

0b = BUCK6 output is good or BUCK6 is OFF

1b = BUCK6 output falls below 80 % of target

BUCK6_FLT

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0x2B – VRFLT1_STS

Bit Name

Reset Type

S

Type

Reset Description

BUCK5 Fault status, deglitched with t_{DEB_POKB}

0b = BUCK5 output is good or BUCK5 is OFF

1b = BUCK5 output falls below 80 % of target

4

3

2

1

0

BUCK5_FLT

BUCK4_FLT

BUCK3_FLT

BUCK2_FLT

BUCK1_FLT

R/W/C

0

BUCK4 Fault status, deglitched with t_{DEB_POKB}

0b = BUCK4 output is good or BUCK4 is OFF

1b = BUCK4 output is below 80 %

R/W/C

BUCK3 Fault status, deglitched with t_{DEB_POKB}

0b = BUCK3 output is good or BUCK3 is OFF

1b = BUCK3 output falls below 80 % of target

BUCK2 Fault status, deglitched with t_{DEB_POKB}

0b = BUCK2 output is good or BUCK2 is OFF

1b = BUCK2 output falls below 80 % of target

BUCK1 Fault status, deglitched with t_{DEB_POKB}

0b = BUCK1 output is good or BUCK1 is OFF

1b = BUCK1 output falls below 80 % of target

8.2.40 0x2C VRFLT2_STS

Voltage regulator fault status register. It is latched to 1 once corresponding regulator

detects fault. If the bit is overwritten to 1, the corresponding bit is newly updated by

current status.

Table 66.ꢀ0x2C VRFLT2_STS

0x2C – VRFLT2_STS

Reset Type

S

Bit Name

Type

Reset Description

7:5 RSVD

R/W/C

000

Reserved

LDO5 Fault status, deglitched with t_{DEB_POKB}

0b = LDO5 output is good or LDO5 is OFF

1b = LDO5 output falls below 80 % of target

4

3

2

1

0

LDO5_FLT

LDO4_FLT

LDO3_FLT

LDO2_FLT

LDO1_FLT

R/W/C

0

LDO4 Fault status, deglitched with t_{DEB_POKB}

0b = LDO4 output is good or LDO4 is OFF

1b = LDO4 output falls below 80 % of target

0

LDO3 Fault status, deglitched with t_{DEB_POKB}

0b = LDO3 output is good or LDO3 is OFF

1b = LDO3 output falls below 80 % of target

LDO2 Fault status, deglitched with t_{DEB_POKB}

0b = LDO2 output is good or LDO2 is OFF

1b = LDO2 output falls below 80 % of target

LDO1 Fault status, deglitched with t_{DEB_POKB}

0b = LDO1 output is good or LDO1 is OFF

1b = LDO1 output falls below 80 % of target

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8.2.41 0x2D VRFLT1_MASK

VR fault mask bit. Once the bit is masked, PCA9450 doesn’t enter Fault shutdown even if

fault condition of corresponding regulator happens

Table 67.ꢀ0x2D VRFLT1_MASK

0x2D – VRFLT1_MASK

Reset Type

S

Bit

7

Name

RSVD

Type

R/W

Reset Description

0

Reserved

6

BUCK6 FLT mask

0b = Unmask

5

4

3

2

1

0

BUCK6_FLT_M

BUCK5_FLT_M

BUCK4_FLT_M

BUCK3_FLT_M

BUCK2_FLT_M

BUCK1_FLT_M

R/W

1

1b = Masked

BUCK5 FLT mask

0b = Unmask

1b = Masked

BUCK4 FLT mask

0b = Unmask

1b = Masked

BUCK3 FLT mask

0b = Unmask

1b = Masked

BUCK2 FLT mask

0b = Unmask

1b = Masked

BUCK1 FLT mask

0b = Unmask

1b = Masked

8.2.42 0x2E VRFLT2_MASK

VR fault mask bit. Once the bit is masked, PCA9450 doesn’t enter Fault shutdown even if

fault condition of corresponding regulator happens

Table 68.ꢀ0x2E VRFLT2_MASK

0x2E – VRFLT2_MASK

Reset Type

S

Bit Name

Type

Reset Description

7

6

5

RSVD

R/W/C

0

Reserved

LDO5 FLT mask

0b = Unmask

1b = Masked

4

LDO5_FLT_M

LDO4_FLT_M

R/W

1

LDO4 FLT mask

0b = Unmask

1b = Masked

3

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0x2E – VRFLT2_MASK

Bit Name

Reset Type

S

Type

Reset Description

LDO3 FLT mask

0b = Unmask

2

1

0

LDO3_FLT_M

LDO2_FLT_M

LDO1_FLT_M

R/W

1

1b = Masked

LDO2 FLT mask

0b = Unmask

1b = Masked

R/W

LDO1 FLT mask

0b = Unmask

1b = Masked

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9 Application design-in information

9.1 Reference schematic

9.1.1 PCA9450A reference schematic

PCA9450A reference schematic with i.MX 8M Mini is illustrated in Figure 21.

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VSYS

VINT

PCA9450A

SYS

C1

1 µF

SBIAS, REF,

UVLO,

TSHDN

INB26

LX2

DVS

INT LDO

LDO1

VSYS

C2

1 µF

C11

10 µF

VDD_ARM

L1

0.47 µH

BUCK2

0.85 V

3 A

C12

22 µF

PMIC_RST_B

PMIC_ON_REQ

PMIC_STBY_REQ

WDOG_B

PGND

R_SNSP2

INB13

DVS

VSYS

C13

10 µF

NVCC_SNVS

LDO1

VDD_SOC

LX1

R1

100 kΩ

L2

0.47 µH

C14

22 µF

BUCK1

0.85 V

3 A

RTC_RESET_B

POR_B

NVCC_1V8

BUCK5

R_SNSP1

DUAL

PHASE

CONFIG

IN

R2

R3

R4

4.7 kΩ

100 kΩ

INB13

SCL

DVS

VSYS

VDD_VPU

VDD_GPU

VDD_DRAM

PCA9450

C15

10 µF

l2C

INTERFACE

SDA

LX3

IRQ_B

L3

0.47 µH

C16

22 µF

BUCK3

0.85 V

3 A

NVCC_1V8

BUCK5

VINT

SWIN

R_SNSP3_CFG

R5

4.7 kΩ

R6

4.7 kΩ

i.MX 8M

Mini

SCLL

SDAL

l2C LEVEL

TRANSLATOR

INB45

C17

VSYS

10 µF

3V3 V

LX4

NVCC_3V3

BUCK4

ON/OFF

CONTROL

AND

I2C

REGISTER

R7

R8

L4

0.47 µH

C18

22 µF

4.7 kΩ

BUCK4

3.3 V

3 A

SDAH

SCLH

i.MX 8M

Mini

C3

XTAL_IN

BUCK4FB

INB45

LX5

32.768 kHz

X-TAL DRIVER

X1, X-tal

XTAL_OUT

VSYS

C4

LDO1

C19

4.7 µF

RTC_XTALI

CLK_32K_OUT

INL1

NVCC_1V8

L5

C20

22 µF

BUCK5

1.8 V

2 A

SYS

0.47 µH

C5

4.7 µF

LDO1

1.8 V

10 mA

LDO1

LDO2

LDO3

LDO4

LDO5

NVCC_SNVS

VDD_SNVS

VDDA

C6

1 µF

BUCK5FB

INB26

LX6

LDO2

0.8 V

10 mA

VSYS

C21

4.7 µF

C7

1 µF

NVCC_DRAM

L6

BUCK6

1.1 V

2 A

C22

22 µF

0.47 µH

LDO3

1.8 V

300 mA

C8

2.2 µF

BUCK6FB

SWIN

LDO4

0.9 V

200 mA

VDD_MIPI_0P9

NVCC_SD2

C9

1 µF

BUCK 4

C23

1 µF

LOAD SW

DRIVER

SWOUT

SW_EN

SD_CARD

LDO5

3.3 V/1.8 V

150 mA

SD_CARD

C24

1 µF

C10

1 µF

SD_VSEL

BUCK4

IN

LDO

1.2 V

150 mA

VDD_MIPI_1P2

EN

BUCK_AGND

AGND

EP

aaa-035724

Figure 21.ꢀPCA9450A application schematic

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9.1.2 PCA9450B reference schematic

PCA9450B reference schematic with i.MX 8M Nano is illustrated in Figure 22.

VSYS

PCA9450B

SYS

C1

VINT

C2

1 µF

SBIAS, REF,

UVLO,

TSHDN

INB26

LX2

DVS

INT LDO

LDO1

VSYS

C11

10 µF

1 µF

VDD_ARM

L1

0.47 µH

BUCK2

0.85 V

3 A

C12

22 µF

PMIC_RST_B

PMIC_ON_REQ

PMIC_STBY_REQ

WDOG_B

PGND

R_SNSP2

INB13

VDD_SOC

VDD_VPU

VDD_GPU

VDD_DRAM

DVS

VSYS

C14

C13

10 µF

NVCC_SNVS

LDO1

LX1

R1

100 kΩ

L2

0.47 µH

BUCK1

0.85 V

3 A

RTC_RESET_B

22 µF

POR_B

NVCC_1V8

BUCK5

R_SNSP1

DUAL

PHASE

CONFIG

IN

R2

R3

R4

4.7 kΩ

100 kΩ

INB13

LX3

SCL

DVS

VSYS

PCA9450

l2C

INTERFACE

SDA

IRQ_B

BUCK3

0.85 V

3 A

NVCC_1V8

BUCK5

VINT

SWIN

R_SNSP3_CFG

R5

4.7 kΩ

R6

4.7 kΩ

i.MX 8M

Nano

SCLL

SDAL

l2C LEVEL

TRANSLATOR

INB45

C17

VSYS

10 µF

3V3 V

LX4

NVCC_3V3

BUCK4

ON/OFF

CONTROL

AND

I2C

REGISTER

R7

R8

L4

0.47 µH

C18

22 µF

4.7 kΩ

BUCK4

3.3 V

3 A

SDAH

SCLH

i.MX 8M

Nano

C3

XTAL_IN

BUCK4FB

INB45

LX5

32.768 kHz

X-TAL DRIVER

X1, X-tal

XTAL_OUT

VSYS

C4

LDO1

C19

4.7 µF

RTC_XTALI

CLK_32K_OUT

INL1

NVCC_1V8

L5

C20

22 µF

BUCK5

1.8 V

2 A

SYS

0.47 µH

C5

4.7 µF

LDO1

1.8 V

10 mA

LDO1

LDO2

LDO3

LDO4

NVCC_SNVS

VDD_SNVS

VDDA

C6

1 µF

BUCK5FB

INB26

LX6

LDO2

0.8 V

10 mA

VSYS

C21

4.7 µF

C7

1 µF

NVCC_DRAM

L6

BUCK6

1.1 V

2 A

C22

22 µF

0.47 µH

LDO3

1.8 V

300 mA

C8

2.2 µF

BUCK6FB

SWIN

LDO4

0.9 V

200 mA

VDD_MIPI_1P2

NVCC_SD2

C9

1 µF

BUCK 4

C23

1 µF

LOAD SW

DRIVER

SWOUT

SW_EN

SD_CARD

LDO5

3.3 V/1.8 V

150 mA

SD_CARD

LDO5

C24

1 µF

C10

1 µF

SD_VSEL

VDD_MIPI_0P9

BUCK_AGND

AGND

EP

aaa-035725

Figure 22.ꢀPCA9450B application schematic

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9.1.3 PCA9450C reference schematic

PCA9450C reference schematic with i.MX 8M Plus is illustrated in Figure 23

VSYS

PCA9450C

SYS

C1

VINT

C2

1 µF

SBIAS, REF,

UVLO,

TSHDN

INB26

LX2

DVS

INT LDO

LDO1

VSYS

C11

10 µF

1 µF

VDD_ARM

L1

0.47 µH

BUCK2

0.85 V

3 A

C12

22 µF

PMIC_RST_B

PMIC_ON_REQ

PMIC_STBY_REQ

WDOG_B

PGND

R_SNSP2

INB13

VDD_SOC

VDD_VPU

VDD_GPU

VDD_DRAM

DVS

VSYS

C14

C13

10 µF

NVCC_SNVS

LDO1

LX1

R1

100 kΩ

L2

0.47 µH

BUCK1

0.85 V

3 A

RTC_RESET_B

22 µF

POR_B

NVCC_1V8

BUCK5

R_SNSP1

DUAL

PHASE

CONFIG

IN

R2

R3

R4

4.7 kΩ

100 kΩ

INB13

LX3

SCL

DVS

VSYS

PCA9450

C15

10 µF

l2C

INTERFACE

SDA

IRQ_B

L3

0.47 µH

BUCK3

0.85 V

3 A

C16

22 µF

NVCC_1V8

BUCK5

VINT

SWIN

R_SNSP3_CFG

R5

4.7 kΩ

R6

4.7 kΩ

i.MX 8M

Plus

SCLL

SDAL

l2C LEVEL

TRANSLATOR

INB45

C17

VSYS

10 µF

3V3 V

LX4

NVCC_3V3

BUCK4

ON/OFF

CONTROL

AND

I2C

REGISTER

R7

R8

L4

0.47 µH

C18

22 µF

4.7 kΩ

BUCK4

3.3 V

3 A

SDAH

SCLH

i.MX 8M

Plus

C3

XTAL_IN

BUCK4FB

INB45

LX5

32.768 kHz

X-TAL DRIVER

X1, X-tal

XTAL_OUT

VSYS

C4

LDO1

C19

4.7 µF

RTC_XTALI

CLK_32K_OUT

INL1

NVCC_1V8

L5

C20

22 µF

BUCK5

1.8 V

2 A

SYS

0.47 µH

C5

4.7 µF

LDO1

1.8 V

10 mA

LDO1

LDO2

LDO3

LDO4

NVCC_SNVS

VDD_SNVS

VDDA

C6

1 µF

BUCK5FB

INB26

LX6

LDO2

0.8 V

10 mA

VSYS

C21

4.7 µF

C7

1 µF

NVCC_DRAM

L6

BUCK6

1.1 V

2 A

C22

22 µF

0.47 µH

LDO3

1.8 V

300 mA

C8

2.2 µF

BUCK6FB

SWIN

LDO4

0.9 V

200 mA

C9

1 µF

BUCK 4

C23

1 µF

LOAD SW

DRIVER

SWOUT

SW_EN

SD_CARD

LDO5

3.3 V/1.8 V

150 mA

NVCC_SD2

SD_CARD

LDO5

C24

1 µF

C10

1 µF

SD_VSEL

BUCK_AGND

AGND

EP

aaa-035726

Figure 23.ꢀPCA9450C application schematic

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9.2 Typical application

Please follow the recommendations below for your schematic/PCB layout design:

• 1 μF bypass capacitor on VINT and VSYS, located as close as possible to those pins to

ground

• Input capacitors must be present on the INB and INL supplies if used

• Output inductors and capacitors must be used on the outputs of the BUCK converters if

used

• Output capacitors must be used on the outputs of the LDOs

9.2.1 Buck regulators

9.2.1.1 Inductor selection for buck converters

Each of the converters on PCA9450 typically uses a 0.47 μH output inductor which

has to be rated for its DC resistance and saturation current. The DC resistance of the

inductance influences directly the efficiency of the converter. Therefore, an inductor with

lowest DC resistance must be selected for highest efficiency.

Equation 1 calculates the maximum inductor current under static load conditions. The

saturation current of the inductor must be rated higher than the maximum inductor

current as calculated with Equation 2. This is needed because during heavy load

transient the inductor current rises above the calculated value.

(1)

(2)

Where

• f = switching frequency (2 MHz)

• L = Inductance

• ΔI_L= Peak to peak inductor ripple current

• I_L.max= Maximum inductor current

A conservative approach is to select the inductor current rating just for the maximum

switch current of the PCA9450

Table 69 shows possible inductors list.

Table 69.ꢀTested inductor list

Buck

Vendor

Sunlord

Murata

Sunlord

Part number

Size

2520

2016

DCR [mΩ]

Isat [A]

5.6

Itemp [A]

4.0

WPN252012HR47MT

1239AS-H-R47M

29

39

28

BUCK1, BUCK2,

BUCK3, BUCK4

3.8

3.7

BUCK5, BUCK6

WPN201610UR47MT

5.0

4.1

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Buck

Vendor

Part number

Size

DCR [mΩ]

Isat [A]

Itemp [A]

Murata

1286AS-H-R47M

2016

52

3.4

3.2

9.2.1.2 Output capacitor selection for buck converters

The fast response adaptive constant ON time control scheme of the buck converters

implemented on PCA9450 allows the use of a single typical 22 µF ceramic capacitor for

each converter output without compromising on output overshoot/undershoot voltage

ripple during heavy load transients. Ceramic capacitors having low ESR values have the

lowest output voltage ripple and are recommended.

If ceramic output capacitors are used, the capacitor RMS ripple current rating always

meets the application requirements. Just for completeness, the RMS ripple current is

calculated in Equation 3.

(3)

At nominal load current, the inductive converters operate in PWM mode. The overall

output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR

plus the voltage ripple caused by charging and discharging the output capacitor:

(4)

Where

• The highest output voltage ripple occurs at the highest input voltage Vin.

At light load currents, the converters operate in PFM mode and the output voltage

ripple is dependent on the output capacitor value. The output voltage ripple is set by the

internal comparator delay and the external capacitor. The typical output voltage ripple is

less than 1 % of the nominal output voltage.

9.2.1.3 Input capacitor selection for buck converters

Low ESR input capacitor is highly recommended for best input voltage filtering and

minimizing the interference with other circuits caused by high input voltage spikes

because of the nature of buck converter. Each DC-DC converter requires a 10 μF

ceramic input capacitor on its input pins. The input capacitor could be increased without

any limit for better input voltage filtering.

9.2.2 Crystal oscillator

9.2.2.1 Crystal selection

The most important parameters when choosing a crystal are:

• Crystal's required effective load capacitance (typically 6 pF to 15 pF)

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• Crystal's ESR (typically 30 kΩ to 100 kΩ)

• Tolerance (typically 5 ppm to 30 ppm)

All of these crystal parameters can usually be found in the crystal datasheet.

9.2.2.2 Effective load capacitance

The crystal oscillator (see Figure 24) uses two load capacitors, C_L1and C_L2, as load

for the crystal. These capacitors generate, together with the crystal's inductance, the

required 180° phase shift of the feedback loop.

180°

XTAL_OUT

XTAL_IN

32.768 kHz

Xtal

C

L2_P

L1_P

L1

L2

180°

aaa-035750

Figure 24.ꢀCrystal oscillator

From the view of the crystal, these capacitors are a serial connection through GND.

Hence, if using two equal capacitors, the values of these capacitors must be twice the

required load capacitance. It is also important to consider PCB parasitic capacitances for

the calculation of the necessary capacitors according to Equation 5.

(5)

Where:

• C’_L1= C_L1+ C_{L1_P}, C_{L1_P}is PCB parasitic capacitance.

• C’_L2= C_L2+ C_{L2_P}, C_{L2_P}is PCB parasitic capacitance.

When using equal capacitors for C_L1and C_L2and a symmetric layout with equal parasitic

capacitance on both crystal pins, the effective load capacitance is shown in Equation 6.

(6)

Example:

Crystal requires 12 pF load.

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Parasitic capacitance per pin is 2 pF.

C_L1= (2 × C_Load) – C_{L1_P}= (2 × 12 pF) – 2 pF = 22 pF

C_L2= C_L1= 22 pF

9.2.2.3 Frequency tuning

The crystal oscillator frequency is very much dependent on the load capacitance that is

connected. Therefore, measuring the oscillator frequency gives a good indication if the

load capacitors that are used match the crystal requirements. This measurement also

automatically includes the parasitic PCB and pin capacitances of the application.

It is strongly recommended not to measure the oscillator frequency directly at the crystal

pins. The capacitance at the crystal pins is in the range of 10 pF, and the impedance on

this signal line is several megaohms. A typical passive probe has a capacitance in the

range of 10 pF and an input impedance of approximately 10 MΩ. Both values are in the

range of the oscillator characteristics and heavily influence the behavior of the crystal

oscillators. Instead, it is recommended to measure frequency at CLK_32K_OUT pin.

Assuming the crystal itself has no tolerance, too low a capacitive load results in a higher

oscillator frequency than expected and, vice versa, the frequency is lower than the

nominal value, if the load is too high. Therefore, if the oscillation frequency is too high,

the value of load capacitors must be increased. When too low frequency is measured,

it is necessary to decrease the value of the load capacitors. Comparing the finally

optimized capacitors with the crystal data sheet value for load capacitance gives the

parasitic capacitance added by the PCB layout and pins.

9.3 Layout guide

Layout guide is shown in Figure 25.

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10 µF

(0603)

22 µF

(0603)

BUCK2

BUCK6

0.47 µH

(2520)

BUCK5

0.47 µH

(2016)

1 µF

(0402)

LDO5

VSYS

LDO3

LX6

LX2

INB26

4.7 µF

(0402)

INL1

1 µF

(0402)

I2C

LDO4

42

41

40

39

38

37

36

35

1

2

LDO2

1 µF

(0402)

3

BUCK2

LDO1

VINT

1 µF

(0402)

0.47 µH

(2520)

4

1 µF

(0402)

5

6

LX1

7

EP

10 µF

(0603)

8

9

34

33

32

31

30

29

INB13

10

11

12

13

14

10 µF

(0603)

PGND

LX3

0.47 µH

(2520)

BUCK1

LX5

INB4/5

LX4

SWIN

SWOUT

0.47 µH

(2520)

10 µF

(0603)

22 µF

(0603)

BUCK4

BUCK5

aaa-035727

Figure 25.ꢀPCA9450 layout

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10 Limiting values

Table 70.ꢀLimiting values

(Absolute maximum ratings)

Explanation

Conditions

Min

Max

Unit

VSYS, INB13, INB26, INB45, INL1,

SWIN

-0.5

+6.0

V

SWOUT

LX1, LX3

LX2, LX6

LX4, LX5

-0.5

SWIN + 0.5

INB13 + 0.5

INB26 + 0.5

INB45 + 0.5

V

R_SNSP1, R_SNSP2, R_SNSP3_

CFG

-0.5

VSYS + 0.5

V

BUCK_AGND, AGND

-0.5

+0.5

V

Voltage range

(with respect to

EP)

BUCK4FB, BUCK5FB, BUCK6FB

LDO1, LDO2, LDO3, LDO4, LDO5

XTAL_IN, XTAL_OUT

VSYS + 0.5

V_INL1+ 0.5

VSYS + 0.5

RTC_RESET_B, PMIC_RST_B,

CLK_32K_OUT

-0.5

LDO1 + 0.5

VSYS + 0.5

V

PMIC_ON_REQ, POR_B PMIC_

STBY_REQ, WDOG_B, IRQ_B,

SCL, SDA, SD_VSEL, SW_EN

SCLH, SDAH

SCLL, SDAL

VINT

-0.5

SWIN + 0.5

VINT + 0.5

+2.0

V

A

LX1, LX2, LX3, LX4

LX5, LX6

RMS current

5.0

Output Current

4.0

SWIN, SWOUT

0.5

Junction

temperature

-40

+150

°C

HBM (JESD22-001)

-2

+2

kV

V

V_ESD

All pins

CDM (JESD22-C101E)

-500

+500

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11 Recommended operating conditions

Table 71.ꢀRecommended Operating Conditions

Explanation

Conditions

Min

2.7

Max

5.5

Unit

V

VSYS, INL1

INB13, INB26, INB45

SWIN

Voltage range

(with respect to

EP)

5.5

V

5.5

V

Junction

temperature

-40

+125

+105

°C

Ambient

temperature

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12 Thermal characteristics

Table 72.ꢀThermal characteristics

Symbol

Parameter

Conditions

Typ

Unit

[1] [2]

Rth(j-a)

thermal resistance from junction to ambient

32.1

°C/W

[1] Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is solely for a thermal

performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an

application-specific environment

[2] Thermal test board meets JEDEC specification for this package (JESD51-9)

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13 Electrical characteristics

13.1 Top level parameter

Table 73.ꢀTop level parameter

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8 V, T_amb= -40 °C ~ +105 °C

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Quiescent Current

LDO1 and LDO2 are ON and

no load, other regulators are

OFF, CLK_32K_OUT enabled,

PMIC_ON_REQ = L, T_amb= 25 °C

23

50

μA

I_{Q_SNVS}

VSYS SNVS Current

LDO1 and LDO2 are ON and

no load, other regulators are

OFF, CLK_32K_OUT enabled,

PMIC_ON_REQ = L, T_amb= -40 °C

~105 °C

23

120

350

μA

LDO1, LDO2, LDO3, LDO4, LDO5,

BUCK1, BUCK3, BUCK4, BUCK5,

BUCK6 are ON and no load. PMIC_

ON_REQ = H, PMIC_STBY_REQ =

H

I_{Q_STADNDBY}VSYS Standby current

220

VSYS

V_{SYS_UVLO}

VSYS UVLO

VSYS Rising

2.85

2.2

3.0

3.15

2.6

V

V_{SYS_UVLO_H}VSYS UVLO Hysteresis VSYS Falling

200

2.4

mV

V

V_{SYS_POR}

VSYS POR

VSYS Rising

VSYS Falling

V_{SYS_POR_H}VSYS POR Hysteresis

200

mV

VINT

Internal Power supply

V_INT

LDO

VSYS = 3.8 V

1.7

1.8

1.9

V

Low VSYS

Low VSYS threshold above

V_{SYS_UVLO}, LOW_VSYS [7:6] = 01b

V_{LOW_VSYS}

Low VSYS

150

200

110

250

mV

V_{LOW_VSYS_}

Low VSYS Hysteresis

HYS

Thermal Shutdown

T_JSHDNThermal Shutdown

T_J105

Tj Rising, 15 °C hysteresis

150

105

125

°C

Thermal interrupt1

Thermal interrupt2

95

125

145

T_J125

115

Logic and Control signals

PMIC_ON_REQ, PMIC_STBY_

REQ, WDOG_B, SD_VSEL, SW_

EN, PMIC_RST_B

V_IL

Input Low level

0.4

V

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Symbol

Parameter

Conditions

Min

Typ

Max

Unit

PMIC_ON_REQ, PMIC_STBY_

REQ, WDOG_B, SD_VSEL, SW_

EN, PMIC_RST_B

V_IH

Input High level

1.4

V

PMIC_ON_REQ, PMIC_STBY_

REQ, WDOG_B, SD_VSEL:

Logic Input leakage

current

I_LEAK

-0.5

+0.5

0.4

μA

V_Logic= 5.5 V, VSYS = 5.5 V

Internal Pull-down

resistor

R_PD

V_OL

R_PU

SW_EN

1.2

MΩ

V

RTC_RESET_B, IRQB, POR_B, I_OL

= 6 mA

Output Low level

RTC_RESET_B, PMIC_RST_B to

LDO1

Internal Pull-up resistor

100

KΩ

Logic signal (PCA9450B/ PCA9450C)

V_IL

V_IH

Input Low level

Input High level

R_SNSP3_CFG

0.4

+1

V

1.4

-1

R_SNSP3_CFG

Logic Input leakage

current

I_LEAK

μA

V_Logic= 5.5 V, VSYS = 5.5 V

Timing spec

t_{DEB_POKB}

Debounce time of

regulator POKB

320

240

90

400

300

120

50

480

360

150

60

μs

ms

Debounce time of Load

SW POKB

t_{DEB_POKB_SW}

Debounce time of

WDOG_B

t_{DEB_WDOGB}

t_{DEB_PMIC_}

Debounce time of

PMIC_RST_B

T_PMIC_RST_DEB[2:0] = 001b

40

RST_B

Time to 90 % of LDO1

from VSYS UVLO

detected

t_{SNVS_PU}

16

20

24

ms

Time to RTC_RESET_B

release from LDO2 POK

t_{RTC_RST}

t_{32K_EN}

16

8

20

10

24

12

ms

Time to 32K buffer

enable from LDO2 POK

Time to transition to Xtal

osc after RTC_RESET_

B release

t_{RTC_TRAN}

0.8

1

1.2

sec

PMIC_ON_REQ high

debounce time

t_{ON_DEB}

t_STEP

t_{OFF_STEP}

t_{OFF_DEB}

Programmable, Ton_Deb[1:0] = 01b 16

Programmable, Tstep[1:0] = 01b 1.6

Programmable, Toff_step[1:0] = 10b 6

20

2

24

ms

μs

Time step to turn on

each regulator

2.4

10

Time step to turn off

each regulator

8

PMIC_ON_REQ low

debounce time

Programmable, Toff_Deb = 0b

90

120

150

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Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Time from LDO5 POK to

POR_B release during

Power on seq

t_PORB

16

20

24

ms

Fault time to POK after

t_{FLT_SD_PU}

regulator enable during At power up sequence

power up sequence

8

10

2

12

ms

POK mask time when

t_{FLT_POK_MSK}regulator is enabled at

RUN/Standby mode

1.6

2.4

Time to enter FAULT_

t_{FLT_THSD}

SD when thermal Fault

occurs

170

80

210

100

250

120

μs

Time to stay at FAULT_

SD to move other mode

t_{FLT_SD_STAY}

ms

Wait time to enter

At Standby and Run mode,

programmable, tFLT_SD_WAIT =

0b1

t_{FLT_SD_WAIT}FAULT_SD after fault

interrupt

80

Wait time to start power

t_RESTART

up after power down at

cold reset

Programmable, Trestart = 0b

200

16

250

20

300

24

ms

POR_B low time at

Warm reset

t_WRESET

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13.2 I2C level translator

Table 74.ꢀI2C level translator

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8 V, T_amb= -40 °C ~ +105 °C

Symbol

VDDH

I_VDDH

Parameter

Conditions

Min

Typ

Max

5.5

5

Unit

V

Operating voltage

Shutdown current

Internally tied to SWIN

SWIN = 3.3 V, I2C_LT_EN bit = 0b

2.7

1

μA

SWIN = 3.3 V, I2C_LT_EN bit = 1b,

SCLL, SDAL = 1.8 V

I_VDDH

Active current

60

90

μA

SWIN = 3.3 V, I2C_LT_EN bit = 1b,

SCLL, SDAL = 0 V

715

850

VINT –

0.2

V_IH

V_IL

High level input voltage SWIN = 3.3 V, I2C_LT_EN bit = 1b

V

Low level input voltage

High level output voltage

SWIN = 3.3 V, I2C_LT_EN bit = 1b

0.15

0.4

SWIN = 3.3 V, I2C_LT_EN bit = 1b, 0.75 *

V_OH

I_OL= 20 μA

SWIN

SWIN = 3.3 V, I2C_LT_EN bit = 1b,

I_OL= 1 mA

V_OL

Low level output voltage

V

Input Output

capacitance

[1]

C_I/O

SWIN = 3.3 V

5

pF

ns

High to Low propagation SWIN = 3.3 V, SCL/SDA to SCLH/

delay SDAH

[1]

t_PHL

4.0

5.0

4.0

4.7

6.8

4.5

Low to High propagation SWIN = 3.3 V, SCL/SDA to SCLH/

delay SDAH

[1]

t_PLH

High to Low propagation SWIN = 3.3 V, SCLH/SDAH to SCL/

delay SDA

[1]

t_PHL

Low to High propagation SWIN = 3.3 V, SCLH/SDAH to SCL/

delay

[1]

t_PLH

4.0

SDA

[1]

t_en

Enable time

Data rate

SWIN = 3.3 V, from I2C enable

100

μs

[1]

f_data

20

Mbps

[1] Guaranteed by design

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13.3 BUCK1 (PCA9560A/PCA9450B)

Table 75.ꢀBUCK1 (PCA9560A/PCA9450B)

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8 V, V_BUCK1= 0.85 V, C_OUT= 22 μF, T_amb= -40 °C ~

+105 °C

Symbol

V_INB13

Parameter

Conditions

Min

Typ

Max

Unit

V

Input voltage range

Shutdown current

INB13 pin

2.85

5.5

I_Shutdown

Regulator disabled, V_INB13= 5.0 V

0.1

20

μA

Regulator enabled, No load, No

switching

I_Q

Quiescent current

μA

mA

V

I_{OUT_MAX}

V_BUCK1

Max Output Current

3000

0.6

Programmable Output

voltage range

I2C programmable, 12.5 mV step

2.1875

V_INB13= 3.8 V, V_{BUCK1_OUT}= 0.85 V,

IOUT = 0 A, FPWM mode, 25 °C

-0.6

+0.6

+2

%

DC Output Voltage

Accuracy

V_{BUCK1_OUT}

V_INB13= 3.8 V, V_{BUCK1_OUT}= 0.85 V, -2

IOUT = 0 A, FPWM mode

[1]

ΔV_OUT(ΔVINB)

DC Line regulation

DC Load regulation

V_INB13= 3 V to 5 V, I_OUT= I_{OUT_MAX}

2

3

mV/V

mV/A

0 mA < I_OUT< I_{OUT_MAX}, V_{BUCK1_OUT}

= 0.85 V

ΔV_OUT(ΔIOUT)

Transient Load

Response

I_OUTchanges 0 to I_{OUT_MAX}(1 A/μs

slope), V_{BUCK1_OUT}= 0.85 V

[1]

ΔV_OUT(ΔIOUT)

50

10

2

mV

[1]

ΔV_OUT

Output voltage Ripple

FPWM mode

mV

Switching Frequency in

CCM

f_SW

MHz

mΩ

V_INB13= 3.8 V, including bonding

wire

High Side P-FET R_DSON

Low Side N-FET R_DSON

87

45

R_DSON

V_INB13= 3.8 V, including bonding

wire

mΩ

High side current limit

Low side current limit

Startup time

V_INB13= 3.8 V

4.0

2.5

4.5

5.0

3.7

500

A

I_LIM

V_INB13= 3.8 V

3.0

A

[1]

t_START

EN rising to 90 % of output voltage

250

12.5

μs

[1]

V_RAMP

Output voltage slew rate Programmable, RAMP[1:0] = 01b

Soft-start slew rate

mV/μs

[1]

V_{soft_strup}

Output Active Discharge

Resistance

R_DIS

100

150

95

Ω

POK

L^[1]

Output Power good

Inductor value

85

%

0.47

µH

μF

[1]

C_OUT

Output capacitance

Minimum nominal capacitance

22

[1] Guaranteed by design

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13.4 Dual Phase BUCK1 (PCA9450C)

Table 76.ꢀDual Phase BUCK1 (PCA9450C)

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8 V, V_BUCK1= 0.85 V, C_OUT= 44 μF, T_amb= -40 °C ~

+105 °C

Symbol

V_INB13

Parameter

Conditions

Min

Typ

Max

Unit

V

Input voltage range

Shutdown current

INB13 pin

2.85

5.5

I_Shutdown

Regulator disabled, V_INB13= 5.0 V

0.2

20

μA

Regulator enabled, No load, No

switching

I_Q

Quiescent current

μA

mA

V

I_{OUT_MAX}

V_BUCK1

Max Output Current

6000

0.6

Programmable Output

voltage range

I2C programmable, 12.5 mV step

2.1875

V_INB13= 3.8 V, V_{BUCK1_OUT}= 0.85 V,

IOUT = 0 A, FPWM mode, 25 °C

-0.6

+0.6

+2

%

DC Output Voltage

Accuracy

V_{BUCK1_OUT}

V_INB13= 3.8 V, V_{BUCK1_OUT}= 0.85 V, -2

IOUT = 0 A, FPWM mode

[1]

ΔV_OUT(ΔVINB)

DC Line regulation

DC Load regulation

V_INB13= 3 V to 5 V, I_OUT= I_{OUT_MAX}

2

3

mV/V

mV/A

0 mA < I_OUT< I_{OUT_MAX}, V_{BUCK1_OUT}

= 0.85 V

ΔV_OUT(ΔIOUT)

Transient Load

Response

I_OUTchanges 0 to I_{OUT_MAX}(1 A/μs

slope), V_{BUCK3_OUT}= 0.85 V

[1]

ΔV_OUT(ΔIOUT)

50

10

2

mV

[1]

ΔV_OUT

Output voltage Ripple

FPWM mode

mV

Switching Frequency in

CCM

f_SW

MHz

mΩ

V_INB13= 3.8 V, including bonding

wire

High Side P-FET R_DSON

Low Side N-FET R_DSON

87

45

R_DSON

V_INB13= 3.8 V, including bonding

wire

mΩ

High side current limit

Low side current limit

Startup time

V_INB13= 3.8 V, each phase

EN rising to 90 % of output voltage

4.0

4.5

5.0

3.7

500

A

I_LIM

2.5

3.0

A

[1]

t_START

250

12.5

85

μs

[1]

V_RAMP

Output voltage slew rate Programmable, RAMP[1:0] = 01b

Soft-start slew rate

mV/μs

%

[1]

V_{soft_strup}

POK

R_DIS

L^[1]

Output Power good

75

44

95

Output Active Discharge

One phase buck

Resistance

100

150

Ω

Inductor value

Each phase

0.47

µH

μF

[1]

C_OUT

Output capacitance

Minimum nominal capacitance

[1] Guaranteed by design

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13.5 BUCK2

Table 77.ꢀBUCK2

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8 V, V_BUCK2= 0.85 V, C_OUT= 22 μF, T_amb= -40 °C ~

+105 °C

Symbol

V_INB26

Parameter

Conditions

Min

Typ

Max

Unit

V

Input voltage range

Shutdown current

INB26 pin

2.85

5.5

I_Shutdown

Regulator disabled, V_INB26= 5.0 V

0.1

20

μA

Regulator enabled, No load, No

switching

I_Q

Quiescent current

μA

mA

V

I_{OUT_MAX}

V_BUCK2

Max Output Current

3000

0.6

Programmable Output

voltage range

I2C programmable, 12.5 mV step

2.1875

V_INB26= 3.8 V, V_{BUCK2_OUT}

=

0.85 V, IOUT = 0A, FPWM mode, -0.6

25 °C

+0.6

+2

%

DC Output Voltage

Accuracy

V_{BUCK2_OUT}

V_INB26= 3.8 V, V_{BUCK2_OUT}

=

-2

0.85 V, IOUT = 0A, FPWM mode

[1]

ΔV_OUT(ΔVINB)

DC Line regulation

DC Load regulation

V_INB26= 3 V to 5 V, I_OUT= I_{OUT_MAX}

2

3

mV/V

mV/A

0 mA < I_OUT< I_{OUT_MAX}

,

ΔV_OUT(ΔIOUT)

V_{BUCK2_OUT}= 0.85 V

Transient Load

Response

I_OUTchanges 0 to I_{OUT_MAX}(1 A/μs

slope), V_{BUCK2_OUT}= 0.85 V

[1]

ΔV_OUT(ΔIOUT)

50

10

2

mV

[1]

ΔV_OUT

Output voltage Ripple

FPWM mode

mV

Switching Frequency in

CCM

f_SW

MHz

mΩ

V_INB26= 3.8 V, including bonding

wire

High Side P-FET R_DSON

Low Side N-FET R_DSON

87

45

R_DSON

V_INB26= 3.8 V, including bonding

wire

mΩ

High side current limit

Low side current limit

Startup time

V_INB26= 3.8 V

4.0

2.5

4.5

5.0

3.7

500

A

I_LIM

V_INB26= 3.8 V

3.0

A

[1]

t_START

EN rising to 90 % of output voltage

250

12.5

85

μs

[1]

V_RAMP

Output voltage slew rate Programmable, RAMP[1:0] = 01b

Soft-start slew rate

mV/μs

%

[1]

V_{soft_strup}

POK

R_DIS

L^[1]

Output Power good

75

22

95

Output Active Discharge

Resistance

100

150

Ω

Inductor value

0.47

µH

μF

[1]

C_OUT

Output capacitance

Minimum nominal capacitance

[1] Guaranteed by design

PCA9450

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 19 November 2019

72 / 96

NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

13.6 BUCK3 (PCA9450A)

Table 78.ꢀBUCK3 (PCA9450A)

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8 V, V_BUCK3= 0.85 V, C_OUT= 22 μF, T_amb= -40 °C ~

+105 °C

Symbol

V_INB13

Parameter

Conditions

Min

Typ

Max

Unit

V

Input voltage range

Shutdown current

INB13 pin

2.85

5.5

I_Shutdown

Regulator disabled, V_INB13= 5.0 V

0.1

20

μA

Regulator enabled, No load, No

switching

I_Q

Quiescent current

μA

mA

V

I_{OUT_MAX}

V_BUCK3

Max Output Current

3000

0.6

Programmable Output

voltage range

I2C programmable, 12.5 mV step

2.1875

V_INB13= 3.8 V, V_{BUCK3_OUT}

=

0.85 V, IOUT = 0 A, FPWM mode,

25 °C

-0.6

-2

+0.6

+2

%

DC Output Voltage

Accuracy

V_{BUCK3_OUT}

V_INB13= 3.8 V, V_{BUCK3_OUT}

=

0.85 V, IOUT = 0 A, FPWM mode

[1]

ΔV_OUT(ΔVINB)

DC Line regulation

DC Load regulation

V_INB13= 3 V to 5 V, I_OUT= I_{OUT_MAX}

2

3

mV/V

mV/A

0 mA < I_OUT< I_{OUT_MAX}, V_{BUCK3_OUT}

= 0.85 V

ΔV_OUT(ΔIOUT)

Transient Load

Response

I_OUTchanges 0 to I_{OUT_MAX}(1 A/μs

slope), V_{BUCK3_OUT}= 0.85 V

[1]

ΔV_OUT(ΔIOUT)

50

10

2

mV

[1]

ΔV_OUT

Output voltage Ripple

FPWM mode

mV

Switching Frequency in

CCM

f_SW

MHz

mΩ

V_INB13= 3.8 V, including bonding

wire

High Side P-FET R_DSON

Low Side N-FET R_DSON

87

45

R_DSON

V_INB13= 3.8 V, including bonding

wire

mΩ

High side current limit

Low side current limit

Startup time

V_INB13= 3.8 V

4.0

2.5

4.5

5.0

3.7

500

A

I_LIM

V_INB13= 3.8 V

3.0

A

[1]

t_START

EN rising to 90 % of output voltage

250

12.5

85

μs

[1]

V_RAMP

Output voltage slew rate Programmable, RAMP[1:0] = 01b

Soft-start slew rate

mV/μs

%

[1]

V_{soft_strup}

POK

R_DIS

L^[1]

Output Power good

75

22

95

Output Active Discharge

Resistance

100

150

Ω

Inductor value

0.47

µH

μF

[1]

C_OUT

Output capacitance

Minimum nominal capacitance

[1] Guaranteed by design

PCA9450

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 19 November 2019

73 / 96

NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

13.7 BUCK4

Table 79.ꢀBUCK4

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8 V, V_BUCK4= 3.3 V, C_OUT= 22 μF, T_amb= -40 °C ~

+105 °C

Symbol

V_INB45

Parameter

Conditions

Min

Typ

Max

Unit

V

Input voltage range

Shutdown current

INB45 pin

2.85

5.5

I_Shutdown

Regulator disabled, V_INB45= 5.0 V

0.1

20

μA

Regulator enabled, No load, No

switching

I_Q

Quiescent current

μA

mA

V

I_{OUT_MAX}

V_BUCK4

Max Output Current

3000

0.6

Programmable Output

voltage range

I2C programmable, 25 mV step

3.4

V_INB45= 3.8 V, V_{BUCK4_OUT}= 3.3 V,

IOUT = 0 A, FPWM mode, 25 °C

-0.5

+0.5

+2

%

DC Output Voltage

Accuracy

V_{BUCK4_OUT}

V_INB45= 3.8 V, V_{BUCK4_OUT}= 3.3 V, -2

IOUT = 0 A, FPWM mode

[1]

ΔV_OUT(ΔVINB)

DC Line regulation

DC Load regulation

V_INB45= 4 V to 5 V, I_OUT= I_{OUT_MAX}

2

6

mV/V

mV/A

0 mA < I_OUT< I_{OUT_MAX}

,

ΔV_OUT(ΔIOUT)

V_{BUCK4_OUT}= 3.3 V

Transient Load

Response

I_OUTchanges 0 to I_{OUT_MAX}(1 A/μs

slope), V_{BUCK4_OUT}= 3.3 V

[1]

ΔV_OUT(ΔIOUT)

160

10

2

mV

[1]

ΔV_OUT

Output voltage Ripple

FPWM mode

mV

Switching Frequency in

CCM

f_SW

MHz

mΩ

V_INB45= 3.8 V, including bonding

wire

High Side P-FET R_DSON

Low Side N-FET R_DSON

87

45

R_DSON

V_INB45= 3.8 V, including bonding

wire

mΩ

High side current limit

Low side current limit

Startup time

V_INB45= 3.8 V

4.0

2.5

4.5

5.0

3.7

500

A

I_LIM

V_INB45= 3.8 V

3.0

A

[1]

t_START

EN rising to 90 % of output voltage

250

12.5

μs

[1]

V_{soft_strup}

Soft-start slew rate

mV/μs

Output Active Discharge

Resistance

R_DIS

L^[1]

100

150

Ω

Inductor value

0.47

µH

μF

[1]

C_OUT

Output capacitance

Minimum nominal capacitance

22

[1] Guaranteed by design

PCA9450

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 19 November 2019

74 / 96

NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

13.8 BUCK5

Table 80.ꢀBUCK5

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8 V, V_BUCK5= 1.8 V, C_OUT= 22 μF, T_amb= -40 °C ~

+105 °C

Symbol

V_INB45

Parameter

Conditions

Min

Typ

Max

Unit

V

Input voltage range

Shutdown current

INB45 pin

2.85

5.5

I_Shutdown

Regulator disabled, V_INB45= 5.0 V

0.1

20

μA

Regulator enabled, No load, No

switching

I_Q

Quiescent current

μA

mA

V

I_{OUT_MAX}

V_BUCK5

Max Output Current

2000

0.6

Programmable Output

voltage range

I2C programmable, 25 mV step

3.4

V_INB45= 3.8 V, V_{BUCK5_OUT}= 1.8 V,

IOUT = 0 A, FPWM mode, 25 °C

-0.5

+0.5

+2

%

DC Output Voltage

Accuracy

V_{BUCK5_OUT}

V_INB45= 3.8 V, V_{BUCK5_OUT}= 1.8 V, -2

IOUT = 0 A, FPWM mode

[1]

ΔV_OUT(ΔVINB)

DC Line regulation

DC Load regulation

V_INB45= 3 V to 5 V, I_OUT= I_{OUT_MAX}

2

7

mV/V

mV/A

0 mA < I_OUT< I_{OUT_MAX}

,

ΔV_OUT(ΔIOUT)

V_{BUCK5_OUT}= 1.8 V

Transient Load

Response

I_OUTchanges 0 to I_{OUT_MAX}(1 A/μs

slope), V_{BUCK5_OUT}= 1.8 V

[1]

ΔV_OUT(ΔIOUT)

50

22

2

mV

[1]

ΔV_OUT

Output voltage Ripple FPWM mode

mV

Switching Frequency in

CCM

f_SW

MHz

mΩ

High Side P-FET

R_DSON

V_INB45= 3.8 V, including bonding

wire

130

70

R_DSON

Low Side N-FET

R_DSON

V_INB45= 3.8 V, including bonding

wire

mΩ

High side current limit V_INB45= 3.8 V

3.0

1.5

3.5

2

4.0

2.7

500

A

I_LIM

Low side current limit

Startup time

V_INB45= 3.8 V

A

[1]

t_START

EN rising to 90 % of output voltage

250

12.5

85

μs

[1]

V_{soft_strup}

Soft-start slew rate

Output Power good

mV/μs

%

POK

R_DIS

L^[1]

75

22

95

Output Active

Discharge Resistance

100

150

Ω

Inductor value

0.47

µH

μF

[1]

C_OUT

Output capacitance

Minimum nominal capacitance

[1] Guaranteed by design

PCA9450

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 19 November 2019

75 / 96

NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

13.9 BUCK6

Table 81.ꢀBUCK6

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8 V, V_BUCK6= 1.1 V, C_OUT= 22 μF, T_amb= -40 °C to

+105 °C

Symbol

V_INB26

Parameter

Conditions

Min

Typ

Max

Unit

V

Input voltage range

Shutdown current

INB26 pin

2.85

5.5

I_Shutdown

Regulator disabled, V_INB26= 5.0 V

0.1

20

μA

Regulator enabled, No load, No

switching

I_Q

Quiescent current

μA

mA

V

I_{OUT_MAX}

V_BUCK6

Max Output Current

2000

0.6

Programmable Output

voltage range

I2C programmable, 25 mV step

3.4

V_INB26= 3.8 V, V_{BUCK6_OUT}= 1.1 V,

IOUT = 0 A, FPWM mode, 25 °C

-0.8

+0.8

+2

%

DC Output Voltage

Accuracy

V_{BUCK6_OUT}

V_INB26= 3.8 V, V_{BUCK6_OUT}= 1.1 V, -2

IOUT = 0 A, FPWM mode

[1]

ΔV_OUT(ΔVINB)

DC Line regulation

DC Load regulation

V_INB26= 3 V to 5 V, I_OUT= I_{OUT_MAX}

2

6

mV/V

mV/A

0 mA < I_OUT< I_{OUT_MAX}

,

ΔV_OUT(ΔIOUT)

V_{BUCK6_OUT}= 1.1 V

Transient Load

Response

I_OUTchanges 0 to I_{OUT_MAX}(1 A/μs

slope), V_{BUCK6_OUT}= 1.1 V

[1]

ΔV_OUT(ΔIOUT)

50

18

2

mV

[1]

ΔV_OUT

Output voltage Ripple

FPWM mode

mV

Switching Frequency in

CCM

f_SW

MHz

mΩ

V_INB26= 3.8 V, including bonding

wire

High Side P-FET R_DSON

Low Side N-FET R_DSON

130

70

R_DSON

V_INB26= 3.8 V, including bonding

wire

mΩ

High side current limit

Low side current limit

Startup time

V_INB26= 3.8 V

3.0

1.5

3.5

2

4.0

2.7

500

A

I_LIM

V_INB26= 3.8 V

A

[1]

t_START

EN rising to 90 % of output voltage

250

12.5

85

μs

[1]

V_{soft_strup}

Soft-start slew rate

Output Power good

mV/μs

%

POK

R_DIS

L^[1]

75

22

95

Output Active Discharge

Resistance

100

150

Ω

Inductor value

0.47

µH

μF

[1]

C_OUT

Output capacitance

Minimum nominal capacitance

[1] Guaranteed by design

PCA9450

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 19 November 2019

76 / 96

NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

13.10 LDO1

Table 82.ꢀLDO1

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8 V, V_LDO1= 1.8 V, C_INL1= 4.7 μF, C_OUT= 1 μF, T_amb

=

-40 °C ~ +105 °C

Symbol

V_IN

Parameter

Conditions

Min

Typ

Max

Unit

V

Input voltage range

Quiescent current

INL1 pin

2.85

5.5

I_Q

Regulator enabled, No load

2

μA

Maximum Output DC

Current

I_{OUT_MAX}

I_LIMIT

V_IN> 2.85 V, V_LDO1= 1.8 V

Output shorted to GND

10

30

mA

mV

Short Current Limit

Dropout Voltage

60

3.3

I_OUT= I_{OUT_MAX,}V_IN= 3.2 V,

L1_OUT[2:0]= 0x7, 3.3 V

V_DO

35

Nominal output voltage I²C Programmable, 100 mV step 1.6

V

V_LDO1

Default voltage

1.8

V

DC accuracy

Output noise

V_LDO1= 1.8 V, I_Load= 5 mA

-3

3

%

f = 10 Hz to 10 kHz, I_OUT= 10 %

of I_MAX,V_LDO1= 1.8 V

[1]

V_NOISE

400

0.2

0.5

μV

%/V

%

V_LDO1+0.3 V < V_IN< 5.5 V,

I_OUT(LDO1)= 10 % of I_{OUT_MAX}

ΔV_OUT(ΔVINL)

DC Line regulation

DC Load regulation

0.5

1

V_IN= V_LDO1+0.3 V to 5.5 V,

0 mA < I_OUT< I_{OUT_MAX}

ΔV_OUT(ΔIOUT)

V_LDO1+0.3 V < V_IN< 5.5 V,

Transient Line

Response

[1]

ΔV_OUT(ΔVINL)

0.5

%/V

I_OUT(LDO1)= 10 % of I_{OUT_MAX,}tr =

10 μs

V_IN= V_LDO1+0.3 V to 5.5 V,

Transient Load

Response

[1]

ΔV_OUT(ΔIOUT)

-3

3

%

1 mA < I_OUT< I_{OUT_MAX ,}tr =

10 μs, V_LDO1= 1.8 V

Power Supply Rejection f = 10 Hz to 10 kHz, I_OUT= 10 %

PSRR^[1]

45

15

dB

ratio

of I_{OUT_MAX}

I_OUT= 0 mA, 10 % to 90 % of

V_LDO1

[1]

V_{soft_strup}

Soft-start slew rate

Overshoot at startup

Enable time

mV/μs

mV

μs

[1]

V_{ov_srtup}

I_OUT= 0 mA

10

EN rising to 90 % of output

voltage

[1]

t_EN

150

85

POK

R_DIS

Output Power good

Percentage of V_LDO1configuration 75

92

%

Active Discharge

Resistance

100

150

Ω

[1]

C_OUT

Output capacitance

Minimum nominal capacitance

1

μF

[1] Guaranteed by design

PCA9450

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 19 November 2019

77 / 96

NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

13.11 LDO2

Table 83.ꢀLDO2

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8 V, V_LDO2= 0.85 V, C_INL1= 4.7 μF, C_OUT= 1 μF, T_amb

=

-40 °C ~ +105 °C

Symbol

V_IN

Parameter

Conditions

Min

Typ

Max

Unit

V

Input voltage range

Quiescent current

INL1 pin

2.85

5.5

I_Q

Regulator enabled, No load

2

μA

Maximum Output DC

Current

I_{OUT_MAX}

V_IN> 2.8 V, V_LDO2= 0.8 V

10

30

mA

I_LIMIT

V_DO

Short Current Limit

Dropout Voltage

Nominal output voltage

Default voltage

Output shorted to GND

I_OUT= I_{OUT_MAX,}

I²C Programmable, 50 mV step

60

1.5

mA

mV

V

35

0.8

-3

V_LDO2

0.85

V

DC accuracy

V_LDO2= 0.8 V, I_Load= 5 mA

3

%

f = 10 Hz to 10 kHz, I_OUT= 10 % of

I_MAX,V_LDO2= 0.8 V

[1]

V_NOISE

Output noise

400

0.2

0.5

μV

%/V

%

V_LDO2+0.3 V < V_IN< 5.5 V,

I_OUT(LDO2)= 10 % of I_{OUT_MAX}

ΔV_OUT(ΔVINL)

DC Line regulation

DC Load regulation

0.5

1

V_IN= V_LDO2+0.3 V to 5.5 V,

0 mA < I_OUT< I_{OUT_MAX}

ΔV_OUT(ΔIOUT)

V_LDO2+0.3 V < V_IN< 5.5 V,

[1]

ΔV_OUT(ΔVINL)

Transient Line Response

0.5

%/V

%

I_OUT(LDO2)= 10 % of I_{OUT_MAX}, tr =

10 μs

V_IN= V_OUT+0.3 V to 5.5 V,

Transient Load

Response

[1]

ΔV_OUT(ΔIOUT)

-3

3

1 mA < I_OUT< I_{OUT_MAX ,}tr = 10 μs,

V_LDO2= 0.8 V

Power Supply Rejection f = 10 Hz to 10 kHz, I_OUT= 10 % of

PSRR^[1]

60

15

dB

ratio

I_{OUT_MAX}

I_OUT= 0 mA, 10 % to 90 % of

V_LDO2

[1]

V_{soft_strup}

Soft-start slew rate

mV/μs

[1]

V_{ov_srtup}

Overshoot at startup

Enable time

I_OUT= 0 mA

10

mV

μs

%

[1]

t_EN

EN rising to 90 % of output voltage

100

85

POK

R_DIS

Output Power good

Percentage of V_LDO2configuration 75

92

Active Discharge

Resistance

100

150

Ω

[1]

C_OUT

Output capacitance

Minimum nominal capacitance

1

μF

[1] Guaranteed by design

PCA9450

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 19 November 2019

78 / 96

NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

13.12 LDO3

Table 84.ꢀLDO3

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8 V, V_LDO3= 1.8 V, C_INL1= 4.7 μF, C_OUT= 2.2 μF, T_amb

=

-40 °C ~ +105 °C

Symbol

V_IN

Parameter

Conditions

Min

Typ

Max

Unit

V

Input voltage range

Shutdown current

Quiescent current

INL1

2.85

5.5

I_Shutdown

I_Q

Regulator disabled, V_IN= 5.0 V

Regulator enabled, No load

0.1

15

μA

Maximum Output DC

Current

I_{OUT_MAX}

I_LIMIT

V_IN> 2.8 V, V_LDO3= 1.8 V

Output shorted to GND

300

310

mA

mV

Short Current Limit

Dropout Voltage

480

100

3.3

I_OUT= I_{OUT_MAX,}V_IN= 3.2 V,

L3_OUT[4:0] = 0x1F, 3.3 V

V_DO

70

Nominal output voltage I²C Programmable, 100 mV step

0.8

-3

V

V_LDO3

Default voltage

1.8

V

DC accuracy

Output noise

V_LDO3= 1.8 V, I_Load= 5 mA

3

%

f = 10 Hz to 10 kHz, I_OUT= 10 % of

I_MAX,V_LDO3= 1.8 V

V_NOISE

150

0.2

0.6

μV

%/V

%

V_LDO3+0.3 V < V_IN< 5.5 V,

I_OUT(LDO3)= 10 % of I_{OUT_MAX}

ΔV_OUT(ΔVINL)

DC Line regulation

DC Load regulation

0.5

V_IN= V_LDO3+0.3 V to 5.5 V,

0 mA < I_OUT< I_{OUT_MAX}

ΔV_OUT(ΔIOUT)

V_LDO3+0.3 V < V_IN< 5.5 V,

Transient Line

Response

[1]

ΔV_OUT(ΔVINL)

0.5

%/V

%

I_OUT(LDO3)= 10 % of I_{OUT_MAX}, tr =

10 μs

V_IN= V_LDO3+0.3 V to 5.5 V,

Transient Load

Response

[1]

ΔV_OUT(ΔIOUT)

-3

3

1 mA < I_OUT< I_{OUT_MAX ,}tr = 10 μs,

V_LDO3= 1.8 V, T_amb= 25 °C

Power Supply Rejection f = 10 Hz to 10 kHz, I_OUT= 10 % of

PSRR^[1]

55

15

dB

ratio

I_{OUT_MAX}

I_OUT= 0 mA, 10 % to 90 % of

V_LDO3

[1]

V_{soft_strup}

Soft-start slew rate

mV/μs

[1]

V_{ov_srtup}

Overshoot at startup

Enable time

I_OUT= 0 mA

10

mV

μs

%

[1]

t_EN

EN rising to 90 % of output voltage

150

85

POK

R_DIS

Output Power good

Percentage of V_LDO3configuration 75

92

Active Discharge

Resistance

100

150

Ω

[1]

C_OUT

Output capacitance

Minimum nominal capacitance

2.2

μF

[1] Guaranteed by design

PCA9450

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 19 November 2019

79 / 96

NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

13.13 LDO4

Table 85.ꢀLDO4

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8 V, V_LDO4= 0.9 V, C_INL1= 4.7 μF, C_OUT= 1 μF, T_amb

=

-40 °C ~ +105 °C

Symbol

V_IN

Parameter

Conditions

Min

Typ

Max

Unit

V

Input voltage range

Shutdown current

Quiescent current

INL1

2.85

5.5

I_Shutdown

I_Q

Regulator disabled, V_IN= 5.0 V

Regulator enabled, No load

0.1

15

μA

Maximum Output DC

Current

I_{OUT_MAX}

I_LIMIT

V_IN> 2.8, V_LDO4= 0.9 V

Output shorted to GND

200

210

mA

mV

Short Current Limit

Dropout Voltage

330

100

3.3

I_OUT= I_{OUT_MAX,}V_IN= 3.2 V,

L4_OUT[4:0] = 0x1F, 3.3 V

I²C Programmable, 100 mV step

V_DO

60

Nominal output voltage

Default voltage

0.8

-3

V

V_LDO4

0.9

V

DC accuracy

V_LDO4= 0.9 V, I_Load= 5 mA

3

%

f = 10 Hz to 10 kHz, I_OUT= 10 % of

I_MAX,V_LDO4= 0.9 V

V_NOISE

Output noise

150

0.2

0.9

μV

%/V

%

V_LDO4+0.3 V < V_IN< 5.5 V,

I_OUT(LDO4)= 10 % of I_{OUT_MAX}

ΔV_OUT(ΔVINL)

DC Line regulation

DC Load regulation

0.5

V_IN= V_LDO4+0.3 V to 5.5 V,

0 mA < I_OUT< I_{OUT_MAX}

ΔV_OUT(ΔIOUT)

V_LDO4+0.3 V < V_IN< 5.5 V,

[1]

ΔV_OUT(ΔVINL)

Transient Line Response

0.5

%/V

I_OUT(LDO4)= 10 % of I_{OUT_MAX}, tr =

10 μs

V_IN= V_LDO4+0.3 V to 5.5 V,

Transient Load

Response

[1]

ΔV_OUT(ΔIOUT)

-4

4

%

1 mA < I_OUT< I_{OUT_MAX ,}tr = 10 μs,

V_LDO4= 0.9 V, T_amb= 25 °C

Power Supply Rejection f = 10 Hz to 10 kHz, I_OUT= 10 % of

PSRR^[1]

60

20

dB

ratio

I_{OUT_MAX}

[1]

V_{soft_strup}

Soft-start slew rate

Overshoot at startup

Enable time

I_OUT= 0 mA, 10 % to 90 % of V_LDO4

I_OUT= 0 mA

mV/μs

mV

μs

[1]

V_{ov_srtup}

10

[1]

t_EN

EN rising to 90 % of output voltage

Percentage of V_LDO4configuration

100

85

POK

R_DIS

Output Power good

75

1

92

%

Active Discharge

Resistance

100

150

Ω

[1]

C_OUT

Output capacitance

Minimum nominal capacitance

μF

[1] Guaranteed by design

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13.14 LDO5

Table 86.ꢀLDO5

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8 V, V_LDO5= 3.3 V, C_INL1= 4.7 μF, C_OUT= 1 μF, T_amb

=

-40 °C ~ +105 °C

Symbol

V_IN

Parameter

Conditions

Min

Typ

Max

Unit

V

Input voltage range

Shutdown current

Quiescent current

INL1 pin

2.85

5.5

I_Shutdown

I_Q

Regulator disabled, V_IN= 5.0 V

Regulator enabled, No load

0.1

15

μA

Maximum Output DC

Current

I_{OUT_MAX}

I_LIMIT

V_IN> 2.8 V, V_LDO5= 3.3 V

Output shorted to GND

150

160

mA

mV

Short Current Limit

Dropout Voltage

280

100

3.3

I_OUT= I_{OUT_MAX,}V_IN= 3.2 V,

L5_OUT_L[3:0] = 0xF, 3.3 V

V_DO

50

Nominal output voltage I²C Programmable, 100 mV step

1.8

-3

V

%

SD_VSEL = Low

Default voltage

3.3

1.8

V_LDO5

SD_VSEL = High

DC accuracy

Output noise

V_LDO5= 1.8 V, I_Load= 5 mA

3

f = 10 Hz to 10 kHz, I_OUT= 10 % of

I_MAX,V_LDO5= 3.3 V

V_NOISE

300

0.2

0.3

0.5

μV

V_LDO5+0.3 V < V_IN< 5.5 V,

I_OUT(LDO5)= 10 % of I_{OUT_MAX}

ΔV_OUT(ΔVINL)

DC Line regulation

DC Load regulation

0.5

%/V

%

V_IN= V_LDO5+0.3 V to 5.5 V,

0 mA < I_OUT< I_{OUT_MAX}

ΔV_OUT(ΔIOUT)

V_LDO5+0.3 V < V_IN< 5.5 V,

I_OUT(LDO5)= 10 % of I_{OUT_MAX}

Transient Line

Response

[1]

ΔV_OUT(ΔVINL)

ΔV_OUT(ΔIOUT)

PSRR^[1]

%/V

V_IN= V_LDO5+0.3 V to 5.5 V,

Transient Load

Response

[1]

-3

3

%

1 mA < I_OUT< I_{OUT_MAX ,}tr = 10 μs,

V_LDO5= 3.3 V, T_amb= 25 °C

Power Supply Rejection f = 10 Hz to 10 kHz, I_OUT= 10 % of

ratio

50

15

dB

I_{OUT_MAX}

[1]

V_{soft_strup}

Soft-start slew rate

Overshoot at startup

Enable time

I_OUT= 0 mA, 10 % to 90 % of V_LDO5

I_OUT= 0 mA

mV/μs

mV

μs

[1]

V_{ov_srtup}

10

[1]

t_EN

EN rising to 90 % of output voltage

200

85

POK

R_DIS

Output Power good

Percentage of V_LDO5configuration 75

92

%

Active Discharge

Resistance

100

150

Ω

[1]

C_OUT

Output capacitance

Minimum nominal capacitance

1

μF

[1] Guaranteed by design

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13.15 Load SW

Table 87.ꢀLoad SW

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8 V, V_SWIN= 3.8 V, C_SWIN= C_SWOUT= 1 μF, T_amb

=

-40 °C ~ +105 °C

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_SWIN

Input voltage range

SWIN

2.8

5.5

V

Switch enabled, No load, V_SWIN

3.3 V

=

I_Q

Quiescent current

5

8

μA

I_SHDN

Shut down current

SWEN = 0 V, V_SWIN= 3.3 V

1

2.5

μA

[1]

I_OC

OverCurrent Threshold

450

800

mA

Short circuit current

threshold

[1]

I_SC

2

A

V_SWIN= 3.3 V, I_LOAD= 200 mA,

including bonding wire resistance

R_DSON

Switch ON resistance

Enable time

150

90

200

80

210

120

500

120

mΩ

μs

Ω

Time to SWOUT 10 % from EN pin

high, V_SWIN= 3.3 V

[1]

t_EN

CL = 10 μF, V_SWIN= 3.3 V, SWOUT

10 % to 90 %

[1]

t_ON

Output rise time

Active Discharge

Resistance

R_DIS

SWEN = 0 V

[1] Guaranteed by design

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13.16 32 kHz Xtal driver

Table 88.ꢀ32 kHz Xtal driver

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8, T_amb= -40 °C ~ +105 °C

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_{OSC_32K}

Clock frequency

Internal Oscillator

29

32.77

36

kHz

External 32.768 kHz crystal

oscillator

[1]

f_CLK

Clock frequency

32.768

1000

50

kHz

ms

%

Oscillator stabilization

time

[1]

t_RTCSTB

External 32.768 kHz crystal

oscillator

Duty^[1]

Output Duty cycle

30

70

V_OL

V_OH

Output Low level

Output High level

I_OL= 1 mA

0.4

V

V_LDO1= 1.8 V, I_OL= 1 mA

1.6

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13.17 I²C-bus interface and logic I/O

Table 89.ꢀI²C-bus interface and logic I/O

Unless otherwise specified, VSYS = 3.8 V, V_INBx= 3.8 V, V_INL1= 3.8, T_amb= -40 °C ~ +105 °C

Symbol

SCL, SDA

f_I2C

Parameter

Conditions

Min

Typ

Max

Unit

I²C Clock frequency

-

1

MHz

V

V_IH

High-level Input voltage SCL, SDA; VSYS= 3.0 V to 5.5 V

1.2

-

V_IL

Low-level Input voltage

SCL, SDA; VSYS= 3.0 V to 5.5 V

0.4

V

Hysteresis of Schmitt

trigger inputs

V_hys

VOL

0.01

0

-

V

SDA, Iload = 20 mA, VSYS = 3.0 V

to 5.5 V

Low-level output voltage

0.4

Fast mode plus; After this period,

the

Hold time (repeated)

START condition

[1]

t_HD,STA

0.26

-

µs

first clock pulse is generated

[1]

t_LOW

LOW period of I2C clock Fast mode plus

HIGH period of I2C clock Fast mode plus

0.5

-

µs

[1]

t_HIGH

0.26

Setup time (repeated)

Fast mode plus

[1]

t_SU,STA

0.26

-

µs

START condition

[1]

t_HD,DAT

Data Hold time

Data Setup time

Fast mode plus

0

-

µs

ns

[1]

t_SU,DAT

50

Rise time of I2C_SCL

and

[1]

t_r

Fast mode plus

-

120

ns

I2C_SDA signals

Fall time of I2C_SCL and

I2C_SDA signals

[1]

t_f

Fast mode plus

-

120

-

ns

µs

Setup time for STOP

condition

[1]

t_SU,STO

0.26

Bus free time between

STOP and START

condition

[1]

t_BUF

Fast mode plus

0.5

-

µs

[1]

t_VD,DAT

Data valid time

Fast mode plus

-

0.45

µs

Data valid acknowledge

time

[1]

t_VD,ACK

Pulse width of spikes that

must be suppressed by

input filter

[1]

t_SP

0

-

50

ns

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13.18 Package outline

Figure 26.ꢀPackage outline HVQFN56(SOT949-6)

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Figure 27.ꢀPackage outline HVQFN56(SOT949-6)

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Figure 28.ꢀPCB Design Guidelines – Solder Mask Opening Pattern

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Figure 29.ꢀPCB Design Guidelines - I/O PADS AND SODERABLE AREA

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Figure 30.ꢀPCB Design Guidelines – Solder Paste Stencil

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14 Revision history

Table 90.ꢀRevision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

PCA9450 v1.0

20191119

Product data sheet

-

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15 Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product

development.

Preliminary [short] data sheet

Product [short] data sheet

Qualification

Production

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

15.2 Definitions

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences

of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product

is deemed to offer functions and qualities beyond those described in the

Product data sheet.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

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No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

15.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

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Tables

Tab. 1.

Tab. 2.

Tab. 3.

Tab. 4.

Tab. 5.

Tab. 6.

Tab. 7.

Tab. 8.

Tab. 9.

Ordering information ..........................................2

Ordering options ................................................2

Tab. 46. 0x19 BUCK4CTRL .......................................... 43

Tab. 47. 0x1A BUCK4OUT ............................................43

Tab. 48. 0x1B BUCK5CTRL ..........................................43

Tab. 49. 0x1C BUCK5OUT ........................................... 44

Tab. 50. 0x1D BUCK6CTRL ..........................................44

Tab. 51. 0x1E BUCK6OUT ............................................44

Tab. 52. BUCK4, BUCK5, BUCK6 Output voltage

table .................................................................45

Pin description ...................................................4

PCA9450 selection guide ..................................8

SNVS mode .................................................... 10

PWRUP mode .................................................12

Power modes summary .................................. 13

tFLT_THSD ..................................................... 15

tFLT_SD_WAIT ............................................... 17

Tab. 53. 0x20 LDO_AD_CTRL ......................................46

Tab. 54. 0x21 LDO1CTRL .............................................46

Tab. 55. 0x22 LDO2CTRL .............................................47

Tab. 56. 0x23 LDO3CTRL .............................................48

Tab. 57. LDO3 output voltage ....................................... 48

Tab. 58. 0x24 LDO4CTRL .............................................48

Tab. 59. LDO4 output voltage ....................................... 48

Tab. 60. 0x25 LDO5CTRL_L .........................................49

Tab. 61. LDO5 output voltage when SD_VSEL = Low ...49

Tab. 62. 0x26 LDO5CTRL_H ........................................ 49

Tab. 63. LDO5 output voltage when SD_VSEL = High .. 49

Tab. 64. 0x2A LOADSW_CTRL .................................... 50

Tab. 65. 0x2B VRFLT1_STS .........................................50

Tab. 66. 0x2C VRFLT2_STS .........................................51

Tab. 67. 0x2D VRFLT1_MASK ..................................... 52

Tab. 68. 0x2E VRFLT2_MASK ......................................52

Tab. 69. Tested inductor list ..........................................58

Tab. 70. Limiting values ................................................ 63

Tab. 71. Recommended Operating Conditions ............. 64

Tab. 72. Thermal characteristics ................................... 65

Tab. 73. Top level parameter ........................................ 66

Tab. 74. I2C level translator ..........................................69

Tab. 75. BUCK1 (PCA9560A/PCA9450B) .....................70

Tab. 76. Dual Phase BUCK1 (PCA9450C) ................... 71

Tab. 77. BUCK2 .............................................................72

Tab. 78. BUCK3 (PCA9450A) ....................................... 73

Tab. 79. BUCK4 .............................................................74

Tab. 80. BUCK5 .............................................................75

Tab. 81. BUCK6 .............................................................76

Tab. 82. LDO1 ............................................................... 77

Tab. 83. LDO2 ............................................................... 78

Tab. 84. LDO3 ............................................................... 79

Tab. 85. LDO4 ............................................................... 80

Tab. 86. LDO5 ............................................................... 81

Tab. 87. Load SW ......................................................... 82

Tab. 88. 32 kHz Xtal driver ........................................... 83

Tab. 89. I2C-bus interface and logic I/O ........................84

Tab. 90. Revision history ...............................................90

Tab. 10. 0x08 – RESET_CTRL .....................................18

Tab. 11. 0x06 – SW_RST ............................................. 18

Tab. 12. tRESTART .......................................................19

Tab. 13. tRESET ............................................................20

Tab. 14. PCA9450A Regulator Control summary ..........20

Tab. 15. PCA9450B/PCA9450C Regulator Control

summary ..........................................................21

Tab. 16. PCA9450A Buck Summary ............................. 22

Tab. 17. PCA9450C Buck Summary .............................22

Tab. 18. LDO summary .................................................24

Tab. 19. PCA9450 I2C Slave Address ..........................27

Tab. 20. Register map ...................................................28

Tab. 21. 0x00 Device_ID ...............................................31

Tab. 22. 0x01 INT1 ........................................................31

Tab. 23. 0x02 INT1_MSK ..............................................32

Tab. 24. 0x03 STATUS1 ............................................... 32

Tab. 25. 0x04 STATUS2 ............................................... 33

Tab. 26. 0x05 PWRON_STAT .......................................34

Tab. 27. 0x06 SW_RST ................................................ 34

Tab. 28. 0x07 PWR_CTRL ............................................34

Tab. 29. 0x08 RESET_CTRL ........................................ 35

Tab. 30. 0x09 CONFIG1 ............................................... 36

Tab. 31. 0x0A CONFIG2 ............................................... 36

Tab. 32. 0x0C BUCK123_DVS ......................................37

Tab. 33. 0x0D BUCK1OUT_LIMIT ................................ 37

Tab. 34. 0x0E BUCK2OUT_LIMIT ................................ 37

Tab. 35. 0x0F BUCK3OUT_LIMIT .................................38

Tab. 36. 0x10 BUCK1CTRL .......................................... 38

Tab. 37. 0x11 BUCK1OUT_DVS0 .................................39

Tab. 38. 0x12 BUCK1OUT_DVS1 .................................39

Tab. 39. 0x13 BUCK2CTRL .......................................... 39

Tab. 40. 0x14 BUCK2OUT_DVS0 .................................40

Tab. 41. 0x15 BUCK2OUT_DVS1 .................................40

Tab. 42. 0x16 BUCK3CTRL .......................................... 40

Tab. 43. 0x17 BUCK3OUT_DVS0 .................................41

Tab. 44. 0x18 BUCK3OUT_DVS1 .................................41

Tab. 45. BUCK1, BUCK2, BUCK3 Output voltage

table .................................................................41

Figures

Fig. 1.

Fig. 2.

Fig. 3.

Fig. 4.

Fig. 5.

Block diagram ................................................... 3

PCA9450 pin map – Top View ..........................4

PCA9450 functional block diagram ................... 8

Power States Diagram ...................................... 9

SNVS mode ON/OFF sequence ..................... 10

Fig. 6.

Fig. 7.

Fig. 8.

Fig. 9.

PCA9450A power ON/OFF sequence .............11

PCA9450B/C power ON/OFF sequence ......... 12

PCA9450A mode transition .............................13

PCA9450 FAULT_SD from Thermal

shutdown ......................................................... 15

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

Fig. 10. PCA9450 Fault event ......................................16

Fig. 11. PCA9450 FAULT_SD from VR Fault except

LDO1/LDO2 in RUN/STANDBY ...................... 17

Fig. 12. PCA9450A Cold reset .....................................19

Fig. 13. Warm reset ......................................................20

Fig. 14. DVS functional diagram .................................. 23

Fig. 15. DVS timing ...................................................... 23

Fig. 16. BUCK1/3 configuration ....................................24

Fig. 17. 32 kHz Crystal oscillator driver block

diagram ............................................................25

Fig. 21. PCA9450A application schematic ................... 55

Fig. 22. PCA9450B application schematic ................... 56

Fig. 23. PCA9450C application schematic ................... 57

Fig. 24. Crystal oscillator ..............................................60

Fig. 25. PCA9450 layout .............................................. 62

Fig. 26. Package outline HVQFN56(SOT949-6) .......... 85

Fig. 27. Package outline HVQFN56(SOT949-6) .......... 86

Fig. 28. PCB Design Guidelines – Solder Mask

Opening Pattern .............................................. 87

Fig. 29. PCB Design Guidelines - I/O PADS AND

SODERABLE AREA ........................................88

Fig. 30. PCB Design Guidelines – Solder Paste

Stencil ..............................................................89

Fig. 18. Load switch internal block diagram ................. 25

Fig. 19. Architecture of I2C Level translator (One

channel) ...........................................................26

Fig. 20. Interrupt diagram .............................................27

PCA9450

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Product data sheet

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NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

Contents

1

2

3

4

5

6

6.1

6.2

7

7.1

7.2

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.3.6

7.3.7

7.3.8

7.4

General description ............................................ 1

8.2.22

8.2.23

8.2.24

8.2.25

8.2.26

8.2.27

8.2.28

8.2.29

8.2.30

8.2.31

8.2.32

8.2.33

8.2.34

8.2.35

8.2.36

8.2.37

8.2.38

8.2.39

8.2.40

8.2.41

8.2.42

9

0x16 BUCK3CTRL ...........................................40

0x17 BUCK3OUT_DVS0 ................................. 41

0x18 BUCK3OUT_DVS1 ................................. 41

0x19 BUCK4CTRL ...........................................42

0x1A BUCK4OUT ............................................43

0x1B BUCK5CTRL .......................................... 43

0x1C BUCK5OUT ............................................44

0x1D BUCK6CTRL ..........................................44

0x1E BUCK6OUT ............................................44

0x20 LDO_AD_CTRL ...................................... 46

0x21 LDO1CTRL ............................................. 46

0x22 LDO2CTRL ............................................. 47

0x23 LDO3CTRL ............................................. 47

0x24 LDO4CTRL ............................................. 48

0x25 LDO5CTRL_L ......................................... 49

0x26 LDO5CTRL_H .........................................49

0x2A LOADSW_CTRL .....................................50

0x2B VRFLT1_STS ......................................... 50

0x2C VRFLT2_STS .........................................51

0x2D VRFLT1_MASK ......................................52

0x2E VRFLT2_MASK ......................................52

Application design-in information ...................54

Reference schematic .......................................54

PCA9450A reference schematic ......................54

PCA9450B reference schematic ......................56

PCA9450C reference schematic ..................... 57

Typical application ........................................... 58

Buck regulators ................................................58

Inductor selection for buck converters ............. 58

Output capacitor selection for buck

converters ........................................................ 59

Input capacitor selection for buck converters ... 59

Crystal oscillator .............................................. 59

Crystal selection .............................................. 59

Effective load capacitance ...............................60

Frequency tuning .............................................61

Layout guide ....................................................61

Limiting values ..................................................63

Recommended operating conditions .............. 64

Thermal characteristics ....................................65

Electrical characteristics ..................................66

Top level parameter ........................................ 66

I2C level translator .......................................... 69

BUCK1 (PCA9560A/PCA9450B) .....................70

Dual Phase BUCK1 (PCA9450C) ....................71

BUCK2 .............................................................72

BUCK3 (PCA9450A) ........................................73

BUCK4 .............................................................74

BUCK5 .............................................................75

BUCK6 .............................................................76

LDO1 ................................................................77

LDO2 ................................................................78

LDO3 ................................................................79

LDO4 ................................................................80

LDO5 ................................................................81

Load SW ..........................................................82

Features and benefits .........................................1

Applications .........................................................2

Ordering information .......................................... 2

Block diagram ..................................................... 3

Pinning information ............................................ 4

Pinning ...............................................................4

Pin description ...................................................4

Functional description ........................................7

Features .............................................................7

Functional diagram ............................................ 8

Power modes .....................................................9

Off mode ............................................................9

READY mode .................................................... 9

SNVS mode .......................................................9

PWRUP mode ................................................. 10

PWRDN mode ................................................. 12

RUN mode .......................................................12

STANDBY mode ..............................................13

FAULT_SD .......................................................14

PMIC reset .......................................................18

Regulator control in each power mode ............ 20

Regulator summary ......................................... 21

BUCK regulator ............................................... 21

Dynamic voltage scaling ..................................22

BUCK output voltage limiting ...........................23

Dual-phase configuration .................................23

LDO and load switch .......................................24

32 kHz Crystal Oscillator Driver .......................24

Load switch ......................................................25

I2C level translator .......................................... 25

Interrupt management ..................................... 26

Software interface .............................................27

Register map ................................................... 28

Register details ................................................31

0x00 Device_ID ............................................... 31

0x01 INT1 ........................................................31

0x02 INT1_MSK .............................................. 32

0x03 STATUS1 ................................................32

0x04 STATUS2 ................................................33

0x05 PWRON_STAT .......................................33

0x06 SW_RST .................................................34

0x07 PWR_CTRL ............................................ 34

0x08 RESET_CTRL .........................................35

0x09 CONFIG1 ................................................36

0x0A CONFIG2 ............................................... 36

0x0C BUCK123_DVS ......................................37

0x0D BUCK1OUT_LIMIT .................................37

0x0E BUCK2OUT_LIMIT .................................37

0x0F BUCK3OUT_LIMIT ................................. 38

0x10 BUCK1CTRL ...........................................38

0x11 BUCK1OUT_DVS0 ................................. 39

0x12 BUCK1OUT_DVS1 ................................. 39

0x13 BUCK2CTRL ...........................................39

0x14 BUCK2OUT_DVS0 ................................. 40

0x15 BUCK2OUT_DVS1 ................................. 40

7.5

7.6

9.1

9.1.1

9.1.2

9.1.3

9.2

9.2.1

9.2.1.1

9.2.1.2

7.6.1

7.6.1.1

7.6.1.2

7.6.1.3

7.6.2

7.7

7.8

7.9

7.10

8

8.1

9.2.1.3

9.2.2

9.2.2.1

9.2.2.2

9.2.2.3

9.3

10

11

12

13

13.1

13.2

13.3

13.4

13.5

13.6

13.7

13.8

13.9

13.10

13.11

13.12

13.13

13.14

13.15

8.2

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.2.7

8.2.8

8.2.9

8.2.10

8.2.11

8.2.12

8.2.13

8.2.14

8.2.15

8.2.16

8.2.17

8.2.18

8.2.19

8.2.20

8.2.21

PCA9450

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Product data sheet

Rev. 1.0 — 19 November 2019

95 / 96

NXP Semiconductors

PCA9450

Power management IC for i.MX 8M application processor family

13.16

13.17

13.18

14

32 kHz Xtal driver ............................................83

I2C-bus interface and logic I/O ........................84

Package outline ............................................... 85

Revision history ................................................ 90

Legal information ..............................................91

15

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 19 November 2019

Document identifier: PCA9450


型号：	PCA9450B
厂家：	NXP
描述：	Power management IC for i.MX 8M application processor family
文件：	总96页 (文件大小：1327K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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