PCA9515ATP [NXP]

I2C-bus repeater; I2C总线中继器
PCA9515ATP
型号: PCA9515ATP
厂家: NXP    NXP
描述:

I2C-bus repeater
I2C总线中继器

中继器
文件: 总20页 (文件大小:222K)
中文:  中文翻译
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PCA9515A  
I2C-bus repeater  
Rev. 5 — 23 March 2012  
Product data sheet  
1. General description  
The PCA9515A is a CMOS integrated circuit intended for application in I2C-bus and  
SMBus systems.  
While retaining all the operating modes and features of the I2C-bus system, it permits  
extension of the I2C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus  
enabling two buses of 400 pF.  
The I2C-bus capacitance limit of 400 pF restricts the number of devices and bus length.  
Using the PCA9515A enables the system designer to isolate two halves of a bus, thus  
more devices or longer length can be accommodated. It can also be used to run two  
buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the  
100 kHz bus is isolated when 400 kHz operation of the other is required.  
Two or more PCA9515As cannot be put in series. The PCA9515A design does not  
allow this configuration. Since there is no direction pin, slightly different ‘legal’ low voltage  
levels are used to avoid lock-up conditions between the input and the output. A ‘regular  
LOW’ applied at the input of a PCA9515A will be propagated as a ‘buffered LOW’ with a  
slightly higher value. When this ‘buffered LOW’ is applied to another PCA9515A,  
PCA9516A or PCA9518/A in series, the second PCA9515A, PCA9516A or PCA9518/A  
will not recognize it as a ‘regular LOW’ and will not propagate it as a ‘buffered LOW’ again.  
The PCA9510/A, PCA9511/A, PCA9512/A, PCA9513/A, PCA9514/A cannot be used in  
series with the PCA9515A, PCA9516A or PCA9518/A, but can be used in series with  
themselves since they use shifting instead of static offsets to avoid lock-up conditions.  
The output pull-down of each internal buffer is set for approximately 0.5 V, while the input  
threshold of each internal buffer is set about 0.07 V lower, when the output is internally  
driven LOW. This prevents a lock-up condition from occurring.  
2. Features and benefits  
2-channel, bidirectional buffer  
I2C-bus and SMBus compatible  
Active HIGH repeater enable input  
Open-drain input/outputs  
Lock-up free operation  
Supports arbitration and clock stretching across the repeater  
Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters  
Powered-off high-impedance I2C-bus pins  
Operating supply voltage range of 2.3 V to 3.6 V  
5.5 V tolerant I2C-bus and enable pins  
PCA9515A  
NXP Semiconductors  
I2C-bus repeater  
0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be  
less than 400 kHz because of the delays added by the repeater)  
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per  
JESD22-C101  
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA  
Packages offered: SO8, TSSOP8 (MSOP8), HWSON8  
3. Ordering information  
Table 1.  
Ordering information  
Tamb = 40 C to +85 C.  
Type number  
Topside  
mark  
Package  
Name  
Description  
Version  
PCA9515AD  
PA9515A SO8  
plastic small outline package; 8 leads; body width 3.9 mm  
SOT96-1  
SOT505-1  
PCA9515ADP 9515A  
TSSOP8[1] plastic thin shrink small outline package; 8 leads;  
body width 3 mm  
PCA9515ATP 15A  
HWSON8  
plastic thermal enhanced very very thin small outline package;  
SOT1069-2  
no leads; 8 terminals; body 2 3 0.8 mm  
[1] Also known as MSOP8.  
4. Functional diagram  
V
CC  
PCA9515A  
SDA0  
SDA1  
SCL0  
EN  
SCL1  
pull-up  
resistor  
002aad738  
GND  
Fig 1. Functional diagram of PCA9515A  
PCA9515A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 5 — 23 March 2012  
2 of 20  
PCA9515A  
NXP Semiconductors  
I2C-bus repeater  
5. Pinning information  
5.1 Pinning  
1
2
3
4
8
7
6
5
n.c.  
SCL0  
SDA0  
GND  
V
CC  
1
2
3
4
8
7
6
5
n.c.  
SCL0  
SDA0  
GND  
V
CC  
SCL1  
SDA1  
EN  
SCL1  
SDA1  
EN  
PCA9515AD  
PCA9515ADP  
002aad737  
002aad736  
Fig 2. Pin configuration for SO8  
Fig 3. Pin configuration for TSSOP8  
(MSOP8)  
terminal 1  
index area  
PCA9515ATP  
SDA0  
GND  
EN  
1
2
3
4
8
7
6
5
SCL0  
n.c.  
V
CC  
SDA1  
SCL1  
002aag783  
Transparent top view  
Fig 4. Pin configuration for HWSON8  
5.2 Pin description  
Table 2.  
Symbol  
Pin description  
Pin  
Description  
SO8, TSSOP8  
HWSON8  
n.c.  
1
2
3
4
5
7
not connected  
SCL0  
SDA0  
GND  
EN  
8
serial clock bus 0; open-drain 5 V tolerant I/O  
serial data bus 0; open-drain 5 V tolerant I/O  
supply ground (0 V)  
1
2[1]  
3
active HIGH repeater enable input  
(internal pull-up with 100 k)  
SDA1  
SCL1  
VCC  
6
7
8
4
5
6
serial data bus 1; open-drain 5 V tolerant I/O  
serial clock bus 1; open-drain 5 V tolerant I/O  
supply voltage  
[1] HWSON8 package die supply ground is connected to both GND pin and exposed center pad. GND pin  
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and  
board level performance, the exposed pad needs to be soldered to the board using a corresponding  
thermal pad on the board and for proper head conduction through the board, thermal vias need to be  
incorporated in the printed-circuit board in the thermal pad region.  
PCA9515A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 5 — 23 March 2012  
3 of 20  
PCA9515A  
NXP Semiconductors  
I2C-bus repeater  
6. Functional description  
Refer to Figure 1 “Functional diagram of PCA9515A”.  
The PCA9515A integrated circuit contains two identical buffer circuits which enable  
I2C-bus and similar bus systems to be extended without degradation of system  
performance.  
The PCA9515A contains two bidirectional, open-drain buffers specifically designed to  
support the standard LOW-level contention arbitration of the I2C-bus. Except during  
arbitration or clock stretching, the PCA9515A acts like a pair of non-inverting, open-drain  
buffers, one for SDA and one for SCL.  
6.1 Enable  
The EN pin is active HIGH with an internal pull-up and allows the user to select when the  
repeater is active. This can be used to isolate a badly behaved slave on power-up until  
after the system power-up reset. It should never change state during an I2C-bus operation  
because disabling during a bus operation will hang the bus and enabling part way through  
a bus cycle could confuse the I2C-bus parts being enabled.  
The enable pin should only change state when the global bus and the repeater port are in  
an idle state to prevent system failures.  
6.2 I2C-bus systems  
As with the standard I2C-bus system, pull-up resistors are required to provide the logic  
HIGH levels on the buffered bus (standard open-collector configuration of the I2C-bus).  
The size of these pull-up resistors depends on the system, but each side of the repeater  
must have a pull-up resistor. This part designed to work with Standard-mode and  
Fast-mode I2C-bus devices in addition to SMBus devices. Standard-mode I2C-bus  
devices only specify 3 mA output drive; this limits the termination current to 3 mA in a  
generic I2C-bus system where Standard-mode devices and multiple masters are possible.  
Under certain conditions higher termination currents can be used.  
Please see Application Note AN255, I2C/SMBus Repeaters, Hubs and Expanders for  
additional information on sizing resistors and precautions when using more than one  
PCA9515A/PCA9516A in a system or using the PCA9515A/PCA9516A in conjunction  
with the P82B96.  
PCA9515A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 5 — 23 March 2012  
4 of 20  
PCA9515A  
NXP Semiconductors  
I2C-bus repeater  
7. Application design-in information  
A typical application is shown in Figure 5. In this example, the system master is running  
on a 3.3 V I2C-bus while the slave is connected to a 5 V bus. Both buses run at 100 kHz  
unless the slave bus is isolated and then the master bus can run at 400 kHz. Master  
devices can be placed on either bus.  
3.3 V  
5 V  
10 kΩ  
10 kΩ  
10 kΩ  
10 kΩ  
V
CC  
SDA0  
SCL0  
SDA1  
SCL1  
SDA  
SCL  
BUS  
MASTER  
400 kHz  
SDA  
SCL  
PCA9515A  
SLAVE  
100 kHz  
EN  
bus 0  
bus 1  
002aad739  
Fig 5. Typical application  
The PCA9515A is 5 V tolerant, so it does not require any additional circuitry to translate  
between the different bus voltages.  
When one side of the PCA9515A is pulled LOW by a device on the I2C-bus, a CMOS  
hysteresis type input detects the falling edge and causes the internal driver on the other  
side to turn on, thus causing the other side to also go LOW. The side driven LOW by the  
PCA9515A will typically be at VOL = 0.5 V.  
In order to illustrate what would be seen in a typical application, refer to Figure 6 and  
Figure 7. If the bus master in Figure 5 were to write to the slave through the PCA9515A,  
we would see the waveform shown in Figure 6 on bus 0. This looks like a normal I2C-bus  
transmission until the falling edge of the eighth clock pulse. At that point, the master  
releases the data line (SDA) while the slave pulls it LOW through the PCA9515A.  
Because the VOL of the PCA9515A is typically round 0.5 V, a step in the SDA will be seen.  
After the master has transmitted the ninth clock pulse, the slave releases the data line.  
On the bus 1 side of the PCA9515A, the clock and data lines would have a positive offset  
from ground equal to the VOL of the PCA9515A. After the eighth clock pulse the data line  
will be pulled to the VOL of the slave device, which is very close to ground in this example.  
It is important to note that any arbitration or clock stretching events on bus 1 require that  
the VOL of the PCA9515A (see VOLVILc in Section 9 “Static characteristics”) to be  
recognized by the PCA9515A and then transmitted to bus 0.  
PCA9515A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 5 — 23 March 2012  
5 of 20  
PCA9515A  
NXP Semiconductors  
I2C-bus repeater  
th  
9
clock pulse  
SCL  
SDA  
V
OL  
of PCA9515A  
V
OL  
of master  
002aad740  
Fig 6. Bus 0 waveform  
th  
9
clock pulse  
SCL  
SDA  
V
OL  
of PCA9515A  
V
of slave  
002aad741  
OL  
Fig 7. Bus 1 waveform  
8. Limiting values  
Table 3.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Voltages with respect to pin GND.  
Symbol  
VCC  
Parameter  
Conditions  
Min  
0.5  
0.5  
-
Max  
+7  
Unit  
V
supply voltage  
I2C-bus voltage  
VI2C-bus  
II/O  
SCL or SDA  
DC; any pin  
+7  
V
input/output current  
total power dissipation  
storage temperature  
ambient temperature  
50  
mA  
mW  
C  
Ptot  
-
100  
+125  
+85  
Tstg  
55  
40  
Tamb  
operating in free air  
C  
PCA9515A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 5 — 23 March 2012  
6 of 20  
PCA9515A  
NXP Semiconductors  
I2C-bus repeater  
9. Static characteristics  
Table 4.  
Static characteristics (VCC = 3.0 V to 3.6 V)  
VCC = 3.0 V to 3.6 V[1]; GND = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.  
Symbol Parameter  
Supplies  
Conditions  
Min  
Typ[2] Max  
Unit  
VCC  
ICCH  
supply voltage  
3.0  
-
-
3.6  
5
V
HIGH-level supply current  
both channels HIGH;  
VCC = 3.6 V;  
0.8  
mA  
SDAn = SCLn = VCC  
ICCL  
LOW-level supply current  
both channels LOW;  
VCC = 3.6 V;  
one SDA and one SCL = GND;  
other SDA and SCL open  
-
-
1.7  
1.6  
5
5
mA  
mA  
ICCLc  
contention LOW-level supply current VCC = 3.6 V;  
SDAn = SCLn = GND  
Input SCLn; input/output SDAn  
VIH  
VIL  
VILc  
VIK  
ILI  
HIGH-level input voltage  
LOW-level input voltage  
contention LOW-level input voltage  
input clamping voltage  
0.7VCC  
-
5.5  
V
[3]  
[3]  
0.5  
-
+0.3VCC  
+0.4  
1.2  
+1  
V
0.5  
-
V
II = 18 mA  
-
-
V
input leakage current  
VI = 3.6 V  
1  
-
A  
A  
V
IIL  
LOW-level input current  
LOW-level output voltage  
SDAn, SCLn; VI = 0.2 V  
IOL = 20 A or 6 mA  
-
-
5
VOL  
0.47  
-
0.52  
-
0.6  
VOLVILc difference between LOW-level output guaranteed by design  
70  
mV  
and LOW-level input voltage  
contention  
Ci  
input capacitance  
VI = 3 V or 0 V  
-
6
7
pF  
Enable  
VIL  
LOW-level input voltage  
HIGH-level input voltage  
LOW-level input current on pin EN  
input leakage current  
0.5  
2.0  
-
-
+0.8  
5.5  
30  
+1  
V
VIH  
-
V
IIL(EN)  
ILI  
VI = 0.2 V  
10  
A  
A  
pF  
1  
-
-
Ci  
input capacitance  
VI = 3.0 V or 0 V  
6
7
[1] For operation between published voltage ranges (Table 4 for VCC = 3.0 V to 3.6 V; Table 5 for VCC = 2.3 V to 2.7 V), refer to worst-case  
parameter in both ranges.  
[2] Typical value taken at VCC = 3.3 V and Tamb = 25 C.  
[3] VIL specification is for the first LOW level seen by the SDAn/SCLn lines. VILc is for the second and subsequent LOW levels seen by the  
SDAn/SCLn lines.  
PCA9515A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 5 — 23 March 2012  
7 of 20  
PCA9515A  
NXP Semiconductors  
I2C-bus repeater  
Table 5.  
V
Static characteristics (VCC = 2.3 V to 2.7 V)  
CC = 2.3 V to 2.7 V[1]; GND = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ[2] Max  
Unit  
Supplies  
VCC  
supply voltage  
2.3  
-
-
2.7  
5
V
ICCH  
HIGH-level supply current  
both channels HIGH;  
VCC = 2.7 V;  
0.8  
mA  
SDAn = SCLn = VCC  
ICCL  
LOW-level supply current  
both channels LOW;  
VCC = 2.7 V;  
one SDA and one SCL = GND;  
other SDA and SCL open  
-
-
1.6  
1.6  
5
5
mA  
mA  
ICCLc  
contention LOW-level supply current VCC = 2.7 V;  
SDAn = SCLn = GND  
Input SCLn; input/output SDAn  
VIH  
VIL  
VILc  
VIK  
ILI  
HIGH-level input voltage  
LOW-level input voltage  
contention LOW-level input voltage  
input clamping voltage  
0.7VCC  
-
5.5  
V
[3]  
[3]  
0.5  
-
+0.3VCC  
+0.4  
1.2  
+1  
V
0.5  
-
V
II = 18 mA  
-
-
V
input leakage current  
VI = 2.7 V  
1  
-
A  
A  
V
IIL  
LOW-level input current  
LOW-level output voltage  
SDAn, SCLn; VI = 0.2 V  
IOL = 20 A or 6 mA  
-
-
10  
VOL  
0.47  
-
0.52  
-
0.6  
VOLVILc difference between LOW-level output guaranteed by design  
70  
mV  
and LOW-level input voltage  
contention  
Ci  
input capacitance  
VI = 3 V or 0 V  
-
6
7
pF  
Enable  
VIL  
LOW-level input voltage  
HIGH-level input voltage  
LOW-level input current on pin EN  
input leakage current  
0.5  
2.0  
-
-
+0.8  
5.5  
30  
+1  
V
VIH  
-
V
IIL(EN)  
ILI  
VI = 0.2 V  
10  
A  
A  
pF  
1  
-
-
Ci  
input capacitance  
VI = 3.0 V or 0 V  
6
7
[1] For operation between published voltage ranges (Table 4 for VCC = 3.0 V to 3.6 V; Table 5 for VCC = 2.3 V to 2.7 V), refer to worst-case  
parameter in both ranges.  
[2] Typical value taken at VCC = 2.5 V and Tamb = 25 C.  
[3]  
V
IL specification is for the first LOW level seen by the SDAn/SCLn lines. VILc is for the second and subsequent LOW levels seen by the  
SDAn/SCLn lines.  
PCA9515A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 5 — 23 March 2012  
8 of 20  
PCA9515A  
NXP Semiconductors  
I2C-bus repeater  
10. Dynamic characteristics  
Table 6.  
Dynamic characteristics (VCC = 2.3 V to 2.7 V)  
VCC = 2.3 V to 2.7 V; GND = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
45  
33  
-
Typ[1] Max  
Unit  
ns  
tPHL  
tPLH  
tTHL  
tTLH  
tsu  
HIGH to LOW propagation delay  
Figure 8  
82  
113  
57  
148  
-
130  
[2]  
[2]  
LOW to HIGH propagation delay  
HIGH to LOW output transition time  
LOW to HIGH output transition time  
set-up time  
Figure 8  
190  
ns  
Figure 8  
-
-
-
-
ns  
Figure 8  
-
ns  
EN HIGH before START condition  
EN HIGH after STOP condition  
100  
130  
ns  
th  
hold time  
-
ns  
[1] Typical values taken at VCC = 2.5 V and Tamb = 25 C.  
[2] Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times.  
Table 7.  
Dynamic characteristics (VCC = 3.0 V to 3.6 V)  
VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
45  
33  
-
Typ[1] Max  
Unit  
ns  
tPHL  
tPLH  
tTHL  
tTLH  
tsu  
HIGH to LOW propagation delay  
Figure 8  
68  
102  
58  
147  
-
120  
[2]  
[2]  
LOW to HIGH propagation delay  
HIGH to LOW output transition time  
LOW to HIGH output transition time  
set-up time  
Figure 8  
180  
ns  
Figure 8  
-
-
-
-
ns  
Figure 8  
-
ns  
EN HIGH before START condition  
EN HIGH after STOP condition  
100  
100  
ns  
th  
hold time  
-
ns  
[1] Typical values taken at VCC = 3.3 V and Tamb = 25 C.  
[2] Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times.  
10.1 AC waveforms  
3.3 V  
input  
1.5 V  
1.5 V  
0.1 V  
t
t
PLH  
PHL  
3.3 V  
80 %  
80 %  
1.5 V  
20 %  
1.5 V  
20 %  
output  
V
OL  
t
t
TLH  
THL  
002aad478  
Fig 8. Propagation delay and transition times  
PCA9515A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 5 — 23 March 2012  
9 of 20  
PCA9515A  
NXP Semiconductors  
I2C-bus repeater  
11. Test information  
V
CC  
V
CC  
R
L
V
V
O
I
PULSE  
GENERATOR  
DUT  
C
L
R
T
002aad479  
RL = load resistor; 1.35 k  
CL = load capacitance includes jig and probe capacitance; 50 pF  
RT = termination resistance should be equal to Zo of pulse generators  
Fig 9. Test circuit for open-drain outputs  
PCA9515A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 5 — 23 March 2012  
10 of 20  
PCA9515A  
NXP Semiconductors  
I2C-bus repeater  
12. Package outline  
SO8: plastic small outline package; 8 leads; body width 3.9 mm  
SOT96-1  
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
4
e
w
M
detail X  
b
p
0
2.5  
5 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(2)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
5.0  
4.8  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.27  
0.05  
1.05  
0.041  
1.75  
0.25  
0.01  
0.25  
0.01  
0.25  
0.1  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.20  
0.014 0.0075 0.19  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.024  
0.028  
0.012  
inches 0.069  
0.01 0.004  
Notes  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-18  
SOT96-1  
076E03  
MS-012  
Fig 10. Package outline SOT96-1 (SO8)  
PCA9515A  
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© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 5 — 23 March 2012  
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TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm  
SOT505-1  
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
A
(A )  
2
A
3
A
1
pin 1 index  
θ
L
p
L
1
4
detail X  
e
w M  
b
p
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT  
v
w
y
Z
θ
1
2
3
p
max.  
0.15  
0.05  
0.95  
0.80  
0.45  
0.25  
0.28  
0.15  
3.1  
2.9  
3.1  
2.9  
5.1  
4.7  
0.7  
0.4  
0.70  
0.35  
6°  
0°  
mm  
1.1  
0.65  
0.25  
0.94  
0.1  
0.1  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-04-09  
03-02-18  
SOT505-1  
Fig 11. Package outline SOT505-1 (TSSOP8)  
PCA9515A  
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© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 5 — 23 March 2012  
12 of 20  
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HWSON8: plastic thermal enhanced very very thin small outline package; no leads;  
8 terminals; body 2 x 3 x 0.8 mm  
SOT1069-2  
X
D
B
A
E
A
2
A
A
1
A
3
terminal 1  
index area  
detail X  
e
1
C
terminal 1  
index area  
v
C A  
C
B
e
b
y
y
w
C
1
1
4
L
K
E
2
8
5
D
2
0
1
2 mm  
K
scale  
Dimensions  
Unit  
(1)  
(1)  
(1)  
A
A
A
A
b
D
D
2
E
E
e
e
1
L
v
w
y
y
1
1
2
3
2
max 0.80 0.05 0.65  
mm nom 0.75 0.02 0.55 0.2 0.25 2.0 1.5 3.0 1.5 0.5 1.5 0.35 0.40 0.1 0.05 0.05 0.05  
min 0.70 0.00 0.45 0.18 1.9 1.4 2.9 1.4 0.30 0.35  
0.30 2.1 1.6 3.1 1.6  
0.40 0.45  
Note  
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.  
sot1069-2_po  
References  
Outline  
version  
European  
projection  
Issue date  
IEC  
- - -  
JEDEC  
JEITA  
- - -  
09-10-22  
09-11-18  
SOT1069-2  
MO-229  
Fig 12. Package outline SOT1069-2 (HWSON8)  
PCA9515A  
All information provided in this document is subject to legal disclaimers.  
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Product data sheet  
Rev. 5 — 23 March 2012  
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13. Soldering of SMD packages  
This text provides a very brief insight into a complex technology. A more in-depth account  
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow  
soldering description”.  
13.1 Introduction to soldering  
Soldering is one of the most common methods through which packages are attached to  
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both  
the mechanical and the electrical connection. There is no single soldering method that is  
ideal for all IC packages. Wave soldering is often preferred when through-hole and  
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not  
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high  
densities that come with increased miniaturization.  
13.2 Wave and reflow soldering  
Wave soldering is a joining technology in which the joints are made by solder coming from  
a standing wave of liquid solder. The wave soldering process is suitable for the following:  
Through-hole components  
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board  
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless  
packages which have solder lands underneath the body, cannot be wave soldered. Also,  
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,  
due to an increased probability of bridging.  
The reflow soldering process involves applying solder paste to a board, followed by  
component placement and exposure to a temperature profile. Leaded packages,  
packages with solder balls, and leadless packages are all reflow solderable.  
Key characteristics in both wave and reflow soldering are:  
Board specifications, including the board finish, solder masks and vias  
Package footprints, including solder thieves and orientation  
The moisture sensitivity level of the packages  
Package placement  
Inspection and repair  
Lead-free soldering versus SnPb soldering  
13.3 Wave soldering  
Key characteristics in wave soldering are:  
Process issues, such as application of adhesive and flux, clinching of leads, board  
transport, the solder wave parameters, and the time during which components are  
exposed to the wave  
Solder bath specifications, including temperature and impurities  
PCA9515A  
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© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 5 — 23 March 2012  
14 of 20  
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13.4 Reflow soldering  
Key characteristics in reflow soldering are:  
Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to  
higher minimum peak temperatures (see Figure 13) than a SnPb process, thus  
reducing the process window  
Solder paste printing issues including smearing, release, and adjusting the process  
window for a mix of large and small components on one board  
Reflow temperature profile; this profile includes preheat, reflow (in which the board is  
heated to the peak temperature) and cooling down. It is imperative that the peak  
temperature is high enough for the solder to make reliable solder joints (a solder paste  
characteristic). In addition, the peak temperature must be low enough that the  
packages and/or boards are not damaged. The peak temperature of the package  
depends on package thickness and volume and is classified in accordance with  
Table 8 and 9  
Table 8.  
SnPb eutectic process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (C)  
Volume (mm3)  
< 350  
350  
220  
< 2.5  
235  
220  
2.5  
220  
Table 9.  
Lead-free process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (C)  
Volume (mm3)  
< 350  
260  
350 to 2000  
> 2000  
260  
< 1.6  
260  
250  
245  
1.6 to 2.5  
> 2.5  
260  
245  
250  
245  
Moisture sensitivity precautions, as indicated on the packing, must be respected at all  
times.  
Studies have shown that small packages reach higher temperatures during reflow  
soldering, see Figure 13.  
PCA9515A  
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Product data sheet  
Rev. 5 — 23 March 2012  
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maximum peak temperature  
= MSL limit, damage level  
temperature  
minimum peak temperature  
= minimum soldering temperature  
peak  
temperature  
time  
001aac844  
MSL: Moisture Sensitivity Level  
Fig 13. Temperature profiles for large and small components  
For further information on temperature profiles, refer to Application Note AN10365  
“Surface mount reflow soldering description”.  
14. Abbreviations  
Table 10. Abbreviations  
Acronym  
CDM  
Description  
Charged-Device Model  
Complementary Metal-Oxide Semiconductor  
ElectroStatic Discharge  
Human Body Model  
CMOS  
ESD  
HBM  
I/O  
Input/Output  
I2C-bus  
Inter-Integrated Circuit bus  
System Management Bus  
SMBus  
PCA9515A  
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© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 5 — 23 March 2012  
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15. Revision history  
Table 11. Revision history  
Document ID  
PCA9515A v.5  
Modifications:  
Release date  
Data sheet status  
Change notice  
Supersedes  
20120323  
Product data sheet  
-
PCA9515A v.4  
Section 2 “Features and benefits”:  
12th bullet item: deleted phrase “200 V MM per JESD22-A115”  
14th bullet item: added “HWSON8” package  
Table 1 “Ordering information”: added Type number PCA9515ATP (HWSON8 package)  
Section 5.1 “Pinning”: added (new) Figure 4 “Pin configuration for HWSON8”  
Table 2 “Pin description”: added column for HWSON8 pinning  
Table 3 “Limiting values”:  
Symbol/Parameter “Vbus, voltage on I2C-bus, SCL or SDA” changed to “VI2C-bus, I2C-bus  
voltage” with “SCL or SDA” in Conditions column  
Symbol/Parameter “I, DC current” changed to “II/O, input/output current”  
Table 4 “Static characteristics (VCC = 3.0 V to 3.6 V)”, Table note [1]: added phrase “(Table 4 for  
VCC = 3.0 V to 3.6 V; Table 5 for VCC = 2.3 V to 2.7 V)”  
Table 5 “Static characteristics (VCC = 2.3 V to 2.7 V)”, Table note [1]: added phrase “(Table 4 for  
VCC = 3.0 V to 3.6 V; Table 5 for VCC = 2.3 V to 2.7 V)”  
Section 12 “Package outline”: added (new) Figure 12 “Package outline SOT1069-2 (HWSON8)”  
PCA9515A v.4  
20080411  
Product data sheet  
-
PCA9515A v.3  
PCA9515A v.3  
20040929  
Product data sheet  
-
PCA9515A v.2  
(9397 750 14098)  
PCA9515A v.2  
(9397 750 13709)  
20040709  
20040617  
Product data sheet  
Objective data sheet  
-
-
PCA9515A v.1  
-
PCA9515A v.1  
(9397 98 13237)  
PCA9515A  
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© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 5 — 23 March 2012  
17 of 20  
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16. Legal information  
16.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
Suitability for use — NXP Semiconductors products are not designed,  
16.2 Definitions  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors and its suppliers accept no liability for  
inclusion and/or use of NXP Semiconductors products in such equipment or  
applications and therefore such inclusion and/or use is at the customer’s own  
risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
16.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information. NXP Semiconductors takes no  
responsibility for the content in this document if provided by an information  
source outside of NXP Semiconductors.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
PCA9515A  
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© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 5 — 23 March 2012  
18 of 20  
PCA9515A  
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Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
liability, damages or failed product claims resulting from customer design and  
use of the product for automotive applications beyond NXP Semiconductors’  
standard warranty and NXP Semiconductors’ product specifications.  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific NXP Semiconductors product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. NXP  
Semiconductors accepts no liability for inclusion and/or use of  
Translations — A non-English (translated) version of a document is for  
reference only. The English version shall prevail in case of any discrepancy  
between the translated and English versions.  
non-automotive qualified products in automotive equipment or applications.  
16.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
NXP Semiconductors’ specifications such use shall be solely at customer’s  
I2C-bus — logo is a trademark of NXP B.V.  
17. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
PCA9515A  
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© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 5 — 23 March 2012  
19 of 20  
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18. Contents  
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
5
5.1  
5.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3  
6
6.1  
6.2  
Functional description . . . . . . . . . . . . . . . . . . . 4  
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
I2C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 4  
7
Application design-in information . . . . . . . . . . 5  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9  
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Test information. . . . . . . . . . . . . . . . . . . . . . . . 10  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11  
8
9
10  
10.1  
11  
12  
13  
Soldering of SMD packages . . . . . . . . . . . . . . 14  
Introduction to soldering . . . . . . . . . . . . . . . . . 14  
Wave and reflow soldering . . . . . . . . . . . . . . . 14  
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 14  
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 15  
13.1  
13.2  
13.3  
13.4  
14  
15  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17  
16  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
16.1  
16.2  
16.3  
16.4  
17  
18  
Contact information. . . . . . . . . . . . . . . . . . . . . 19  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2012.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 23 March 2012  
Document identifier: PCA9515A  

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