PCA9518_技术文档

INTEGRATED CIRCUITS

PCA9518

Expandable 5-channel I²C hub

Product data sheet

2004 Sep 29

Supersedes data of 2004 Jun 24

Philips

Semiconductors

Philips Semiconductors

Product data sheet

Expandable 5-channel I²C hub

PCA9518

DESCRIPTION

The PCA9518 is a BiCMOS integrated circuit intended for

2

application in I C and SMBus systems.

2

While retaining all the operating modes and features of the I C

2

system, it permits extension of the I C-bus by buffering both the

data (SDA) and the clock (SCL) lines, thus enabling virtually

unlimited buses of 400 pF.

PIN CONFIGURATION

2

The I C-bus capacitance limit of 400 pF restricts the number of

devices and bus length. Using the PCA9518 enables the system

designer to divide the bus into an unlimited number of segments off

of a hub where any segment to segment transition sees only one

repeater delay and is multiple master capable on each segment.

EXPSCL1

EXPSCL2

SCL0

1

2

3

4

5

6

7

8

9

20 V

CC

19 EXPSDA2

18 EXPSDA1

17 EN4

1

Using multiple PCA9518 parts, any width hub (in multiples of five)

SDA0

can be implemented using the expansion pins.

SCL1

16 SDA4

15 SCL4

14 EN3

A PCA9518 cluster cannot be put in series with a PCA9515/16

or with another PCA9518 cluster. Multiple PCA9518 devices can

be grouped with other PCA9518 devices into any size cluster thanks

to the EXPxxxx pins that allow the I2C signals to be sent/received

from/to one PCA9518 to/from another PCA9518 within the cluster.

Since there is no direction pin, slightly different “legal” low voltage

levels are used to avoid lock up conditions between the input and

the output of individual repeaters in the cluster. A “regular low”

applied at the input of any of the PCA9518 devices will then be

propagated as a “buffered low” with a slightly higher value to all

enabled outputs in the PCA9518 cluster. When this “buffered low” is

applied to a PCA9515 and PCA9516 or separate PCA9518 cluster

(not connected via the EXPxxx pins) in series, the second PCA9515

and PCA9516 or PCA9518 cluster will not recognize it as a “regular

low” and will not propagate it as a “buffered low ” again. The

PCA9510/9511/9513/9514 and PCA9512 cannot be used in series

with the PCA9515 and PCA9516 or PCA9518 but can be used in

series with themselves since they use shifting instead of static

offsets to avoid lock up conditions.

SDA1

EN1

SCL2

13 SDA3

12 SCL3

11 EN2

SDA2

GND 10

SU01595

Figure 1. Pin configuration

PIN DESCRIPTION

1

SYMBOL

FUNCTION

EXPSCL1

EXPSCL2

SCL0

Expandable serial clock pin 1

Expandable serial clock pin 2

Serial clock bus 0

2

3

4

SDA0

SCL1

Serial data bus 0

5

Serial clock bus 1

FEATURES

6

SDA1

EN1

Serial data bus 1

• Expandable 5 channel, bi-directional buffer

• I C-bus and SMBus compatible

• Active-HIGH individual repeater enable inputs

• Open-drain input/outputs

• Lock-up free operation

2

7

Active-HIGH Bus 1 enable Input

Serial clock bus 2

8

SCL2

9

SDA2

GND

Serial data bus 2

10

11

12

13

14

15

16

17

18

19

20

Supply ground

EN2

Active-HIGH Bus 2 enable Input

Serial clock bus 3

• Supports arbitration and clock stretching across the repeater

2

SCL3

• Accommodates standard mode and fast mode I C devices and

multiple masters

SDA3

EN3

Serial data bus 3

2

• Powered-off high-impedance I C pins

Active-HIGH Bus 3 enable Input

Serial clock bus 4

• Operating supply voltage range of 3.0 V to 3.6 V

SCL4

2

• 5 V tolerant I C and enable pins

• 0 kHz to 400 kHz clock frequency

SDA4

EN4

Serial data bus 4

2

Active-HIGH Bus 4 enable Input

Expandable serial data pin 1

Expandable serial data pin 2

Supply power

• ESD protection exceeds 2000 V HBM per JESD22-A114,

200 V MM per JESD22-A115, and 1000 V CDM per

JESD22-C101.

EXPSDA1

EXPSDA2

V

CC

• Latch-up testing is done to JEDEC Standard JESD78 which

exceeds 100 mA.

• Package offerings: SO and TSSOP

ORDERING INFORMATION

PACKAGES

20-pin plastic SO

20-pin plastic TSSOP

TEMPERATURE RANGE

–40 °C to +85 °C

ORDER CODE

TOPSIDE MARK

DRAWING NUMBER

SOT163-1

PCA9518D

PCA9518

–40 °C to +85 °C

PCA9518PW

SOT360-1

Standard packing quantities and other packaging data is available at www.standardproducts.philips.com/packaging.

1.

2.

Only four ports per device are available if individual Enable is required.

The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.

2

2004 Sep 29

Philips Semiconductors

Product data sheet

Expandable 5-channel I²C hub

PCA9518

V

CC

PCA9518

EXPSCL1

EXPSCL2

Buffer

SCL0

Buffer

SCL4

SCL3

Hub

Logic

Buffer

SCL1

SCL2

EXPSDA1

EXPSDA2

Buffer

SDA0

Buffer

SDA4

SDA3

Hub

Logic

Buffer

SDA1

SDA2

EN4

EN1

EN2

EN3

GND

SU01596

Figure 2. Block Diagram: PCA9518

A more detailed view of Figure 2 buffer is shown in Figure 3.

The output pull-down voltage of each internal buffer is set for

approximately 0.5 V, while the input threshold of each internal buffer

is set about 0.07 V lower, when the output is internally driven LOW.

This prevents a lock-up condition from occurring.

To output

Data

z

In

Inc

Enable

SW00712

Figure 3. Buffer detail

3

2004 Sep 29

Philips Semiconductors

Product data sheet

Expandable 5-channel I²C hub

PCA9518

connected to a 3.3 V or 5 V bus. All buses run at 100 kHz unless

slave 3, 4 and 5 are isolated from the bus. Then the master bus and

slave 1, 2 and 6 can run at 400 kHz.

FUNCTIONAL DESCRIPTION

The PCA9518 BiCMOS integrated circuit is a five way hub repeater,

2

which enables I C and similar bus systems to be expanded in

increments of five with only one repeater delay and no functional

degradation of system performance.

Any segment of the hub can talk to any other segment of the hub.

Bus masters and slaves can be located on any segment with 400 pF

load allowed on each segment.

The PCA9518 BiCMOS integrated circuit contains five

multi-directional, open drain buffers specifically designed to support

the standard low-level-contention arbitration of the I C-bus. Except

during arbitration or clock stretching, the PCA9518 acts like a pair of

non-inverting, open drain buffers, one for SDA and one for SCL.

The PCA9518 is 5 V tolerant so it does not require any additional

circuitry to translate between the different bus voltages.

2

When one port of the PCA9518 is pulled LOW by a device on the

2

I C-bus, a CMOS hysteresis type input detects the falling edge and

drives the EXPXXX1 line LOW, when the EXPXXX1 voltage is less

Enable

than1/2V , the other ports are pulled down to the V of the

The enable pins EN1 through EN4 are active-HIGH and have

internal pull-up resistors. Each enable pin ENn controls its

associated SDAn and SCLn ports. When LOW, the ENn pin blocks

the inputs from SDAn and SCLn, as well as disabling the output

drivers on the SDAn and SCLn pins. The enable pins should only

change state when both the global bus and the local port are in an

idle state to prevent system failures.

CC

OL

PCA9518 which is typically 0.5 V.

In order to illustrate what would be seen in a typical application, refer

to Figure 5. If the bus master in Figure 4 were to write to the slave

through the PCA9518, we would see the waveform shown in Figure

2

5. This looks like a normal I C transmission except for the small foot

preceding each clock LOW to HIGH transition and proceeding each

data LOW to HIGH transition for the master. The foot height is the

difference between the LOW level driven by the master and the

higher voltage LOW level driven by the PCA9518 repeater. Its width

corresponds to an effective clock stretching coming from the

PCA9518 which delays the rising edge of the clock. That same

magnitude of delay is seen on the rising edge of the data. The foot

on the rising edge of the data is extended through the 9th clock

pulse as the PCA9518 repeats the acknowledge from the slave to

The active-HIGH enable pins allow the use of open drain drivers

which can be wire-ORed to create a distributed enable where either

centralized control signal (master) or spoke signal (submaster) can

enable the channel when it is idle.

Expansion

The PCA9518 includes 4 open drain I/O pins used for expansion.

Two expansion pins, EXPSDA1 and EXPSDA2 are used to

communicate the internal state of the serial data within each hub to

the other hubs. The EXPSDA1 pins of all hubs are connected

together to form an open-drain bus. Similarly, all EXPSDA2 pins,

EXPSCL1 pins, and all EXPSCL2 pins are connected together

forming a 4-wire bus between hubs.

the master. The clock of the slave looks normal except the V is

OL

the 0.5 V level generated by the PCA9518. The SDA at the slave

has a particularly interesting shape during the 9th clock cycle where

the slave pulls the line below the value driven by the PCA9518

during the acknowledge and then returns to the PCA9518 level

creating a foot before it completes the LOW to HIGH transition. SDA

lines other than the one with the master and the one with the slave

have a uniform LOW level driven by the PCA9518 repeater.

When it is necessary to be able to deselect every port, each

expansion device only contributes 4 ports which can be enabled or

disables because the fifth does not have an enable pin.

The other four waveforms are the expansion bus signals and are

included primarily for timing reference points. All timing on the

3

Pull-up resistors are required on the EXPXXXX pins even if only

one PCA9518 is used.

expansion bus is with respect to 0.5 V . EXPSDA1 is the

CC

expansion bus that is driven LOW whenever any SDA pin falls

2

I C Systems

below 0.3 V . EXPSDA2 is the expansion bus that is driven LOW

CC

2

As with the standard I C system, pull-up resistors are required to

provide the logic HIGH levels on the Buffered bus. (Standard

open-collector or open-drain configuration of the I C-bus). The size

of these pull-up resistors depends on the system, but each side of

the repeater must have a pull-up resistor. This part is designed to

work with standard mode (0 to 100 kHz) and fast mode (0 to

whenever any pin is ≤0.4 V. EXPSCL1 is the expansion bus that is

driven LOW whenever any SCL pin falls below 0.3 V . EXPSCL2

CC

2

is the expansion bus that is driven LOW whenever any SCL pin is

≤0.4 V. The EXPSDA2 returns HIGH after the SDA pin that was the

last one being held below 0.4 V by an external driver starts to rise.

The last SDA to rise above 0.4 V is held down by the PCA 9518 to

0.5 V until after the delay of the circuit which determines that it was

the last to rise, then it is allowed to rise above the 0.5 V level driven

by the PCA9518. Considering the bus 0 SDA to be the last one to go

above 0.4 V, then the EXPSDA1 returns to HIGH after the

2

400 kHz) I C devices in addition to SMBus devices. Standard mode

2

I C devices only specify 3 mA output drive, this limits the termination

2

current to 3 mA in a generic I C system where standard mode

devices and multiple masters are possible. Please see Application

Note AN255 “I C & SMBus Repeaters, Hubs and Expanders” for

additional information on sizing resistors.

2

EXPSDA2 is HIGH and either the bus 0 SDA rise time is 1 µs or,

when the bus 0 SDA reaches 0.7 V , whichever occurs first. After

CC

both EXPSDA2 and EXPSDA1 are HIGH the rest of the SDA lines

are allowed to rise. The same description applies for the EXPSCL1,

EXPSCL2, and SCL pins.

APPLICATION INFORMATION

A typical application is shown in Figure 4. In this example, the

2

system master is running on a 3.3 V I C-bus while the slaves are

3.

XXXX is SDA1, SDA2, SCL1, or SCL2

XXX is SDA or SCL

4

2004 Sep 29

Philips Semiconductors

Product data sheet

Expandable 5-channel I²C hub

PCA9518

3.3 V

5 V

V

DD

V

DD

SDA

SDA1

SCL1

EXPSDA1

EXPSDA2

EXPSCL1

EXPSCL2

SUBSYSTEM 1

SDA

SUBSYSTEM 5

SCL

SDA1

SCL1

SCL

EXPSDA2

EXPSCL1

EXPSCL2

400 kHz

3.3 V

100 kHz

3.3 V

SDA

SDA2

SCL2

SDA2

SCL2

SDA

SUBSYSTEM 6

SUBSYSTEM 2

SCL

400 kHz

5 V

SDA0

SCL0

SDA0

SCL0

SDA

SCL

3.3 V or 5 V

PCA9518

DEVICE 2

PCA9518

DEVICE 1

BUS

MASTER

SDA3

SDA

SUBSYSTEM 3

SCL3

SCL

100 kHz

3.3 V

3.3 V or 5 V

EN1

EN2

EN3

EN4

DISABLED

NOT CONNECTED

EN1

EN2

EN3

EN4

SDA4

SCL4

400 kHz

SDA4

SCL4

SDA

SUBSYSTEM 4

GND

SCL

GND

100 kHz

SW00974

NOTE:

1. Only two of the five channels on the PCA9518 Device 2 are being used. EN3 and EN4 are connected to GND to disable channels 3 and 4

2

and/or SDA3/SCL3 and SDA4/SCL4 are pulled up to V . SDA0 and SCL0 can be used as a normal I C port, but if unused then it must be

CC

pulled-up to V since there is no enable pin.

CC

2

Figure 4. Typical application: Multiple expandable 5-channel I C hubs

5

2004 Sep 29

Philips Semiconductors

Product data sheet

Expandable 5-channel I²C hub

PCA9518

9TH CLOCK CYCLE

V

OF PCA9518

OL

V

OF MASTER

OL

SCL OF MASTER

SDA OF MASTER

BUS 0

t

st

EXPSDA1

t

f1

t

r1

t

Er1

EXPSDA2

EXPANSION

BUS

t

r2

t

f2

EXPSCL1

EXPSCL2

SCL OF SLAVE

SDA OF SLAVE

BUS 1

V

OF PCA9518

OL

V

OF SLAVE

OL

t

PHL

t

PLH

BUS n

WITH n > 1

SW01090

Figure 5. Bus waveforms

It is important to note that any arbitration or clock stretching events on Bus 1 require that the V of the devices on Bus 1 be 70 mV below the

OL

V

OL

of the PCA9518 (see V – V in the DC Characteristics section) to be recognized by the PCA9518 and then transmitted to Bus 0.

OL ilc

6

2004 Sep 29

Philips Semiconductors

Product data sheet

Expandable 5-channel I²C hub

PCA9518

ABSOLUTE MAXIMUM RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134).

Voltages with respect to pin GND.

LIMITS

SYMBOL

to GND

PARAMETER

MIN.

–0.5

—

MAX.

UNIT

V

CC

Supply voltage range V

+7

CC

2

V

bus

Voltage range I C-bus, SCL or SDA

DC current (any pin)

V

I

50

mA

mW

°C

P

tot

Power dissipation

—

300

+125

+85

T

stg

Storage temperature range

Operating ambient temperature range

–55

–40

T

amb

°C

DC ELECTRICAL CHARACTERISTICS

V

CC

= 3.0 to 3.6 V; GND = 0 V; T

= –40 to +85 °C; unless otherwise specified.

amb

LIMITS

TYP.

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

MIN.

MAX.

Supplies

V

DC supply voltage

3.0

—

3.3

7.5

3.6

10

V

CC

I

Quiescent supply current,

both channels HIGH

V

= 3.6 V;

mA

CCH

CC

SDAn = SCLn = V

CC

I

Quiescent supply current,

both channels LOW

V

= 3.6 V;

—

9

11

mA

CCL

CC

one SDA and one SCL = GND,

other SDA and SCL open

I

Quiescent supply current in contention

V

CC

= 3.6 V;

CCLc

SDAn = SCLn = GND

Input SCL; input/output SDA

V

HIGH-level input voltage, SCL, SDA

0.7 V

—

5.5

V

IH

CC

V

LOW-level input voltage, SCL, SDA

(Note 1)

–0.5

0.3 V

CC

IL

V

ILc

LOW-level input voltage contention,

SCL, SDA (Note 1)

–0.5

—

0.4

V

Input clamp voltage

I = –18 mA

—

–1.2

±1

V

µA

V

IK

I

Input leakage current

V = 3.6 V

I

Input current LOW, SDA, SCL

LOW level output, SCL, SDA

V = 0.2 V, SDA, SCL

—

5

IL

OL

I

2

V

I

OL

= 0 or 6 mA

0.47

—

0.52

—

0.6

70

V

–V

LOW level input voltage below

output LOW level voltage

Guaranteed by design

mV

OL

ILc

C

Input capacitance

V = 3 V or 0 V

I

—

6

8

pF

I

Enable 1–4

V

LOW level input voltage

HIGH level input voltage

Input current LOW

–0.5

2.0

—

10

—

3

0.8

5.5

30

1

V

IL

IH

IL

V

I

V

V = 0.2 V, EN1–EN4

µA

pF

I

LI

Input leakage current

Input capacitance

–1

C

V = 3.0 V or 0 V

I

—

7

I

Expansion Pins

0.55

V

IH

HIGH level input voltage, EXP*

—

5.5

V

CC

V

LOW level input voltage, EXP*

Input current LOW, EXP*

LOW level output, EXP*

Input capacitance

–0.5

—

6

0.45 V

V

µA

V

IL

CC

I

IL

V = 0.2 V, EXP*

5

0.5

8

I

V

OL

I

OL

= 12 mA

—

C

V = 3.0 V or 0 V

I

—

pF

I

NOTE:

1. V specification is for the first LOW level seen by the SDAx/SCLx lines. V is for the second and subsequent LOW levels seen by the

IL

ILc

SDAx/SCLx lines.

2. Test performed with I = 10 µA.

OL

7

2004 Sep 29

Philips Semiconductors

Product data sheet

Expandable 5-channel I²C hub

PCA9518

1

AC ELECTRICAL CHARACTERISTICS

3

LIMITS

TYP

SYMBOL

PARAMETER

TEST CONDITIONS

Waveform 1; Note 2

UNIT

MAX

MIN

t

Propagation delay

SDA to SDAn or SCL to SCLn

105

202

389

265

327

179

279

ns

PHLs

Propagation delay

SDA to SDAn or SCL to SCLn

Waveform 1; Note 3

Waveform 1

110

109

130

160

259

193

153

234

110

PLHs

Propagation delay

EXPSDA1 to SDA or EXPSCL1 to SCL

PHLE1s

PLHE1s

PLHE2s

Propagation delay

EXPSDA1 to SDA or EXPSCL1 to SCL

Waveform 1

Propagation delay

EXPSDA2 to SDA or EXPSCL2 to SCL

Waveform 1

t

Transition time, SDA/SCL

Enable to Start condition

Enable after Stop condition

Waveform 1

58

—

187

—

ns

THLs

TLHs

SET

0.85 RC

300

—

HOLD

NOTES:

1. The SDA and SCL propagation delays are dominated by rise times or fall times. The fall times are mostly internally controlled and are only

sensitive to load capacitance. The rise times are RC time constant controlled and therefor a specific numerical value can only be given for

fixed RC time constants.

2. The SDA HIGH to LOW propagation delay, t

, includes the fall time from V to 0.5 V of the EXPSDA1 or EXPSCL1 pins and the SDA

PLHs

CC CC

or SCL fall time from the quiescent HIGH (usually V ) to below 0.3 V . The SDA and SCL outputs have edge rate control circuits included

CC

which make the fall time almost independent of load capacitance.

3. The SDA or SCL LOW to HIGH propagation delay includes the rise time constant from the quiescent LOW to 0.5 V for the EXPSDA1 or

CC

EXPSCL2, the rise time constant for the quiescent LOW to 0.5 V for the EXPSDA1 or EXPSCL1, and the rise time constant from the

CC

quiescent external driven LOW to 0.7 V for the SDA or SCL output. All of these rise times are RC time constants determined by the

CC

external R and total C for the various nodes.

AC WAVEFORMS

TEST CIRCUIT

INPUT

SDA

t

THLs

t

V

CC

V

CC

TLHs

OR SCL

0.7 V

CC

0.7 V

CC

0.3 V

R

CC

0.3 V

L

CC

V

0.4 V

IN

OUT

0.4 V

PULSE

GENERATOR

D.U.T.

t

EFFECTIVE

STRETCH

PHLs

EXPSDA1

OR

R

T

C

L

EXPSCL1

0.5 V

CC

Test circuit for open-drain outputs

EXPSDA2

OR

EXPSCL2

DEFINITIONS

R = Load resistor; 1.1 kΩ for I C and 500 Ω for EXP.

2

L

t

PLHs

0.5 V

CC

C = Load capacitance includes jig and probe capacitance;

L

2

t

100 pF for I C and 100 pF for EXP

PLHE1s

R = Termination resistance should be equal to Z

T

of

OUT

t

PHLs

PLHE2s

pulse generators.

PLHs

SW01088

t

THLs

OUTPUT

SDA

OR SCL

0.7 V

CC

Figure 6. Test circuit

0.3 V

CC

0.52 V

SW01089

Waveform 1.

8

2004 Sep 29

Philips Semiconductors

Product data sheet

Expandable 5-channel I²C hub

PCA9518

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

9

2004 Sep 29

Philips Semiconductors

Product data sheet

Expandable 5-channel I²C hub

PCA9518

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SOT360-1

10

2004 Sep 29

Philips Semiconductors

Product data sheet

Expandable 5-channel I²C hub

PCA9518

REVISION HISTORY

Rev

Date

Description

_4

20040929

Product data sheet (9397 750 14109). Supersedes data of 2004 Jun 24 (9397 750 13253).

Modifications:

• “Description” section on page 2, last sentence: change from “The PCA9511/9513/9514 and the PCA9512

cannot be used in series ...” to “The PCA9510/9511/9513/9514 and PCA9512 cannot be used in series ...”

• Figure 4 on page 5 modified.

• Note 1 on page 5 re-written.

_3

_2

20040624

20031110

Product data sheet (9397 750 13253). Supersedes data of 10 November 2003 (9397 750 12295).

Product data (9397 750 12295); ECN 853-2364 30410 dated 03 October 2003.

Supersedes data of 20 August 2002 (9397 750 10258).

_1

20020820

Product data (9397 750 10258); ECN: 853–2364 28791 (2002 Aug 20)

11

2004 Sep 29

Philips Semiconductors

Product data sheet

Expandable 5-channel I²C hub

PCA9518

2

Purchase of Philips I C components conveys a license under the Philips’ I C patent

2

to use the components in the I C system provided the system conforms to the

I C specifications defined by Philips. This specification can be ordered using the

2

code 9398 393 40011.

Data sheet status

Product

status

Definitions

[1]

Level

Data sheet status

[2] [3]

I

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

II

Preliminary data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in

order to improve the design and supply the best possible product.

III

Product data

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given

in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no

representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree

to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described

or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated

viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys

nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,

copyright, or mask work right infringement, unless otherwise specified.

Koninklijke Philips Electronics N.V. 2004

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 09-04

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document number:

9397 750 14109

Philips

Semiconductors

12

2004 Sep 29


型号：	PCA9518
厂家：	NXP
描述：	Expandable 5-channel I2C hub 可扩展5通道I2C集线器
文件：	总12页 (文件大小：111K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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