PCA9535APW,118 [NXP]
PCA9535A - Low-voltage 16-bit I²C-bus I/O port with interrupt TSSOP2 24-Pin;
| 型号： | PCA9535APW,118 |
| 厂家： | 
NXP |
| 描述： | PCA9535A - Low-voltage 16-bit I²C-bus I/O port with interrupt TSSOP2 24-Pin PC 光电二极管 外围集成电路 |
| 文件： | 总38页 (文件大小：2410K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9535A
Low-voltage 16-bit I2C-bus I/O port with interrupt
Rev. 1 — 11 September 2012
Product data sheet
1. General description
The PCA9535A is a low-voltage 16-bit General Purpose Input/Output (GPIO) expander
with interrupt and reset for I2C-bus/SMBus applications. NXP I/O expanders provide a
simple solution when additional I/Os are needed while keeping interconnections to a
minimum, for example, in ACPI power switches, sensors, push buttons, LEDs, fan control,
etc.
In addition to providing a flexible set of GPIOs, the wide VDD range of 1.65 V to 5.5 V
allows the PCA9535A to interface with next-generation microprocessors and
microcontrollers where supply levels are dropping down to conserve power.
The PCA9535A contains the PCA9535 register set of four pairs of 8-bit Configuration,
Input, Output, and Polarity Inversion registers.
The PCA9535A is a pin-to-pin replacement to the PCA9535 and other industry-standard
devices. A more fully featured device, the PCAL9535A, is available with Agile I/O
features. See the respective data sheet for more details.
The PCA9535A open-drain interrupt (INT) output is activated when any input state differs
from its corresponding Input Port register state and is used to indicate to the system
master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I2C-bus. Thus, the PCA9535A can
remain a simple slave device.
The device outputs have 25 mA sink capabilities for directly driving LEDs while consuming
low device current.
The power-on reset sets the registers to their default values and initializes the device state
machine.
Three hardware pins (A0, A1, A2) select the fixed I2C-bus address and allow up to eight
devices to share the same I2C-bus/SMBus.
2. Features and benefits
I2C-bus to parallel port expander
Pin and function compatible with PCA9535
Operating power supply voltage range of 1.65 V to 5.5 V
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
Low standby current consumption:
1.5 A (typical at 5 V VDD
1.0 A (typical at 3.3 V VDD
)
)
Schmitt-trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs
Vhys = 0.10 VDD (typical)
5 V tolerant I/Os
Open-drain active LOW interrupt output (INT)
400 kHz Fast-mode I2C-bus
Internal power-on reset
Power-up with all channels configured as inputs
No glitch on power-up
Latched outputs with 25 mA drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100 mA per JESD78, Class II
ESD protection exceeds JESD22
2000 V Human Body Model (A114-A)
1000 V Charged-Device Model (C101)
Packages offered: TSSOP24, HWQFN24
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
PCA9535AHF
PCA9535APW
HWQFN24 plastic thermal enhanced very very thin quad flat package; no leads;
SOT994-1
24 terminals; body 4 4 0.75 mm
TSSOP24
plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
3.1 Ordering options
Table 2.
Ordering options
Type number
PCA9535AHF
PCA9535APW
Topside mark
535A
Temperature range
40 C to +85 C
40 C to +85 C
PCA9535A
PCA9535A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 11 September 2012
2 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
4. Block diagram
PCA9535A
P1_0
P1_1
8-bit
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
A0
A1
A2
INPUT/
OUTPUT
PORTS
write pulse
read pulse
2
I C-BUS/SMBus
CONTROL
SCL
SDA
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
INPUT
FILTER
8-bit
INPUT/
OUTPUT
PORTS
write pulse
read pulse
V
DD
POWER-ON
RESET
V
DD
V
SS
INT
LP
FILTER
002aag207
Remark: All I/Os are set to inputs at reset.
Fig 1. Block diagram of PCA9535A
5. Pinning information
5.1 Pinning
PCA9535AHF
INT
A1
1
2
24
23
22
21
20
19
18
17
16
15
14
13
V
DD
terminal 1
SDA
SCL
index area
A2
3
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
4
A0
1
2
3
4
5
6
18
17
16
15
14
13
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
A0
5
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
P1_7
P1_6
P1_5
P1_4
P1_3
6
PCA9535APW
7
8
9
10
11
12
002aag209
V
SS
Transparent top view
002aag208
Fig 2. Pin configuration for TSSOP24
Fig 3. Pin configuration for HWQFN24
PCA9535A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 11 September 2012
3 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
5.2 Pin description
Table 3.
Symbol Pin
TSSOP24
Pin description
Type
Description
HWQFN24
INT
1
22
O
Interrupt output. Connect to VDD through a
pull-up resistor.
A1
2
23
24
1
I
Address input 1. Connect directly to VDD or VSS
Address input 2. Connect directly to VDD or VSS
Port 0 input/output 0.
.
.
A2
3
I
P0_0[2]
P0_1[2]
P0_2[2]
P0_3[2]
P0_4[2]
P0_5[2]
P0_6[2]
P0_7[2]
VSS
P1_0[3]
P1_1[3]
P1_2[3]
P1_3[3]
P1_4[3]
P1_5[3]
P1_6[3]
P1_7[3]
A0
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
5
2
Port 0 input/output 1.
6
3
Port 0 input/output 2.
7
4
Port 0 input/output 3.
8
5
Port 0 input/output 4.
9
6
Port 0 input/output 5.
10
11
12
13
14
15
16
17
18
19
20
21
22
7
Port 0 input/output 6.
8
Port 0 input/output 7.
9[1]
10
11
12
13
14
15
16
17
18
19
Ground.
Port 1 input/output 0.
Port 1 input/output 1.
Port 1 input/output 2.
Port 1 input/output 3.
Port 1 input/output 4.
Port 1 input/output 5.
Port 1 input/output 6.
Port 1 input/output 7.
Address input 0. Connect directly to VDD or VSS
.
SCL
I
Serial clock bus. Connect to VDD through a
pull-up resistor.
SDA
VDD
23
24
20
21
I/O
Serial data bus. Connect to VDD through a
pull-up resistor.
power
Supply voltage.
[1] HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
[2] Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-up, all I/O are configured as high-impedance
inputs.
[3] Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-up, all I/O are configured as high-impedance
inputs.
PCA9535A
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 11 September 2012
4 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
6. Functional description
Refer to Figure 1 “Block diagram of PCA9535A”.
6.1 Device address
slave address
0
1
0
0
A2 A1 A0 R/W
fixed
hardware
selectable
002aah371
Fig 4. PCA9535A device address
A2, A1 and A0 are the hardware address package pins and are held to either HIGH
(logic 1) or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit
of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH
(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
6.2 Registers
6.2.1 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCA9535A. The lower
three bits of this data byte state the operation (read or write) and the internal registers
(Input, Output, Polarity Inversion, or Configuration) that will be affected. This register is
write only.
B7 B6 B5 B4 B3 B2 B1 B0
002aaf540
Fig 5. Pointer register bits
Table 4.
Command byte
Pointer register bits
B7 B6 B5 B4 B3 B2 B1 B0
Command byte Register
(hexadecimal)
Protocol
Power-up
default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
00h
01h
02h
03h
04h
05h
06h
07h
Input port 0
read byte
read byte
xxxx xxxx[1]
xxxx xxxx
Input port 1
Output port 0
read/write byte 1111 1111
read/write byte 1111 1111
read/write byte 0000 0000
read/write byte 0000 0000
read/write byte 1111 1111
read/write byte 1111 1111
Output port 1
Polarity Inversion port 0
Polarity Inversion port 1
Configuration port 0
Configuration port 1
[1] Undefined.
PCA9535A
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 11 September 2012
5 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
6.2.2 Input port register pair (00h, 01h)
The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by the Configuration
register. The Input port registers are read only; writes to these registers have no effect.
The default value ‘X’ is determined by the externally applied logic level. An Input port
register read operation is performed as described in Section 7.2 “Reading the port
registers”.
Table 5.
Bit
Input port 0 register (address 00h)
7
I0.7
X
6
I0.6
X
5
I0.5
X
4
I0.4
X
3
I0.3
X
2
I0.2
X
1
I0.1
X
0
I0.0
X
Symbol
Default
Table 6.
Bit
Input port 1 register (address 01h)
7
I1.7
X
6
I1.6
X
5
I1.5
X
4
I1.4
X
3
I1.3
X
2
I1.2
X
1
I1.1
X
0
I1.0
X
Symbol
Default
6.2.3 Output port register pair (02h, 03h)
The Output port registers (registers 2 and 3) show the outgoing logic levels of the pins
defined as outputs by the Configuration register. Bit values in these registers have no
effect on pins defined as inputs. In turn, reads from these registers reflect the value that
was written to these registers, not the actual pin value. A register pair write is described in
Section 7.1 and a register pair read is described in Section 7.2.
Table 7.
Bit
Output port 0 register (address 02h)
7
O0.7
1
6
O0.6
1
5
O0.5
1
4
O0.4
1
3
O0.3
1
2
O0.2
1
1
O0.1
1
0
O0.0
1
Symbol
Default
Table 8.
Bit
Output port 1 register (address 03h)
7
O1.7
1
6
O1.6
1
5
O1.5
1
4
O1.4
1
3
O1.3
1
2
O1.2
1
1
O1.1
1
0
O1.0
1
Symbol
Default
PCA9535A
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 11 September 2012
6 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
6.2.4 Polarity inversion register pair (04h, 05h)
The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined
as inputs by the Configuration register. If a bit in these registers is set (written with ‘1’), the
corresponding port pin’s polarity is inverted in the Input register. If a bit in this register is
cleared (written with a ‘0’), the corresponding port pin’s polarity is retained. A register pair
write is described in Section 7.1 and a register pair read is described in Section 7.2.
Table 9.
Bit
Polarity inversion port 0 register (address 04h)
7
N0.7
0
6
N0.6
0
5
N0.5
0
4
N0.4
0
3
N0.3
0
2
N0.2
0
1
N0.1
0
0
N0.0
0
Symbol
Default
Table 10. Polarity inversion port 1 register (address 05h)
Bit
7
N1.7
0
6
N1.6
0
5
N1.5
0
4
N1.4
0
3
N1.3
0
2
N1.2
0
1
N1.1
0
0
N1.0
0
Symbol
Default
6.2.5 Configuration register pair (06h, 07h)
The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a
bit in these registers is set to 1, the corresponding port pin is enabled as a
high-impedance input. If a bit in these registers is cleared to 0, the corresponding port pin
is enabled as an output. A register pair write is described in Section 7.1 and a register pair
read is described in Section 7.2.
Table 11. Configuration port 0 register (address 06h)
Bit
7
C0.7
1
6
C0.6
1
5
C0.5
1
4
C0.4
1
3
C0.3
1
2
C0.2
1
1
C0.1
1
0
C0.0
1
Symbol
Default
Table 12. Configuration port 1 register (address 07h)
Bit
7
C1.7
1
6
C1.6
1
5
C1.5
1
4
C1.4
1
3
C1.3
1
2
C1.2
1
1
C1.1
1
0
C1.0
1
Symbol
Default
PCA9535A
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 11 September 2012
7 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
6.3 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin and
either VDD or VSS. The external voltage applied to this I/O pin should not exceed the
recommended levels for proper operation.
data from
output port
shift register
register data
configuration
register
V
DD
data from
shift register
Q1
D
Q
FF
write
configuration
pulse
D
Q
CK
Q
FF
P0_0 to P0_7
P1_0 to P1_7
Q2
write pulse
CK
ESD
protection
diode
output port
register
input port
register
V
SS
D
Q
input port
register data
FF
read pulse
CK
to INT
polarity
inversion
register
data from
shift register
polarity
inversion
register data
D
Q
FF
write polarity
pulse
CK
002aah246
At power-on reset, all registers return to default values.
Fig 6. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)
PCA9535A
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 11 September 2012
8 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
6.4 Power-on reset
When power (from 0 V) is applied to VDD, an internal power-on reset holds the PCA9535A
in a reset condition until VDD has reached VPOR. At that time, the reset condition is
released and the PCA9535A registers and I2C-bus/SMBus state machine initializes to
their default states. After that, VDD must be lowered to below VPORF and back up to the
operating voltage for a power-reset cycle. See Section 8.2 “Power-on reset requirements”.
6.5 Interrupt output
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.
After time tv(INT), the signal INT is valid. The interrupt is reset when data on the port
changes back to the original value or when data is read form the port that generated the
interrupt (see Figure 10 and Figure 11). Resetting occurs in the Read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL
signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very
short) due to the resetting of the interrupt during this pulse. Any change of the I/Os after
resetting is detected and is transmitted as INT.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output
to an input may cause a false interrupt to occur, if the state of the pin does not match the
contents of the Input Port register.
7. Bus transactions
The PCA9535A is an I2C-bus slave device. Data is exchanged between the master and
PCA9535A through write and read commands using I2C-bus. The two communication
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Writing to the port registers
Data is transmitted to the PCA9535A by sending the device address and setting the least
significant bit to a logic 0 (see Figure 4 “PCA9535A device address”). The command byte
is sent after the address and determines which register will receive the data following the
command byte.
Eight registers within the PCA9535A are configured to operate as four register pairs. The
four pairs are input port, output port, polarity inversion, configuration registers. After
sending data to one register, the next data byte is sent to the other register in the pair (see
Figure 7 and Figure 8). For example, if the first byte is sent to Output Port 1 (register 3),
the next byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this
way, the host can continuously update a register pair independently of the other registers,
or the host can simply update a single register.
PCA9535A
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 11 September 2012
9 of 38
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SCL
SDA
1
2
3
4
5
6
7
8
9
slave address
A2 A1 A0
command byte
data to port 0
DATA 0
data to port 1
DATA 1
S
0
1
0
0
0
A
0
0
0
0
0
0
1
0
A
0.7
0.0
A
1.7
1.0
A
P
START condition
R/W acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
STOP
condition
write to port
t
v(Q)
data out
from port 0
t
v(Q)
data out
DATA VALID
from port 1
002aah372
Fig 7. Write to output port registers
SCL
1
2
3
4
5
6
7
8
9
STOP
condition
slave address
A2 A1 A0
command byte
0/1 0/1 0/1 0/1
data to register
DATA 0
data to register
DATA 1
SDA
S
0
1
0
0
0
A
0
0/1
0
0
A
A
A
P
MSB
LSB
MSB
LSB
START condition
R/W acknowledge
from slave
acknowledge
acknowledge
acknowledge
from slave
from slave
from slave
002aah373
Fig 8. Write to control registers
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
7.2 Reading the port registers
In order to read data from the PCA9535A, the bus master must first send the PCA9535A
address with the least significant bit set to a logic 0 (see Figure 4 “PCA9535A device
address”). The command byte is sent after the address and determines which register will
be accessed. After a restart, the device address is sent again, but this time the least
significant bit is set to a logic 1. Data from the register defined by the command byte is
sent by the PCA9535A (see Figure 9, Figure 10 and Figure 11). Data is clocked into the
register on the falling edge of the acknowledge clock pulse. After the first byte is read,
additional bytes may be read but the data now reflects the information in the other register
in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0. There is
no limit on the number of data bytes received in one read transmission, but on the final
byte received the bus master must not acknowledge the data.
After a subsequent restart, the command byte contains the value of the next register to be
read in the pair. For example, if Input Port 1 was read last before the restart, the register
that is read after the restart is the Input Port 0.
command byte
0/1 0/1 0/1 0/1 A
slave address
A2 A1 A0
(cont.)
SDA
S
0
1
0
0
0
A
0
0/1
0
0
START condition
R/W
acknowledge
from slave
acknowledge
from slave
data from lower or
data from upper or
upper byte of register
lower byte of register
slave address
A2 A1 A0
MSB
LSB
MSB
LSB
(cont.)
S
0
1
0
0
1
A
DATA (first byte)
A
DATA (last byte)
NA P
(repeated)
START condition
R/W
acknowledge
from slave
acknowledge
from master
no acknowledge STOP
from master condition
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
002aah374
Remark: Transfer can be stopped at any time by a STOP condition.
Fig 9. Read from register
PCA9535A
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 11 September 2012
11 of 38
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
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data into port 0
data into port 1
INT
t
t
rst(INT)
v(INT)
SCL
SDA
1
2
3
4
5
6
7
8
9
R/W
STOP condition
slave address
A2 A1 A0
I0.x
I1.x
I0.x
I1.x
S
0
1
0
0
1
A
7
6
5
4
3
2
1
0
A
7
6
5
4
3
2
1
0
A
7
6
5
4
3
2
1
0
A
7
6
5
4
3
2
1
0
1
P
START condition
acknowledge
from slave
acknowledge
from master
acknowledge
from master
acknowledge
from master
non acknowledge
from master
read from port 0
read from port 1
002aah375
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It
is assumed that the command byte has previously been set to ‘00’ (read input port register).
This figure eliminates the command byte transfer and a restart between the initial slave address call and the actual data transfer from P port (see Figure 9).
Fig 10. Read input port register, scenario 1
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
data into port 0
data into port 1
INT
DATA 00
DATA 01
DATA 02
t
DATA 03
t
h(D)
su(D)
DATA 10
DATA 11
DATA 12
t
t
su(D)
h(D)
t
t
rst(INT)
v(INT)
SCL
SDA
1
2
3
4
5
6
7
8
9
R/W
STOP condition
slave address
A2 A1 A0
I0.x
DATA 00
I1.x
I0.x
DATA 03
I1.x
S
0
1
0
0
1
A
A
DATA 10
A
A
DATA 12
1
P
START condition
acknowledge
from slave
acknowledge
from master
acknowledge
from master
acknowledge
from master
non acknowledge
from master
read from port 0
read from port 1
002aah376
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It
is assumed that the command byte has previously been set to ‘00’ (read input port register).
This figure eliminates the command byte transfer and a restart between the initial slave address call and the actual data transfer from P port (see Figure 9).
Fig 11. Read input port register, scenario 2
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
8. Application design-in information
V
DD
(1)
(3.3 V)
SUB-SYSTEM 1
10 kΩ
10 kΩ
10 kΩ
2 kΩ
100 kΩ
(×3)
(e.g., temp sensor)
V
DD
V
DD
INT
MASTER
CONTROLLER
PCA9535A
SCL
SDA
INT
SCL
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
SUB-SYSTEM 2
(e.g., counter)
SDA
INT
RESET
A
V
SS
controlled
switch
(e.g., CBT device)
enable
B
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
(1)
SUB-SYSTEM 3
(e.g., alarm system)
10 DIGIT
NUMERIC
KEYPAD
ALARM
A2
A1
A0
V
DD
V
SS
002aag212
Device address configured as 0100 000X for this example.
P0_0, P0_2, P0_3 configured as outputs.
P0_1, P0_4, P0_5 configured as inputs.
P0_6, P0_7 and (P1_0 to P1_7) configured as inputs.
(1) External resistors are required for inputs (on P port) that may float. If a driver to an input will never let the input float, a resistor
is not needed. If an output in the P port is configured as a push-pull output there is no need for external pull-up resistors. If an
output in the P port is configured as an open-drain output, external pull-up resistors are required.
Fig 12. Typical application
8.1 Minimizing IDD when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 12. Since the LED acts as a diode, when the LED is off the I/O
VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower
than VDD
.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater than or equal to VDD when the LED is off.
Figure 13 shows a high value resistor in parallel with the LED. Figure 14 shows VDD less
than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI
at or above VDD and prevents additional supply current consumption when the LED is off.
PCA9535A
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Product data sheet
Rev. 1 — 11 September 2012
14 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
3.3 V
5 V
V
DD
V
100 kΩ
V
DD
DD
LED
LED
Pn
Pn
002aag164
002aag165
Fig 13. High value resistor in parallel with
the LED
Fig 14. Device supplied by a lower voltage
8.2 Power-on reset requirements
In the event of a glitch or data corruption, PCA9535A can be reset to its default conditions
by using the power-on reset feature. Power-on reset requires that the device go through a
power cycle to be completely reset. This reset also happens when the device is
powered on for the first time in an application.
The two types of power-on reset are shown in Figure 15 and Figure 16.
V
DD
ramp-up
ramp-down
re-ramp-up
t
d(rst)
time
time to re-ramp
when V drops
(dV/dt)
(dV/dt)
(dV/dt)
r
r
f
DD
002aah329
below 0.2 V or to V
SS
Fig 15. VDD is lowered below 0.2 V or to 0 V and then ramped up to VDD
V
DD
ramp-down
ramp-up
t
d(rst)
V drops below POR levels
I
time
time to re-ramp
(dV/dt)
(dV/dt)
r
f
when V
drops
DD
to V
− 50 mV
POR(min)
002aah330
Fig 16. VDD is lowered below the POR threshold, then ramped back up to VDD
Table 13 specifies the performance of the power-on reset feature for PCA9535A for both
types of power-on reset.
PCA9535A
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 11 September 2012
15 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
Table 13. Recommended supply sequencing and ramp rates
Tamb = 25 C (unless otherwise noted). Not tested; specified by design.
Symbol
(dV/dt)f
(dV/dt)r
td(rst)
Parameter
Condition
Min
0.1
0.1
1
Typ
Max
2000
2000
-
Unit
ms
ms
s
fall rate of change of voltage
rise rate of change of voltage
reset delay time
Figure 15
-
-
-
Figure 15
Figure 15; re-ramp time when
VDD drops below 0.2 V or to VSS
Figure 16; re-ramp time when
1
-
-
s
VDD drops to VPOR(min) 50 mV
[1]
[2]
VDD(gl)
tw(gl)VDD
VPOR(trip)
glitch supply voltage difference
supply voltage glitch pulse width
power-on reset trip voltage
Figure 17
Figure 17
falling VDD
rising VDD
-
-
-
-
-
1
V
-
10
-
s
V
0.7
-
1.4
V
[1] Level that VDD can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when tw(gl)VDD < 1 s.
[2] Glitch width that will not cause a functional disruption when VDD(gl) = 0.5 VDD
.
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance. Figure 17 and Table 13 provide more information on
how to measure these specifications.
V
DD
∆V
DD(gl)
time
002aah331
t
w(gl)VDD
Fig 17. Glitch width and glitch height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition
is released and all the registers and the I2C-bus/SMBus state machine are initialized to
their default states. The value of VPOR differs based on the VDD being lowered to or from
0 V. Figure 18 and Table 13 provide more details on this specification.
V
DD
V
(rising V
(falling V
)
)
POR
DD
DD
V
POR
time
POR
time
002aah332
Fig 18. Power-on reset voltage (VPOR
)
PCA9535A
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Product data sheet
Rev. 1 — 11 September 2012
16 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
9. Limiting values
Table 14. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
VI
Parameter
Conditions
Min
Max
+6.5
+6.5
+6.5
20
20
20
20
50
Unit
V
supply voltage
0.5
[1]
[1]
input voltage
0.5
V
VO
output voltage
0.5
V
IIK
input clamping current
output clamping current
input/output clamping current
A0, A1, A2, SCL; VI < 0 V
INT; VO < 0 V
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
C
IOK
-
IIOK
P port; VO < 0 V or VO > VDD
SDA; VO < 0 V or VO > VDD
continuous; I/O port
-
-
IOL
LOW-level output current
-
continuous; SDA, INT
continuous; P port
-
25
IOH
HIGH-level output current
supply current
-
25
IDD
-
160
200
200
+150
125
ISS
ground supply current
total power dissipation
storage temperature
-
Ptot
Tstg
Tj(max)
-
65
maximum junction temperature
-
C
[1] The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
10. Recommended operating conditions
Table 15. Operating conditions
Symbol
VDD
Parameter
Conditions
Min
Max
5.5
Unit
V
supply voltage
1.65
0.7 VDD
0.7 VDD
0.5
0.5
-
VIH
HIGH-level input voltage
SCL, SDA
5.5
V
A0, A1, A2, P1_7 to P0_0
SCL, SDA
5.5
V
VIL
LOW-level input voltage
0.3 VDD
0.3 VDD
10
V
A0, A1, A2, P1_7 to P0_0
P1_7 to P0_0
V
IOH
HIGH-level output current
LOW-level output current
ambient temperature
mA
mA
C
IOL
P1_7 to P0_0
-
25
Tamb
operating in free air
40
+85
11. Thermal characteristics
Table 16. Thermal characteristics
Symbol
Parameter
Conditions
Max
Unit
[1]
Zth(j-a)
transient thermal impedance from junction to ambient TSSOP24 package
HWQFN24 package
88
66
K/W
K/W
[1]
[1] The package thermal impedance is calculated in accordance with JESD 51-7.
PCA9535A
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 11 September 2012
17 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
12. Static characteristics
Table 17. Static characteristics
Tamb = 40 C to +85 C; VDD = 1.65 V to 5.5 V; unless otherwise specified.
Symbol Parameter
Conditions
Min
1.2
-
Typ[1] Max
Unit
V
VIK
input clamping voltage
power-on reset voltage
LOW-level output current
II = 18 mA
-
-
VPOR
IOL
VI = VDD or VSS; IO = 0 mA
VOL = 0.4 V; VDD = 1.65 V to 5.5 V
SDA
1.1
1.4
V
3
3
-
-
-
mA
mA
INT
15[2]
P port
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
VOL = 0.5 V; VDD = 1.65 V
VOL = 0.7 V; VDD = 1.65 V
VOL = 0.5 V; VDD = 2.3 V
VOL = 0.7 V; VDD = 2.3 V
VOL = 0.5 V; VDD = 3.0 V
VOL = 0.7 V; VDD = 3.0 V
VOL = 0.5 V; VDD = 4.5 V
VOL = 0.7 V; VDD = 4.5 V
P port
8
10
13
10
13
14
19
17
24
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
10
8
10
8
10
8
10
VOH
HIGH-level output voltage
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
IOH = 8 mA; VDD = 1.65 V
1.2
1.1
1.8
1.7
2.6
2.5
4.1
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
I
OH = 10 mA; VDD = 1.65 V
IOH = 8 mA; VDD = 2.3 V
IOH = 10 mA; VDD = 2.3 V
IOH = 8 mA; VDD = 3.0 V
IOH = 10 mA; VDD = 3.0 V
IOH = 8 mA; VDD = 4.5 V
IOH = 10 mA; VDD = 4.5 V
P port; IOL = 8 mA
VOL
LOW-level output voltage
VDD = 1.65 V
-
-
-
-
-
-
-
-
0.45
0.25
0.25
0.2
V
V
V
V
VDD = 2.3 V
VDD = 3.0 V
VDD = 4.5 V
II
input current
VDD = 1.65 V to 5.5 V
SCL, SDA; VI = VDD or VSS
A0, A1, A2; VI = VDD or VSS
P port; VI = VDD; VDD = 1.65 V to 5.5 V
P port; VI = VSS; VDD = 1.65 V to 5.5 V
-
-
-
-
-
-
-
-
1
1
1
A
A
A
A
IIH
IIL
HIGH-level input current
LOW-level input current
1
PCA9535A
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Product data sheet
Rev. 1 — 11 September 2012
18 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
Table 17. Static characteristics …continued
Tamb = 40 C to +85 C; VDD = 1.65 V to 5.5 V; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1] Max
Unit
IDD
supply current
SDA, P port, A0, A1, A2;
VI on SDA = VDD or VSS
;
VI on P port and A0, A1, A2 = VDD
;
IO = 0 mA; I/O = inputs; fSCL = 400 kHz
VDD = 3.6 V to 5.5 V
-
-
-
10
6.5
4
25
15
9
A
A
A
VDD = 2.3 V to 3.6 V
VDD = 1.65 V to 2.3 V
SCL, SDA, P port, A0, A1, A2;
VI on SCL, SDA = VDD or VSS
;
VI on P port and A0, A1, A2 = VDD
;
IO = 0 mA; I/O = inputs; fSCL = 0 kHz
VDD = 3.6 V to 5.5 V
-
-
-
1.5
1
7
A
A
A
VDD = 2.3 V to 3.6 V
3.2
1.7
VDD = 1.65 V to 2.3 V
0.5
Active mode; P port, A0, A1, A2;
VI on P port, A0, A1, A2 = VDD
;
IO = 0 mA; I/O = inputs;
fSCL = 400 kHz, continuous register read
VDD = 3.6 V to 5.5 V
-
-
-
-
60
40
20
-
125
75
A
A
A
A
VDD = 2.3 V to 3.6 V
VDD = 1.65 V to 2.3 V
45
IDD
additional quiescent
supply current
SCL, SDA; one input at VDD 0.6 V, other
25
inputs at VDD or VSS; VDD = 1.65 V to 5.5 V
P port, A0, A1, A2; one input at VDD 0.6 V,
-
-
80
A
other inputs at VDD or VSS
;
VDD = 1.65 V to 5.5 V
Ci
input capacitance
VI = VDD or VSS; VDD = 1.65 V to 5.5 V
VI/O = VDD or VSS; VDD = 1.65 V to 5.5 V
VI/O = VDD or VSS; VDD = 1.65 V to 5.5 V
-
-
-
6
7
pF
pF
pF
Cio
input/output capacitance
7
8
7.5
8.5
[1] For IDD, all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V, 3.6 V or 5 V VDD) and Tamb = 25 C. Except for IDD, the
typical values are at VDD = 3.3 V and Tamb = 25 C.
[2] Typical value for Tamb = 25 C. VOL = 0.4 V and VDD = 3.3 V. Typical value for VDD < 2.5 V, VOL = 0.6 V.
[3] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 200 mA.
[4] The total current sourced by all I/Os must be limited to 160 mA.
PCA9535A
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Product data sheet
Rev. 1 — 11 September 2012
19 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
12.1 Typical characteristics
002aah333
002aah334
20
16
12
8
1400
I
DD
I
DD(stb)
(nA)
(μA)
V
= 5.5 V
5.0 V
3.6 V
3.3 V
DD
V
DD
= 5.5 V
5.0 V
3.6 V
3.3 V
2.5 V
2.3 V
1000
800
600
400
200
0
2.5 V
2.3 V
1.8 V
1.65 V
4
V
= 1.8 V
DD
1.65 V
0
−40
−15
10
35
60
85
(°C)
−40
−15
10
35
60
85
(°C)
T
T
amb
amb
Fig 19. Supply current versus ambient temperature
Fig 20. Standby supply current versus
ambient temperature
002aah335
20
I
DD
(μA)
16
12
8
4
0
1.5
2.5
3.5
4.5
5.5
V
DD
(V)
Tamb = 25 C
Fig 21. Supply current versus supply voltage
PCA9535A
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 11 September 2012
20 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
002aaf578
002aaf579
35
35
I
I
sink
(mA)
sink
(mA)
30
25
20
15
10
5
30
25
20
15
10
5
T
amb
= −40 °C
25 °C
T
amb
= −40 °C
25 °C
85 °C
85 °C
0
0
0
0.1
0.2
0.3
0
0.1
0.2
0.3
V
V
V
(V)
V
V
V
(V)
OL
OL
a. VDD = 1.65 V
b. VDD = 1.8 V
002aaf580
002aaf581
50
60
I
sink
(mA)
I
sink
(mA)
T
= −40 °C
amb
40
30
20
10
0
25 °C
85 °C
T
amb
= −40 °C
25 °C
40
85 °C
20
0
0
0.1
0.2
0.3
0
0.1
0.2
0.3
(V)
(V)
OL
OL
c. VDD = 2.5 V
d. VDD = 3.3 V
002aaf582
002aaf583
70
70
I
I
sink
(mA)
sink
(mA)
T
amb
= −40 °C
T
= −40 °C
25 °C
60
50
40
30
20
10
0
60
50
40
30
20
10
0
amb
25 °C
85 °C
85 °C
0
0.1
0.2
0.3
0
0.1
0.2
0.3
(V)
(V)
OL
OL
e. VDD = 5.0 V
Fig 22. I/O sink current versus LOW-level output voltage
f. VDD = 5.5 V
PCA9535A
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Product data sheet
Rev. 1 — 11 September 2012
21 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
002aah110
002aah111
30
35
I
source
(mA)
I
T
= −40 °C
25 °C
source
(mA)
amb
30
25
20
15
10
5
T
amb
= −40 °C
25 °C
85 °C
20
10
0
85 °C
0
0
0.2
0.4
0.6
(V)
0
0.2
0.4
0.6
(V)
V
− V
V
− V
OH
DD
DD
DD
OH
DD
DD
DD
a. VDD = 1.65 V
b. VDD = 1.8 V
002aah112
002aah113
60
70
I
source
(mA)
I
T
= −40 °C
25 °C
source
(mA)
amb
60
50
40
30
20
10
0
T
= −40 °C
amb
85 °C
25 °C
85 °C
40
20
0
0
0.2
0.4
0.6
(V)
0
0.2
0.4
0.6
(V)
V
− V
V
− V
OH
OH
c. VDD = 2.5 V
d. VDD = 3.3 V
002aah114
002aah115
90
90
I
I
source
(mA)
source
(mA)
T
= −40 °C
25 °C
T
amb
= −40 °C
25 °C
amb
85 °C
85 °C
60
60
30
0
30
0
0
0.2
0.4
0.6
(V)
0
0.2
0.4
0.6
(V)
V
− V
V
− V
OH
OH
e. VDD = 5.0 V
Fig 23. I/O source current versus HIGH-level output voltage
f. VDD = 5.5 V
PCA9535A
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Product data sheet
Rev. 1 — 11 September 2012
22 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
002aah056
002aah343
120
200
V
OL
V
− V
(mV)
DD
OH
(mV)
100
80
60
40
20
0
160
(1)
(2)
(3)
120
80
40
0
V
= 1.8 V
5 V
DD
(4)
−40
−15
10
35
60
85
(°C)
−40
−15
10
35
60
85
(°C)
T
T
amb
amb
(1) VDD = 1.8 V; Isink = 10 mA
(2) VDD = 5 V; Isink = 10 mA
(3) VDD = 1.8 V; Isink = 1 mA
(4) VDD = 5 V; Isink = 1 mA
Isource = 10 mA
Fig 24. LOW-level output voltage versus temperature
Fig 25. I/O high voltage versus temperature
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PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
13. Dynamic characteristics
Table 18. I2C-bus interface timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 26.
Symbol Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Unit
Min
0
Max
100
-
Min
0
Max
fSCL
tHIGH
tLOW
tSP
SCL clock frequency
400 kHz
HIGH period of the SCL clock
LOW period of the SCL clock
4
0.6
1.3
0
-
-
s
s
4.7
0
-
pulse width of spikes that must
be suppressed by the input filter
50
50 ns
tSU;DAT
data set-up time
250
-
-
100
0
-
-
ns
ns
tHD;DAT
data hold time
0
-
tr
tf
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
1000
300
20
300 ns
300 ns
-
20
(VDD / 5.5 V)
tBUF
bus free time between a STOP and
START condition
4.7
4.7
-
-
1.3
0.6
-
-
s
s
tSU;STA
set-up time for a repeated START
condition
tHD;STA
tSU;STO
tVD;DAT
hold time (repeated) START condition
set-up time for STOP condition
data valid time
4
4
-
-
-
0.6
0.6
-
-
-
s
s
SCL LOW to
3.45
0.9 s
SDA output valid
tVD;ACK
data valid acknowledge time
ACK signal
-
3.45
-
0.9 s
from SCL LOW
to SDA (out) LOW
Table 19. Switching characteristics
Over recommended operating free air temperature range; CL 100 pF; unless otherwise specified. See Figure 27.
Symbol Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Unit
Min
Max
Min
Max
tv(INT)
trst(INT)
tv(Q)
valid time on pin INT
from P port to INT
from SCL to INT
-
1
1
-
1
s
s
ns
ns
ns
reset time on pin INT
data output valid time
data input set-up time
data input hold time
-
-
-
-
1
from SCL to P port
from P port to SCL
from P port to SCL
400
-
400
tsu(D)
th(D)
0
0
-
-
300
-
300
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24 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
14. Parameter measurement information
V
DD
R
= 1 kΩ
L
SDA
DUT
C
= 50 pF
L
002aag803
a. SDA load configuration
(1)
two bytes for read Input port register
STOP
condition condition
(P) (S)
START
Address
Bit 7
Data
Data
Bit 0
STOP
condition
(P)
R/W
Bit 0
Address
Bit 1
ACK
(A)
Bit 7
(MSB)
(MSB)
(LSB)
(LSB)
002aag952
b. Transaction format
t
HIGH
t
t
SP
LOW
0.7 × V
0.3 × V
DD
DD
SCL
t
t
r
VD;DAT
t
t
SU;STO
BUF
t
f
t
t
SU;STA
VD;ACK
t
f(o)
0.7 × V
0.3 × V
DD
DD
SDA
t
f
t
r
t
VD;ACK
t
t
t
HD;DAT
HD;STA
SU;DAT
repeat START condition
STOP condition
002aag804
c. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
All parameters and waveforms are not applicable to all devices.
Byte 1 = I2C-bus address; Byte 2, byte 3 = P port data.
(1) See Figure 9.
Fig 26. I2C-bus interface load circuit and voltage waveforms
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PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
V
DD
R
= 4.7 kΩ
L
INT
DUT
C
= 100 pF
L
002aah069
a. Interrupt load configuration
acknowledge
from slave
acknowledge
from slave
no acknowledge
from master
START condition
slave address
R/W
STOP
8 bits (one data byte)
from port
condition
data from port
DATA 2
SDA
S
1
1
1
0
1
A1 A0
1
A
DATA 1
A
1
P
SCL
1
2
3
4
5
6
7
8
9
B
B
t
t
rst(INT)
rst(INT)
INT
A
A
t
v(INT)
t
su(D)
data into
port
ADDRESS
DATA 1
SCL
DATA 2
0.7 × V
0.3 × V
DD
DD
INT
0.5 × V
R/W
A
DD
t
v(INT)
t
rst(INT)
Pn
0.5 × V
INT
0.5 × V
DD
DD
View A - A
View B - B
002aah070
b. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
All parameters and waveforms are not applicable to all devices.
Fig 27. Interrupt load circuit and voltage waveforms
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PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
500 Ω
Pn
DUT
2 × V
DD
C
= 50 pF
500 Ω
L
002aag805
a. P port load configuration
0.7 × V
0.3 × V
DD
DD
SCL
P0
A
P7
SDA
Pn
t
v(Q)
last stable bit
unstable
data
002aag806
b. Write mode (R/W = 0)
0.7 × V
0.3 × V
DD
DD
SCL
P0
A
P7
t
t
h(D)
su(D)
Pn
002aag807
c. Read mode (R/W = 1)
CL includes probe and jig capacitance.
tv(Q) is measured from 0.7 VDD on SCL to 50 % I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Fig 28. P port load circuit and voltage waveforms
PCA9535A
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Product data sheet
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PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
15. Package outline
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c
H
v
M
A
y
E
Z
13
24
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT355-1
MO-153
Fig 29. Package outline SOT355-1 (TSSOP24)
PCA9535A
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Product data sheet
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28 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.75 mm
SOT994-1
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
e
1
1/2 e
b
C
M
M
∅ v
∅ w
C A
B
e
y
y
C
C
1
7
12
L
13
6
e
E
e
2
h
1/2 e
1
18
terminal 1
index area
24
19
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
D
D
E
E
e
e
1
e
2
L
v
w
y
y
1
1
h
h
max
0.05 0.30
0.00 0.18
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
0.5
0.3
mm
0.8
0.2
0.5
2.5
2.5
0.1
0.05 0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
07-02-07
07-03-03
SOT994-1
- - -
MO-220
Fig 30. Package outline SOT994-1 (HWQFN24)
PCA9535A
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29 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
PCA9535A
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Product data sheet
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30 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 31) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 20 and 21
Table 20. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
235
350
220
< 2.5
2.5
220
220
Table 21. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 31.
PCA9535A
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Product data sheet
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PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 31. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCA9535A
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PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
18. Soldering: PCB footprints
Footprint information for reflow soldering of TSSOP24 package
SOT355-1
Hx
Gx
P2
(0.125)
(0.125)
Hy Gy
By Ay
C
D2 (4x)
P1
D1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650 0.750 7.200 4.500 1.350 0.400 0.600 8.200 5.300 8.600 7.450
sot355-1_fr
Fig 32. PCB footprint for SOT355-1 (TSSOP24); reflow soldering
PCA9535A
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Product data sheet
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PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
Footprint information for reflow soldering of HVQFN24 package
SOT994-1
Hx
Gx
D
P
0.025
0.025
C
(0.105)
SPx
SPy
nSPx
Hy Gy
SLy By
Ay
nSPy
SPx tot
SLx
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
occupied area
nSPx nSPy
2
2
Dimensions in mm
Ax
P
Ay
Bx
By
C
D
SLx
SLy
SPx tot
1.200
SPy tot
1.200
SPx
SPy
Gx
Gy
Hx
Hy
0.500 5.000 5.000 3.200 3.200 0.900 0.240 2.100 2.100
0.450 0.450 4.300 4.300 5.250 5.250
07-09-24
Issue date
sot994-1_fr
09-06-15
Fig 33. PCB footprint for SOT994-1 (HWQFN24); reflow soldering
PCA9535A
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PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
19. Abbreviations
Table 22. Abbreviations
Acronym
ACPI
CBT
Description
Advanced Configuration and Power Interface
Cross-Bar Technology
Charged-Device Model
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
Field-Effect Transistor
Flip-Flop
CDM
CMOS
ESD
FET
FF
GPIO
HBM
I2C-bus
I/O
General Purpose Input/Output
Human Body Model
Inter-Integrated Circuit bus
Input/Output
LED
Light Emitting Diode
PCB
Printed-Circuit Board
POR
SMBus
Power-On Reset
System Management Bus
20. Revision history
Table 23. Revision history
Document ID
Release date
20120911
Data sheet status
Change notice
Supersedes
PCA9535A v.1
Product data sheet
-
-
PCA9535A
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PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
21. Legal information
21.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
21.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
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Product data sheet
Rev. 1 — 11 September 2012
36 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
I2C-bus — logo is a trademark of NXP B.V.
22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9535A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 11 September 2012
37 of 38
PCA9535A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt
23. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
21.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 36
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 37
21.2
21.3
21.4
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
3.1
4
22
23
Contact information . . . . . . . . . . . . . . . . . . . . 37
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.3
Functional description . . . . . . . . . . . . . . . . . . . 5
Device address. . . . . . . . . . . . . . . . . . . . . . . . . 5
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pointer register and command byte . . . . . . . . . 5
Input port register pair (00h, 01h) . . . . . . . . . . . 6
Output port register pair (02h, 03h) . . . . . . . . . 6
Polarity inversion register pair (04h, 05h). . . . . 7
Configuration register pair (06h, 07h). . . . . . . . 7
I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9
Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.4
6.5
7
7.1
7.2
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 9
Writing to the port registers. . . . . . . . . . . . . . . . 9
Reading the port registers . . . . . . . . . . . . . . . 11
8
8.1
Application design-in information . . . . . . . . . 14
Minimizing IDD when the I/Os are used to
control LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-on reset requirements . . . . . . . . . . . . . 15
8.2
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17
Recommended operating conditions. . . . . . . 17
Thermal characteristics . . . . . . . . . . . . . . . . . 17
Static characteristics. . . . . . . . . . . . . . . . . . . . 18
Typical characteristics . . . . . . . . . . . . . . . . . . 20
Dynamic characteristics . . . . . . . . . . . . . . . . . 24
Parameter measurement information . . . . . . 25
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 28
Handling information. . . . . . . . . . . . . . . . . . . . 30
10
11
12
12.1
13
14
15
16
17
Soldering of SMD packages . . . . . . . . . . . . . . 30
Introduction to soldering . . . . . . . . . . . . . . . . . 30
Wave and reflow soldering . . . . . . . . . . . . . . . 30
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 30
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 31
17.1
17.2
17.3
17.4
18
19
20
21
Soldering: PCB footprints. . . . . . . . . . . . . . . . 33
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 35
Legal information. . . . . . . . . . . . . . . . . . . . . . . 36
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 September 2012
Document identifier: PCA9535A
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