PCA9535D [NXP]

16-bit I2C and SMBus, low power I/O port with interrupt; 16位I2C和SMBus ，中断与低功率I / O端口


型号：	PCA9535D
厂家：	NXP
描述：	16-bit I2C and SMBus, low power I/O port with interrupt 16位I2C和SMBus ，中断与低功率I / O端口并行IO端口微控制器和处理器外围集成电路光电二极管
文件：	总19页 (文件大小：141K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

PCA9535

16-bit I²C and SMBus, low power I/O port

with interrupt

Product data

2003 Jun 27

Philips

Semiconductors

Philips Semiconductors

Product data

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9535

I C/SMBus applications and was developed to enhance the Philips

family of I C I/O expanders. The improvements include higher drive

capability, 5 V I/O tolerance, lower supply current, individual I/O

configuration, and smaller packaging. I/O expanders provide a

simple solution when additional I/O is needed for ACPI power

switches, sensors, pushbuttons, LEDs, fans, etc.

The PCA9535 consist of two 8-bit Configuration (Input or Output

selection); Input, Output and Polarity inversion (Active HIGH or

Active LOW operation) registers. The system master can enable the

I/Os as either inputs or outputs by writing to the I/O configuration

bits. The data for each Input or Output is kept in the corresponding

Input or Output register. The polarity of the read register can be

inverted with the Polarity Inversion Register. All registers can be

read by the system master. Although pin-to-pin and I C address

compatible with the PCF8575, software changes are required due to

the enhancements and are discussed in Application Note AN469.

FEATURES

• Operating power supply voltage range of 2.3 V-5.5 V

• 5 V tolerant I/Os

• Polarity inversion register

• Active LOW interrupt output

• Low stand-by current

The PCA9535 is identical to the PCA9555 except for the removal of

the internal I/O pull-up resistor which greatly reduces power

consumption when the I/Os are held LOW.

• Noise filter on SCL/SDA inputs

• No glitch on power-up

• Internal power-on reset

The PCA9535 open-drain interrupt output is activated when any

input state differs from its corresponding input port register state and

is used to indicate to the system master that an input state has

changed. The power-on reset sets the registers to their default

values and initializes the device state machine.

• 16 I/O pins which default to 16 inputs

• 0 to 400 kHz clock frequency

Three hardware pins (A0, A1, A2) vary the fixed I C address and

allow up to eight devices to share the same I C/SMBus. The fixed

• ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V

I C address of the PCA9535 is the same as the PCA9554 allowing

MM per JESD22-A115, and 1000 V CDM per JESD22-C101

up to eight of these devices in any combination to share the same

I C/SMBus.

• Latch-up testing is done to JESDEC Standard JESD78 which

exceeds 100 mA

• Offered in three different packages: SO24, TSSOP24, and

HVQFN24

DESCRIPTION

The PCA9535 is a 24-pin CMOS device that provide 16 bits of

General Purpose parallel Input/Output (GPIO) expansion for

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

DRAWING NUMBER

24-Pin Plastic SO

24-Pin Plastic TSSOP

24-Pin Plastic HVQFN

-40 to +85 °C

PCA9535D

PCA9535PW

PCA9535BS

PCA9535D

PCA9535PW

9535

SOT137-1

SOT355-1

SOT616-1

Standard packing quantities and other packing data are available at www.philipslogic.com/packaging.

I C is a trademark of Philips Semiconductors Corporation.

SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I C patent.

2003 Jun 27

Philips Semiconductors

Product data

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9535

PIN CONFIGURATION — SO, TSSOP

PIN CONFIGURATION —HVQFN

24 V

INT

23 SDA

I/O0.0

18 A0

I/O0.0

I/O0.1

I/O0.2

I/O0.3

I/O0.4

I/O0.5

22 SCL

I/O1.7

I/O1.6

I/O1.5

I/O1.4

21 A0

I/O0.1

I/O0.2

I/O0.3

I/O0.4

20 I/O1.7

19 I/O1.6

18 I/O1.5

17 I/O1.4

16 I/O1.3

15 I/O1.2

14 I/O1.1

13 I/O1.0

I/O0.5

I/O1.3

I/O0.6 10

I/O0.7 11

TOP VIEW

Figure 2. Pin configuration — HVQFN

su01683

SU01438

Figure 1. Pin configuration — SO, TSSOP

PIN DESCRIPTION

SO,

TSSOP

HVQFN

NUMBER

SYMBOL

FUNCTION

NUMBER

INT

Interrupt output (open drain)

Address input 1

Address input 2

I/O0.0 to I/O0.7

Supply ground

4-11

1-8

I/O0.0-I/O0.7

13-20

10-17

I/O1.0-I/O1.7

I/O1.0 to I/O1.7

Address input 0

Serial clock line

Serial data line

SCL

SDA

Supply voltage

2003 Jun 27

Philips Semiconductors

Product data

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9535

BLOCK DIAGRAM

I/O1.0

I/O1.1

I/O1.2

I/O1.3

INPUT/

OUTPUT

PORTS

8-BIT

I/O1.4

I/O1.5

WRITE pulse

READ pulse

I/O1.6

I/O1.7

I C/SMBUS

CONTROL

I/O0.0

I/O0.1

I/O0.2

I/O0.3

SCL

SDA

INPUT

FILTER

INPUT/

OUTPUT

PORTS

8-BIT

I/O0.4

I/O0.5

WRITE pulse

READ pulse

I/O0.6

I/O0.7

INT

POWER-ON

RESET

LP FILTER

INT

NOTE: ALL I/Os ARE SET TO INPUTS AT RESET

SU01439

Figure 3. Block diagram

2003 Jun 27

Philips Semiconductors

Product data

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9535

SIMPLIFIED SCHEMATIC OF I/Os

DATA FROM

SHIFT REGISTER

OUTPUT PORT

CONFIGURATION

DATA FROM

SHIFT REGISTER

WRITE CONFIGURATION

PULSE

I/O PIN

WRITE PULSE

OUTPUT

PORT

INPUT PORT

READ PULSE

TO INT

DATA FROM

SHIFT REGISTER

POLARITY

WRITE

POLARITY

PULSE

POLARITY

INVERSION

SU01682

NOTE: At Power-on Reset, all registers return to default values.

Figure 4. Simplified schematic of I/Os

I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off,

creating a high impedance input. The input voltage may be raised

above V to a maximum of 5.5 V.

If the I/O is configured as an output, then either Q1 or Q2 is on,

depending on the state of the Output Port register. Care should be

exercised if an external voltage is applied to an I/O configured as an

output because of the low impedance path that exists between the

pin and either V or V

2003 Jun 27

Philips Semiconductors

Product data

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9535

REGISTERS

POWER-ON RESET

When power is applied to V , an internal power-on reset holds the

Command Byte

PCA9535 in a reset state until V has reached V

the reset condition is released and the PCA9535 registers and

SMBus state machine will initialize to their default states.

. At that point,

POR

Command

Input port 0

Input port 1

DEVICE ADDRESS

Output port 0

slave address

Output port 1

Polarity inversion port 0

Polarity inversion port 1

Configuration port 0

Configuration port 1

A2 A1 A0 R/W

programmable

fixed

su01441

The command byte is the first byte to follow the address byte during

a write transmission. It is used as a pointer to determine which of the

following registers will be written or read.

Figure 5. PCA9535 address

BUS TRANSACTIONS

Registers 0 and 1 — Input Port Registers

Writing to the port registers

Data is transmitted to the PCA9535 by sending the device address

and setting the least significant bit to a logic 0 (see Figure 5 for

device address). The command byte is sent after the address and

determines which register will receive the data following the

command byte.

This register is an input-only port. It reflects the incoming logic levels

of the pins, regardless of whether the pin is defined as an input or an

output by Register 3. Writes to this register have no effect.

Registers 2 and 3 — Output Port Registers

The eight registers within the PCA9535 are configured to operate

as four register pairs. The four pairs are Input Ports, Output Ports,

Polarity Inversion Ports, and Configuration Ports. After sending data

to one register, the next data byte will be sent to the other register in

the pair (see Figures 6 and 7). For example, if the first byte is sent to

Output Port (register 3), then the next byte will be stored in Output

Port 0 (register 2). There is no limitation on the number of data bytes

sent in one write transmission. In this way, each 8-bit register may

be updated independently of the other registers.

O0.7

O0.6

O0.5

O0.4

O0.3

O0.2

O0.1

O0.0

bit

default

bit

O1.7

O1.6

O1.5

O1.4

O1.3

O1.2

O1.1

O1.0

default

This register is an output-only port. It reflects the outgoing logic

levels of the pins defined as outputs by Register 6 and 7. Bit values

in this register have no effect on pins defined as inputs. In turn,

reads from this register reflect the value that is in the flip-flop

controlling the output selection, NOT the actual pin value.

Reading the port registers

In order to read data from the PCA9535, the bus master must first

send the PCA9535 address with the least significant bit set to a

logic 0 (see Figure 5 for device address). The command byte is sent

after the address and determines which register will be accessed.

After a restart, the device address is sent again but this time, the

least significant bit is set to a logic 1. Data from the register defined

by the command byte will then be sent by the PCA9535 (see

Figures 8 , 9, and 10). Data is clocked into the register on the falling

edge of the acknowledge clock pulse. After the first byte is read,

additional bytes may be read but the data will now reflect the

information in the other register in the pair. For example, if you read

Input Port 1, then the next byte read would be Input Port 0. There is

no limitation on the number of data bytes received in one read

transmission but the final byte received, the bus master must not

acknowledge the data.

Registers 4 and 5 — Polarity Inversion Registers

bit

N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0

default

bit

N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0

default

This register allows the user to invert the polarity of the Input Port

Port data polarity is inverted. If a bit in this register is cleared (written

with a ‘0’), the Input Port data polarity is retained.

Registers 6 and 7 — Configuration Registers

bit

C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0

Interrupt Output

default

bit

The open-drain interrupt output is activated when one of the port

pins change state and the pin is configured as an input. The

interrupt is deactivated when the input returns to its previous state or

the input port register is read (see Figure 9). A pin configured as an

output cannot cause an interrupt. Since each 8-bit port is read

independently, the interrupt caused by Port 0 will not be cleared by a

read of Port 1 or the other way around.

C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0

default

This register configures the directions of the I/O pins. If a bit in this

as an input with high impedance output driver. If a bit in this register

is cleared (written with ‘0’), the corresponding port pin is enabled as

an output. At reset the device’s ports are inputs.

Note that changing an I/O from an output to an input may cause a

false interrupt to occur if the state of the pin does not match the

contents of the Input Port register.

2003 Jun 27

SCL

SDA

command byte

slave address

data to port 0

DATA 0

data to port 1

DATA 1

0.7

0.0

1.7

1.0

A2 A1 A0

start condition

R/W acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

WRITE TO

PORT

DATA OUT

FROM PORT 0

DATA OUT

FROM PORT 1

DATA VALID

SU01442

Figure 6. WRITE to output port registers

SCL

SDA

command byte

slave address

data to register

DATA 0

data to register

DATA 1

MSB

LSB

MSB

LSB

A2 A1 A0

start condition

R/W acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

SU01443

Figure 7. WRITE to configuration registers

data from lower

or upper byte

of register

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

acknowledge

from master

slave address

A2 A1 A0

COMMAND BYTE

DATA

MSB

LSB

first byte

R/W

at this moment master-transmitter

becomes master-receiver and

slave-receiver becomes

slave-transmitter

data from upper

or lower byte of

no acknowledge

from master

MSB

LSB NA

DATA

last byte

SU01463

NOTE: Transfer can be stopped at any time by a STOP condition.

Figure 8. READ from register

SCL

SDA

I0.x

I1.x

I0.x

I1.x

A2 A1 A0

R/W ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

NON ACKNOWLEDGE

FROM MASTER

READ FROM PORT 0

DATA INTO PORT 0

READ FROM PORT 1

DATA INTO PORT 1

INT

SU01464

NOTES: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).

It is assumed that the command byte has previously been set to 00 (read input port port register).

Figure 9. READ input port register — scenario 1

SCL

SDA

I0.x

I1.x

I0.x

I1.x

A2 A1 A0

DATA 00

DATA 10

DATA 03

DATA 12

R/W ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

NON ACKNOWLEDGE

FROM MASTER

READ FROM PORT 0

DATA INTO PORT 0

READ FROM PORT 1

DATA INTO PORT 1

DATA 00

DATA 01

DATA 02

DATA 03

DATA 10

DATA 11

DATA 12

INT

SU01651

NOTES: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).

It is assumed that the command byte has previously been set to 00 (read input port port register).

Figure 10. READ input port register — scenario 2

Philips Semiconductors

Product data

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9535

TYPICAL APPLICATION

SUBSYSTEM 1

(e.g. temp sensor)

2 kΩ

SUBSYSTEM 2

(e.g. counter)

1.6 kΩ

1.1 kΩ

2 kΩ

INT

RESET

I/O

SCL

SDA

SCL

0.0

0.1

0.2

MASTER

CONTROLLER

SDA

INT

I/O

0.3

0.4

0.5

ENABLE

GND

ALARM

SUBSYSTEM 3

(e.g. alarm system)

PCA9535

Controlled Switch

(e.g. CBT device)

I/O

0.6

0.7

1.0

1.1

10 DIGIT

NUMERIC

KEYPAD

I/O

1.2

I/O

1.3

I/O

1.4

I/O

1.5

I/O

1.6

I/O

1.7

NOTE: Device address configured as 0100100 for this example

I/O , I/O , I/O , configured as outputs

0.0

0.1

0.2

I/O , I/O , I/O , configured as inputs

0.3

0.4

0.5

I/O , I/O , and I/O to I/O configured as inputs

0.6

0.7

1.0

1.7

SW02094

Figure 11. Typical application

Minimizing I when the I/O is used to control LEDs

When the I/Os are used to control LEDs, they are normally connected to V through a resistor as shown in Figure 11. Since the LED acts as a

diode, when the LED is off the I/O V is about 1.2 V less than V . The supply current, I , increases as V becomes lower than V and is

specified as ∆I in the DC characteristics table.

Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or

equal to V when the LED is off. Figure 12 shows a high value resistor in parallel with the LED. Figure 13 shows V less than the LED supply

voltage by at least 1.2 V. Both of these methods maintain the I/O V at or above V and prevents additional supply current consumption when

the LED is off.

3.3 V

5 V

100 k

LED

LEDx

SW02087

SW02086

Figure 12. High value resistor in parallel with the LED

Figure 13. Device supplied by a lower voltage

2003 Jun 27

Philips Semiconductors

Product data

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9535

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Supply voltage

-0.5

6.0

DC input current on an I/O

DC output current on an I/O

DC input current

- 0.5

I/O

—

°C

Supply current

—

160

200

+150

+85

Supply current

—

Total power dissipation

Storage temperature range

Operating ambient temperature

—

tot

-65

-40

stg

amb

°C

2003 Jun 27

Philips Semiconductors

Product data

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9535

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take

precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”Handling MOS devices”.

DC CHARACTERISTICS

= 2.3 to 5.5 V; V = 0 V; T

= -40 to +85 °C; unless otherwise specified.

amb

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Supplies

Supply voltage

Supply current

2.3

—

5.5

Operating mode; V = 5.5 V; no load;

—

135

200

µA

stbl

= 100 kHz; I/O = inputs

SCL

Standby mode; V = 5.5 V; no load;

Standby current

—

0.25

µA

V = V ; f

= 0 kHz; I/O = inputs

SS SCL

Standby mode; V = 5.5 V; no load;

Standby current

—

0.25

1.5

µA

stbh

V = V ; f

= 0 kHz; I/O = inputs

DD SCL

Power-on reset voltage

No load; V = V or V

1.65

POR

input SCL; input/output SDA

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

Leakage current

-0.5

—

0.3 V

0.7 V

5.5

—

= 0.4V

µA

V = V = V

-1

Input capacitance

V = V

—

I/Os

LOW-level input voltage

HIGH-level input voltage

-0.5

2.0

—

0.8

5.5

—

= 0.5 V; V

= 0.7 V; V

= 2.3-5.5 V; Note 1

8-20

10-24

—

LOW-level output current

1.8

1.7

2.6

2.5

4.1

4.0

—

= -8 mA; V = 2.3 V; Note 2

= -10 mA; V = 2.3 V; Note 2

—

= -8 mA; V = 3.0 V; Note 2

—

HIGH-level output voltage

= -10 mA; V = 3.0 V; Note 2

—

= -8 mA; V = 4.75 V; Note 2

—

= -10 mA; V = 4.75 V; Note 2

—

Input leakage current

Input capacitance

= 5.5 V; V = V

—

µA

= 5.5 V; V = V

—

-1

—

3.7

Output capacitance

—

Interrupt INT

LOW-level output current

= 0.4 V

—

Select Inputs A0, A1, A2

LOW-level input voltage

HIGH-level input voltage

Input leakage current

-0.5

2.0

-1

—

0.8

5.5

µA

NOTES:

1. The total current sunk by all I/Os must be limited to 200 mA.

2. The total current sourced by all I/Os must be limited to 160 mA.

2003 Jun 27

Philips Semiconductors

Product data

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9535

SDA

LOW

SU;DAT

BUF

HD;STA

SCL

SU;STD

SU;STA

HD;STA

HD;DAT HIGH

SU01469

Figure 14. Definition of timing

AC CHARACTERISTICS

STANDARD MODE

FAST MODE

I C BUS

SYMBOL

PARAMETER

UNITS

MIN

MAX

100

—

MIN

MAX

400

—

Operating frequency

kHz

µs

SCL

Bus free time between STOP and START conditions

Hold time after (repeated) START condition

Repeated START condition setup time

Set-up time for STOP condition

4.7

4.0

4.7

4.0

0.3

1.3

0.6

0.1

BUF

—

HD;STA

SU;STA

—

SU;STO

VD;ACK

Valid time of ACK condition

3.45

—

0.9

—

Data in hold time

HD;DAT

Data out valid time

300

250

4.7

4.0

—

VD;DAT

SU;DAT

Data set-up time

—

100

1.3

0.6

—

Clock LOW period

Clock HIGH period

Clock/Data fall time

Clock/Data rise time

—

LOW

—

HIGH

300

1000

20 + 0.1C

—

300

—

Pulse width of spikes that must be suppressed by the input

filters

—

Port Timing

Output data valid

—

150

200

—

150

200

—

µs

Input data set-up time

Input data hold time

—

Interrupt Timing

Interrupt valid

Interrupt reset

—

µs

NOTES:

1. C = total capacitance of one bus line in pF.

2. t

3. t

= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

= minimum time for SDA data out to be valid following SCL LOW.

VD;ACK

VD;DAT

4. t measured from 0.7V on SCL to 50% I/O output.

2003 Jun 27

Philips Semiconductors

Product data

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9535

OUT

PULSE

GENERATOR

D.U.T.

TEST CIRCUIT FOR OUTPUTS

DEFINITIONS

R = 1 kΩ

C = 50 pF

= Termination resistance should be equal to Z

pulse generators.

OUT

su01760

Figure 15. t set-up conditions

2003 Jun 27

Philips Semiconductors

Product data

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9535

SO24: plastic small outline package; 24 leads; body width 7.5 mm

SOT137-1

2003 Jun 27

Philips Semiconductors

Product data

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9535

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm

SOT355-1

2003 Jun 27

Philips Semiconductors

Product data

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9535

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals;

body 4 x 4 x 0.85 mm

SOT616-1

2003 Jun 27

Philips Semiconductors

Product data

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9535

REVISION HISTORY

Rev

Date

Description

20030627

Product data (9397 750 11681); ECN 853-2430 30019 dated 11 June 2003.

Initial version

2003 Jun 27

Philips Semiconductors

Product data

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9535

Purchase of Philips I C components conveys a license under the Philips’ I C patent

to use the components in the I C system provided the system conforms to the

I C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Data sheet status

Product

status

Definitions

[1]

Level

Data sheet status

[2] [3]

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in

order to improve the design and supply the best possible product.

III

Product data

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given

in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no

representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree

to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described

or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated

via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys

no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,

 Koninklijke Philips Electronics N.V. 2003

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 06-03

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

9397 750 11681

Philips

Semiconductors

2003 Jun 27

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