PCA9539D [NXP]

16-bit I2C and SMBus, low power I/O port with interrupt and reset; 16位I2C和SMBus ，具有中断和复位低功率I / O端口


型号：	PCA9539D
厂家：	NXP
描述：	16-bit I2C and SMBus, low power I/O port with interrupt and reset 16位I2C和SMBus ，具有中断和复位低功率I / O端口并行IO端口微控制器和处理器外围集成电路光电二极管
文件：	总21页 (文件大小：169K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

PCA9539

16-bit I²C and SMBus, low power I/O port

with interrupt and reset

Product data sheet

2004 Sep 30

Supersedes data of 2004 Aug 27

Philips

Semiconductors

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port

with interrupt and reset

PCA9539

DESCRIPTION

The PCA9539 is a 24-pin CMOS device that provide 16 bits of

General Purpose parallel Input/Output (GPIO) expansion with

interrupt and reset for I C/SMBus applications and was developed

to enhance the Philips family of I C I/O expanders. I/O expanders

provides a simple solution when additional I/O is needed for ACPI

power switches, sensors, pushbuttons, LEDs, fans, etc.

The PCA9539 consists of two 8-bit Configuration (Input or Output

selection); Input, Output and Polarity inversion (Active HIGH or

Active LOW operation) registers. The system master can enable the

I/Os as either inputs or outputs by writing to the I/O configuration

bits. The data for each Input or Output is kept in the corresponding

Input or Output register. The polarity of the read register can be

inverted with the Polarity Inversion Register. All registers can be

read by the system master.

FEATURES

• 16-bit I C GPIO with interrupt and reset

• Operating power supply voltage range of 2.3 V–5.5 V

• 5 V tolerant I/Os

• Polarity inversion register

• Active LOW interrupt output

• Active LOW reset input

• Low stand-by current

• Noise filter on SCL/SDA inputs

• No glitch on power-up

• Internal power-on reset

• 16 I/O pins which default to 16 inputs

• 0 kHz to 400 kHz clock frequency

• ESD protection exceeds 2000 V HBM per JESD22-A114,

200 V MM per JESD22-A115, and 1000 V CDM per

JESD22-C101

The PCA9539 is identical to the PCA9555 except for the removal of

the internal I/O pull-up resistor which greatly reduces power

consumption when the I/Os are held LOW, repleacement of A2 with

RESET and different address range.

The PCA9539 open-drain interrupt output is activated when any

input state differs from its corresponding input port register state and

is used to indicate to the system master that an input state has

changed. The power-on reset sets the registers to their default

values and initializes the device state machine. The RESET pin

causes the same reset/sonfiguration to occur without depowering

the device.

Two hardware pins (A0, A1) vary the fixed I C address and allow up

to four devices to share the same I C/SMBus.

• Latch-up testing is done to JESDEC Standard JESD78 which

exceeds 100 mA

• Offered in three different packages: SO24, TSSOP24, and

HVQFN24

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

–40 °C to +85 °C

ORDER CODE

PCA9539D

TOPSIDE MARK

PCA9539D

PCA9539PW

9539

DRAWING NUMBER

SOT137-1

24-Pin Plastic SO

24-Pin Plastic TSSOP

24-Pin Plastic HVQFN

–40 °C to +85 °C

PCA9539PW

PCA9539BS

SOT355-1

–40 °C to +85 °C

SOT616-1

Standard packing quantities and other packing data are available at www.standardproducts.philips.com/packaging.

I C is a trademark of Philips Semiconductors Corporation.

SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I C patent.

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port

with interrupt and reset

PCA9539

PIN CONFIGURATION — SO, TSSOP

PIN CONFIGURATION —HVQFN

24 V

INT

23 SDA

22 SCL

RESET

I/O0.0

I/O0.1

I/O0.2

I/O0.3

I/O0.4

I/O0.5

I/O0.0

21 A0

I/O1.7

I/O1.6

I/O1.5

I/O1.4

I/O0.1

I/O0.2

I/O0.3

I/O0.4

20 I/O1.7

19 I/O1.6

18 I/O1.5

17 I/O1.4

16 I/O1.3

15 I/O1.2

14 I/O1.1

13 I/O1.0

I/O0.5

I/O1.3

I/O0.6 10

I/O0.7 11

TOP VIEW

SW02200

SW02201

Figure 1. Pin configuration — SO, TSSOP

Figure 2. Pin configuration — HVQFN

PIN DESCRIPTION

SO, TSSOP

PIN NUMBER

HVQFN

PIN NUMBER

SYMBOL

FUNCTION

INT

Interrupt output (open drain)

Address input 1

RESET

I/O0.0–I/O0.7

Active LOW reset input

I/O0.0 to I/O0.7

4–11

1–8

Supply ground

13–20

10–17

I/O1.0–I/O1.7

I/O1.0 to I/O1.7

Address input 0

SCL

SDA

Serial clock line

Serial data line

Supply voltage

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port

with interrupt and reset

PCA9539

BLOCK DIAGRAM

PCA9539

I/O1.0

I/O1.1

I/O1.2

I/O1.3

INPUT/

OUTPUT

PORTS

8-BIT

I/O1.4

I/O1.5

WRITE pulse

READ pulse

I/O1.6

I/O1.7

I C/SMBUS

CONTROL

I/O0.0

I/O0.1

I/O0.2

I/O0.3

SCL

INPUT

FILTER

INPUT/

OUTPUT

PORTS

8-BIT

SDA

I/O0.4

I/O0.5

WRITE pulse

READ pulse

I/O0.6

I/O0.7

POWER-ON

RESET

INT

FILTER

NOTE: ALL I/Os ARE SET TO INPUTS AT RESET

SW02202

Figure 3. Block diagram

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port

with interrupt and reset

PCA9539

SIMPLIFIED SCHEMATIC OF I/Os

DATA FROM

SHIFT REGISTER

OUTPUT PORT

CONFIGURATION

DATA FROM

SHIFT REGISTER

ESD PROTECTION DIODE

WRITE CONFIGURATION

PULSE

I/O PIN

WRITE PULSE

ESD PROTECTION DIODE

OUTPUT

PORT

INPUT PORT

READ PULSE

TO INT

DATA FROM

SHIFT REGISTER

POLARITY

WRITE

POLARITY

PULSE

POLARITY

INVERSION

SU02203

NOTE: At Power-on Reset, all registers return to default values.

Figure 4. Simplified schematic of I/Os

I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off,

creating a high impedance input. The input voltage may be raised

above V to a maximum of 5.5 V.

If the I/O is configured as an output, then either Q1 or Q2 is on,

depending on the state of the Output Port register. Care should be

exercised if an external voltage is applied to an I/O configured as an

output because of the low impedance path that exists between the

pin and either V or V

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port

with interrupt and reset

PCA9539

REGISTERS

bit

C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0

default

Command Byte

This register configures the directions of the I/O pins. If a bit in this

as an input with high impedance output driver. If a bit in this register

is cleared (written with ‘0’), the corresponding port pin is enabled as

an output. At reset the device’s ports are inputs.

Command

Input port 0

Input port 1

Output port 0

Output port 1

Polarity inversion port 0

Polarity inversion port 1

Configuration port 0

Configuration port 1

POWER-ON RESET

When power is applied to V , an internal power-on reset holds the

PCA9539 in a reset condition until V has reached V

. At that

POR

point, the reset condition is released and the PCA9539 registers and

SMBus state machine will initialize to their default states. Therefore,

must be lowered below 0.2 V to reset the device.

The command byte is the first byte to follow the address byte during

a write transmission. It is used as a pointer to determine which of the

following registers will be written or read.

For a power reset cycle, V must be lowered below 0.2 V and then

restored to the operating voltage.

RESET Input

Registers 0 and 1 — Input Port Registers

A reset can be accomplished by holding the RESET pin LOW for a

bit

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1 IO.0

minimum of t . The PCA9539 registers and SMBus/I C state

machine will be held in their default state until the RESET input is

once again HIGH. This input typically requires a pull-up to V

default

bit

I1.1

I1.0

I1.7

I1.6

I1.5

I1.4

I1.3

I1.2

default

DEVICE ADDRESS

This register is an input-only port. It reflects the incoming logic levels

of the pins, regardless of whether the pin is defined as an input or an

output by Register 3. Writes to this register have no effect.

slave address

A1 A0 R/W

The default value ‘X’ is determined by the externally applied logic

level.

fixed

programmable

SW02204

Registers 2 and 3 — Output Port Registers

O0.7

O0.6

O0.5

O0.4

O0.3

O0.2

O0.1

O0.0

bit

Figure 5. PCA9539 address

default

bit

O1.7

O1.6

O1.5

O1.4

O1.3

O1.2

O1.1

O1.0

default

This register is an output-only port. It reflects the outgoing logic

levels of the pins defined as outputs by Register 6 and 7. Bit values

in this register have no effect on pins defined as inputs. In turn,

reads from this register reflect the value that is in the flip-flop

controlling the output selection, NOT the actual pin value.

Registers 4 and 5 — Polarity Inversion Registers

bit

N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0

default

bit

N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0

default

This register allows the user to invert the polarity of the Input Port

Port data polarity is inverted. If a bit in this register is cleared (written

with a ‘0’), the Input Port data polarity is retained.

Registers 6 and 7 — Configuration Registers

bit

C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0

default

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port

with interrupt and reset

PCA9539

After a restart, the device address is sent again but this time, the

least significant bit is set to a logic 1. Data from the register defined

by the command byte will then be sent by the PCA9539 (see

Figures 8 , 9, and 10). Data is clocked into the register on the falling

edge of the acknowledge clock pulse. After the first byte is read,

additional bytes may be read but the data will now reflect the

information in the other register in the pair. For example, if you read

Input Port 1, then the next byte read would be Input Port 0. There is

no limitation on the number of data bytes received in one read

transmission but the final byte received, the bus master must not

acknowledge the data.

BUS TRANSACTIONS

Writing to the port registers

Data is transmitted to the PCA9539 by sending the device address

and setting the least significant bit to a logic 0 (see Figure 5 for

device address). The command byte is sent after the address and

determines which register will receive the data following the

command byte.

The eight registers within the PCA9539 are configured to operate

as four register pairs. The four pairs are Input Ports, Output Ports,

Polarity Inversion Ports, and Configuration Ports. After sending data

to one register, the next data byte will be sent to the other register in

the pair (see Figures 6 and 7). For example, if the first byte is sent to

Output Port (register 3), then the next byte will be stored in Output

Port 0 (register 2). There is no limitation on the number of data bytes

sent in one write transmission. In this way, each 8-bit register may

be updated independently of the other registers.

Interrupt Output

The open-drain interrupt output is activated when one of the port

pins change state and the pin is configured as an input. The

interrupt is deactivated when the input returns to its previous state or

the input port register is read (see Figure 9). A pin configured as an

output cannot cause an interrupt. Since each 8-bit port is read

independently, the interrupt caused by Port 0 will not be cleared by a

read of Port 1 or the other way around.

Reading the port registers

In order to read data from the PCA9539, the bus master must first

send the PCA9539 address with the least significant bit set to a

logic 0 (see Figure 5 for device address). The command byte is sent

after the address and determines which register will be accessed.

Note that changing an I/O from an output to an input may cause a

false interrupt to occur if the state of the pin does not match the

contents of the Input Port register.

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port

with interrupt and reset

PCA9539

WS025

US026

2004 Sep 30

data from lower

or upper byte

of register

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

acknowledge

from master

slave address

A1 A0

COMMAND BYTE

DATA

MSB

LSB

first byte

R/W

at this moment master-transmitter

becomes master-receiver and

slave-receiver becomes

slave-transmitter

data from upper

or lower byte of

no acknowledge

from master

MSB

LSB NA

DATA

last byte

SW02207

NOTE: Transfer can be stopped at any time by a STOP condition.

Figure 8. READ from register

SCL

SDA

I0.x

I1.x

I0.x

I1.x

A1 A0

R/W ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

NON ACKNOWLEDGE

FROM MASTER

READ FROM PORT 0

DATA INTO PORT 0

READ FROM PORT 1

DATA INTO PORT 1

INT

SW02208

NOTES: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).

It is assumed that the command byte has previously been set to 00 (read input port port register).

Figure 9. READ input port register — scenario 1

SCL

SDA

I0.x

I1.x

I0.x

I1.x

A1 A0

DATA 00

DATA 10

DATA 03

DATA 12

R/W ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

NON ACKNOWLEDGE

FROM MASTER

READ FROM PORT 0

DATA INTO PORT 0

READ FROM PORT 1

DATA INTO PORT 1

DATA 00

DATA 01

DATA 02

DATA 03

DATA 10

DATA 11

DATA 12

INT

SW02209

NOTES: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).

It is assumed that the command byte has previously been set to 00 (read input port port register).

Figure 10. READ input port register — scenario 2

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9539

TYPICAL APPLICATION

(5 V)

SUBSYSTEM 1

(e.g. temp sensor)

100 kΩ

(×3)

2 kΩ

SUBSYSTEM 2

(e.g. counter)

10 kΩ

INT

RESET

I/O

SCL

SDA

SCL

0.0

0.1

0.2

MASTER

CONTROLLER

SDA

INT

I/O

0.3

I/O

0.4

I/O

0.5

ENABLE

ALARM

RESET

GND

SUBSYSTEM 3

(e.g. alarm system)

PCA9539

Controlled Switch

(e.g. CBT device)

I/O

0.6

I/O

0.7

I/O

1.0

I/O

1.1

10 DIGIT

NUMERIC

KEYPAD

I/O

1.2

1.3

1.4

1.5

1.6

1.7

I/O

NOTE: Device address configured as 1110100 for this example

I/O , I/O , I/O , configured as outputs

0.0

0.2

0.3

I/O , I/O , I/O , configured as inputs

0.1

0.4

0.5

I/O , I/O , and I/O to I/O configured as inputs

0.6

0.7

1.0

1.7

SW02094

Figure 11. Typical application

Minimizing I when the I/O is used to control LEDs

When the I/Os are used to control LEDs, they are normally connected to V through a resistor as shown in Figure 11. Since the LED acts as a

diode, when the LED is off the I/O V is about 1.2 V less than V . The supply current, I , increases as V becomes lower than V and is

specified as ∆I in the DC characteristics table.

Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or

equal to V when the LED is off. Figure 12 shows a high value resistor in parallel with the LED. Figure 13 shows V less than the LED supply

voltage by at least 1.2 V. Both of these methods maintain the I/O V at or above V and prevents additional supply current consumption when

the LED is off.

3.3 V

5 V

LED

100 kΩ

LED

LEDx

SW02086

SW02087

Figure 12. High value resistor in parallel with the LED

Figure 13. Device supplied by a lower voltage

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9539

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Supply voltage

–0.5

6.0

DC input current on an I/O

DC output current on an I/O

DC input current

– 0.5

I/O

—

± 50

± 20

160

200

+150

+85

+125

°C

Supply current

—

Supply current

—

tot

Total power dissipation

Storage temperature range

Operating ambient temperature

Maximum junction temperature

—

stg

–65

–40

—

amb

°C

J(MAX)

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9539

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take

precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under “Handling MOS devices”.

DC CHARACTERISTICS

= 2.3 V to 5.5 V; V = 0 V; T

= –40 °C to +85 °C; unless otherwise specified.

amb

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Supplies

Supply voltage

Supply current

2.3

—

5.5

Operating mode; V = 5.5 V; no load;

135

200

µA

= 100 kHz; I/O = inputs

SCL

Standby mode; V = 5.5 V; no load;

Standby current

—

0.25

µA

stbl

V = V ; f

= 0 kHz; I/O = inputs

SS SCL

Standby mode; V = 5.5 V; no load;

Standby current

—

0.25

1.5

µA

stbh

V = V ; f

= 0 kHz; I/O = inputs

DD SCL

Power-on reset voltage (Note 1)

No load; V = V or V

1.65

POR

input SCL; input/output SDA

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

Leakage current

–0.5

—

tbd

—

0.3V

0.7V

5.5

—

= 0.4 V

µA

V = V = V

–1

—

Input capacitance

V = V

I/Os

LOW-level input voltage

HIGH-level input voltage

–0.5

—

0.3V

0.7V

5.5

—

= 0.5 V; V = 2.3 V to 5.5 V; Note 2

8–20

10–24

—

LOW-level output current

= 0.7 V; V = 2.3 V to 5.5 V; Note 2

1.8

1.7

2.6

2.5

4.1

4.0

—

= –8 mA; V = 2.3 V; Note 3

= –10 mA; V = 2.3 V; Note 3

—

= –8 mA; V = 3.0 V; Note 3

—

HIGH-level output voltage

= –10 mA; V = 3.0 V; Note 3

—

= –8 mA; V = 4.75 V; Note 3

—

= –10 mA; V = 4.75 V; Note 3

—

Input leakage current

Input capacitance

= 5.5 V; V = V

—

µA

= 5.5 V; V = V

—

–1

—

3.7

Output capacitance

—

Interrupt INT

LOW-level output current

= 0.4 V

tbd

—

Select Inputs A0, A1, and RESET

LOW-level input voltage

HIGH-level input voltage

Input leakage current

–0.5

—

0.3V

0.7V

5.5

–1

µA

NOTES:

1. V must be lowered to 0.2 V in order to reset part.

2. Each I/O must be externally limited to a maximum of 25 mA and each octal (I/O0.0 to I/O0.7, and I/O1.0 to I/O1.7) must be limited to a

maximum current of 100 mA for a device total of 200 mA.

3. The total current sourced by all I/Os must be limited to 160 mA (80 mA for I/O 0.0 through 0.7 and 80 mA for I/O 1.0 through 1.7).

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9539

AC CHARACTERISTICS

STANDARD MODE

FAST MODE

I C-bus

SYMBOL

PARAMETER

UNITS

MIN

MAX

100

—

MIN

MAX

400

—

Operating frequency

1.3

kHz

µs

SCL

Bus free time between STOP and START conditions

Hold time after (repeated) START condition

Repeated START condition setup time

Set-up time for STOP condition

4.7

4.0

4.7

4.0

0.3

BUF

—

0.6

—

HD;STA

—

0.6

—

SU;STA

—

0.6

—

SU;STO

VD;ACK

Valid time of ACK condition

3.45

—

0.1

0.9

—

Data in hold time

HD;DAT

Data out valid time

300

250

4.7

4.0

—

VD;DAT

SU;DAT

Data set-up time

—

100

—

Clock LOW period

—

1.3

—

LOW

Clock HIGH period

—

0.6

—

HIGH

Clock/Data fall time

300

1000

20 + 0.1C

—

300

Clock/Data rise time

—

Pulse width of spikes that must be suppressed by the input filters

—

Port Timing

Output data valid

—

150

200

—

150

200

—

µs

Input data set-up time

Input data hold time

—

Interrupt Timing

Interrupt valid

Interrupt reset

—

µs

RESET

Reset pulse width

Reset recovery time

Time to reset

—

REC

5,6

400

RESET

NOTES:

1. C = total capacitance of one bus line in pF.

2. t

3. t

= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

= minimum time for SDA data out to be valid following SCL LOW.

VD;ACK

VD;DAT

4. t measured from 0.7V on SCL to 50% I/O output.

5. Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.

6. Upon reset, the full delay will be the sum of t

and the RC time constant of the SDA bus.

RESET

SDA

LOW

SU;DAT

BUF

HD;STA

SCL

SU;STD

SU;STA

HD;STA

HD;DAT HIGH

SU01469

Figure 14. Definition of timing

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9539

START

ACK OR READ CYCLE

SCL

SDA

30%

RESET

50%

REC

RESET

50%

I/Ox

I/O configured as inputs

SW02340

Figure 15. Definition of RESET timing

70 %

30 %

SCL

SDA

INPUT

50 %

INT

SW02329

Figure 16. Expanded view of Read input port register

70 %

30 %

SCL

SDA

OUTPUT

50 %

SW02330

Figure 17. Expanded view of Write to output port register

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9539

BIT 7

MSB

(A7)

START

CONDITION

(S)

STOP

CONDITION

(S)

BIT 6

(A6)

BIT 0

(R/W)

ACKNOWLEDGE

(A)

PROTOCOL

HIGH

SU;STA

LOW

1 / f

SCL

SDA

BUF

SU;STO

HD;STA

SU;DAT

VD;DAT

HD;DAT

VD;ACK

SW02210

Figure 18. I C-bus timing diagram; rise and fall times refer to V and V

TEST CIRCUITS

Open

= 500 Ω

PULSE

GENERATOR

D.U.T.

50 pF

DEFINITIONS

R = Load resistor.

C = Load capacitance includes jig and probe capacitance

R = Termination resistance should be equal to the output

impedance Z of the pulse generators.

SW02181

Figure 19. Test circuitry for switching times

500 Ω

From Output

Under Test

Open

GND

500 Ω

= 50 pF

Load Circuit

TEST

2 V

SA00652

Figure 20. Test circuit

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9539

SO24: plastic small outline package; 24 leads; body width 7.5 mm

SOT137-1

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9539

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm

SOT355-1

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9539

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals;

body 4 x 4 x 0.85 mm

SOT616-1

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9539

REVISION HISTORY

Rev

Date

Description

20040930

Product data sheet (9397 750 14048). Supersedes data of 2004 Aug 27 (9397 750 12898).

Modifications:

• Section “Registers 0 and 1—Input Port Registers” on page 6:

– add table and second paragraph

• Figure 11 on page 11: resistor values modified

• “DC Characteristics” table on page 13:

– sub-section “I/Os”:

change V (max) from 0.8 V to 0.3V

change V (min) from 2.0 V to 0.7V

– sub-section “Select inputs A0, A1, and RESET:

change V (max) from 0.8 V to 0.3V

change V (min) from 2.0 V to 0.7V

• Figure 15 on page 15 modified.

20040827

Product data sheet (9397 750 12898).

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus, low power I/O port with interrupt

PCA9539

Purchase of Philips I C components conveys a license under the Philips’ I C patent

to use the components in the I C system provided the system conforms to the

I C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Data sheet status

Product

status

Definitions

[1]

Level

Data sheet status

[2] [3]

Objective data sheet

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data sheet

Product data sheet

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in

order to improve the design and supply the best possible product.

III

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given

in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no

representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree

to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described

or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated

viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys

nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,

Koninklijke Philips Electronics N.V. 2004

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 09-04

9397 750 14048

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

2004 Sep 30

PCA9539D [NXP]

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