PCA9540D [NXP]
2-channel I2C multiplexer; 2通道I2C多路复用器
| 型号： | PCA9540D |
| 厂家： | 
NXP |
| 描述： | 2-channel I2C multiplexer |
| 文件： | 总10页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
PCA9540
2-channel I2C multiplexer
Product specification
1999 Dec 15
Philips
Semiconductors
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
FEATURES
PIN CONFIGURATION
• 1-of-2 bi-directional translating multiplexer
2
• Channel selection via I C bus
• Operating supply voltage 2.5 to 3.6 V
• Operating temperature range 0°C to 70°C
• Power-up with all multiplexer channels deselected
• Low on resistance
SCL
SDA
1
2
3
4
8
7
6
5
SC1
SD1
V
V
SS
DD
SC0
SD0
DESCRIPTION
The PCA9540 is a 1-of-2 bi-directional translating multiplexer,
controlled via the I C bus. The SCL/SDA upstream pair fans out to
SW00491
2
two SCx/SDx downstream pairs, or channels. Only one SCx/SDx
channel is selected at a time, determined by the contents of the
programmable control register.
PIN DESCRIPTION
The pass gates of the multiplexer are constructed such that the V
pin can be used to limit the maximum high voltage which will be
passed by the PCA9540. This allows the use of different bus
voltages on each SCx/SDx pair, so that 3.3 V parts can
communicate with 5 V parts without any additional protection.
DD
PIN
SYMBOL
NUMBER
FUNCTION
1
2
3
4
5
6
7
8
SCL
SDA
Serial clock line
Serial data line
Supply voltage
Serial data 0
External pull-up resistors can pull the bus up to the desired voltage
level for this channel.
V
DD
SD0
SC0
Serial clock 0
Supply ground
Serial data 1
V
SS
SD1
SC1
Serial clock 1
ORDERING INFORMATION
PACKAGES
8-Pin Plastic SO
8-Pin Plastic TSSOP
TEMPERATURE RANGE
0°C to +70°C
ORDER CODE
DRAWING NUMBER
SOT96-1
PCA9540D
0°C to +70°C
PCA9540PW DH
SOT505-1
2
1999 Dec 15
853–2185 22852
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
BLOCK DIAGRAM
SC0
SC1
SD0
SD1
V
SS
Power-on
Reset
V
DD
SCL
SDA
2
Input
Filter
I C-Bus
Control
SW00492
3
1999 Dec 15
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
2
CHANNEL SELECTION
CHARACTERISTICS OF THE I C-BUS
2
A SC0x/SD0x downstream pair, or channel, is selected by the
contents of the control register. This register is written after the
PCA9540 has been addressed. The 2 LSBs of the control byte are
used to determine which channel is to be selected. When a channel
is selected, the channel will become active after a stop condition has
The I C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
2
been placed on the I C bus. This ensures that all SCx/SDx lines will
Bit transfer
be in a HIGH state when the channel is made active, so that no
false conditions are generated at the time of connection.
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see FIgure 1).
CONTROL BYTE
SELECTED
CHANNEL
7
X
X
X
6
X
X
X
5
X
X
X
4
X
X
X
3
X
X
X
2
0
1
1
1
X
0
0
0
X
0
1
none
0 (SC0/SD0)
1 (SC1/SD1)
SDA
SCL
CONTROL REGISTER
data line
stable;
data valid
change
of data
allowed
7
6
5
4
3
2
1
0
X
X
X
X
X
B2 B1 B0
SW00363
Figure 1. Bit transfer
Start and stop conditions
Channel select bits
(read/write)
SW00497
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 2).
POWER-ON RESET
During power-up the control register defaults to all zeroes causing
all the channels to be deselected.
System configuration
A device generating a message is a ‘transmitter’, a device receiving
is the ‘receiver’. The device that controls the message is the
‘master’ and the devices which are controlled by the master are the
‘slaves’ (see Figure 3).
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
SW00365
Figure 2. Definition of start and stop conditions
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
2
SLAVE
RECEIVER
I C
MASTER
TRANSMITTER
TRANSMITTER/
RECEIVER
MULTIPLEXER
SLAVE
SW00366
Figure 3. System configuration
4
1999 Dec 15
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START condition
SW00368
2
Figure 4. Acknowledgement on the I C-bus
slave address
1
1
1
0
0
0
0
fixed
hardware selectable
SW00564
Figure 5. Slave address
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SDA
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SLAVE ADDRESS
CONTROL REGISTER
SDA
1
1
1
0
0
0
0
X
X
X
X
X
B2 B1 B0
A
P
S
0
A
start condition
R/W acknowledge
from slave
acknowledge
from slave
PREVIOUS CHANNEL
NEW CHANNEL
SW00498
t
pv
Figure 6. WRITE control register
SLAVE ADDRESS
CONTROL REGISTER
last byte
SDA
1
1
1
0
0
0
0
S
1
A
X
X
X
X
X
B2 B1 B0 NA
P
start condition
R/W acknowledge
from slave
no acknowledge
from master
stop condition
SW00499
Figure 7. READ control register
5
1999 Dec 15
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
1, 2
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +7.0
–0.5 to +7.0
±20
UNIT
V
V
DD
V
I
DC input voltage
V
I
I
DC input current
mA
mA
mA
mA
mW
°C
I
O
DC output current
±25
I
Supply current
±100
DD
I
SS
Supply current
±100
P
tot
total power dissipation
Storage temperature range
Operating ambient temperature
400
T
stg
–60 to +150
0 to +70
T
amb
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
DC CHARACTERISTICS
V
= 2.5 to 3.6 V; V = 0 V; T
= 0°C to +70°C; unless otherwise specified.
DD
SS
amb
LIMITS
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
Supply
VDDQn ≤ V
Supply voltage
Supply current
2.5
–
3.6
V
DD
Operating mode; V = 3.6 V;
DD
no load; V = V or V ;
I
20
100
µA
I
DD
SS
DD
f
= 100 kHz
SCL
I
Power on current
Standby current
Power on mode with no channels selected
Standby mode; V = 3.6 V;
–
–
140
2.5
200
100
µA
µA
DP
DD
I
stb
no load; V = V or V
I
DD
SS
V
= 3.6 V; no load;
DD
I
V
POR
Power-on reset voltage
–
1.3
2.1
V
V = V or V
DD
SS
Input SCL; input/output SDA
V
LOW level input voltage
HIGH level input voltage
–0.5
–
–
–
–
–
–
0.3 V
6
V
IL
DD
V
IH
0.3 V
V
DD
V
V
= 0.4 V
= 0.6 V
3
6
–
mA
mA
µA
pF
OL
I
OL
LOW level output current
–
OL
I
L
Leakage current
Input capacitance
V = V or V
SS
–1
–
+1
10
I
DD
C
V = V
I SS
i
Select inputs A0 to A2 / INT0 to INT3
V
LOW level input voltage
HIGH level input voltage
Input leakage current
–0.5
–
–
–
+0.3 V
V
V
IL
IH
LI
DD
V
0.7 V
–1
V
DD
+ 0.5
DD
I
pin at V or V
+1
µA
DD
SS
Pass Gate
V
= 3.67 V, V = 0.4 V, I = 15 mA
5
7
20
26
21
55
CC
O
O
R
Switch resistance
Ω
ON
V
= 2.3 to 2.7 V, V = 0.4 V, I = 10 mA
CC
O
O
V
swin
= V = 3.3 V; I = –100 µA
swout
2.2
DD
V
V
= V = 3.0 to 3.6 V; I = –100 µA
swout
1.6
1.1
2.8
2.0
swin
DD
V
Pass
Switch output voltage
V
V
= V = 2.5 V; I = –100 µA
swout
1.5
swin
DD
= V = 2.3 to 2.7 V; I = –100 µA
swout
swin
DD
6
1999 Dec 15
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
AC CHARACTERISTICS
STANDARD-MODE
FAST-MODE
I C-BUS
2
2
I C-BUS
SYMBOL
PARAMETER
UNIT
MIN
MAX
MIN
MAX
1
1
t
Propagation delay from SDA to SD or SCL to SC
0.3
0.3
ns
kHz
µs
pd
n
n
f
SCL clock frequency
0
100
–
0
400
–
SCL
BUF
t
Bus free time between a STOP and START condition
4.7
1.3
Hold time (repeated) START condition
After this period, the first clock pulse is generated
t
t
4.0
–
0.6
–
µs
HD:STA
t
LOW period of the SCL clock
4.7
4.0
4.7
–
–
–
1.3
0.6
0.6
–
–
µs
µs
µs
LOW
t
HIGH period of the SCL clock
HIGH
Set-up time for a repeated START condition
SU:STA
Data hold time:
t
for CBUS compatible masters
for I C-bus devices
5.0
0
–
–
–
0
–
0.9
µs
µs
HD:DAT
2
2
2
3
4
t
Data set-up time
250
–
–
1000
300
–
100
20 + 0.1C
20 + 0.1C
0.6
–
ns
ns
ns
µs
pF
SU:DAT
5
5
t
Set-up time for STOP condition
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Capacitive load for each bus line
300
300
–
SU:STO
b
b
t
r
–
t
f
4.0
C
400
–
400
b
NOTES:
1. Pass gate propagation delay is calculated from the 20 Ω typical R and and the 15 pF load capacitance.
ON
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH
of the SCL signal) in order to bridge
min
the undefined region of the falling edge of SCL.
3. The maximum t
has only to be met if the device does not stretch the LOW period (t
) of the SCL signal.
LOW
HD:DAT
2
2
4. A fast-mode I C bus device can be used in a standard-mode I C-bus system, but the requirement t
≥ 250 ns must then be met. This
SU:DAT
will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line t
I C-bus specification) before the SCL line is released.
+ t
= 1000 + 250 = 1250 ns (according to the standard-mode
rmax
SU:DAT
2
5. C = total capacitance of one bus line in pF.
b
SDA
t
R
t
F
t
t
SP
HD;STA
t
t
LOW
BUF
SCL
t
t
t
SU;STO
HD;STA
SU;STA
t
t
t
SU;DAT
HD;DAT
HIGH
P
S
Sr
P
SU00645
2
Figure 8. Definition of timing on the I C-bus
7
1999 Dec 15
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
SO8: plastic small outline package; 8 leads; body width 3.9mm
SOT96-1
8
1999 Dec 15
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
9
1999 Dec 15
Philips Semiconductors
Product specification
2-channel I2C multiplexer
PCA9540
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent
2
to use the components in the I C system provided the system conforms to the
I C specifications defined by Philips. This specification can be ordered using the
2
code 9398 393 40011.
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 02-00
Document order number:
9397 750 06882
Philips
Semiconductors
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