PCA9554B [NXP]
Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, weak pull-up; 低压8位I2C总线和SMBus低功率I /带中断输出口，弱上拉
| 型号： | PCA9554B |
| 厂家： | 
NXP |
| 描述： | Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, weak pull-up |
| 文件： | 总36页 (文件大小：2481K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9554B; PCA9554C
Low-voltage 8-bit I2C-bus and SMBus low power I/O port with
interrupt, weak pull-up
Rev. 1 — 19 September 2012
Product data sheet
1. General description
The PCA9554B and PCA9554C are low-voltage 8-bit General Purpose Input/Output
(GPIO) expanders with interrupt for I2C-bus/SMBus applications. The only difference
between the PCA9554B and PCA9554C is their I2C fixed address allowing a larger
number of the same device on the I2C-bus with no chance of address conflict. NXP I/O
expanders provide a simple solution when additional I/Os are needed while keeping
interconnections to a minimum, for example, in ACPI power switches, sensors,
push buttons, LEDs, fan control, etc.
In addition to providing a flexible set of GPIOs, the wide VDD range of 1.65 V to 5.5 V allow
the PCA9554B/PCA9554C to interface with next-generation microprocessors and
microcontrollers where supply levels are dropping down to conserve power.
The PCA9554B/PCA9554C contain a register set of 8-bit Configuration, Input, Output,
and Polarity Inversion registers.
The PCA9554B is a pin-to-pin replacement for the PCA9554, while the PCA9554C
replaces the PCA9554A. Both of these devices replace other industry-standard part
numbers. More fully-featured parts PCAL9554B and PCAL9554C are also available with
Agile I/O features. See the respective data sheet for more details.
The PCA9554B/PCA9554C open-drain interrupt (INT) output is activated when any input
state differs from its corresponding Input Port register state and is used to indicate to the
system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I2C-bus. Thus, the
PCA9554B/PCA9554C can remain a simple slave device.
The device outputs have 25 mA sink capabilities for directly driving LEDs while consuming
low device current.
The power-on reset sets the registers to their default values and initializes the device state
machine.
Three hardware pins (A0, A1, A2) select the fixed I2C-bus address and allow up to eight
devices to share the same I2C-bus/SMBus. The PCA9554B and PCA9554C differ only in
their base I2C-bus addresses permitting a total of 16 devices on the I2C-bus, minimizing
the chance for address conflict, even in the most complex system.
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
2. Features and benefits
I2C-bus to parallel port expander
Operating power supply voltage range of 1.65 V to 5.5 V
Low standby current consumption:
1.5 A (typical at 5 V VDD
)
1.0 A (typical at 3.3 V VDD
)
Schmitt-trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs
Vhys = 0.10 VDD (typical)
5 V tolerant I/Os
Open-drain active LOW interrupt output (INT)
400 kHz Fast-mode I2C-bus
Input/output configuration register
Polarity inversion register
Internal power-on reset
Power-up with all channels configured as inputs
No glitch on power-up
Latched outputs with 25 mA drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100 mA per JESD78, Class II
ESD protection exceeds JESD22
2000 V Human Body Model (A114-A)
1000 V Charged-Device Model (C101)
Packages offered: TSSOP16 and HVQFN16
PCA9554B_PCA9554C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
2 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
3. Ordering information
Table 1.
Ordering information
Type number
Topside
mark
Package
Name
Description
Version
PCA9554BBS
P4B
HVQFN16
plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3 3 0.85 mm
SOT758-1
SOT403-1
SOT758-1
SOT403-1
PCA9554BPW PA9554B TSSOP16
PCA9554CBS P4C HVQFN16
PCA9554CPW PA9554C TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3 3 0.85 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
HVQFN16
TSSOP16
HVQFN16
TSSOP16
Packing method
Minimum
order quantity
Temperature range
Tamb = 40 C to +85 C
amb = 40 C to +85 C
Tamb = 40 C to +85 C
PCA9554BBS
PCA9554BBSHP
Reel pack, SMD,
13-inch, Turned
6000
2500
6000
2500
PCA9554BPW PCA9554BPWJ
PCA9554CBS PCA9554CBSHP
PCA9554CPW PCA9554CPWJ
Reel pack, SMD,
13-inch
T
Reel pack, SMD,
13-inch, Turned
Reel pack, SMD,
13-inch
T
amb = 40 C to +85 C
4. Block diagram
P0
P1
P2
P3
P4
P5
P6
P7
A0
A1
A2
8-bit
INPUT/
OUTPUT
PORTS
2
I C-BUS/SMBus
SCL
SDA
INPUT
FILTER
CONTROL
write pulse
read pulse
POWER-ON
RESET
V
DD
V
DD
PCA9554B
PCA9554C
INT
LP
FILTER
V
SS
002aah117
Remark: All I/Os are set to inputs at reset.
Fig 1. Block diagram of PCA9554B; PCA9554C
PCA9554B_PCA9554C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
3 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
5. Pinning information
5.1 Pinning
terminal 1
index area
1
2
3
4
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A2
P0
P1
P2
SCL
INT
P7
A0
A1
A2
P0
P1
P2
P3
V
DD
SDA
SCL
INT
P7
PCA9554BBS
PCA9554CBS
PCA9554BPW
PCA9554CPW
P6
P6
P5
V
SS
P4
002aah120
Transparent top view
002aah119
Fig 2. Pin configuration for TSSOP16
Fig 3. Pin configuration for HVQFN16
5.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
TSSOP16
HVQFN16
A0
1
15
16
1
address input 0
A1
2
address input 1
A2
3
address input 2
P0[1]
P1[1]
P2[1]
P3[1]
VSS
P4[1]
P5[1]
P6[1]
P7[1]
INT
4
2
Port P input/output 0
Port P input/output 1
Port P input/output 2
Port P input/output 3
supply ground
5
3
6
4
7
5
6[2]
8
9
7
Port P input/output 4
Port P input/output 5
Port P input/output 6
Port P input/output 7
interrupt output (open-drain)
serial clock line
10
11
12
13
14
15
16
8
9
10
11
12
13
14
SCL
SDA
VDD
serial data line
supply voltage
[1] All I/O are configured as input at power-on.
[2] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The
SS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
V
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
PCA9554B_PCA9554C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
4 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
6. Functional description
Refer to Figure 1 “Block diagram of PCA9554B; PCA9554C”.
6.1 Device address
slave address
slave address
0
1
0
0
A2 A1 A0 R/W
0
1
1
1
A2 A1 A0 R/W
fixed
hardware
selectable
fixed
hardware
selectable
002aah121
002aah122
a. PCA9554B address
b. PCA9554C address
Fig 4. Device address
A2, A1 and A0 are the hardware address package pins and are held to either HIGH
(logic 1) or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit
of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH
(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
6.2 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCA9554B/PCA9554C.
Two bits of this data byte state the operation (read or write) and the internal registers
(Input, Output, Polarity Inversion, or Configuration) that will be affected. This register is
write only.
B7 B6 B5 B4 B3 B2 B1 B0
002aaf540
Fig 5. Pointer register bits
Table 4.
Command byte
Pointer register bits
B7 B6 B5 B4 B3 B2 B1 B0
Command byte Register
(hexadecimal)
Protocol
Power-up
default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
00h
01h
02h
03h
Input port
read byte
xxxx xxxx[1]
1111 1111
0000 0000
1111 1111
Output port
read/write byte
read/write byte
read/write byte
Polarity Inversion
Configuration
[1] Undefined.
PCA9554B_PCA9554C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
5 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
6.3 Interface definition
Table 5.
Byte
Interface definition
Bit
7 (MSB)
6
5
4
3
2
1
0 (LSB)
PCA9554B
I2C-bus slave address
L
H
L
L
A2
A1
A0
R/W
PCA9554C
L
H
H
H
A2
P3
A1
P2
A0
P1
R/W
P0
I2C-bus slave address
I/O data bus
P7
P6
P5
P4
6.4 Register descriptions
6.4.1 Input port register (00h)
The Input port register (register 0) reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by the Configuration register. The
Input port register is read only; writes to this register have no effect. The default value ‘X’
is determined by the externally applied logic level. An Input port register read operation is
performed as described in Section 7.2 “Read commands”.
Table 6.
Bit
Input port register (address 00h)
7
I7
X
6
I6
X
5
I5
X
4
I4
X
3
I3
X
2
I2
X
1
I1
X
0
I0
X
Symbol
Default
6.4.2 Output port register (01h)
The Output port register (register 1) shows the outgoing logic levels of the pins defined as
outputs by the Configuration register. Bit values in these registers have no effect on pins
defined as inputs. In turn, reads from this register reflect the value that was written to this
register, not the actual pin value.
Table 7.
Bit
Output port register (address 01h)
7
O7
1
6
O6
1
5
O5
1
4
O4
1
3
O3
1
2
O2
1
1
O1
1
0
O0
1
Symbol
Default
6.4.3 Polarity inversion register (02h)
The Polarity inversion register (register 2) allows polarity inversion of pins defined as
inputs by the Configuration register. If a bit in this register is set (written with ‘1’), the
corresponding port pin’s polarity is inverted. If a bit in this register is cleared (written with a
‘0’), the corresponding port pin’s original polarity is retained.
Table 8.
Bit
Polarity inversion register (address 02h)
7
N7
0
6
N6
0
5
N5
0
4
N4
0
3
N3
0
2
N2
0
1
N1
0
0
N0
0
Symbol
Default
PCA9554B_PCA9554C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
6 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
6.4.4 Configuration register (03h)
The Configuration register (register 3) configures the direction of the I/O pins. If a bit in this
register is set to 1, the corresponding port pin is enabled as a high-impedance input. If a
bit in this register is cleared to 0, the corresponding port pin is enabled as an output.
Table 9.
Bit
Configuration register (address 03h)
7
C7
1
6
C6
1
5
C5
1
4
C4
1
3
C3
1
2
C2
1
1
C1
1
0
C0
1
Symbol
Default
6.5 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin and
either VDD or VSS. The external voltage applied to this I/O pin should not exceed the
recommended levels for proper operation.
data from
shift register
output port
register data
configuration
register
V
DD
data from
shift register
Q1
D
Q
FF
100 kΩ
write configuration
pulse
D
Q
CK
Q
FF
P0 to P7
write pulse
CK
Q2
output port
register
V
SS
input port
register
D
Q
input port
register data
FF
read pulse
CK
to INT
polarity inversion
register
data from
shift register
polarity inversion
register data
D
Q
FF
write polarity
pulse
CK
002aah123
On power-up or reset, all registers return to default values.
Fig 6. Simplified schematic of the I/Os (P0 to P7)
PCA9554B_PCA9554C
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
7 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
6.6 Power-on reset
When power (from 0 V) is applied to VDD, an internal power-on reset holds the
PCA9554B/PCA9554C in a reset condition until VDD has reached VPOR. At that time, the
reset condition is released and the PCA9554B/PCA9554C registers and I2C-bus/SMBus
state machine initialize to their default states. After that, VDD must be lowered to below
V
PORF and back up to the operating voltage for a power-reset cycle. See Section 8.2
“Power-on reset requirements”.
6.7 Interrupt output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.
After time tv(INT), the signal INT is valid. Resetting the interrupt circuit is achieved when
data on the port is changed to the original setting or when data is read from the port that
generated the interrupt (see Figure 10). Resetting occurs in the Read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL
signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very
short) due to the reset of the interrupt during this pulse. Each change of the I/Os after
resetting is detected and is transmitted as INT.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output
to an input may cause a false interrupt to occur, if the state of the pin does not match the
contents of the Input port register.
The INT output has an open-drain structure and requires a pull-up resistor to VDD. INT
should be connected to the voltage source of the device that requires the interrupt
information. When using the input latch feature, the input pin state is latched. The interrupt
is reset only when data is read from the port that generated the interrupt. The reset occurs
in the Read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the
rising edge of the SCL signal.
PCA9554B_PCA9554C
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
8 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
7. Bus transactions
The PCA9554B/PCA9554C is an I2C-bus slave device. Data is exchanged between the
master and PCA9554B/PCA9554C through write and read commands using I2C-bus. The
two communication lines are a serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up resistor when connected to the
output stages of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Write commands
Data is transmitted to the PCA9554B/PCA9554C by sending the device address and
setting the Least Significant Bit (LSB) to a logic 0 (see Figure 4 for device address). The
command byte is sent after the address and determines which register receives the data
that follows the command byte. There is no limitation on the number of data bytes sent in
one write transmission.
SCL
1
2
3
4
5
6
7
8
9
STOP
condition
(1)
slave address
command byte
data to port
DATA 1
SDA
S
0
1
0
0
A2 A1 A0
0
A
0
0
0
0
0
0
0
1
A
A
P
START condition
R/W acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
write to port
t
v(Q)
data out from port
DATA 1 VALID
002aah124
(1) PCA9554B address shown. Address for PCA9554C is 0111,A2,A1,A0.
Fig 7. Write to Output port register
SCL
1
2
3
4
5
6
7
8
9
STOP
condition
(1)
slave address
command byte
data to register
DATA 1
SDA
S
0
1
0
0
A2 A1 A0
0
A
0
0
0
0
0
0
1/0 1/0
A
A
P
START condition
R/W acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
002aah125
(1) PCA9554B address shown. Address for PCA9554C is 0111,A2,A1,A0.
Fig 8. Write to Configuration or Polarity inversion registers
PCA9554B_PCA9554C
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
9 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
7.2 Read commands
To read data from the PCA9554B/PCA9554C, the bus master must first send the
PCA9554B/PCA9554C address with the least significant bit set to a logic 0 (see Figure 4
for device address). The command byte is sent after the address and determines which
register is to be accessed.
After a restart the device address is sent again, but this time the LSB is set to a logic 1.
Data from the register defined by the command byte then is sent by the
PCA9554B/PCA9554C (see Figure 9 and Figure 10).
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no
limit on the number of data bytes received in one read transmission, but on the final byte
received the bus master must not acknowledge the data.
(1)
slave address
(cont.)
SDA
S
0
1
0
0
A2 A1 A0
0
A
COMMAND BYTE
A
START condition
slave address
R/W acknowledge from slave
acknowledge from slave
data from register
(1)
data from register
(cont.)
S
0
1
0
0
A2 A1 A0
1
A
DATA (first byte)
A
DATA (last byte)
NA P
(repeated)
START condition
R/W
acknowledge
from slave
acknowledge
from master
no acknowledge STOP
from master condition
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
002aah126
(1) PCA9554B address shown. Address for PCA9554C is 0111,A2,A1,A0.
Fig 9. Read from register
SCL
1
2
3
4
5
6
7
8
9
no acknowledge
from master
(1)
slave address
data from port
DATA 1
data from port
DATA 4
SDA
S
0
1
0
0
A2 A1 A0
1
A
A
1
P
START condition
R/W acknowledge from slave
acknowledge from master
DATA 4
STOP
read from
port
condition
data into
DATA 1
DATA 2
DATA 3
DATA 5
port
t
t
su(D)
h(D)
INT is cleared by
read from port
INT
STOP not needed
to clear INT
t
t
rst(INT)
v(INT)
002aah127
Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port
register).
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and
actual data transfer from P port (see Figure 9).
(1) PCA9554B address shown. Address for PCA9554C is 0111,A2,A1,A0.
Fig 10. Read Input port register
PCA9554B_PCA9554C
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
10 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
8. Application design-in information
V
DD
(3.3 V)
SUB-SYSTEM 1
100 kΩ
10 kΩ
10 kΩ
10 kΩ
2 kΩ
(1)
(× 3)
(e.g., temp sensor)
V
DD
V
DD
INT
MASTER
CONTROLLER
PCA9554B
SCL
SDA
INT
SCL
P0
SUB-SYSTEM 2
(e.g., counter)
SDA
INT
P1
P2
P3
P4
P5
P6
P7
RESET
A
V
SS
controlled
switch
(e.g., CBT device)
enable
A2
A1
A0
B
SUB-SYSTEM 3
(e.g., alarm system)
V
SS
ALARM
V
DD
002aah128
Device address is 0100 000x for this example (PCA9554B).
P0, P2, P3 configured as outputs.
P1, P4, P5 configured as inputs.
(1) External resistors are not needed due to the internal weak pull-up resistors.
Fig 11. Typical application
8.1 Minimizing IDD when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 11. Since the LED acts as a diode, when the LED is off the
I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes
lower than VDD
.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater than or equal to VDD when the LED is off.
Figure 12 and Figure 13 show typical solutions to minimizing current consumption.
Figure 12 shows a high value resistor in parallel with the LED. Figure 13 shows VDD less
than the LED supply voltage by at least 1.2 V. However, the PCA9554B/PCA9554C needs
no external resistors due to the integrated 100 k pull-up resistors.
PCA9554B_PCA9554C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
11 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
3.3 V
5 V
V
DD
V
100 kΩ
V
DD
DD
LED
LED
Pn
Pn
002aag164
002aag165
Fig 12. High value resistor in parallel with
the LED
Fig 13. Device supplied by a lower voltage
8.2 Power-on reset requirements
In the event of a glitch or data corruption, PCA9554B/PCA9554C can be reset to its
default conditions by using the power-on reset feature. Power-on reset requires that the
device go through a power cycle to be completely reset. This reset also happens when the
device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 14 and Figure 15.
V
DD
ramp-up
ramp-down
re-ramp-up
t
d(rst)
time
time to re-ramp
when V drops
(dV/dt)
(dV/dt)
(dV/dt)
r
r
f
DD
002aah329
below 0.2 V or to V
SS
Fig 14. VDD is lowered below 0.2 V or 0 V and then ramped up to VDD
V
DD
ramp-down
ramp-up
t
d(rst)
V drops below POR levels
I
time
time to re-ramp
(dV/dt)
(dV/dt)
r
f
when V
drops
DD
to V
− 50 mV
POR(min)
002aah330
Fig 15. VDD is lowered below the POR threshold, then ramped back up to VDD
Table 10 specifies the performance of the power-on reset feature for
PCA9554B/PCA9554C for both types of power-on reset.
PCA9554B_PCA9554C
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
12 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
Table 10. Recommended supply sequencing and ramp rates
Tamb = 25 C (unless otherwise noted). Not tested; specified by design.
Symbol
(dV/dt)f
(dV/dt)r
td(rst)
Parameter
Condition
Min
0.1
0.1
1
Typ
Max
2000
2000
-
Unit
ms
ms
s
fall rate of change of voltage
rise rate of change of voltage
reset delay time
Figure 14
-
-
-
Figure 14
Figure 14; re-ramp time when
VDD drops to VSS
Figure 15; re-ramp time when
1
-
-
s
VDD drops to VPOR(min) 50 mV
[1]
[2]
VDD(gl)
tw(gl)VDD
VPOR(trip)
glitch supply voltage difference
supply voltage glitch pulse width
power-on reset trip voltage
Figure 16
Figure 16
falling VDD
rising VDD
-
-
-
-
-
1.0
10
-
V
-
s
V
0.7
-
1.4
V
[1] Level that VDD can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when tw(gl)VDD < 1 s.
[2] Glitch width that will not cause a functional disruption when VDD(gl) = 0.5 VDD
.
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance. Figure 16 and Table 10 provide more information on
how to measure these specifications.
V
DD
∆V
DD(gl)
time
002aah331
t
w(gl)VDD
Fig 16. Glitch width and glitch height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition
is released and all the registers and the I2C-bus/SMBus state machine are initialized to
their default states. The value of VPOR differs based on the VDD being lowered to or from
0 V. Figure 17 and Table 10 provide more details on this specification.
V
DD
V
(rising V
(falling V
)
)
POR
DD
DD
V
POR
time
POR
time
002aah332
Fig 17. Power-on reset voltage (VPOR
)
PCA9554B_PCA9554C
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
13 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
8.3 Device current consumption with internal pull-up and pull-down
resistors
The PCA9554B/PCA9554C integrates programmable pull-up and pull-down resistors to
eliminate external components when pins are configured as inputs and pull-up or
pull-down resistors are required (for example, nothing is driving the inputs to the power
supply rails. Since these pull-up and pull-down resistors are internal to the device itself,
they contribute to the current consumption of the device and must be considered in the
overall system design.
The pull-up or pull-down function is selected in registers 48h and 49h, while the resistor is
connected by the enable registers 46h and 47h. The configuration of the resistors is
shown in Figure 6.
If the resistor is configured as a pull-up, that is, connected to VDD, a current will flow from
the VDD pin through the resistor to ground when the pin is held LOW. This current will
appear as additional IDD upsetting any current consumption measurements.
In the same manner, if the resistor is configured as a pull-down and the pin is held HIGH,
current will flow from the power supply through the pin to the VSS pin. While this current
will not be measured as part of IDD, one must be mindful of the 200 mA limiting value
through VSS
.
The pull-up and pull-down resistors are simple resistors and the current is linear with
voltage. The resistance specification for these devices spans from 50 k with a nominal
100 k value. Any current flow through these resistors is additive by the number of pins
held HIGH or LOW and the current can be calculated by Ohm’s law. See Figure 21 for a
graph of supply current versus the number of pull-up resistors.
PCA9554B_PCA9554C
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
14 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
9. Limiting values
Table 11. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
VI
Parameter
Conditions
Min
Max
+6.5
+6.5
+6.5
20
20
20
20
50
Unit
V
supply voltage
0.5
[1]
[1]
input voltage
0.5
V
VO
output voltage
0.5
V
IIK
input clamping current
output clamping current
input/output clamping current
A0, A1, A2, SCL; VI < 0 V
INT; VO < 0 V
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
C
IOK
-
IIOK
P port; VO < 0 V or VO > VDD
SDA; VO < 0 V or VO > VDD
continuous; I/O port
-
-
IOL
LOW-level output current
-
continuous; SDA, INT
continuous; P port
-
25
IOH
HIGH-level output current
supply current
-
25
IDD
-
160
200
200
+150
125
ISS
ground supply current
total power dissipation
storage temperature
-
Ptot
Tstg
Tj(max)
-
65
maximum junction temperature
-
C
[1] The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
10. Recommended operating conditions
Table 12. Operating conditions
Symbol
VDD
Parameter
Conditions
Min
Max
5.5
Unit
V
supply voltage
1.65
0.7 VDD
0.7 VDD
0.5
0.5
-
VIH
HIGH-level input voltage
SCL, SDA
5.5
V
A0, A1, A2, P port
SCL, SDA
5.5
V
VIL
LOW-level input voltage
0.3 VDD
0.3 VDD
10
V
A0, A1, A2, P port
P port
V
IOH
HIGH-level output current
LOW-level output current
ambient temperature
mA
mA
C
IOL
P port
-
25
Tamb
operating in free air
40
+85
11. Thermal characteristics
Table 13. Thermal characteristics
Symbol
Parameter
transient thermal impedance from junction to ambient
Conditions
Max
Unit
K/W
K/W
[1]
Zth(j-a)
HVQFN16 package
TSSOP16 package
53
[1]
108
[1] The package thermal impedance is calculated in accordance with JESD 51-7.
PCA9554B_PCA9554C
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
15 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
12. Static characteristics
Table 14. Static characteristics
Tamb = 40 C to +85 C; VDD = 1.65 V to 5.5 V; unless otherwise specified.
Symbol Parameter
Conditions
Min
1.2
-
Typ[1] Max
Unit
V
VIK
input clamping voltage
power-on reset voltage
LOW-level output current
II = 18 mA
-
-
VPOR
IOL
VI = VDD or VSS; IO = 0 mA
VOL = 0.4 V; VDD = 1.65 V to 5.5 V
SDA
1.1
1.4
V
3
3
-
-
-
mA
mA
INT
15[2]
P port
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
VOL = 0.5 V; VDD = 1.65 V
VOL = 0.7 V; VDD = 1.65 V
VOL = 0.5 V; VDD = 2.3 V
VOL = 0.7 V; VDD = 2.3 V
VOL = 0.5 V; VDD = 3.0 V
VOL = 0.7 V; VDD = 3.0 V
VOL = 0.5 V; VDD = 4.5 V
VOL = 0.7 V; VDD = 4.5 V
P port
8
10
13
10
13
14
19
17
24
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
10
8
10
8
10
8
10
VOH
HIGH-level output voltage
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
IOH = 8 mA; VDD = 1.65 V
1.2
1.1
1.8
1.7
2.6
2.5
4.1
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
I
OH = 10 mA; VDD = 1.65 V
IOH = 8 mA; VDD = 2.3 V
IOH = 10 mA; VDD = 2.3 V
IOH = 8 mA; VDD = 3.0 V
IOH = 10 mA; VDD = 3.0 V
IOH = 8 mA; VDD = 4.75 V
IOH = 10 mA; VDD = 4.75 V
VDD = 1.65 V to 5.5 V
II
input current
SCL, SDA; VI = VDD or VSS
A0, A1, A2; VI = VDD or VSS
P port; VI = VDD; VDD = 1.65 V to 5.5 V
P port; VI = VSS; VDD = 1.65 V to 5.5 V
-
-
-
-
-
-
-
-
0.1
1
A
A
A
A
IIH
IIL
HIGH-level input current
LOW-level input current
1
100
PCA9554B_PCA9554C
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Product data sheet
Rev. 1 — 19 September 2012
16 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
Table 14. Static characteristics …continued
Tamb = 40 C to +85 C; VDD = 1.65 V to 5.5 V; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1] Max
Unit
IDD
supply current
SDA, P port, A0, A1, A2;
VI on SCL, SDA = VDD or VSS
;
VI on P port and A0, A1, A2 = VDD
;
IO = 0 mA; I/O = inputs; fSCL = 400 kHz
VDD = 3.6 V to 5.5 V
-
-
-
10
6.5
4
25
15
9
A
A
A
VDD = 2.3 V to 3.6 V
VDD = 1.65 V to 2.3 V
SCL, SDA, P port, A0, A1, A2;
VI on SCL, SDA = VDD or VSS
;
VI on P port and A0, A1, A2 = VDD
;
IO = 0 mA; I/O = inputs; fSCL = 0 kHz
VDD = 3.6 V to 5.5 V
-
-
-
1.5
1
7
A
A
A
VDD = 2.3 V to 3.6 V
3.2
1.7
VDD = 1.65 V to 2.3 V
0.5
Active mode; P port, A0, A1, A2;
VI on P port and A0, A1, A2 = VDD
;
IO = 0 mA; I/O = inputs; fSCL = 400 kHz,
continuous register read
VDD = 3.6 V to 5.5 V
VDD = 2.3 V to 3.6 V
VDD = 1.65 V to 2.3 V
-
-
-
60
40
20
125
75
A
A
A
45
with pull-ups enabled;
P port, A0, A1, A2;
VI on SCL, SDA = VDD or VSS
VI on P port = VSS
VI on A0, A1, A2 = VDD or VSS
;
;
;
IO = 0 mA; I/O = inputs with pull-up enabled;
fSCL = 0 kHz
VDD = 1.65 V to 5.5 V
-
-
0.55
-
0.75
25
mA
IDD
additional quiescent
supply current
SCL, SDA; one input at VDD 0.6 V, other
A
inputs at VDD or VSS; VDD = 1.65 V to 5.5 V
P port, A0, A1, A2; one input at VDD 0.6 V,
-
-
80
A
other inputs at VDD or VSS
;
VDD = 1.65 V to 5.5 V
Ci
input capacitance
VI = VDD or VSS; VDD = 1.65 V to 5.5 V
VI/O = VDD or VSS; VDD = 1.65 V to 5.5 V
VI/O = VDD or VSS; VDD = 1.65 V to 5.5 V
input/output
-
6
7
pF
pF
pF
k
Cio
input/output capacitance
-
7
8
-
7.5
100
8.5
150
Rpu(int)
internal pull-up resistance
50
[1] For IDD, all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V, 3.6 V or 5 V VDD) and Tamb = 25 C. Except for IDD, the
typical values are at VDD = 3.3 V and Tamb = 25 C.
[2] Typical value for Tamb = 25 C. VOL = 0.4 V and VDD = 3.3 V. Typical value for VDD < 2.5 V, VOL = 0.6 V.
[3] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[4] The total current sourced by all I/Os must be limited to 85 mA.
PCA9554B_PCA9554C
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
17 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
12.1 Typical characteristics
002aah333
002aah334
20
16
12
8
1400
I
DD
I
DD(stb)
(nA)
(μA)
V
= 5.5 V
5.0 V
3.6 V
3.3 V
DD
V
DD
= 5.5 V
5.0 V
3.6 V
3.3 V
2.5 V
2.3 V
1000
800
600
400
200
0
2.5 V
2.3 V
1.8 V
1.65 V
4
V
= 1.8 V
DD
1.65 V
0
−40
−15
10
35
60
85
(°C)
−40
−15
10
35
60
85
(°C)
T
T
amb
amb
Fig 18. Supply current versus ambient temperature
Fig 19. Standby supply current versus
ambient temperature
002aah335
002aah212
20
0.8
I
T
amb
= −40 °C
25 °C
DD
I
DD
(μA)
16
(mA)
0.6
85 °C
12
8
0.4
0.2
0
4
0
1.5
2.5
3.5
4.5
5.5
0
2
4
6
8
V
DD
(V)
number of I/O held LOW
Tamb = 25 C
Fig 20. Supply current versus supply voltage
Fig 21. Supply current versus number of I/O held LOW
PCA9554B_PCA9554C
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
18 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
002aaf578
002aaf579
35
35
I
I
sink
(mA)
sink
(mA)
30
25
20
15
10
5
30
25
20
15
10
5
T
amb
= −40 °C
25 °C
T
amb
= −40 °C
25 °C
85 °C
85 °C
0
0
0
0.1
0.2
0.3
0
0.1
0.2
0.3
V
V
V
(V)
V
V
V
(V)
OL
OL
a. VDD = 1.65 V
b. VDD = 1.8 V
002aaf580
002aaf581
50
60
I
sink
(mA)
I
sink
(mA)
T
= −40 °C
amb
40
30
20
10
0
25 °C
85 °C
T
amb
= −40 °C
25 °C
40
85 °C
20
0
0
0.1
0.2
0.3
0
0.1
0.2
0.3
(V)
(V)
OL
OL
c. VDD = 2.5 V
d. VDD = 3.3 V
002aaf582
002aaf583
70
70
I
I
sink
(mA)
sink
(mA)
T
amb
= −40 °C
T
= −40 °C
25 °C
60
50
40
30
20
10
0
60
50
40
30
20
10
0
amb
25 °C
85 °C
85 °C
0
0.1
0.2
0.3
0
0.1
0.2
0.3
(V)
(V)
OL
OL
e. VDD = 5.0 V
Fig 22. I/O sink current versus LOW-level output voltage
f. VDD = 5.5 V
PCA9554B_PCA9554C
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
19 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
002aah110
002aah111
30
35
I
source
(mA)
I
T
= −40 °C
25 °C
source
(mA)
amb
30
25
20
15
10
5
T
amb
= −40 °C
25 °C
85 °C
20
10
0
85 °C
0
0
0.2
0.4
0.6
(V)
0
0.2
0.4
0.6
(V)
V
− V
V
− V
OH
DD
DD
DD
OH
DD
DD
DD
a. VDD = 1.65 V
b. VDD = 1.8 V
002aah112
002aah113
60
70
I
source
(mA)
I
T
= −40 °C
25 °C
source
(mA)
amb
60
50
40
30
20
10
0
T
= −40 °C
amb
85 °C
25 °C
85 °C
40
20
0
0
0.2
0.4
0.6
(V)
0
0.2
0.4
0.6
(V)
V
− V
V
− V
OH
OH
c. VDD = 2.5 V
d. VDD = 3.3 V
002aah114
002aah115
90
90
I
I
source
(mA)
source
(mA)
T
= −40 °C
25 °C
T
amb
= −40 °C
25 °C
amb
85 °C
85 °C
60
60
30
0
30
0
0
0.2
0.4
0.6
(V)
0
0.2
0.4
0.6
(V)
V
− V
V
− V
OH
OH
e. VDD = 5.0 V
Fig 23. I/O source current versus HIGH-level output voltage
f. VDD = 5.5 V
PCA9554B_PCA9554C
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
20 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
002aah056
002aah343
120
200
V
OL
V
− V
(mV)
DD
OH
(mV)
100
80
60
40
20
0
160
(1)
(2)
(3)
120
80
40
0
V
= 1.8 V
5 V
DD
(4)
−40
−15
10
35
60
85
(°C)
−40
−15
10
35
60
85
(°C)
T
T
amb
amb
(1) VDD = 1.8 V; Isink = 10 mA
(2) VDD = 5 V; Isink = 10 mA
(3) VDD = 1.8 V; Isink = 1 mA
(4) VDD = 5 V; Isink = 1 mA
Isource = 10 mA
Fig 24. LOW-level output voltage versus temperature
Fig 25. I/O high voltage versus temperature
PCA9554B_PCA9554C
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Product data sheet
Rev. 1 — 19 September 2012
21 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
13. Dynamic characteristics
Table 15. I2C-bus interface timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 26.
Symbol Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Unit
Min
0
Max
100
-
Min
0
Max
fSCL
tHIGH
tLOW
tSP
SCL clock frequency
400 kHz
HIGH period of the SCL clock
LOW period of the SCL clock
4
0.6
1.3
0
-
-
s
s
4.7
0
-
pulse width of spikes that must
be suppressed by the input filter
50
50 ns
tSU;DAT
data set-up time
250
-
-
100
0
-
-
ns
ns
tHD;DAT
data hold time
0
-
tr
tf
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
1000
300
20
300 ns
300 ns
-
20
(VDD / 5.5 V)
tBUF
bus free time between a STOP and
START condition
4.7
4.7
-
-
1.3
0.6
-
-
s
s
tSU;STA
set-up time for a repeated START
condition
tHD;STA
tSU;STO
tVD;DAT
hold time (repeated) START condition
set-up time for STOP condition
data valid time
4
4
-
-
-
0.6
0.6
-
-
-
s
s
SCL LOW to SDA
output valid
3.45
0.9 s
tVD;ACK
data valid acknowledge time
ACK signal from
SCL LOW to SDA
(out) LOW
-
3.45
-
0.9 s
Table 16. Switching characteristics
Over recommended operating free air temperature range; CL 100 pF; unless otherwise specified. See Figure 26.
Symbol Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Unit
Min
Max
Min
Max
tv(INT)
trst(INT)
tv(Q)
valid time on pin INT
from P port to INT
from SCL to INT
-
1
1
-
1
s
s
ns
ns
ns
reset time on pin INT
data output valid time
data input set-up time
data input hold time
-
-
-
-
1
from SCL to P port
from P port to SCL
from P port to SCL
400
-
400
tsu(D)
th(D)
0
0
-
-
300
-
300
PCA9554B_PCA9554C
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Product data sheet
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22 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
14. Parameter measurement information
V
DD
R
= 1 kΩ
L
SDA
DUT
C
= 50 pF
L
002aaf848
a. SDA load configuration
(1)
two bytes for read Input port register
STOP
condition condition
(P) (S)
START
Address
Bit 7
Data
Data
Bit 0
STOP
condition
(P)
R/W
Bit 0
Address
Bit 1
ACK
(A)
Bit 7
(MSB)
(MSB)
(LSB)
(LSB)
002aag952
b. Transaction format
t
HIGH
t
t
SP
LOW
0.7 × V
0.3 × V
DD
DD
SCL
t
t
r
VD;DAT
t
t
SU;STO
BUF
t
f
t
t
SU;STA
VD;ACK
t
f(o)
0.7 × V
0.3 × V
DD
DD
SDA
t
f
t
r
t
VD;ACK
t
t
t
HD;DAT
HD;STA
SU;DAT
repeat START condition
STOP condition
002aag804
c. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
All parameters and waveforms are not applicable to all devices.
Byte 1 = I2C-bus address; Byte 2, byte 3 = P port data.
(1) See Figure 9.
Fig 26. I2C-bus interface load circuit and voltage waveforms
PCA9554B_PCA9554C
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Product data sheet
Rev. 1 — 19 September 2012
23 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
V
DD
R
= 4.7 kΩ
L
INT
DUT
C
= 100 pF
L
002aah069
a. Interrupt load configuration
acknowledge
from slave
acknowledge
from slave
no acknowledge
from master
START condition
slave address
R/W
STOP
8 bits (one data byte)
from port
condition
(1)
data from port
DATA 2
SDA
S
0
1
0
0
A2 A1 A0
1
A
DATA 1
A
1
P
SCL
1
2
3
4
5
6
7
8
9
B
B
t
t
rst(INT)
rst(INT)
INT
A
A
t
v(INT)
t
su(D)
data into
port
ADDRESS
DATA 1
SCL
DATA 2
0.7 × V
0.3 × V
DD
DD
INT
0.5 × V
R/W
A
DD
t
v(INT)
t
rst(INT)
Pn
0.5 × V
INT
0.5 × V
DD
DD
View A - A
View B - B
002aah130
b. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
All parameters and waveforms are not applicable to all devices.
(1) PCA9554B address shown. Address for PCA9554C is 0111,A2,A1,A0.
Fig 27. Interrupt load circuit and voltage waveforms
PCA9554B_PCA9554C
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Product data sheet
Rev. 1 — 19 September 2012
24 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
500 Ω
Pn
DUT
2 × V
DD
C
= 50 pF
500 Ω
L
002aag805
a. P port load configuration
0.7 × V
0.3 × V
DD
DD
SCL
P0
A
P7
SDA
Pn
t
v(Q)
last stable bit
unstable
data
002aag806
b. Write mode (R/W = 0)
0.7 × V
0.3 × V
DD
DD
SCL
P0
A
P7
t
t
h(D)
su(D)
Pn
002aag807
c. Read mode (R/W = 1)
CL includes probe and jig capacitance.
tv(Q) is measured from 0.7 VDD on SCL to 50 % I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Fig 28. P port load circuit and voltage waveforms
PCA9554B_PCA9554C
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Product data sheet
Rev. 1 — 19 September 2012
25 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
15. Package outline
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 29. Package outline SOT403-1 (TSSOP16)
PCA9554B_PCA9554C
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Product data sheet
Rev. 1 — 19 September 2012
26 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3 x 3 x 0.85 mm
SOT758-1
B
A
D
terminal 1
index area
A
E
A
1
c
detail X
e
C
1
1/2 e
y
y
v
M
C
A B
C
1
e
b
w
M
C
5
8
L
4
9
e
e
E
2
h
1/2 e
12
1
16
13
terminal 1
index area
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
e
2
D
D
E
L
y
1
v
w
y
1
h
1
h
max.
0.05 0.30
0.00 0.18
3.1 1.75
2.9 1.45
3.1
2.9
1.75
1.45
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
1.5
1.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-03-25
02-10-21
SOT758-1
- - -
MO-220
- - -
Fig 30. Package outline SOT758-1 (HVQFN16)
PCA9554B_PCA9554C
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Product data sheet
Rev. 1 — 19 September 2012
27 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
PCA9554B_PCA9554C
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Product data sheet
Rev. 1 — 19 September 2012
28 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 31) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 17 and 18
Table 17. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
235
350
220
< 2.5
2.5
220
220
Table 18. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 31.
PCA9554B_PCA9554C
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Product data sheet
Rev. 1 — 19 September 2012
29 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 31. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCA9554B_PCA9554C
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Product data sheet
Rev. 1 — 19 September 2012
30 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
18. Soldering: PCB footprints
Footprint information for reflow soldering of TSSOP16 package
SOT403-1
Hx
Gx
P2
(0.125)
(0.125)
Hy Gy
By Ay
C
D2 (4x)
P1
D1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650 0.750 7.200 4.500 1.350 0.400 0.600 5.600 5.300 5.800 7.450
sot403-1_fr
Fig 32. PCB footprint for SOT403-1 (TSSOP16); reflow soldering
PCA9554B_PCA9554C
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
31 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
Footprint information for reflow soldering of HVQFN16 package
SOT758-1
Hx
Gx
P
D
0.025
0.025
C
(0.105)
SPx
nSPx
SPy
Hy
Gy
nSPy
SLy By
Ay
SPx tot
SLx
Bx
Ax
solder land
solder paste deposit
solder land plus solder paste
occupied area
nSPx nSPy
2
2
Dimensions in mm
P
Ax
Ay
Bx
By
C
D
SLx
SLy SPx tot SPy tot SPx
1.50 0.90 0.90 0.30
SPy
0.30
Gx
Gy
3.30
Hx
Hy
0.50
4.00
4.00
2.20
2.20
0.90
0.24
1.50
3.30
4.25
4.25
12-03-07
12-03-08
Issue date
sot758-1_fr
Fig 33. PCB footprint for SOT758-1 (HVQFN16); reflow soldering
PCA9554B_PCA9554C
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
32 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
19. Abbreviations
Table 19. Abbreviations
Acronym
ACPI
CBT
Description
Advanced Configuration and Power Interface
Cross-Bar Technology
Charged-Device Model
Complementary Metal-Oxide Semiconductor
Device Under Test
CDM
CMOS
DUT
ESD
FET
ElectroStatic Discharge
Field-Effect Transistor
Flip-Flop
FF
GPIO
HBM
I2C-bus
I/O
General Purpose Input/Output
Human Body Model
Inter-Integrated Circuit bus
Input/Output
LED
Light Emitting Diode
LP
Low-Pass
LSB
Least Significant Bit
MSB
PCB
POR
SCR
SMBus
Most Significant Bit
Printed-Circuit Board
Power-On Reset
Silicon Controlled Rectifier
System Management Bus
20. Revision history
Table 20. Revision history
Document ID
Release date
20120919
Data sheet status
Change notice Supersedes
PCA9554B_PCA9554C v.1
Product data sheet
-
-
PCA9554B_PCA9554C
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Product data sheet
Rev. 1 — 19 September 2012
33 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
21. Legal information
21.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
21.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
PCA9554B_PCA9554C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
34 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
I2C-bus — logo is a trademark of NXP B.V.
22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9554B_PCA9554C
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 19 September 2012
35 of 36
PCA9554B; PCA9554C
NXP Semiconductors
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
23. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
19
20
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision history . . . . . . . . . . . . . . . . . . . . . . . 33
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
3.1
4
21
Legal information . . . . . . . . . . . . . . . . . . . . . . 34
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 34
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 35
21.1
21.2
21.3
21.4
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
22
23
Contact information . . . . . . . . . . . . . . . . . . . . 35
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6
6.1
6.2
6.3
Functional description . . . . . . . . . . . . . . . . . . . 5
Device address. . . . . . . . . . . . . . . . . . . . . . . . . 5
Pointer register and command byte . . . . . . . . . 5
Interface definition . . . . . . . . . . . . . . . . . . . . . . 6
Register descriptions . . . . . . . . . . . . . . . . . . . . 6
Input port register (00h) . . . . . . . . . . . . . . . . . . 6
Output port register (01h) . . . . . . . . . . . . . . . . . 6
Polarity inversion register (02h) . . . . . . . . . . . . 6
Configuration register (03h) . . . . . . . . . . . . . . . 7
I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8
Interrupt output (INT) . . . . . . . . . . . . . . . . . . . . 8
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.5
6.6
6.7
7
7.1
7.2
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 9
Write commands. . . . . . . . . . . . . . . . . . . . . . . . 9
Read commands . . . . . . . . . . . . . . . . . . . . . . 10
8
8.1
Application design-in information . . . . . . . . . 11
Minimizing IDD when the I/Os are used to
control LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-on reset requirements . . . . . . . . . . . . . 12
Device current consumption with internal
8.2
8.3
pull-up and pull-down resistors. . . . . . . . . . . . 14
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15
Recommended operating conditions. . . . . . . 15
Thermal characteristics . . . . . . . . . . . . . . . . . 15
Static characteristics. . . . . . . . . . . . . . . . . . . . 16
Typical characteristics . . . . . . . . . . . . . . . . . . 18
Dynamic characteristics . . . . . . . . . . . . . . . . . 22
Parameter measurement information . . . . . . 23
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26
Handling information. . . . . . . . . . . . . . . . . . . . 28
10
11
12
12.1
13
14
15
16
17
Soldering of SMD packages . . . . . . . . . . . . . . 28
Introduction to soldering . . . . . . . . . . . . . . . . . 28
Wave and reflow soldering . . . . . . . . . . . . . . . 28
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 28
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 29
17.1
17.2
17.3
17.4
18
Soldering: PCB footprints. . . . . . . . . . . . . . . . 31
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 19 September 2012
Document identifier: PCA9554B_PCA9554C
相关型号：
PCA9554BPWJ
PCA9554B; PCA9554C - Low-voltage 8-bit I²C-bus and SMBus low power I/O port with interrupt, weak pull-up TSSOP 16-Pin
NXP
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