PCA9557D_技术文档

INTEGRATED CIRCUITS

PCA9557

8-bit I²C and SMBus I/0 port with reset

Product data

2001 Dec 12

File under Integrated Circuits — ICL03

Philips

Semiconductors

Philips Semiconductors

Product data

8-bit I²C and SMBus I/0 port with reset

PCA9557

The system master can also invert the PCA9557 inputs by writing to

the active HIGH polarity inversion register.

Finally, the system master can reset the PCA9557 in the event of a

timeout by asserting a LOW in the reset input.

The power-on reset puts the registers in their default state and

2

initializes the I C/SMBus state machine. The RESET pin causes the

same reset/initialization to occur without depowering the part.

PIN CONFIGURATION

FEATURES

V

1

2

3

4

5

6

7

8

• Lower voltage, higher performance migration path for the

16

DD

SCL

SDA

PCA9556

15 RESET

• 8 general purpose input/output expander/collector

• Input/output configuration register

I/O7

14

A0

A1

I/O6

13

I/O5

I/O4

A2

12

11

10

9

• Active HIGH polarity inversion register

2

I/O0

I/O1

• I C and SMBus interface logic

I/O3

I/O2

• Internal power-on reset

• Noise filter on SCL/SDA inputs

• Active LOW reset input

V

SS

su01045

Figure 1. Pin configuration

2

• 3 address pins allowing up to 8 devices on the I C/SMBus

• High impedance open drain on I/O0

• No glitch on power-up

• Power-up with all channels configured as inputs

• Low standby current

• Operating power supply voltage range of 2.3 V to 5.5 V

• 5 V tolerant inputs/outputs

• 0 to 400 kHz clock frequency

PIN DESCRIPTION

NUMBER

SYMBOL

FUNCTION

Serial clock line

1

2

SCL

SDA

A0

Serial data line

Address input 0

Address input 1

Address input 2

I/O0 (open drain)

I/O1

3

4

A1

5

A2

• ESD protection exceeds 2000 V HBM per JESD22-A114,

6

I/O0

I/O1

200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

7

• Latch-up testing is done to JESDEC Standard JESD78 which

8

V

SS

Supply ground

I/O2

exceeds 100 mA

9

I/O2

I/O3

• Package offer: SO 16, TSSOP 16

10

11

12

13

14

15

16

I/O3

I/O4

DESCRIPTION

The PCA9557 is a silicon CMOS circuit which provides parallel

input/output expansion for SMBus and I C applications. The

I/O5

2

I/O6

PCA9557 consists of an 8-bit input port register, 8-bit output port

2

I/O7

register, and an I C/SMBus interface. It has low current

consumption and a high impedance open drain output pin, I/O0.

RESET

Active low reset input

Supply voltage

The system master can enable the PCA9557’s I/O as either input or

output by writing to the configuration register.

V

DD

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

DRAWING NUMBER

16-Pin Plastic SO (narrow)

16-Pin Plastic TSSOP

–40 to +85 °C

PCA9557D

SOT109-1

SOT403-1

PCA9557PW

Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.

2

SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I C patent.

2

I C is a trademark of Philips Semiconductors Corporation.

2

2001 Dec 12

853-2308 27449

Philips Semiconductors

Product data

8-bit I²C and SMBus I/0 port with reset

PCA9557

BLOCK DIAGRAM

PCA9557

A0

A1

A2

I/O0

I/O1

I/O2

I/O3

SCL

INPUT

FILTER

INPUT/

OUTPUT

PORTS

8-BIT

2

I C/SMBus

CONTROL

SDA

I/O4

I/O5

WRITE pulse

READ pulse

I/O6

I/O7

V

DD

V

SS

POWER-ON

RESET

SW00827

Figure 2. Block diagram

SYSTEM DIAGRAM

Input Port

Polarity Inversion

Q7

Configuration

Q7

Output Port

Q7

V

= 16

CC

1.1 KΩ

GND = 8

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

6

Q6

Q5

Q4

Q3

Q2

Q1

Q0

Q6

Q5

Q4

Q3

Q2

Q1

Q0

Q6

Q5

Q4

Q3

Q2

Q1

Q0

7

1.1 KΩ

1.6 KΩ

RESET

15

9

2

I C/SMBus

Interface

logic

SCL

SDA

1

2

5

4

3

10

11

12

13

14

1.6 KΩ

1.1 KΩ

or

A2

1.1 KΩ

or

A1

A0

SW00794

Figure 3. System diagram

3

2001 Dec 12

Philips Semiconductors

Product data

8-bit I²C and SMBus I/0 port with reset

PCA9557

SIMPLIFIED SCHEMATIC OF I/O0

DATA FROM

SHIFT REGISTER

CONFIGURATION

REGISTER

DATA FROM

SHIFT REGISTER

Q

D

OUTPUT PORT

REGISTER DATA

FF

WRITE

CONFIGURATION

PULSE

D

Q

C

K

FF

I/O0

WRITE PULSE

C

K

ESD PROTECTION DIODE

OUTPUT

PORT

REGISTER

V

SS

INPUT PORT

REGISTER

INPUT PORT

REGISTER DATA

D

Q

FF

Q

C

K

READ PULSE

DATA FROM

SHIFT REGISTER

POLARITY

REGISTER DATA

D

Q

FF

WRITE POLARITY

PULSE

C

K

POLARITY

INVERSION

REGISTER

SW00795

NOTE: On power–up or reset, all registers return to default values.

Figure 4. Simplified schematic of I/O0

4

2001 Dec 12

Philips Semiconductors

Product data

8-bit I²C and SMBus I/0 port with reset

PCA9557

SIMPLIFIED SCHEMATIC OF I/O1 TO I/O7

DATA FROM

SHIFT REGISTER

OUTPUT PORT

REGISTER DATA

CONFIGURATION

REGISTER

V

DD

DATA FROM

SHIFT REGISTER

Q

D

ESD PROTECTION DIODE

FF

WRITE

CONFIGURATION

PULSE

D

Q

C

K

FF

I/O1 TO I/O7

WRITE PULSE

C

K

ESD PROTECTION DIODE

OUTPUT

PORT

REGISTER

V

SS

INPUT PORT

REGISTER

INPUT PORT

REGISTER DATA

D

Q

FF

Q

C

K

READ PULSE

DATA FROM

SHIFT REGISTER

POLARITY

REGISTER DATA

D

Q

FF

WRITE POLARITY

PULSE

C

K

POLARITY

INVERSION

REGISTER

SW00796

NOTE: On power–up or reset, all registers return to default values.

Figure 5. Simplified schematic of I/O1 to I/O7

5

2001 Dec 12

Philips Semiconductors

Product data

8-bit I²C and SMBus I/0 port with reset

PCA9557

DEVICE ADDRESS

Register 1 – Output Port Register

Following a START condition the bus master must output the

address of the slave it is accessing. The address of the PCA9557 is

shown in Figure 6. To conserve power, no internal pullup resistors

are incorporated on the hardware selectable address pins and they

must be pulled HIGH or LOW.

bit

O7

0

O6

0

O5

0

O4

0

O3

0

O2

0

O1

0

O0

0

default

This register reflects the outgoing logic levels of the pins defined as

outputs by the Configuration Register. Bit values in this register have

no effect on pins defined as inputs. In turn, reads from this register

reflect the value that is in the flip-flop controlling the output selection,

NOT the actual pin value.

slave address

0

1

A2 A1 A0 R/W

programmable

Register 2 – Polarity Inversion Register

bit

N7

1

N6

1

N5

1

N4

1

N3

0

N2

0

N1

0

N0

0

fixed

default

su01048

Figure 6. PCA9557 address

The last bit of the slave address defines the operation to be

performed. When set to logic 1 a read is selected while a logic 0

selects a write operation.

This register enables polarity inversion of pins defined as inputs by

the Configuration Register. If a bit in this register is set (written

with ‘1’), the corresponding port pin’s polarity is inverted. If a bit in

this register is cleared (written with a ‘0’), the corresponding port

pin’s original polarity is retained.

CONTROL REGISTER

Register 3 – Configuration Register

Following the successful acknowledgement of the slave address,

the bus master will send a byte to the PCA9557, which will be stored

in the control register. This register can be written and read via the

bit

C7

1

C6

1

C5

1

C4

1

C3

1

C2

1

C1

1

C0

1

2

default

I C bus.

This register configures the directions of the I/O pins. If a bit in this

register is set, the corresponding port pin is enabled as an input with

high impedance output driver. If a bit in this register is cleared, the

corresponding port pin is enabled as an output.

0

D1

D0

POWER-ON RESET

SW00953

When power is applied to V , an internal power-on reset holds the

DD

PCA9557 in a reset state until V has reached V

. At that point,

DD

POR

Figure 7. Control Register

the reset condition is released and the PCA9557 registers and

I C/SMBus state machine will initialize to their default states.

2

For a power reset cycle, V must be set to 0 V, then ramped back

to the operating voltage.

DD

REGISTER DEFINITION

D1

0

D0

0

NAME

Register 0

Register 1

TYPE

FUNCTION

Read

Input port register

RESET INPUT

A reset can be accomplished by holding the RESET pin LOW for a

0

1

Read/Write Output port register

2

minimum of t . The PCA9557 registers and SMBus/I C state

W

Polarity inversion

Read/Write

1

0

1

Register 2

Register 3

machine will be held in their default state until the RESET input is

once again HIGH. This input typically requires a pull-up to V

register

CC.

Configuration

Read/Write

register

REGISTER DESCRIPTION

Register 0 – Input Port Register

I7

I6

I5

I4

I3

I2

I1

I0

This register is an read-only port. It reflects the incoming logic levels

of the pins, regardless of whether the pin is defined as an input or an

output by the Configuration Register. Writes to this register have no

effect.

6

2001 Dec 12

Philips Semiconductors

Product data

8-bit I²C and SMBus I/0 port with reset

PCA9557

2

CHARACTERISTICS OF THE I C-BUS

Start and stop conditions

2

The I C-bus is for 2-way, 2-line communication between different ICs

Both data and clock lines remain HIGH when the bus is not busy. A

HIGH-to-LOW transition of the data line, while the clock is HIGH is

defined as the start condition (S). A LOW-to-HIGH transition of the

data line while the clock is HIGH is defined as the stop condition (P)

(see Figure 9).

or modules. The two lines are a serial data line (SDA) and a serial

clock line (SCL). Both lines must be connected to a positive supply

via a pull-up resistor when connected to the output stages of a device.

Data transfer may be initiated only when the bus is not busy.

Bit transfer

System configuration

One data bit is transferred during each clock pulse. The data on the

SDA line must remain stable during the HIGH period of the clock

pulse as changes in the data line at this time will be interpreted as

control signals (see Figure 8).

A device generating a message is a ‘transmitter’, a device receiving

is the ‘receiver’. The device that controls the message is the

‘master’ and the devices which are controlled by the master are the

‘slaves’ (see Figure 10).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

SW00363

Figure 8. Bit transfer

SDA

SCL

S

P

START condition

STOP condition

SW00365

Figure 9. Definition of start and stop conditions

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

2

SLAVE

RECEIVER

I C

MASTER

TRANSMITTER

MULTIPLEXER

SLAVE

SW00366

Figure 10. System configuration

7

2001 Dec 12

Philips Semiconductors

Product data

8-bit I²C and SMBus I/0 port with reset

PCA9557

Acknowledge

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits

is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an

extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an

acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock

pulse, set-up and hold times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of

the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.

DATA OUTPUT

BY TRANSMITTER

not acknowledge

DATA OUTPUT

BY RECEIVER

acknowledge

SCL FROM

MASTER

1

2

8

9

S

clock pulse for

acknowledgement

START condition

SW00368

2

Figure 11. Acknowledgement on the I C-bus

8

2001 Dec 12

Philips Semiconductors

Product data

8-bit I²C and SMBus I/0 port with reset

PCA9557

Bus Transactions

Data is transmitted to the PCA9557 registers using Write Byte transfers (see Figures 12 and 13). Data is read from the PCA9557 registers using

Read and Receive Byte transfers (see Figures 14 and 15).

1

2

3

4

5

6

7

8

9

SCL

SDA

command byte

slave address

data to port

DATA 1

0

1

A2 A1 A0

S

0

A

0

1

A

P

start condition

R/W acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

WRITE TO

PORT

DATA OUT

FROM PORT

DATA 1 VALID

t

pv

SW00797

Figure 12. WRITE to output port register

1

2

3

4

5

6

7

8

0

9

SCL

SDA

command byte

slave address

data to register

DATA

0

1

A2 A1 A0

S

A

P

0

1

1/0

start condition

R/W acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

SW00798

Figure 13. WRITE to I/O configuration or polarity inversion registers

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

acknowledge

from master

slave address

data from register

1

A2 A1

1

A2 A1

A0

0

1

A0

0

1

COMMAND BYTE

DATA

S

0

A

S

A

first byte

R/W

at this moment master-transmitter

becomes master-receiver and

slave-receiver becomes

slave-transmitter

no acknowledge

from master

data from register

NA

P

DATA

last byte

su01052

Figure 14. READ from register

9

2001 Dec 12

Philips Semiconductors

Product data

8-bit I²C and SMBus I/0 port with reset

PCA9557

slave address

data from port

DATA 1

data from port

DATA 4

SDA

0

1

A2 A1 A0

S

1

A

NA

P

start condition

R/W acknowledge

from slave

acknowledge

from master

no acknowledge

from master

stop

condition

READ FROM

PORT

DATA INTO

PORT

DATA 2

DATA 3

DATA 4

t

ph

t

ps

SW00799

NOTES:

1. This figure assumes the command byte has previously been programmed with 00h.

2. Transfer of data can be stopped at any moment by a stop condition. When this occurs, data present at the last acknowledge phase is valid

(output mode). Input data is lost.

Figure 15. READ input port register

TYPICAL APPLICATION

V

DD

2 kΩ

V

1.6 kΩ

1.1 kΩ

2 kΩ

DD

V

DD

SUBSYSTEM 1

(e.g. temp sensor)

SCL

SDA

SCL

SDA

I/0

0

MASTER

INT

1

CONTROLLER

RESET

I/0

2

RESET

GND

3

PCA9557

SUBSYSTEM 2

(e.g. counter)

I/0

4

I/0

5

I/0

6

I/0

7

A

B

A2

Controlled Switch

(e.g. CBT device)

ENABLE

A1

A0

GND

ALARM

SUBSYSTEM 3

(e.g. alarm

system)

NOTE: Device address configured as 0011100 for this example

I/0 , I/0 , I/0 , configured as outputs

0

1

2

I/0 , I/0 , I/0 , configured as inputs

3

4

5

I/0 , I/0 , are not used and have to be configured as outputs

06

7

V

DD

SW00993

Figure 16. Typical application

10

2001 Dec 12

Philips Semiconductors

Product data

8-bit I²C and SMBus I/0 port with reset

PCA9557

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNIT

V

DD

DC supply voltage

DC input voltage

DC input current

–0.5

+6

5.5

V

I

V

– 0.5

V

SS

I

—

± 20

mA

Maximum allowed input current through protection

diode (I/O1 – I/O7)

I

V ≥ V or V ≤ V

SS

±400

µA

IHL(max)

I

DD

I

V

DC voltage on an I/O as an input other than I/O0

DC voltage on I/O0 as an input

V

– 0.5

5.5

V

I/O

SS

V

I/O0

– 0.5

SS

—

+400

–20

± 50

85

µA

mA

mW

°C

I

DC input current on I/O0

I/O0

—

I

DC output current on an I/O

DC supply current

I/O

I

—

DD

I

DC supply current

—

100

200

+150

+85

SS

P

Total power dissipation

Storage temperature range

Operating ambient temperature

—

tot

T

–65

–40

stg

T

°C

amb

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take

precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”Handling MOS devices”.

11

2001 Dec 12

Philips Semiconductors

Product data

8-bit I²C and SMBus I/0 port with reset

PCA9557

DC CHARACTERISTICS

V

= 2.3 to 5.5 V; V = 0 V; T

= –40 to +85 °C; unless otherwise specified.

DD

SS

amb

LIMITS

TYP

SYMBOL

Supplies

PARAMETER

CONDITIONS

UNIT

MAX

MIN

V

Supply voltage

Supply current

2.3

—

5.5

1

V

DD

Operating mode; V = 3.6 V; no load;

DD

V = V or V

;

I

µA

I

DD

SS

DD

stbl

f

= 100 kHz

SCL

Standby mode; V = 5.5 V; no load;

DD

I

Standby current

—

1

µA

V

V = V ; f

= 0 kHz; I/O = inputs

I

SS SCL

Standby mode; V = 5.5 V; no load;

DD

I

Standby current

stbh

V = V ; f

= 0 kHz; I/O = inputs

I

DD SCL

No load; Temp = 25 °C

V

POR

Power-on reset voltage

1.65

—

V = V or V

I

DD

SS

Input SCL; input/output SDA

V

LOW level input voltage

HIGH level input voltage

LOW level output current

Leakage current

–0.5

—

6

0.3 V

V

IL

IH

DD

V

0.7 V

3

5.5

—

DD

I

OL

V

= 0.4 V

mA

µA

pF

OL

I

L

V = V or V

I

–1

+1

10

DD

SS

C

Input capacitance

V = V

I

—

I

I/Os

V

LOW level input voltage

–0.5

2.0

8

—

0.8

5.5

—

1

V

IL

V

IH

HIGH level input voltage

I

OL

LOW level output current

V

OL

V

OH

V

OH

V

OH

V

DD

= 0.55 V; note 1

= 2.4 V; note 2

= 4.6 V

10

—

mA

HIGH level output current except I/O0

4

I

—

OH

HIGH level output current on I/O0

µA

= 3.3 V

—

1

I

L

Input leakage current

Input capacitance

Output capacitance

= 5.5 V, V = V

SS

—

–100

5

µA

pF

I

C

3.7

I

C

5

O

Select Inputs A0, A1, A2, and RESET

V

LOW level input voltage

HIGH level input voltage

Input leakage current

–0.5

2.0

–1

—

0.8

5.5

1

V

IL

IH

LI

V

I

µA

NOTES:

1. The total amount sunk by all I/Os must be limited to 100 mA and 25 mA per bit.

2. The total current sourced by all I/Os must be limited to 85 mA and 20 mA per bit.

12

2001 Dec 12

Philips Semiconductors

Product data

8-bit I²C and SMBus I/0 port with reset

PCA9557

AC SPECIFICATIONS

STANDARD MODE

FAST MODE

I C BUS

2

I C BUS

SYMBOL

PARAMETER

UNITS

MIN

0

MAX

100

—

MIN

MAX

f

Operating frequency

0

400

—

kHz

µs

ns

µs

ns

µs

ns

SCL

t

Bus free time between STOP and START conditions

Hold time after (repeated) START condition

Repeated START condition setup time

Setup time for STOP condition

4.7

4.0

4.7

4.0

0

1.3

BUF

t

—

0.6

—

HD;STA

t

—

0.6

—

SU;STA

SU;STO

t

—

0.6

—

t

Data in hold time

—

0

—

HD;DAT

VD;ACK

2

t

Valid time for ACK condition

—

1

—

0.9

—

3

t

Data out valid time

—

1

VD;DAT

Data setup time

250

4.7

4.0

—

100

SU;DAT

t

Clock LOW period

Clock HIGH period

Clock/Data fall time

Clock/Data rise time

—

1.3

—

LOW

t

—

0.6

—

HIGH

1

t

F

300

1000

50

20 + 0.1 C

—

300

50

b

t

R

—

b

t

Pulse width of spikes that must be suppressed by the

input filters

—

SP

Port Timing

t

Output data valid I/O0

Output data valid I/O1 – I/O7

Input data setup time

Input data hold time

—

250

200

—

250

200

—

ns

PV

PS

PH

0

t

200

—

200

—

Reset

t

Reset pulse width

Reset recovery time

Time to reset

4

0

—

4

0

—

ns

W

t

REC

t

400

RESET

NOTES:

1. C = total capacitance of one bus line in pF.

b

2. t

3. t

= time for Acknowledgement signal from SCL low to SDA (out) low.

= minimum time for SDA data out to be valid following SCL low.

VD;ACK

VD;DAT

SDA

SCL

t

R

t

F

t

SP

HD;STA

t

LOW

BUF

t

SU;STO

HD;STA

SU;STA

t

SU;DAT

HD;DAT

HIGH

P

S

Sr

P

SU00645

2

Figure 17. Definition of timing on the I C-bus

13

2001 Dec 12

Philips Semiconductors

Product data

8-bit I²C and SMBus I/0 port with reset

PCA9557

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

14

2001 Dec 12

Philips Semiconductors

Product data

8-bit I²C and SMBus I/0 port with reset

PCA9557

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

15

2001 Dec 12

Philips Semiconductors

Product data

8-bit I²C and SMBus I/0 port with reset

PCA9557

2

Purchase of Philips I C components conveys a license under the Philips’ I C patent

2

to use the components in the I C system provided the system conforms to the

I C specifications defined by Philips. This specification can be ordered using the

2

code 9398 393 40011.

Data sheet status

Product

status

Definitions

[1]

Data sheet status

[2]

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be

published at a later date. Philips Semiconductors reserves the right to change the specification

without notice, in order to improve the design and supply the best possible product.

Product data

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply.

Changes will be communicated according to the Customer Product/Process Change Notification

(CPCN) procedure SNW-SQ-650A.

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Koninklijke Philips Electronics N.V. 2001

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 12-01

9397 750 09217

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

16

2001 Dec 12


型号：	PCA9557D
厂家：	NXP
描述：	8-bit I2C and SMBus I/0 port with reset 8位I2C和SMBus I / O端口，复位并行IO端口微控制器和处理器外围集成电路光电二极管
文件：	总16页 (文件大小：128K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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