PCA9626B_技术文档

PCA9626

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

Rev. 02 — 31 August 2009

Product data sheet

1. General description

The PCA9626 is an I²C-bus controlled 24-bit LED driver optimized for voltage switch

dimming and blinking 100 mA Red/Green/Blue/Amber (RGBA) LEDs. Each LED output

has its own 8-bit resolution (256 steps) ﬁxed frequency individual PWM controller that

operates at 97 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the

LED to be set to a speciﬁc brightness value. An additional 8-bit resolution (256 steps)

group PWM controller has both a ﬁxed frequency of 190 Hz and an adjustable frequency

between 24 Hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 %

to 99.6 % that is used to either dim or blink all LEDs with the same value.

Each LED output can be off, on (no PWM control), set at its individual PWM controller

value or at both individual and group PWM controller values. The PCA9626 operates with

a supply voltage range of 2.3 V to 5.5 V and the 100 mA open-drain outputs allow

voltages up to 40 V.

The PCA9626 is one of the ﬁrst LED controller devices in a new Fast-mode Plus (Fm+)

family. Fm+ devices offer higher frequency (up to 1 MHz) and more densely populated bus

operation (up to 4000 pF).

The active LOW Output Enable input pin (OE) blinks all the LED outputs and can be used

to externally PWM the outputs, which is useful when multiple devices need to be dimmed

or blinked together without using software control.

Software programmable LED Group and three Sub Call I²C-bus addresses allow all or

deﬁned groups of PCA9626 devices to respond to a common I²C-bus address, allowing

for example, all red LEDs to be turned on or off at the same time or marquee chasing

effect, thus minimizing I²C-bus commands. Seven hardware address pins allow up to

126 devices on the same bus.

The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9626

through the I²C-bus, identical to the Power-On Reset (POR) that initializes the registers to

their default state causing the output NAND FETs to be OFF (LED off). This allows an

easy and quick way to reconﬁgure all device registers to the same condition.

In addition to these features found in PCA9633, PCA9634, PCA9635, PCA9622 and

PCA9624, a new feature to control LED output pattern is incorporated in the PCA9626. A

new control byte called ‘Chase Byte’ allows enabling or disabling of selective LED outputs

depending on the value of the Chase Byte. This feature greatly reduces the number of

bytes to be sent to the PCA9626 when repetitive patterns need to be displayed as in

creating a marquee chasing effect.

If the PCA9626 on-chip 100 mA NAND FETs do not provide enough current or voltage to

drive the LEDs, then the PCA9635 and the PCA9635 with larger current or higher voltage

external drivers can be used.

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

2. Features

I 24 LED drivers. Each output programmable at:

N Off

N On

N Programmable LED brightness

N Programmable group dimming/blinking mixed with individual LED brightness

I 1 MHz Fast-mode Plus compatible I²C-bus interface with 30 mA high drive capability

on SDA output for driving high capacitive buses

I 256-step (8-bit) linear programmable brightness per LED output varying from fully off

(default) to maximum brightness using a 97 kHz PWM signal

I 256-step group brightness control allows general dimming (using a 190 Hz PWM

signal) from fully off to maximum brightness (default)

I 256-step group blinking with frequency programmable from 24 Hz to 10.73 s and

duty cycle from 0 % to 99.6 %

I 24 open-drain outputs can sink between 0 mA to 100 mA and are tolerant to a

maximum off state voltage of 40 V. No input function.

I Output state change programmable on the Acknowledge or the STOP Command to

update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).

I Active LOW Output Enable (OE) input pin allows for hardware blinking and dimming of

the LEDs

I 7 hardware address pins allow 126 PCA9626 devices to be connected to the same

I²C-bus and to be individually programmed

I 4 software programmable I²C-bus addresses (one LED Group Call address and three

LED Sub Call addresses) allow groups of devices to be addressed at the same time in

any combination (for example, one register used for ‘All Call’ so that all the PCA9626s

on the I²C-bus can be addressed at the same time and the second register used for

three different addresses so that ¹⁄₃of all devices on the bus can be addressed at the

same time in a group). Software enable and disable for I²C-bus address.

I A Chase Byte allows execution of predeﬁned ON/OFF pattern for the 24 LED outputs

I Software Reset feature (SWRST Call) allows the device to be reset through the

I²C-bus

I 25 MHz internal oscillator requires no external components

I Internal power-on reset

I Noise ﬁlter on SDA/SCL inputs

I No glitch on power-up

I Supports hot insertion

I Low standby current

I Operating power supply voltage (V_DD) range of 2.3 V to 5.5 V

I 5.5 V tolerant inputs on non-LED pins

I −40 °C to +85 °C operation

I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115 and 1000 V CDM per JESD22-C101

I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

I Packages offered: LQFP48, HVQFN48

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

2 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

3. Applications

I RGB or RGBA LED drivers

I LED status information

I LED displays

I LCD backlights

I Keypad backlights for cellular phones or handheld devices

4. Ordering information

Table 1.

Ordering information

Type number

Topside mark Package

Name

LQFP48

Description

Version

PCA9626B

PCA9626

plastic low proﬁle quad ﬂat package; 48 leads;

body 7 × 7 × 1.4 mm

SOT313-2

PCA9626BS

HVQFN48 plastic thermal enhanced very thin quad ﬂat package;

SOT778-4

no leads; 48 terminals; body 6 × 6 × 0.85 mm

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

3 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

6. Pinning information

6.1 Pinning

1

2

36

35

34

33

32

31

30

29

28

27

26

25

V

SS

LED0

LED1

LED2

LED3

LED19

LED18

LED17

LED16

3

4

5

6

V

SS

V

SS

V

SS

PCA9626B

7

8

LED4

LED5

LED6

LED7

LED15

LED14

LED13

LED12

9

10

11

12

V

SS

V

SS

002aad662

Fig 2. Pin conﬁguration for LQFP48

terminal 1

index area

1

2

36

35

34

33

32

31

30

29

28

27

26

25

V

SS

LED0

LED1

LED2

LED3

LED19

LED18

LED17

LED16

3

4

5

6

V

SS

PCA9626BS

7

V

8

LED4

LED5

LED6

LED7

LED15

LED14

LED13

LED12

9

10

11

12

V

SS

V

SS

002aad609

Transparent top view

Fig 3. Pin conﬁguration for HVQFN48

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

5 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

6.2 Pin description

Table 2.

Symbol

LED22

LED23

V_SS

Pin description

43

Type

O

Description

LED driver 22

LED driver 23

44

O

1, 6, 7, 12, 16, 21, 25,

30, 31, 36, 37, 45, 48^[1]

power supply

supply ground

A0

46

47

2

I

address input 0

address input 1

LED driver 0

A1

I

LED0

LED1

LED2

LED3

LED4

LED5

LED6

LED7

A2

O

3

O

LED driver 1

4

O

LED driver 2

5

O

LED driver 3

8

O

LED driver 4

9

O

LED driver 5

10

11

13

14

15

17

18

19

20

22

23

24

26

27

28

29

32

33

34

35

38

39

40

41

42

O

LED driver 6

O

LED driver 7

I

address input 2

address input 3

address input 4

LED driver 8

A3

I

A4

I

LED8

LED9

LED10

LED11

A5

O

LED driver 9

O

LED driver 10

LED driver 11

address input 5

address input 6

active LOW output enable

LED driver 12

LED driver 13

LED driver 14

LED driver 15

LED driver 16

LED driver 17

LED driver 18

LED driver 19

serial clock line

serial data line

supply voltage

LED driver 20

LED driver 21

O

I

A6

I

OE

I

LED12

LED13

LED14

LED15

LED16

LED17

LED18

LED19

SCL

O

I

SDA

I/O

V_DD

power supply

LED20

LED21

O

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

6 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

[1] HVQFN48 package supply ground is connected to both V_SSpins and exposed center pad. V_SSpins must

be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board

level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad

on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the

PCB in the thermal pad region.

7. Functional description

Refer to Figure 1 “Block diagram of PCA9626”.

7.1 Device addresses

Following a START condition, the bus master must output the address of the slave it is

accessing.

There are a maximum of 128 possible programmable addresses using the 7 hardware

address pins. Two of these addresses, Software Reset and LED All Call, cannot be used

because their default power-up state is ON, leaving a maximum of 126 addresses. Using

other reserved addresses, as well as any other Sub Call address, will reduce the total

number of possible addresses even further.

7.1.1 Regular I²C-bus slave address

The I²C-bus slave address of the PCA9626 is shown in Figure 4. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW externally.

Remark: Using reserved I²C-bus addresses will interfere with other devices, but only if the

devices are on the bus and/or the bus will be open to other I²C-bus systems at some later

date. In a closed system where the designer controls the address assignment these

addresses can be used since the PCA9626 treats them like any other address. The

LED All Call, Software Rest and PCA9564 or PCA9665 slave address (if on the bus) can

never be used for individual device addresses.

• PCA9626 LED All Call address (1110 000) and Software Reset (0000 0110) which

are active on start-up

• PCA9564 (0000 000) or PCA9665 (1110 000) slave address which is active on

start-up

• ‘reserved for future use’ I²C-bus addresses (0000 011, 1111 1XX)

• slave devices that use the 10-bit addressing scheme (1111 0XX)

• slave devices that are designed to respond to the General Call address (0000 000)

• High-speed mode (Hs-mode) master code (0000 1XX)

slave address

A6 A5 A4 A3 A2 A1 A0 R/W

hardware selectable

002aab319

Fig 4. Slave address

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

7 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

The last bit of the address byte deﬁnes the operation to be performed. When set to logic 1

a read is selected, while a logic 0 selects a write operation.

7.1.2 LED All Call I²C-bus address

• Default power-up value (ALLCALLADR register): E0h or 1110 000

• Programmable through I²C-bus (volatile programming)

• At power-up, LED All Call I²C-bus address is enabled. PCA9626 sends an ACK when

E0h (R/W = 0) or E1h (R/W = 1) is sent by the master.

See Section 7.3.9 “ALLCALLADR, LED All Call I²C-bus address” for more detail.

Remark: The default LED All Call I²C-bus address (E0h or 1110 000) must not be used

as a regular I²C-bus slave address since this address is enabled at power-up. All of the

PCA9626s on the I²C-bus will acknowledge the address if sent by the I²C-bus master.

7.1.3 LED Sub Call I²C-bus addresses

• 3 different I²C-bus addresses can be used

• Default power-up values:

– SUBADR1 register: E2h or 1110 001

– SUBADR2 register: E4h or 1110 010

– SUBADR3 register: E8h or 1110 100

• Programmable through I²C-bus (volatile programming)

• At power-up, Sub Call I²C-bus addresses are disabled. PCA9626 does not send an

ACK when E2h (R/W = 0) or E3h (R/W = 1), E4h (R/W = 0) or E5h (R/W = 1), or

E8h (R/W = 0) or E9h (R/W = 1) is sent by the master.

See Section 7.3.8 “SUBADR1 to SUBADR3, I²C-bus subaddress 1 to 3” for more detail.

Remark: The default LED Sub Call I²C-bus addresses may be used as regular I²C-bus

slave addresses as long as they are disabled.

7.1.4 Software Reset I²C-bus address

The address shown in Figure 5 is used when a reset of the PCA9626 needs to be

performed by the master. The Software Reset address (SWRST Call) must be used with

R/W = logic 0. If R/W = logic 1, the PCA9626 does not acknowledge the SWRST. See

Section 7.6 “Software reset” for more detail.

R/W

0

1

0

002aab416

Fig 5. Software Reset address

Remark: The Software Reset I²C-bus address is a reserved address and cannot be used

as a regular I²C-bus slave address or as an LED All Call or LED Sub Call address.

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

8 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

7.2 Control register

Following the successful acknowledgement of the slave address, LED All Call address or

LED Sub Call address, the bus master will send a byte to the PCA9626, which will be

stored in the Control register.

The lowest 6 bits are used as a pointer to determine which register will be accessed

(D[5:0]). The highest bit is used as Auto-Increment Flag (AIF).

This bit along with the MODE1 register bit 5 and bit 6 provide the Auto-Increment feature.

Bit 6 of the Control register is not used.

register address

AIF

X

D5 D4 D3 D2 D1 D0

Don't care

Auto-Increment Flag

002aad610

reset state = 80h

Remark: The Control register does not apply to the Software Reset I²C-bus address.

Fig 6. Control register

When the Auto-Increment Flag is set (AIF = logic 1), the six low order bits of the Control

register are automatically incremented after a read or write. This allows the user to

program the registers sequentially. Four different types of Auto-Increment are possible,

depending on AI1 and AI0 values of MODE1 register.

Table 3.

Auto-Increment options

AI1^[1]AI0^[1]Function

AIF

0

no Auto-Increment

1

Auto-Increment for all registers. D[5:0] roll over to 0h after the last register

26h is accessed.

1

0

1

0

1

Auto-Increment for individual brightness registers only. D[5:0] roll over to

2h after the last register (19h) is accessed.

Auto-Increment for global control registers and CHASE register. D[5:0] roll

over to 1Ah after the last register (1Ch) is accessed.

Auto-Increment for individual brightness registers; global control registers

and CHASE register. D[5:0] roll over to 2h after the last register (1Ch) is

accessed.

[1] AI1 and AI0 come from MODE1 register.

Remark: Other combinations not shown in Table 3 (AIF + AI[1:0] = 001b, 010b, 011b and

111b) are reserved and must not be used for proper device operation.

AIF + AI[1:0] = 000b is used when the same register must be accessed several times

during a single I²C-bus communication, for example, changes the brightness of a single

LED. Data is overwritten each time the register is accessed during a write operation.

AIF + AI[1:0] = 100b is used when all the registers must be sequentially accessed, for

example, power-up programming.

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

9 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

AIF + AI[1:0] = 101b is used when the 16 LED drivers must be individually programmed

with different values during the same I²C-bus communication, for example, changing color

setting to another color setting.

AIF + AI[1:0] = 110b is used when the LED drivers must be globally programmed with

different settings during the same I²C-bus communication, for example, global brightness

or blinking change.

AIF + AI[1:0] = 111b is used when the 16 LED drivers must be individually programmed

with different values in addition to global programming.

Only the 6 least signiﬁcant bits D[5:0] are affected by the AIF, AI1 and AI0 bits.

When the Control register is written, the register entry point determined by D[5:0] is the

ﬁrst register that will be addressed (read or write operation), and can be anywhere

between 0h and 26h (as deﬁned in Table 4). When AIF = 1, the Auto-Increment Flag is set

and the rollover value at which the register increment stops and goes to the next one is

determined by AIF, AI1 and AI2. See Table 3 for rollover values. For example, if MODE1

register bit AI1 = 0 and AI0 = 1 and if the Control register = 1001 0010, then the register

addressing sequence will be (in hex):

20 → 21 → … → 26 → 0 → 1 → 2 → … → 19 → 02 → 03 → … → 19 → 02 … as long

as the master keeps sending or reading data.

7.3 Register deﬁnitions

Table 4.

Register summary^[1][2]

Register number D5

(hex)

D4

D3

D2

D1

D0

Name

Type

Function

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MODE1

MODE2

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

PWM7

PWM8

PWM9

PWM10

PWM11

PWM12

PWM13

PWM14

PWM15

PWM16

PWM17

read/write

Mode register 1

Mode register 2

brightness control LED0

brightness control LED1

brightness control LED2

brightness control LED3

brightness control LED4

brightness control LED5

brightness control LED6

brightness control LED7

brightness control LED8

brightness control LED9

brightness control LED10

brightness control LED11

brightness control LED12

brightness control LED13

brightness control LED14

brightness control LED15

brightness control LED16

brightness control LED17

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

10 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

Table 4.

Register summary^[1][2]…continued

Register number D5

(hex)

D4

D3

D2

D1

D0

Name

Type

Function

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

PWM18

read/write

brightness control LED18

brightness control LED19

brightness control LED20

brightness control LED21

brightness control LED22

brightness control LED23

group duty cycle control

group frequency

PWM19

PWM20

PWM21

PWM22

PWM23

GRPPWM

GRPFREQ

CHASE

chase control

LEDOUT0

LEDOUT1

LEDOUT2

LEDOUT3

LEDOUT4

LEDOUT5

SUBADR1

SUBADR2

SUBADR3

LED output state 0

LED output state 1

LED output state 2

LED output state 3

LED output state 4

LED output state 5

I²C-bus subaddress 1

I²C-bus subaddress 2

I²C-bus subaddress 3

LED All Call I²C-bus address

ALLCALLADR read/write

[1] Only D[5:0] = 00 0000 to 10 0110 are allowed and will be acknowledged. D[5:0] = 10 0111 to 11 1111 are reserved and may not be

acknowledged.

[2] When writing to the Control register, bit 6 should be programmed with logic 0 for proper device operation.

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

11 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

7.3.1 Mode register 1, MODE1

Table 5.

MODE1 - Mode register 1 (address 00h) bit description

Legend: * default value.

Bit

Symbol

Access

Value

0

Description

7

AI2

read only

Register Auto-Increment disabled.

1*

0*

1

Register Auto-Increment enabled.

6

5

4

3

2

1

0

AI1

R/W

Auto-Increment bit 1 = 0. Auto-increment range as deﬁned in Table 3.

Auto-Increment bit 1 = 1. Auto-increment range as deﬁned in Table 3.

Auto-Increment bit 0 = 0. Auto-increment range as deﬁned in Table 3.

Auto-Increment bit 0 = 1. Auto-increment range as deﬁned in Table 3.

Normal mode^[1].

Low power mode. Oscillator off^[2].

PCA9626 does not respond to I²C-bus subaddress 1.

PCA9626 responds to I²C-bus subaddress 1.

PCA9626 does not respond to I²C-bus subaddress 2.

PCA9626 responds to I²C-bus subaddress 2.

PCA9626 does not respond to I²C-bus subaddress 3.

PCA9626 responds to I²C-bus subaddress 3.

PCA9626 does not respond to LED All Call I²C-bus address.

PCA9626 responds to LED All Call I²C-bus address.

AI0

0*

1

SLEEP

SUB1

SUB2

SUB3

ALLCALL

0

1*

0*

1

0*

1

0*

1

0

1*

[1] It takes 500 µs max. for the oscillator to be up and running once SLEEP bit has been set to logic 1. Timings on LEDn outputs are not

guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 µs window.

[2] No blinking or dimming is possible when the oscillator is off.

7.3.2 Mode register 2, MODE2

Table 6.

MODE2 - Mode register 2 (address 01h) bit description

Legend: * default value.

Bit

7

Symbol

Access

read only

R/W

Value Description

-

0*

1

reserved

6

-

reserved

5

DMBLNK

group control = dimming.

group control = blinking.

reserved

outputs change on STOP command^[1]

outputs change on ACK

reserved

4

3

INVRT

OCH

read only

R/W

0*

1

2

1

0

-

read only

1*

0*

1*

reserved

[1] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9626. Applicable to registers from

02h (PWM0) to 08h (LEDOUT) only.

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

12 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

7.3.3 PWM0 to PWM23, individual brightness control

Table 7.

PWM0 to PWM23 - PWM registers 0 to 23 (address 02h to 19h) bit description

Legend: * default value.

Address Register Bit

Symbol

Access Value

Description

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

PWM7

PWM8

PWM9

7:0

IDC0[7:0]

IDC1[7:0]

IDC2[7:0]

IDC3[7:0]

IDC4[7:0]

IDC5[7:0]

IDC6[7:0]

IDC7[7:0]

IDC8[7:0]

IDC9[7:0]

R/W

0000 0000* PWM0 Individual Duty Cycle

0000 0000* PWM1 Individual Duty Cycle

0000 0000* PWM2 Individual Duty Cycle

0000 0000* PWM3 Individual Duty Cycle

0000 0000* PWM4 Individual Duty Cycle

0000 0000* PWM5 Individual Duty Cycle

0000 0000* PWM6 Individual Duty Cycle

0000 0000* PWM7 Individual Duty Cycle

0000 0000* PWM8 Individual Duty Cycle

0000 0000* PWM9 Individual Duty Cycle

0000 0000* PWM10 Individual Duty Cycle

0000 0000* PWM11 Individual Duty Cycle

0000 0000* PWM12 Individual Duty Cycle

0000 0000* PWM13 Individual Duty Cycle

0000 0000* PWM14 Individual Duty Cycle

0000 0000* PWM15 Individual Duty Cycle

0000 0000* PWM16 Individual Duty Cycle

0000 0000* PWM17 Individual Duty Cycle

0000 0000* PWM18 Individual Duty Cycle

0000 0000* PWM19 Individual Duty Cycle

0000 0000* PWM20 Individual Duty Cycle

0000 0000* PWM21 Individual Duty Cycle

0000 0000* PWM22 Individual Duty Cycle

0000 0000* PWM23 Individual Duty Cycle

PWM10 7:0

PWM11 7:0

PWM12 7:0

PWM13 7:0

PWM14 7:0

PWM15 7:0

PWM16 7:0

PWM17 7:0

PWM18 7:0

PWM19 7:0

PWM20 7:0

PWM21 7:0

PWM22 7:0

PWM23 7:0

IDC10[7:0] R/W

IDC11[7:0] R/W

IDC12[7:0] R/W

IDC13[7:0] R/W

IDC14[7:0] R/W

IDC15[7:0] R/W

IDC16[7:0] R/W

IDC17[7:0] R/W

IDC18[7:0] R/W

IDC19[7:0] R/W

IDC20[7:0] R/W

IDC21[7:0] R/W

IDC22[7:0] R/W

IDC23[7:0] R/W

A 97 kHz ﬁxed frequency signal is used for each output. Duty cycle is controlled through

256 linear steps from 00h (0 % duty cycle = LED output off) to FFh

(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs

programmed with LDRx = 10 or 11 (LEDOUT0 to LEDOUT5 registers).

IDCx[7:0]

duty cycle =

(1)

---------------------------

256

PCA9626_2

Product data sheet

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13 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

7.3.4 GRPPWM, group duty cycle control

Table 8.

GRPPWM - Group brightness control register (address 1Ah) bit description

Legend: * default value

Address Register

Bit Symbol

Access Value

Description

1Ah

GRPPWM

7:0 GDC[7:0]

R/W 1111 1111 GRPPWM register

When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz ﬁxed

frequency signal is superimposed with the 97 kHz individual brightness control signal.

GRPPWM is then used as a global brightness control allowing the LED outputs to be

dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.

General brightness for the 16 outputs is controlled through 256 linear steps from 00h

(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT5

registers).

When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers

deﬁne a global blinking pattern, where GRPFREQ contains the blinking period (from

24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).

GDC[7:0]

duty cycle =

(2)

--------------------------

256

7.3.5 GRPFREQ, group frequency

Table 9.

GRPFREQ - Group Frequency register (address 1Bh) bit description

Legend: * default value.

Address Register

Bit Symbol

Access Value

Description

1Bh

GRPFREQ 7:0 GFRQ[7:0] R/W

0000 0000* GRPFREQ register

GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2

register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT5

registers).

Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)

to FFh (10.73 s).

GFRQ[7:0] + 1

global blinking period =

(s)

(3)

---------------------------------------

24

PCA9626_2

Product data sheet

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14 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

7.3.6 CHASE control

Table 10. CHASE - Chase pattern control register (address 1Ch) bit description

Legend: * default value.

Address Register

Bit Symbol

Access Value

Description

1Ch

CHASE

7:0 CHC[7:0]

R/W 0000 0000* CHASE register

CHASE is used to program the LED output ON/OFF pattern. The contents of the CHASE

register is used to enable one of the LED output patterns, as indicated in Table 11.

By repeated, sequential access to this table via the CHASE register, a chase pattern, e.g.,

marquee effect, can be easily programmed with minimal number of commands. Once the

CHASE register is accessed, the data bytes that follow will be used as an index value to

pick the LED output patterns deﬁned by Table 11 “CHASE sequence”.

This register always updates on ACK. It is used to gate the OE signal at each of the LEDn

pins such that:

• OE = 1: all LEDs are off

• OE = 0: those LEDs corresponding to the ‘X’s in Table 11 are on

Any write to this register takes effect at the ACK.

PCA9626_2

Product data sheet

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15 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

7.3.7 LEDOUT0 to LEDOUT5, LED driver output state

Table 12. LEDOUT0 to LEDOUT5 - LED driver output state register (address 1Dh to 22h)

bit description

Legend: * default value.

Address Register

Bit Symbol

7:6 LDR3

5:4 LDR2

3:2 LDR1

1:0 LDR0

7:6 LDR7

5:4 LDR6

3:2 LDR5

1:0 LDR4

7:6 LDR11

5:4 LDR10

3:2 LDR9

1:0 LDR8

7:6 LDR15

5:4 LDR14

3:2 LDR13

1:0 LDR12

7:6 LDR19

5:4 LDR18

3:2 LDR17

1:0 LDR16

7:6 LDR23

5:4 LDR22

3:2 LDR21

1:0 LDR20

Access Value

Description

1Dh

1Eh

1Fh

20h

21h

22h

LEDOUT0

LEDOUT1

LEDOUT2

LEDOUT3

LEDOUT4

LEDOUT5

R/W

00*

LED3 output state control

LED2 output state control

LED1 output state control

LED0 output state control

LED7 output state control

LED6 output state control

LED5 output state control

LED4 output state control

LED11 output state control

LED10 output state control

LED9 output state control

LED8 output state control

LED15 output state control

LED14 output state control

LED13 output state control

LED12 output state control

LED19 output state control

LED18 output state control

LED17 output state control

LED16 output state control

LED23 output state control

LED22 output state control

LED21 output state control

LED20 output state control

LDRx = 00 — LED driver x is off (default power-up state).

LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking

not controlled).

LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx

register.

LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be

controlled through its PWMx register and the GRPPWM registers.

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

22 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

7.3.8 SUBADR1 to SUBADR3, I²C-bus subaddress 1 to 3

Table 13. SUBADR1 to SUBADR3 - I²C-bus subaddress registers 0 to 3 (address 23h to 25h)

bit description

Legend: * default value.

Address Register

Bit

7:1

0

Symbol

A1[7:1]

A1[0]

Access Value

Description

1110 001* I²C-bus subaddress 1

0* reserved

1110 010* I²C-bus subaddress 2

0* reserved

1110 100* I²C-bus subaddress 3

0* reserved

23h

24h

25h

SUBADR1

SUBADR2

SUBADR3

R/W

R only

R/W

7:1

0

A2[7:1]

A2[0]

R only

R/W

7:1

0

A3[7:1]

A3[0]

R only

Subaddresses are programmable through the I²C-bus. Default power-up values are E2h,

E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up

(the corresponding SUBx bit in MODE1 register is equal to 0).

Once subaddresses have been programmed to their right values, SUBx bits need to be

set to logic 1 in order to have the device acknowledging these addresses (MODE1

register).

Only the 7 MSBs representing the I²C-bus subaddress are valid. The LSB in SUBADRx

register is a read-only bit (0).

When SUBx is set to logic 1, the corresponding I²C-bus subaddress can be used during

either an I²C-bus read or write sequence.

7.3.9 ALLCALLADR, LED All Call I²C-bus address

Table 14. ALLCALLADR - LED All Call I²C-bus address register (address 26h) bit

description

Legend: * default value.

Address Register

Bit

Symbol Access Value

Description

26h

ALLCALLADR 7:1

AC[7:1]

R/W

1110 000* ALLCALL I²C-bus

address register

0

AC[0]

R only

0*

reserved

The LED All Call I²C-bus address allows all the PCA9626s on the bus to be programmed

at the same time (ALLCALL bit in register MODE1 must be equal to logic 1 (power-up

default state)). This address is programmable through the I²C-bus and can be used during

either an I²C-bus read or write sequence. The register address can also be programmed

as a Sub Call.

Only the 7 MSBs representing the All Call I²C-bus address are valid. The LSB in

ALLCALLADR register is a read-only bit (0).

If ALLCALL bit = 0, the device does not acknowledge the address programmed in register

ALLCALLADR.

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

23 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

7.4 Active LOW output enable input

The active LOW output enable (OE) pin, allows to enable or disable all the LED outputs at

the same time.

• When a LOW level is applied to OE pin, all the LED outputs are enabled as deﬁned by

the CHASE register.

• When a HIGH level is applied to OE pin, all the LED outputs are high-impedance.

The OE pin can be used as a synchronization signal to switch on/off several PCA9626

devices at the same time. This requires an external clock reference that provides blinking

period and the duty cycle.

The OE pin can also be used as an external dimming control signal. The frequency of the

external clock must be high enough not to be seen by the human eye, and the duty cycle

value determines the brightness of the LEDs.

Remark: Do not use OE as an external blinking control signal when internal global

blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an undeﬁned

blinking pattern. Do not use OE as an external dimming control signal when internal global

dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an undeﬁned

dimming pattern.

Remark: During power-down, slow decay of voltage supplies may keep LEDs illuminated.

Consider disabling LED outputs using HIGH level applied to OE pin.

7.5 Power-on reset

When power is applied to V_DD, an internal power-on reset holds the PCA9626 in a reset

condition until V_DDhas reached V_POR. At this point, the reset condition is released and the

PCA9626 registers and I²C-bus state machine are initialized to their default states (all

zeroes) causing all the channels to be deselected. Thereafter, V_DDmust be lowered below

0.2 V to reset the device.

7.6 Software reset

The Software Reset Call (SWRST Call) allows all the devices in the I²C-bus to be reset to

the power-up state value through a speciﬁc formatted I²C-bus command. To be performed

correctly, it implies that the I²C-bus is functional and that there is no device hanging the

bus.

The SWRST Call function is deﬁned as the following:

1. A START command is sent by the I²C-bus master.

2. The reserved SWRST I²C-bus address ‘0000 011’ with the R/W bit set to ‘0’ (write) is

sent by the I²C-bus master.

3. The PCA9626 device(s) acknowledge(s) after seeing the SWRST Call address

‘0000 0110’ (06h) only. If the R/W bit is set to ‘1’ (read), no acknowledge is returned to

the I²C-bus master.

4. Once the SWRST Call address has been sent and acknowledged, the master sends

2 bytes with 2 speciﬁc values (SWRST data byte 1 and byte 2):

a. Byte 1 = A5h: the PCA9626 acknowledges this value only. If byte 1 is not equal to

A5h, the PCA9626 does not acknowledge it.

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

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PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

b. Byte 2 = 5Ah: the PCA9626 acknowledges this value only. If byte 2 is not equal to

5Ah, then the PCA9626 does not acknowledge it.

If more than 2 bytes of data are sent, the PCA9626 does not acknowledge any more.

5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and

correctly acknowledged, the master sends a STOP command to end the SWRST Call:

the PCA9626 then resets to the default value (power-up value) and is ready to be

addressed again within the speciﬁed bus free time (t_BUF).

The I²C-bus master must interpret a non-acknowledge from the PCA9626 (at any time) as

a ‘SWRST Call Abort’. The PCA9626 does not initiate a reset of its registers. This

happens only when the format of the SWRST Call sequence is not correct.

7.7 Individual brightness control with group dimming/blinking

A 97 kHz ﬁxed frequency signal with programmable duty cycle (8 bits, 256 steps) is used

to control individually the brightness for each LED.

On top of this signal, one of the following signals can be superimposed (this signal can be

applied to the 4 LED outputs):

• A lower 190 Hz ﬁxed frequency signal with programmable duty cycle (8 bits,

256 steps) is used to provide a global brightness control.

• A programmable frequency signal from 24 Hz to ¹⁄_10.73Hz (8 bits, 256 steps) with

programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking

control.

508

510

512

1

2

3

4

5

6

7

8

9

10 11 12

507

509

511

1

2

3

4

5

6

7

8

9

10 11

Brightness Control signal (LEDn)

N × 40 ns

with N = (0 to 255)

(PWMx Register)

M × 256 × 2 × 40 ns

with M = (0 to 255)

(GRPPWM Register)

256 × 40 ns = 10.24 µs

(97.6 kHz)

Group Dimming signal

256 × 2 × 256 × 40 ns = 5.24 ms (190.7 Hz)

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

002aab417

resulting Brightness + Group Dimming signal

Minimum pulse width for LEDn Brightness Control is 40 ns.

Minimum pulse width for Group Dimming is 20.48 µs.

When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal will have 2 pulses of

the LED Brightness Control signal (pulse width = N × 40 ns, with ‘N’ deﬁned in PWMx register).

This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 4 (8 pulses).

Fig 7. Brightness + Group Dimming signals

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

25 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

8. Characteristics of the I²C-bus

The I²C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 8).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 8. Bit transfer

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P) (see Figure 9).

SDA

SCL

S

P

STOP condition

START condition

mba608

Fig 9. Deﬁnition of START and STOP conditions

8.2 System conﬁguration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 10).

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

26 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

SDA

SCL

SLAVE

TRANSMITTER/

RECEIVER

MASTER

2

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

I C-BUS

TRANSMITTER/

RECEIVER

MULTIPLEXER

SLAVE

002aaa966

Fig 10. System conﬁguration

8.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold

time must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from master

1

2

8

9

S

clock pulse for

START

condition

acknowledgement

002aaa987

Fig 11. Acknowledgement on the I²C-bus

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

27 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

9. Bus transactions

(1)

slave address

control register

data for register D[5:0]

S

A6 A5 A4 A3 A2 A1 A0

0

A

X

D5 D4 D3 D2 D1 D0

A

P

START condition

R/W

Auto-Increment flag

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

STOP

condition

002aad612

(1) See Table 4 for register deﬁnition.

Fig 12. Write to a speciﬁc register

slave address

control register

MODE1 register

MODE2 register

(cont.)

S

A6 A5 A4 A3 A2 A1 A0

0

A

1

X

0

A

MODE1

register selection

START condition

R/W

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

acknowledge Auto-Increment on

from slave

SUBADR3 register

ALLCALLADR register

(cont.)

A

P

acknowledge

from slave

acknowledge

from slave

STOP

condition

002aad613

Fig 13. Write to all registers using the Auto-Increment feature

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

28 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

ReSTART

condition

slave address

control register

slave address

data from MODE1 register

(cont.)

A

S

A6 A5 A4 A3 A2 A1 A0

0

A

1

X

0

A

Sr A6 A5 A4 A3 A2 A1 A0

1

A

MODE1

register selection

START condition

R/W

acknowledge

from slave

R/W

acknowledge

from master

acknowledge

from slave

acknowledge

from slave

Auto-Increment on

data from

ALLCALLADR register

data from

MODE1 register

data from MODE2 register

data from PWM0

(cont.)

A

(cont.)

A

acknowledge

from master

acknowledge

from master

acknowledge

from master

acknowledge

from master

data from last read byte

A

P

not acknowledge STOP

from master condition

002aad615

This example assumes that the MODE1[5] = 0 and MODE1[6] = 0.

Fig 15. Read all registers using the Auto-Increment feature

(1)

2

(2)

slave address

control register

new LED All Call I C address

sequence (A)

S

A6 A5 A4 A3 A2 A1 A0

0

A

1

X

1

0

1

0

A

1

0

1

0

1

0

1

X

A

P

ALLCALLADR

START condition

R/W

acknowledge

from slave

acknowledge

from slave

register selection

acknowledge

from slave

Auto-Increment on

STOP

condition

(3)

the 16 LEDs are on at the acknowledge

LEDOUT register (LED fully ON)

2

LED All Call I C address

control register

sequence (B)

S

1

0

1

0

1

0

1

0

A

X

0

1

0

A

0

1

0

1

0

1

0

1

A

P

LEDOUT

register selection

START condition

R/W

acknowledge

from the

4 devices

acknowledge

from the

acknowledge

from the

4 devices

STOP

condition

4 devices

002aad616

(1) In this example, several PCA9626s are used and the same sequence (A) (above) is sent to each of them.

(2) ALLCALL bit in MODE1 register is previously set to 1 for this example.

(3) OCH bit in MODE2 register is previously set to 1 for this example.

Fig 16. LED All Call I²C-bus address programming and LED All Call sequence example

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

30 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

10. Application design-in information

up to 40 V

V

= 2.5 V, 3.3 V or 5.0 V

DD

(1)

10 kΩ

2

I C-BUS/SMBus

MASTER

SDA

V

DD

SDA

LED0

LED1

LED2

LED3

SCL

OE

PCA9626

LED light bar

up to 40 V

LED4

LED5

LED6

LED7

LED light bar

up to 40 V

LED8

LED9

LED10

LED11

LED light bar

up to 40 V

LED12

LED13

LED14

LED15

LED16

LED17

LED18

LED19

A0

A1

A2

A3

A4

A5

A6

LED20

LED21

LED22

LED23

V

SS

V

SS

002aad607

(1) OE requires pull-up resistor if control signal from the master is open-drain.

I²C-bus address = 0010 101x.

Remark: During power-down, slow decay of voltage supplies may keep LEDs illuminated. Consider disabling LED outputs

using HIGH level applied to OE pin.

Fig 17. Typical application

PCA9626_2

Product data sheet

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31 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

10.1 Junction temperature calculation

A device junction temperature can be calculated when the ambient temperature or the

case temperature is known.

When the ambient temperature is known, the junction temperature is calculated using

Equation 4 and the ambient temperature, junction to ambient thermal resistance and

power dissipation.

T _j= T_amb+ R_{th( j-a)}× P_tot

(4)

where:

T_j= junction temperature

T_amb= ambient temperature

R_th(j-a)= junction to ambient thermal resistance

P_tot= (device) total power dissipation

When the case temperature is known, the junction temperature is calculated using

Equation 5 and the case temperature, junction to case thermal resistance and power

dissipation.

T _j= T_case+ R_{th( j-c)}× P_tot

(5)

where:

T_j= junction temperature

T_case= case temperature

R_th(j-c)= junction to case thermal resistance

P_tot= (device) total power dissipation

Here are two examples regarding how to calculate the junction temperature using junction

to case and junction to ambient thermal resistance. In the first example (Section 10.1.1),

given the operating condition and the junction to ambient thermal resistance, the junction

temperature of PCA9626B, in the LQFP48 package, is calculated for a system operating

condition in 50 °C¹ambient temperature. In the second example (Section 10.1.2), based

on a specific customer application requirement where only the case temperature is

known, applying the junction to case thermal resistance equation, the junction

temperature of the PCA9626B, in the LQFP48 package, is calculated.

1. 50 °C is a typical temperature inside an enclosed system. The designers should feel free, as needed, to perform their own

calculation using the examples.

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

32 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

10.1.1 Example 1: T_jcalculation when T_ambis known (PCA9626B, LQFP48)

R_th(j-a)= 63 °C/W

T_amb= 50 °C

LED output low voltage (LED V_OL) = 0.5 V

LED output current per channel = 80 mA

Number of outputs = 24

I_DD(max)= 18 mA

V_DD(max)= 5.5 V

I²C-bus clock (SCL) maximum sink current = 25 mA

I²C-bus data (SDA) maximum sink current = 25 mA

1. Find P_tot(device total power dissipation):

– output total power = 30 mA × 24 × 0.5 V = 960 mW

– chip core power consumption = 18 mA × 5.5 V = 99 mW

– SCL power dissipation = 25 mA 0.4 V = 10 mW

– SDA power dissipation = 25 mA 0.4 V = 10 mW

P

_tot= (960 + 99 + 10 + 10) mW = 1079 mW

2. Find T_j(junction temperature):

T_j= (T_amb+ R_th(j-a)× P_tot) = (50 °C + 63 °C/W × 1079 mW) = 118 °C

10.1.2 Example 2: T_jcalculation where only T_caseis known

This example uses a customer’s speciﬁc application of the PCA9626B, 24-channel LED

controller in the LQFP48 package, where only the case temperature (T_case) is known.

T_j= T_case+ R_th(j-c)× P_tot, where:

R_th(j-c)= 18 °C/W

T_case(measured) = 94.6 °C

V_OLof LED ~ 0.5 V

I_DD(max)= 18 mA

V_DD(max)= 5.5 V

LED output voltage LOW = 0.5 V

LED output current:

60 mA on 1 port = (60 mA × 1)

50 mA on 6 ports = (50 mA × 6)

40 mA on 2 ports = (40 mA × 2)

20 mA on 12 ports = (20 mA × 12)

1 mA on 3 ports = (1 mA × 3)

I²C-bus maximum sink current on clock line = 25 mA

I²C-bus maximum sink current on data line = 25 mA

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

33 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

1. Find P_tot(device total power dissipation)

– output current (60 mA × 1 port); output power (60 mA × 1 × 0.5 V) = 30 mW

– output current (50 mA × 6 ports); output power (50 mA × 6 × 0.5 V) = 150 mW

– output current (40 mA × 2 ports); output power (40 mA × 2 × 0.5 V) = 40 mW

– output current (20 mA × 12 ports); output power (20 mA × 12 × 0.5 V) = 120 mW

– output current (1 mA × 3 ports); output power (1 mA × 3 × 0.5 V) = 1.5 mW

Output total power = 341.5 mW

– chip core power consumption = 18 mA × 5.5 V = 99 mW

– SCL power dissipation = 25 mA × 0.4 V = 10 mW

– SDA power dissipation = 25 mA × 0.4 V = 10 mW

P_tot(device total power dissipation) = 460.5 mW

2. Find T_j(junction temperature):

T_j= T_case+ R_th(j-a)× P_tot= 94.6 °C + 18 °C/W × 460.5 mW = 102.9 °C

11. Limiting values

Table 15. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

Unit

V

V_DD

V_I/O

supply voltage

−0.5

+6.0

voltage on an input/output pin

V_SS− 0.5 5.5

V

V_drv(LED)LED driver voltage

I_O(LEDn)output current on pin LEDn

I_OL(tot)

V

_SS− 0.5 40

V

-

100

-

mA

[1]

total LOW-level output current LED driver outputs;

2400

V_OL= 0.5 V

I_SS

ground supply current

total power dissipation

per V_SSpin

T_amb= 25 °C

T_amb= 85 °C

-

800

1.8

mA

W

P_tot

-

0.72

100

45

W

P/ch

power dissipation per channel T_amb= 25 °C

T_amb= 85 °C

-

mW

°C

-

[2]

T_j

junction temperature

-

+125

+150

+85

T_stg

T_amb

storage temperature

−65

−40

°C

ambient temperature

operating

°C

[1] Each bit must be limited to a maximum of 100 mA and the total package limited to 2400 mA due to internal

busing limits.

[2] Refer to Section 10.1 for calculation.

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

34 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

Table 16. LQFP48 versus HVQFN48 power dissipation and output current capability

Measurement

LQFP48

HVQFN48

T_amb= 25 °C

maximum power

dissipation (chip + output

drivers)

1590 mW

2780 mW

maximum power

dissipation (output drivers

only)

1460 mW

2650 mW

maximum drive current

per channel

1460 mW

-----------------------------------

24-bit × 0.5 V

2650 mW

-----------------------------------

24-bit × 0.5 V

<

= 121.7 mA ^[1]

<

= 220.8 mA ^[1]

T_amb= 60 °C

maximum power

dissipation (chip + output

drivers)

1030 mW

1810 mW

maximum power

dissipation (output drivers

only)

901 mW

1680 mW

maximum drive current

per channel

901 mW

24-bit × 0.5 V

1680 mW

-----------------------------------

24-bit × 0.5 V

<

= 75.1 mA

<

= 140 mA ^[1]

-----------------------------------

T_amb= 80 °C

maximum power

dissipation (chip + output

drivers)

714 mW

585 mW

1250 mW

maximum power

dissipation (output drivers

only)

1120 mW

maximum drive current

per channel

585 mW

24-bit × 0.5 V

1120 mW

-----------------------------------

24-bit × 0.5 V

<

= 48.8 mA

<

= 93.3 mA

-----------------------------------

[1] This value signiﬁes package’s ability to handle more than 100 mA per output driver. The device’s maximum

current rating per output is 100 mA.

12. Thermal characteristics

Table 17. Thermal characteristics

Symbol

Parameter

Conditions

LQFP48

Typ

63

Unit

[1]

R_th(j-a)

thermal resistance from junction to ambient

°C/W

HVQFN48

LQFP48

36

R_th(j-c)

thermal resistance from junction to case

18

HVQFN48

14

[1] Calculated in accordance with JESD 51-7.

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

35 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

13. Static characteristics

Table 18. Static characteristics

V_DD= 2.3 V to 5.5 V; V_SS= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Supply

V_DD

Parameter

Conditions

Min

Typ

Max

Unit

supply voltage

supply current

2.3

-

5.5

V

I_DD

on pin V_DD; operating mode;

no load; f_SCL= 1 MHz

V_DD= 2.7 V

V_DD= 3.6 V

V_DD= 5.5 V

-

0.5

1.5

13

4

mA

6

18

I_stb

standby current

on pin V_DD;

no load; f_SCL= 0 Hz;

I/O = inputs; V_I= V_DD

V_DD= 2.7 V

-

0.5

1.0

6

5

µA

V

V_DD= 3.6 V

10

15

2.0

V_DD= 5.5 V

[1]

V_POR

power-on reset voltage

no load; V_I= V_DDor V_SS

1.70

Input SCL; input/output SDA

V_IL

V_IH

I_OL

LOW-level input voltage

−0.5

0.7V_DD

20

-

+0.3V_DD

V

HIGH-level input voltage

LOW-level output current

-

5.5

-

V

V_OL= 0.4 V; V_DD= 2.3 V

V_OL= 0.4 V; V_DD= 5.0 V

V_I= V_DDor V_SS

-

mA

µA

pF

30

-

I_L

leakage current

−1

-

+1

10

C_i

input capacitance

V_I= V_SS

-

6

LED driver outputs

V_drv(LED)LED driver voltage

I_OL

0

-

40

-

V

[2]

LOW-level output current

V_OL= 0.5 V; V_DD≥ 4.5 V

V_drv(LED)= 5 V

100

-

mA

µA

Ω

I_LOH

HIGH-level output leakage

current

-

±1

15

5

V_drv(LED)= 40 V

±1

2

R_on

ON-state resistance

output capacitance

V_drv(LED)= 40 V; V_DD= 2.3 V

C_o

15

40

pF

OE input

V_IL

V_IH

I_LI

LOW-level input voltage

HIGH-level input voltage

input leakage current

input capacitance

−0.5

0.7V_DD

−1

-

+0.8

5.5

+1

V

-

V

-

µA

pF

C_i

-

3.7

5

Address inputs

V_IL

V_IH

I_LI

LOW-level input voltage

−0.5

0.7V_DD

−1

-

+0.3V_DD

V

HIGH-level input voltage

input leakage current

input capacitance

-

5.5

+1

5

V

-

µA

pF

C_i

-

3.7

[1] V_DDmust be lowered to 0.2 V in order to reset part.

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

36 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

[2] Each bit must be limited to a maximum of 100 mA and the total package limited to 2400 mA due to internal busing limits.

14. Dynamic characteristics

Table 19. Dynamic characteristics

Symbol Parameter

Conditions

Standard-mod

e I²C-bus

Fast-mode

I²C-bus

Fast-mode

Plus I²C-bus

Unit

Min

0

Max

100

-

Min

0

Max

Min

0

Max

1000 kHz

f_SCL

t_BUF

SCL clock frequency

400

-

bus free time

4.7

1.3

0.5

-

µs

between a STOP and

START condition

t_HD;STA

t_SU;STA

hold time (repeated)

START condition

4.0

4.7

-

0.6

-

0.26

-

µs

set-up time for a

repeated START

condition

t_SU;STO

set-up time for STOP

condition

4.0

-

0.6

-

0.26

-

µs

t_HD;DAT

t_VD;ACK

data hold time

0

-

0

-

0

ns

[1]

[2]

data valid

acknowledge time

0.3

3.45

0.1

0.9

0.05

0.45 µs

t_VD;DAT

t_SU;DAT

t_LOW

data valid time

0.3

250

4.7

3.45

0.1

100

1.3

0.9

0.05

50

0.45 µs

data set-up time

-

ns

LOW period of the

SCL clock

0.5

µs

t_HIGH

t_f

HIGH period of the

SCL clock

4.0

-

0.6

-

0.26

-

µs

[3][4]

[5]

fall time of both SDA

and SCL signals

-

300 20 + 0.1C_b

300

50

-

120 ns

t_r

rise time of both SDA

and SCL signals

1000 20 + 0.1C_b

[6]

t_SP

pulse width of spikes

that must be

50

-

50

ns

suppressed by the

input ﬁlter

Output propagation delay

t_PLH

LOW to HIGH

propagation delay

OE to LEDn;

MODE2[1:0] = 01

-

150 ns

t_PHL

HIGH to LOW

OE to LEDn;

propagation delay

MODE2[1:0] = 01

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

37 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

Table 19. Dynamic characteristics …continued

Symbol Parameter

Conditions

Standard-mod

e I²C-bus

Fast-mode

I²C-bus

Fast-mode

Plus I²C-bus

Unit

Min

Max

Min

Max

Min

Max

Output port timing

t_d(SCL-Q)delay time from SCL SCL to LEDn;

-

450 ns

to data output

MODE2[3] = 1;

outputs change on

ACK

t_d(SDA-Q)delay time from SDA SDA to LEDn;

-

to data output

MODE2[3] = 0;

outputs change on

STOP condition

[1] t_VD;ACK= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[2] t_VD;DAT= minimum time for SDA data out to be valid following SCL LOW.

[3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V_ILof the SCL signal) in order to

bridge the undeﬁned region of SCL’s falling edge.

[4] The maximum t_ffor the SDA and SCL bus lines is speciﬁed at 300 ns. The maximum fall time (t_f) for the SDA output stage is speciﬁed at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum speciﬁed t_f.

[5] C_b= total capacitance of one bus line in pF.

[6] Input ﬁlters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

SDA

t

SP

t

r

f

HD;STA

BUF

t

LOW

SCL

t

SU;STO

HD;STA

SU;STA

t

SU;DAT

HD;DAT

HIGH

P

S

Sr

P

002aaa986

Fig 18. Deﬁnition of timing

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

38 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

START

condition

(S)

bit 7

MSB

(A7)

STOP

condition

(P)

bit 6

(A6)

bit 1

(D1)

bit 0

(D0)

acknowledge

(A)

protocol

t

HIGH

SU;STA

LOW

1 / f

SCL

SDA

t

BUF

f

t

r

t

HD;DAT

VD;DAT

VD;ACK

SU;STO

002aab285

HD;STA

SU;DAT

Rise and fall times refer to V_ILand V_IH.

Fig 19. I²C-bus timing diagram

15. Test information

V

DD

open

GND

V

R

500 Ω

DD

L

V

O

I

PULSE

GENERATOR

DUT

C

50 pF

L

R

T

002aab284

R_L= Load resistor for LEDn. R_Lfor SDA and SCL > 1 kΩ (3 mA or less current).

C_L= Load capacitance includes jig and probe capacitance.

R_T= Termination resistance should be equal to the output impedance Z_oof the pulse generators.

Fig 20. Test circuitry for switching times

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

39 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

16. Package outline

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y

X

36

25

A

E

37

24

Z

E

e

H

E

A

2

A

(A )

3

A

1

w M

p

θ

pin 1 index

b

L

p

L

13

48

detail X

1

12

Z

v M

D

A

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 21. Package outline SOT313-2 (LQFP48)

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

40 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;

48 terminals; body 6 x 6 x 0.85 mm

SOT778-4

D

B

A

terminal 1

index area

E

A

1

c

detail X

C

e

1

y

C

1

y

M

v

C

A

B

b

e

1/2 e

w

13

24

L

25

12

e

2

E

h

1/2 e

1

36

terminal 1

index area

48

37

X

D

h

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

D

h

E

e

1

e

2

L

v

w

y

1

h

max

0.05 0.25

0.00 0.15

6.1

5.9

4.75

4.45

6.1

5.9

4.75

4.45

0.5

0.3

1

mm

0.2

0.4

4.4

0.1

0.05 0.05

0.1

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

- - -

04-07-30

04-10-07

SOT778-4

- - -

Fig 22. Package outline SOT778-4 (HVQFN48)

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

41 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

17. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate precautions are taken as

described in JESD625-A or equivalent standards.

18. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

18.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

42 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

18.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 23) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 20 and 21

Table 20. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 21. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 23.

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

43 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 23. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

19. Abbreviations

Table 22. Abbreviations

Acronym

ACK

Description

Acknowledge

CDM

DUT

Charged Device Model

Device Under Test

ESD

ElectroStatic Discharge

Field-Effect Transistor

Human Body Model

Inter-Integrated Circuit bus

Light Emitting Diode

Least Signiﬁcant Bit

Machine Model

FET

HBM

I²C-bus

LED

LSB

MM

MSB

Most Signiﬁcant Bit

Printed-Circuit Board

Pulse Width Modulation

Red/Green/Blue

PCB

PWM

RGB

RGBA

SMBus

Red/Green/Blue/Amber

System Management Bus

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

44 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

20. Revision history

Table 23. Revision history

Document ID

PCA9626_2

Modiﬁcations:

Release date

Data sheet status

Change notice

Supersedes

20090831

Product data sheet

-

PCA9626_1

• Table 11 “CHASE sequence” modiﬁed (corrected commands 02, 03, 04, 06; added additional

commands)

• Section 7.4 “Active LOW output enable input”: added 2^nd“Remark”

• Figure 17 “Typical application”: added “Remark”

• Added (new) Section 10.1 “Junction temperature calculation”

• Section 11 “Limiting values”:

–

Table 15 “Limiting values”: added “T_j, junction temperature” speciﬁcation

–

Added (new) Table 16 “LQFP48 versus HVQFN48 power dissipation and output current

capability”

• Added (new) Table 17 “Thermal characteristics”

• Table 18 “Static characteristics”, sub-section “LED driver outputs”: added I_LOHspeciﬁcation

PCA9626_1

20090602

Product data sheet

-

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

45 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

21. Legal information

21.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

21.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

21.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

21.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

22. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

PCA9626_2

Product data sheet

Rev. 02 — 31 August 2009

46 of 47

PCA9626

NXP Semiconductors

24-bit Fm+ I²C-bus 100 mA 40 V LED driver

23. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

12

13

14

15

16

17

Thermal characteristics . . . . . . . . . . . . . . . . . 35

Static characteristics . . . . . . . . . . . . . . . . . . . 36

Dynamic characteristics. . . . . . . . . . . . . . . . . 37

Test information. . . . . . . . . . . . . . . . . . . . . . . . 39

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 40

Handling information . . . . . . . . . . . . . . . . . . . 42

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

18

Soldering of SMD packages . . . . . . . . . . . . . . 42

Introduction to soldering. . . . . . . . . . . . . . . . . 42

Wave and reﬂow soldering . . . . . . . . . . . . . . . 42

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 42

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 43

18.1

18.2

18.3

18.4

7

7.1

7.1.1

7.1.2

7.1.3

7.1.4

7.2

Functional description . . . . . . . . . . . . . . . . . . . 7

Device addresses . . . . . . . . . . . . . . . . . . . . . . . 7

Regular I²C-bus slave address. . . . . . . . . . . . . 7

LED All Call I²C-bus address . . . . . . . . . . . . . . 8

LED Sub Call I²C-bus addresses . . . . . . . . . . . 8

Software Reset I²C-bus address . . . . . . . . . . . 8

Control register . . . . . . . . . . . . . . . . . . . . . . . . . 9

Register deﬁnitions . . . . . . . . . . . . . . . . . . . . . 10

Mode register 1, MODE1 . . . . . . . . . . . . . . . . 12

Mode register 2, MODE2 . . . . . . . . . . . . . . . . 12

PWM0 to PWM23, individual

brightness control . . . . . . . . . . . . . . . . . . . . . . 13

GRPPWM, group duty cycle control . . . . . . . . 14

GRPFREQ, group frequency . . . . . . . . . . . . . 14

CHASE control . . . . . . . . . . . . . . . . . . . . . . . . 15

LEDOUT0 to LEDOUT5, LED driver

19

20

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 44

Revision history . . . . . . . . . . . . . . . . . . . . . . . 45

21

Legal information . . . . . . . . . . . . . . . . . . . . . . 46

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 46

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 46

21.1

21.2

21.3

21.4

7.3

7.3.1

7.3.2

7.3.3

22

23

Contact information . . . . . . . . . . . . . . . . . . . . 46

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.3.4

7.3.5

7.3.6

7.3.7

output state. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SUBADR1 to SUBADR3, I²C-bus

7.3.8

subaddress 1 to 3 . . . . . . . . . . . . . . . . . . . . . . 23

ALLCALLADR, LED All Call I²C-bus address. 23

Active LOW output enable input . . . . . . . . . . . 24

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 24

Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 24

Individual brightness control with group

7.3.9

7.4

7.5

7.6

7.7

dimming/blinking. . . . . . . . . . . . . . . . . . . . . . . 25

8

Characteristics of the I²C-bus. . . . . . . . . . . . . 26

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

START and STOP conditions . . . . . . . . . . . . . 26

System conﬁguration . . . . . . . . . . . . . . . . . . . 26

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.1

8.1.1

8.2

8.3

9

Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 28

10

10.1

10.1.1

Application design-in information . . . . . . . . . 31

Junction temperature calculation . . . . . . . . . . 32

Example 1: T_jcalculation when T_ambis known

(PCA9626B, LQFP48) . . . . . . . . . . . . . . . . . . 33

Example 2: T_jcalculation where only T_caseis

known . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.1.2

11

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 34

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 31 August 2009

Document identifier: PCA9626_2


型号：	PCA9626B
厂家：	NXP
描述：	24-bit Fm I2C-bus 100 mA 40 V LED driver 24位调频I2C总线100毫安40 V的LED驱动器驱动器 PC
文件：	总47页 (文件大小：240K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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