PCA9633DP2,118_技术文档

PCA9633

4-bit Fm+ I²C-bus LED driver

Rev. 05 — 25 July 2008

Product data sheet

1. General description

The PCA9633 is an I²C-bus controlled 4-bit LED driver optimized for

Red/Green/Blue/Amber (RGBA) color mixing applications. Each LED output has its own

8-bit resolution (256 steps) ﬁxed frequency Individual PWM controller that operates at

97 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set

to a speciﬁc brightness value. A ﬁfth 8-bit resolution (256 steps) Group PWM controller

has both a ﬁxed frequency of 190 Hz and an adjustable frequency between 24 Hz to once

every 10.73 seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to

either dim or blink all LEDs with the same value.

Each LED output can be off, on (no PWM control), set at its Individual PWM controller

value or at both Individual and Group PWM controller values. The LED output driver is

programmed to be either open-drain with a 25 mA current sink capability at 5 V or totem

pole with a 25 mA sink, 10 mA source capability at 5 V. The PCA9633 operates with a

supply voltage range of 2.3 V to 5.5 V and the outputs are 5.5 V tolerant. LEDs can be

directly connected to the LED output (up to 25 mA, 5.5 V) or controlled with external

drivers and a minimum amount of discrete components for larger current or higher voltage

LEDs.

The PCA9633 is one of the ﬁrst LED controller devices in a new Fast-mode Plus (Fm+)

family. Fm+ devices offer higher frequency (up to 1 MHz) and more densely populated bus

operation (up to 4000 pF).

The active LOW Output Enable input pin (OE) allows asynchronous control of the LED

outputs and can be used to set all the outputs to a deﬁned I²C-bus programmable logic

state. The OE can also be used to externally PWM the outputs, which is useful when

multiple devices need to be dimmed or blinked together using software control. This

feature is available for the 16-pin version only.

Software programmable LED Group and three Sub Call I²C addresses allow all or deﬁned

groups of PCA9633 devices to respond to a common I²C address, allowing for example,

all red LEDs to be turned on or off at the same time or marquee chasing effect, thus

minimizing I²C-bus commands.

The PCA9633 is offered with 3 different I²C-bus address options: ﬁxed I²C-bus address

(8-pin version), 4 different I²C-bus addresses from 2 programmable address pins (10-pin

version), and 126 different I²C-bus addresses from 7 programmable address pins (16-pin

version). They are software identical except for the different number of address

combinations.

The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9633

through the I²C-bus, identical to the Power-On Reset (POR) that initializes the registers to

their default state causing the outputs to be set HIGH (LED off). This allows an easy and

quick way to reconﬁgure all device registers to the same condition.

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

2. Features

I 4 LED drivers. Each output programmable at:

N Off

N On

N Programmable LED brightness

N Programmable group dimming/blinking mixed with individual LED brightness

I 1 MHz Fast-mode Plus I²C-bus interface with 30 mA high drive capability on SDA

output for driving high capacitive buses

I 256-step (8-bit) linear programmable brightness per LED output varying from fully off

(default) to maximum brightness using a 97 kHz PWM signal

I 256-step group brightness control allows general dimming (using a 190 Hz PWM

signal) from fully off to maximum brightness (default)

I 256-step group blinking with frequency programmable from 24 Hz to 10.73 s and

duty cycle from 0 % to 99.6 %

I Four totem pole outputs (sink 25 mA and source 10 mA at 5 V) with software

programmable open-drain LED outputs selection (default at totem pole). No input

function.

I Output state change programmable on the Acknowledge or the STOP Command to

update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).

I Active LOW Output Enable (OE) input pin. LED outputs programmable to ‘1’, ‘0’ or

‘high-impedance’ (default at power-up) when OE is HIGH, thus allowing hardware

blinking and dimming of the LEDs (16-pin version only).

I 2 hardware address pins (10-pin version) and 7 hardware address pins (16-pin

version) allow respectively up to 4 and 126 devices to be connected to the same

I²C-bus. No hardware address pins in the 8-pin version.

I 4 software programmable I²C-bus addresses (one LED Group Call address and three

LED Sub Call addresses) allow groups of devices to be addressed at the same time in

any combination (for example, one register used for ‘All Call’ so that all the PCA9633s

on the I²C-bus can be addressed at the same time and the second register used for

three different addresses so that ¹⁄₃of all devices on the bus can be addressed at the

same time in a group). Software enable and disable for I²C-bus address.

I Software Reset feature (SWRST Call) allows the device to be reset through the

I²C-bus

I 25 MHz internal oscillator requires no external components

I Internal power-on reset

I Noise ﬁlter on SDA/SCL inputs

I Edge rate control on outputs

I No glitch on power-up

I Supports hot insertion

I Low standby current

I Operating power supply voltage range of 2.3 V to 5.5 V

I 5.5 V tolerant inputs

I −40 °C to +85 °C operation

I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

2 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

I Packages offered: SO, TSSOP (MSOP), HVQFN, HVSON

3. Applications

I RGB or RGBA LED drivers

I LED status information

I LED displays

I LCD backlights

I Keypad backlights for cellular phones or handheld devices

4. Ordering information

Table 1.

Ordering information

Type number

Topside

mark

Package

Name

Description

Version

PCA9633D16

PCA9633DP1

PCA9633

9633

SO16

plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

SOT505-1

TSSOP8

plastic thin shrink small outline package; 8 leads;

body width 3 mm

PCA9633DP2

PCA9633PW

PCA9633BS

PCA9633TK

9633

TSSOP10 plastic thin shrink small outline package; 10 leads;

body width 3 mm

SOT552-1

SOT403-1

PCA9633

9633

TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

HVQFN16 plastic thermal enhanced very thin quad ﬂat package; no leads; SOT629-1

16 terminals; body 4 × 4 × 0.85 mm

9633

HVSON8

plastic thermal enhanced very thin small outline package;

SOT908-1

no leads; 8 terminals; body 3 × 3 × 0.85 mm

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

3 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

5. Block diagram

16-pin version

10-pin version

A0 A1 A2 A3 A4 A5 A6

PCA9633

SCL

INPUT FILTER

SDA

2

I C-BUS

CONTROL

POWER-ON

RESET

V

DD

V

DD

V

SS

LED

STATE

SELECT

REGISTER

PWM

REGISTER X

BRIGHTNESS

CONTROL

LEDn

MUX/

CONTROL

24.3 kHz

97 kHz

GRPFREQ

REGISTER

GRPPWM

REGISTER

25 MHz

OSCILLATOR

190 Hz

'0' – permanently OFF

'1' – permanently ON

OE

(16-pin

version

only)

002aab283

Fig 1. Block diagram of PCA9633

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

4 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

6. Pinning information

6.1 Pinning

1

2

3

4

5

10

9

LED0

LED1

LED2

LED3

A0

V

DD

1

2

3

4

8

7

6

5

LED0

LED1

LED2

LED3

V

DD

SDA

SCL

A1

SDA

SCL

8

PCA9633DP2

PCA9633DP1

7

V

SS

6

V

SS

002aab314

002aab315

Fig 2. Pin conﬁguration for TSSOP8

Fig 3. Pin conﬁguration for TSSOP10

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

A0

A1

V

DD

A6

LED0

LED1

LED2

LED3

A2

A5

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

A0

A1

V

DD

A6

SDA

SCL

A4

PCA9633D16

LED0

LED1

LED2

LED3

A2

A5

SDA

SCL

A4

PCA9633PW

OE

A3

V

SS

A3

V

SS

002aab316

002aab313

Fig 4. Pin conﬁguration for TSSOP16

Fig 5. Pin conﬁguration for SO16

terminal 1

index area

terminal 1

index area

1

2

3

4

12

11

10

9

LED0

LED1

LED2

LED3

A5

1

2

3

4

8

7

6

5

LED0

LED1

LED2

LED3

V

DD

SDA

SCL

A4

PCA9633BS

SDA

SCL

PCA9633TK

V

SS

002aab317

002aab807

Transparent top view

Fig 6. Pin conﬁguration for HVQFN16

Fig 7. Pin conﬁguration for HVSON8

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

5 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

6.2 Pin description

Table 2.

Symbol

LED0

LED1

LED2

LED3

V_SS

Pin description for TSSOP8 and HVSON8

1

Type

Description

LED driver 0

LED driver 1

LED driver 2

LED driver 3

supply ground

serial clock line

serial data line

supply voltage

O

2

O

3

O

4

O

5

power supply

SCL

6

I

SDA

7

I/O

V_DD

8

power supply

Table 3.

Symbol

LED0

LED1

LED2

LED3

A0

Pin description for TSSOP10

1

Type

Description

O

LED driver 0

2

O

LED driver 1

3

O

LED driver 2

4

O

LED driver 3

5

I

address input 0

supply ground

address input 1

serial clock line

serial data line

supply voltage

V_SS

6

power supply

A1

7

I

SCL

8

I

SDA

9

I/O

V_DD

10

power supply

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

6 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

Table 4.

Pin description for SO16 and TSSOP16

Symbol

A0

1

Type

Description

I

address input 0

address input 1

LED driver 0

A1

2

I

LED0

LED1

LED2

LED3

A2

3

O

4

O

LED driver 1

5

O

LED driver 2

6

O

LED driver 3

7

I

address input 2

address input 3

supply ground

active LOW Output Enable

address input 4

serial clock line

serial data line

address input 5

address input 6

supply voltage

A3

8

I

V_SS

OE

9

power supply

10

11

12

13

14

15

16

I

A4

I

SCL

SDA

A5

I

I/O

I

A6

I

V_DD

power supply

Table 5.

Symbol

LED0

LED1

LED2

LED3

A2

Pin description for HVQFN16

1

Type

Description

O

LED driver 0

2

O

LED driver 1

3

O

LED driver 2

4

O

LED driver 3

5

I

address input 2

address input 3

supply ground

active LOW Output Enable

address input 4

serial clock line

serial data line

address input 5

address input 6

supply voltage

address input 0

address input 1

A3

6

I

[1]

V_SS

7

power supply

OE

A4

8

I

9

I

SCL

SDA

A5

10

11

12

13

14

15

16

I

I/O

I

A6

I

V_DD

A0

power supply

I

A1

[1] HVQFN16 package die supply ground is connected to both the V_SSpin and the exposed center pad. The

V_SSpin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,

and board-level performance, the exposed pad needs to be soldered to the board using a corresponding

thermal pad on the board, and for proper heat conduction through the board thermal vias need to be

incorporated in the PCB in the thermal pad region.

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

7 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

7. Functional description

Refer to Figure 1 “Block diagram of PCA9633”.

7.1 Device addresses

Following a START condition, the bus master must output the address of the slave it is

accessing.

There are a maximum of 128 possible programmable addresses using the 7 hardware

address pins. Two of these addresses, Software Reset and LED All Call, cannot be used

because their default power-up state is ON, leaving a maximum of 126 addresses. Using

other reserved addresses, as well as any other subcall address, will reduce the total

number of possible addresses even further.

7.1.1 Regular I²C-bus slave address

The I²C-bus slave address of the PCA9633 is shown in Figure 8. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW (10-pin and 16-pin versions).

Remark: Using reserved I²C-bus addresses will interfere with other devices, but only if the

devices are on the bus and/or the bus will be open to other I²C-bus systems at some later

date. In a closed system where the designer controls the address assignment these

addresses can be used since the PCA9633 treats them like any other address. The

LED All Call, Software Reset and PCA9564 or PCA9665 slave address (if on the bus) can

never be used for individual device addresses.

• PCA9633 LED All Call address (1110 000) and Software Reset (0000 0110) which

are active on start-up

• PCA9564 (0000 000) or PCA9665 (1110 000) slave address which is active on

start-up

• ‘reserved for future use’ I²C-bus addresses (0000 011, 1111 1XX)

• slave devices that use the 10-bit addressing scheme (1111 0XX)

• slave devices that are designed to respond to the General Call address (0000 000)

• High-speed mode (Hs-mode) master code (0000 1XX).

slave address

1

0

A1 A0 R/W

1

0

1

0

R/W

A6 A5 A4 A3 A2 A1 A0 R/W

fixed

hardware

selectable

fixed

hardware selectable

002aab319

002aab318

002aab295

a. 8-pin version

b. 10-pin version

c. 16-pin version

Fig 8. Slave address

The last bit of the address byte deﬁnes the operation to be performed. When set to logic 1

a read is selected, while a logic 0 selects a write operation.

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

8 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

7.1.2 LED All Call I²C-bus address

• Default power-up value (ALLCALLADR register): E0h or 1110 000X

• Programmable through I²C-bus (volatile programming)

• At power-up, LED All Call I²C-bus address is enabled. PCA9633 sends an ACK when

E0h (R/W = 0) or E1h (R/W = 1) is sent by the master.

See Section 7.3.8 “LED All Call I²C-bus address, ALLCALLADR” for more detail.

Remark: The default LED All Call I²C-bus address (E0h or 1110 000X) must not be used

as a regular I²C-bus slave address since this address is enabled at power-up. All the

PCA9633s on the I²C-bus will acknowledge the address if sent by the I²C-bus master.

7.1.3 LED Sub Call I²C-bus addresses

• 3 different I²C-bus addresses can be used

• Default power-up values:

– SUBADR1 register: E2h or 1110 001X

– SUBADR2 register: E4h or 1110 010X

– SUBADR3 register: E8h or 1110 100X

• Programmable through I²C-bus (volatile programming)

• At power-up, Sub Call I²C-bus addresses are disabled. PCA9633 does not send an

ACK when E2h (R/W = 0) or E3h (R/W = 1), E4h (R/W = 0) or E5h (R/W = 1), or

E8h (R/W = 0) or E9h (R/W = 1) is sent by the master.

See Section 7.3.7 “I²C-bus subaddress 1 to 3, SUBADRx” for more detail.

Remark: The default LED Sub Call I²C-bus addresses may be used as regular I²C-bus

slave addresses as long as they are disabled.

7.1.4 Software Reset I²C-bus address

The address shown in Figure 9 is used when a reset of the PCA9633 needs to be

performed by the master. The Software Reset address (SWRST Call) must be used with

R/W = 0. If R/W = 1, the PCA9633 does not acknowledge the SWRST. See Section 7.6

“Software Reset” for more detail.

R/W

0

1

0

002aab416

Fig 9. Software Reset address

Remark: The Software Reset I²C-bus address is a reserved address and cannot be used

as a regular I²C-bus slave address (16-pin version) or as an LED All Call or LED Sub Call

address.

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

9 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

7.2 Control register

Following the successful acknowledgement of the slave address, LED All Call address or

LED Sub Call address, the bus master will send a byte to the PCA9633, which will be

stored in the Control register.

The lowest 4 bits are used as a pointer to determine which register will be accessed

(D[3:0]). The highest 3 bits are used as Auto-Increment ﬂag and Auto-Increment options

(AI[2:0]). Bit 4 is unused and must be programmed with zero (0) for proper device

operation.

register address

AI2 AI1 AI0

0

D3 D2 D1 D0

002aab296

Auto-Increment options

Auto-Increment flag

reset state = 80h

Remark: The Control register does not apply to the Software Reset I²C-bus address.

Fig 10. Control register

When the Auto-Increment ﬂag is set (AI2 = 1), the four low order bits of the Control

register are automatically incremented after a read or write. This allows the user to

program the registers sequentially. Four different types of Auto-Increment are possible,

depending on AI1 and AI0 values.

Table 6.

Auto-Increment options

AI2

0

AI1

0

AI0

0

Function

no Auto-Increment

1

0

Auto-Increment for all registers. D3, D2, D1, D0 roll over to ‘0000’ after

the last register (1100) is accessed.

1

0

1

0

1

Auto-Increment for individual brightness registers only. D3, D2, D1, D0

roll over to ‘0010’ after the last register (0101) is accessed.

Auto-Increment for global control registers only. D3, D2, D1, D0 roll over

to ‘0110’ after the last register (0111) is accessed.

Auto-Increment for individual and global control registers only. D3, D2,

D1, D0 roll over to ‘0010’ after the last register (0111) is accessed.

Remark: Other combinations not shown in Table 6 (AI[2:0] = 001, 010, and 011) are

reserved and must not be used for proper device operation.

AI[2:0] = 000 is used when the same register must be accessed several times during a

single I²C-bus communication, for example, changes the brightness of a single LED. Data

is overwritten each time the register is accessed during a write operation.

AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example,

power-up programming.

AI[2:0] = 101 is used when the four LED drivers must be individually programmed with

different values during the same I²C-bus communication, for example, changing color

setting to another color setting.

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

10 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

AI[2:0] = 110 is used when the LED drivers must be globally programmed with different

settings during the same I²C-bus communication, for example, global brightness or

blinking change.

AI[2:0] = 111 is used when individual and global changes must be performed during the

same I²C-bus communication, for example, changing a color and global brightness at the

same time.

Only the 4 least signiﬁcant bits D[3:0] are affected by the AI[2:0] bits.

When the Control register is written, the register entry point determined by D[3:0] is the

ﬁrst register that will be addressed (read or write operation), and can be anywhere

between 0000 and 1100 (as deﬁned in Table 7). When AI[2] = 1, the Auto-Increment ﬂag

is set and the rollover value at which the point where the register increment stops and

goes to the next one is determined by AI[2:0]. See Table 6 for rollover values. For

example, if the Control register = 1110 1000 (E8h), then the register addressing sequence

will be (in hex):

08 → … → 0C → 00 → … → 07 → 02 → … → 07 → 02 → … → 07 → 02 → … as long

as the master keeps sending or reading data.

7.3 Register deﬁnitions

Table 7.

Register number (hex) D3

Register summary^[1][2]

D2

0

1

0

1

D1

0

1

0

1

0

1

0

D0

0

1

0

1

0

1

0

1

0

1

0

1

0

Name

Type

Function

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0

1

MODE1

read/write

Mode register 1

MODE2

Mode register 2

PWM0

brightness control LED0

brightness control LED1

brightness control LED2

brightness control LED3

group duty cycle control

group frequency

PWM1

PWM2

PWM3

GRPPWM

GRPFREQ

LEDOUT

SUBADR1

SUBADR2

SUBADR3

ALLCALLADR

LED output state

I²C-bus subaddress 1

I²C-bus subaddress 2

I²C-bus subaddress 3

LED All Call I²C-bus address

[1] Only D[3:0] = 0000 to 1100 are allowed and will be acknowledged. D[3:0] = 1101, 1110, or 1111 are reserved and will not be

acknowledged.

[2] When writing to the Control register, bit 4 must be programmed with logic 0 for proper device operation.

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

11 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

7.3.1 Mode register 1, MODE1

Table 8.

MODE1 - Mode register 1 (address 00h) bit description

Legend: * default value.

Bit

Symbol

Access

Value

0

Description

7

AI2

read only

Register Auto-Increment disabled

Register Auto-Increment enabled

Auto-Increment bit 1 = 0

Auto-Increment bit 1 = 1

Auto-Increment bit 0 = 0

Auto-Increment bit 0 = 1

Normal mode^[1].

Low power mode. Oscillator off^[2].

PCA9633 does not respond to I²C-bus subaddress 1.

PCA9633 responds to I²C-bus subaddress 1.

PCA9633 does not respond to I²C-bus subaddress 2.

PCA9633 responds to I²C-bus subaddress 2.

PCA9633 does not respond to I²C-bus subaddress 3.

PCA9633 responds to I²C-bus subaddress 3.

PCA9633 does not respond to LED All Call I²C-bus address.

PCA9633 responds to LED All Call I²C-bus address.

1*

0*

1

6

5

4

3

2

1

0

AI1

read only

R/W

AI0

0*

1

SLEEP

SUB1

SUB2

SUB3

ALLCALL

0

1*

0*

1

R/W

0*

1

R/W

0*

1

R/W

0

1*

[1] It takes 500 µs max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not

guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 µs window.

[2] When the oscillator is off (Sleep mode) the LED outputs cannot be turned on, off or dimmed/blinked.

7.3.2 Mode register 2, MODE2

Table 9.

MODE2 - Mode register 2 (address 01h) bit description

Legend: * default value.

Bit

7

Symbol

Access

read only

R/W

Value

0*

Description

-

reserved

6

-

0*

reserved

5

DMBLNK

0*

Group control = dimming

Group control = blinking

1

4

INVRT^[1]

R/W

0*

Output logic state not inverted. Value to use when no external driver used.

Applicable when OE = 0 for PCA9633 16-pin version.

1

Output logic state inverted. Value to use when external driver used.

Applicable when OE = 0 for PCA9633 16-pin version.

3

2

OCH

R/W

0*

1

Outputs change on STOP command.^[2]

Outputs change on ACK.

OUTDRV^[1]

0

The 4 LED outputs are conﬁgured with an open-drain structure.

The 4 LED outputs are conﬁgured with a totem pole structure.

1*

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

12 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

Table 9.

MODE2 - Mode register 2 (address 01h) bit description …continued

Legend: * default value.

Bit

Symbol

Access

Value

00

Description

1 to 0 OUTNE[1:0] R/W

When OE = 1 (output drivers not enabled), LEDn = 0.

When OE = 1 (output drivers not enabled):

LEDn = 1 when OUTDRV = 1

[3][4]

01*

LEDn = high-impedance when OUTDRV = 0 (same as OUTNE[1:0] = 10)

When OE = 1 (output drivers not enabled), LEDn = high-impedance.

reserved

10

11

[1] See Section 7.7 “Using the PCA9633 with and without external drivers” for more details. Normal LEDs can be driven directly in either

mode. Some newer LEDs include integrated Zener diodes to limit voltage transients, reduce EMI and protect the LEDs, and these must

be driven only in the open-drain mode to prevent overheating the IC.

[2] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9633. Applicable to registers from

02h (PWM0) to 08h (LEDOUT) only.

[3] See Section 7.4 “Active LOW output enable input” for more details.

[4] OUTNE[1:0] is only for PCA9633 16-pin version.

7.3.3 PWM registers 0 to 3, PWMx — Individual brightness control registers

Table 10. PWM0 to PWM3 - PWM registers 0 to 3 (address 02h to 05h) bit description

Legend: * default value.

Address Register Bit

Symbol

Access Value

Description

02h

03h

04h

05h

PWM0

PWM1

PWM2

PWM3

7:0

IDC0[7:0]

IDC1[7:0]

IDC2[7:0]

IDC3[7:0]

R/W

0000 0000* PWM0 Individual Duty Cycle

0000 0000* PWM1 Individual Duty Cycle

0000 0000* PWM2 Individual Duty Cycle

0000 0000* PWM3 Individual Duty Cycle

A 97 kHz ﬁxed frequency signal is used for each output. Duty cycle is controlled through

256 linear steps from 00h (0 % duty cycle = LED output off) to FFh

(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs

programmed with LDRx = 10 or 11 (LEDOUT register).

IDC[7:0]

duty cycle =

(1)

------------------------

256

7.3.4 Group duty cycle control, GRPPWM

Table 11. GRPPWM - Group duty cycle control register (address 06h) bit description

Legend: * default value.

Address Register

06h GRPPWM

Bit Symbol

Access Value

Description

7:0 GDC[7:0]

R/W 1111 1111 GRPPWM register

When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz ﬁxed frequency

signal is superimposed with the 97 kHz individual brightness control signal. GRPPWM is

then used as a global brightness control allowing the LED outputs to be dimmed with the

same value. The value in GRPFREQ is then a ‘Don’t care’.

General brightness for the 4 outputs is controlled through 256 linear steps from 00h

(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

13 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

When DMBLNK bit is programmed with 1, GRPPWM and GRPFREQ registers deﬁne a

global blinking pattern, where GRPFREQ contains the blinking period (from 24 Hz to

10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).

GDC[7:0]

duty cycle =

(2)

--------------------------

256

7.3.5 Group frequency, GRPFREQ

Table 12. GRPFREQ - Group Frequency register (address 07h) bit description

Legend: * default value.

Address Register

Bit Symbol

Access Value

Description

07h GRPFREQ 7:0 GFRQ[7:0] R/W

0000 0000* GRPFREQ register

GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2

register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).

Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)

to FFh (10.73 s).

GFRQ[7:0] + 1

global blinking period =

(in seconds)

(3)

---------------------------------------

24

7.3.6 LED driver output state, LEDOUT

Table 13. LEDOUT - LED driver output state register (address 08h) bit description

Legend: * default value.

Address Register

08h LEDOUT

Bit Symbol

7:6 LDR3

5:4 LDR2

3:2 LDR1

1:0 LDR0

Access Value

Description

R/W

00*

LED3 output state control

LED2 output state control

LED1 output state control

LED0 output state control

LDRx = 00 — LED driver x is off (default power-up state).

LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking

not controlled).

LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx

register.

LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be

controlled through its PWMx register and the GRPPWM registers.

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

14 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

7.3.7 I²C-bus subaddress 1 to 3, SUBADRx

Table 14. SUBADR1 to SUBADR3 - I²C-bus subaddress registers 0 to 3 (address 09h to

0Bh) bit description

Legend: * default value.

Address Register

Bit

7:1

0

Symbol

A1[7:1]

A1[0]

Access Value

Description

1110 001* I²C-bus subaddress 1

0* reserved

1110 010* I²C-bus subaddress 2

0* reserved

1110 100* I²C-bus subaddress 3

0* reserved

09h

0Ah

0Bh

SUBADR1

SUBADR2

SUBADR3

R/W

R only

R/W

7:1

0

A2[7:1]

A2[0]

R only

R/W

7:1

0

A3[7:1]

A3[0]

R only

Subaddresses are programmable through the I²C-bus. Default power-up values are E2h,

E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up

(the corresponding SUBx bit in MODE1 register is equal to 0).

Once subaddresses have been programmed to their right values, SUBx bits need to be

set to 1 in order to have the device acknowledging these addresses (MODE1 register).

Only the 7 MSBs representing the I²C-bus subaddress are valid. The LSB in SUBADRx

register is a read-only bit (0).

When SUBx is set to 1, the corresponding I²C-bus subaddress can be used during either

an I²C-bus read or write sequence.

7.3.8 LED All Call I²C-bus address, ALLCALLADR

Table 15. ALLCALLADR - LED All Call I²C-bus address register (address 0Ch) bit

description

Legend: * default value.

Address Register

Bit

Symbol Access Value

Description

0Ch

ALLCALLADR 7:1

AC[7:1]

R/W

1110 000* ALLCALL I²C-bus

address register

0

AC[0]

R only

0*

reserved

The LED All Call I²C-bus address allows all the PCA9633s in the bus to be programmed

at the same time (ALLCALL bit in register MODE1 must be equal to 1, power-up default

state). This address is programmable through the I²C-bus and can be used during either

an I²C-bus read or write sequence. The register address can be programmed as a

sub call.

Only the 7 MSBs representing the All Call I²C-bus address are valid. The LSB in

ALLCALLADR register is a Read-only bit (0).

If ALLCALL bit = 0, the device does not acknowledge the address programmed in register

ALLCALLADR.

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

15 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

7.4 Active LOW output enable input

The active LOW output enable (OE) pin, allows to enable or disable all the LED outputs at

the same time.

This control signal is only available for the 16-pin version and does not apply to the 8-pin

or 10-pin versions.

• When a LOW level is applied to OE pin, all the LED outputs are enabled and follow the

output state deﬁned in the LEDOUT register with the polarity deﬁned by INVRT bit

(MODE2 register).

• When a HIGH level is applied to OE pin, all the LED outputs are programmed to the

value that is deﬁned by OUTNE[1:0] in the MODE2 register.

Table 16. LED outputs when OE = 1

OUTNE1

OUTNE0

LED outputs

0

1

0

1

0

1

0

1 if OUTDRV = 1, high-impedance if OUTDRV = 0

high-impedance

reserved

The OE pin can be used as a synchronization signal to switch on/off several PCA9633

devices at the same time. This requires an external clock reference that provides blinking

period and the duty cycle.

The OE pin can also be used as an external dimming control signal. The frequency of the

external clock must be high enough not to be seen by the human eye, and the duty cycle

value determines the brightness of the LEDs.

Remark: Do not use OE as an external blinking control signal when internal global

blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an undeﬁned

blinking pattern. Do not use OE as an external dimming control signal when internal global

dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an undeﬁned

dimming pattern.

7.5 Power-on reset

When power is applied to V_DD, an internal Power-on reset holds the PCA9633 in a reset

condition until V_DDhas reached V_POR. At this point, the reset condition is released and the

PCA9633 registers and I²C-bus state machine are initialized to their default states (all

zeroes) causing all the channels to be deselected. Thereafter, V_DDmust be lowered below

0.2 V to reset the device.

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

16 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

7.6 Software Reset

The Software Reset Call (SWRST Call) allows all the devices in the I²C-bus to be reset to

the power-up state value through a speciﬁc formatted I²C-bus command. To be performed

correctly, it implies that the I²C-bus is functional and that there is no device hanging the

bus.

The SWRST Call function is deﬁned as the following:

1. A START command is sent by the I²C-bus master.

2. The reserved SWRST I²C-bus address ‘0000 011’ with the R/W bit set to 0 (write) is

sent by the I²C-bus master.

3. The PCA9633 device(s) acknowledge(s) after seeing the SWRST Call address

‘0000 0110’ (06h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to

the I²C-bus master.

4. Once the SWRST Call address has been sent and acknowledged, the master sends

2 bytes with 2 speciﬁc values (SWRST data byte 1 and byte 2):

a. Byte 1 = A5h: the PCA9633 acknowledges this value only. If byte 1 is not equal to

A5h, the PCA9633 does not acknowledge it.

b. Byte 2 = 5Ah: the PCA9633 acknowledges this value only. If byte 2 is not equal to

5Ah, then the PCA9633 does not acknowledge it.

If more than 2 bytes of data are sent, the PCA9633 does not acknowledge any more.

5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and

correctly acknowledged, the master sends a STOP command to end the SWRST Call:

the PCA9633 then resets to the default value (power-up value) and is ready to be

addressed again within the speciﬁed bus free time (t_BUF).

The I²C-bus master must interpret a non-acknowledge from the PCA9633 (at any time) as

a ‘SWRST Call Abort’. The PCA9633 does not initiate a reset of its registers. This

happens only when the format of the SWRST Call sequence is not correct.

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

17 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

7.7 Using the PCA9633 with and without external drivers

The PCA9633 LED output drivers are 5.5 V only tolerant and can sink up to 25 mA at 5 V.

If the device needs to drive LEDs to a higher voltage and/or higher current, use of an

external driver is required.

• INVRT bit (MODE2 register) can be used to keep the LED PWM control ﬁrmware the

same (PWMx and GRPPWM values directly calculated from their respective formulas

and the LED output state determined by LEDOUT register value) independently of the

type of external driver. This bit allows LED output polarity inversion/non-inversion only

when OE = 0.

• OUTDRV bit (MODE2 register) allows minimizing the amount of external components

required to control the external driver (N-type or P-type device).

Table 17. Use of INVRT and OUTDRV based on connection to the LEDn outputs when OE = 0^[1]

INVRT OUTDRV Direct connection to LEDn

External N-type driver

External P-type driver

Firmware

External

Firmware External

pull-up

resistor

0

1

0

1

0

1

formulas and LED

output state values

apply^[2]

LED current formulas and LED required

limiting R^[2]output state

values inverted

formulas and LED required

output state values

apply

formulas and LED

output state values

apply^[2]

LED current formulas and LED not required formulas and LED not

limiting R^[2]output state

values inverted

output state values required^[4]

apply^[4]

formulas and LED

output state values

inverted

LED current formulas and LED required

formulas and LED required

output state values

inverted

limiting R

output state

values apply

formulas and LED

output state values

inverted

LED current formulas and LED not

formulas and LED not required

output state values

inverted

limiting R

output state

values apply^[3]

required^[3]

[1] OE applies to 16-pin version only. When OE = 1, LED output state is controlled only by OUTNE[1:0] bits (MODE2 register).

[2] Correct conﬁguration when LEDs directly connected to the LEDn outputs (connection to V_DDthrough current limiting resistor).

[3] Optimum conﬁguration when external N-type (NPN, NMOS) driver used.

[4] Optimum conﬁguration when external P-type (PNP, PMOS) driver used.

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

18 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

Table 18. Output transistors based on LEDOUT registers, INVRT and OUTDRV bits when OE = 0^[1]

LEDOUT

INVRT OUTDRV Upper transistor Lower transistor LEDn state

(V_DDto LEDn)

(LEDn to V_SS)

00

0

1

0

1

0

1

0

1

0

1

0

1

0

off

on

off

on

off

on

off

high-Z^[2]

LED driver off

V_DD

V_SS

01

V_SS

LED driver on

V_SS

high-Z^[2]

V_DD

10

Individual PWM

(non-inverted)

V_SSor high-Z^[2]= PWMx value

Individual

brightness

control

0

1

0

1

0

1

0

Individual PWM

(non-inverted)

Individual PWM

(non-inverted)

V_SSor V_DD= PWMx value

off

Individual PWM

(inverted)

high-Z^[2]or V_SS= 1 − PWMx value

V_DDor V_SS= 1 − PWMx value

Individual PWM

(inverted)

Individual PWM

(inverted)

11

off

Individual + Group V_SSor high-Z^[2]= PWMx/GRPPWM values

PWM

(non-inverted)

Individual +

Group

dimming/blinking

0

1

0

1

Individual PWM

(non-inverted)

Individual PWM

(non-inverted)

Individual + Group high-Z^[2]or V_SS= (1 − PWMx) or

V_SSor V_DD= PWMx/GRPPWM values

off

PWM (inverted)

(1 − GRPPWM) values

Individual PWM

(inverted)

Individual PWM

(inverted)

V_DDor V_SS= (1 − PWMx) or

(1 − GRPPWM) values

[1] OE applies to 16-pin version only. When OE = 1, LED output state is controlled only by OUTNE[1:0] bits (MODE2 register).

[2] External pull-up or LED current limiting resistor connects LEDn to V_DD

.

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

19 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

7.8 Individual brightness control with group dimming/blinking

A 97 kHz ﬁxed frequency signal with programmable duty cycle (8 bits, 256 steps) is used

to control individually the brightness for each LED.

On top of this signal, one of the following signals can be superimposed (this signal can be

applied to the 4 LED outputs):

• A lower 190 Hz ﬁxed frequency signal with programmable duty cycle (8 bits,

256 steps) is used to provide a global brightness control.

• A programmable frequency signal from 24 Hz to ¹⁄_10.73Hz (8 bits, 256 steps) with

programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking

control.

508

510

512

1

2

3

4

5

6

7

8

9

10 11 12

507

509

511

1

2

3

4

5

6

7

8

9

10 11

Brightness Control signal (LEDn)

N × 40 ns

with N = (0 to 255)

(PWMx Register)

M × 256 × 2 × 40 ns

with M = (0 to 255)

(GRPPWM Register)

256 × 40 ns = 10.24 µs

(97.6 kHz)

Group Dimming signal

256 × 2 × 256 × 40 ns = 5.24 ms (190.7 Hz)

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

002aab417

resulting Brightness + Group Dimming signal

Minimum pulse width for LEDn Brightness Control is 40 ns.

Minimum pulse width for Group Dimming is 20.48 µs.

When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal will have 2 pulses of

the LED Brightness Control signal (pulse width = N × 40 ns, with ‘N’ deﬁned in PWMx register).

This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 4 (8 pulses).

Fig 11. Brightness + Group Dimming signals

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

20 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

8. Characteristics of the I²C-bus

The I²C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 12).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 12. Bit transfer

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P) (see Figure 13).

SDA

SCL

SDA

SCL

S

P

STOP condition

START condition

mba608

Fig 13. Deﬁnition of START and STOP conditions

8.2 System conﬁguration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 14).

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

21 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

SDA

SCL

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

2

SLAVE

RECEIVER

MASTER

TRANSMITTER

I C-BUS

MULTIPLEXER

SLAVE

002aaa966

Fig 14. System conﬁguration

8.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold

time must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from master

1

2

8

9

S

clock pulse for

START

condition

acknowledgement

002aaa987

Fig 15. Acknowledgement on the I²C-bus

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

22 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

9. Bus transactions

(1)

(2)

slave address

control register

D3 D2 D1 D0

data for register D3, D2, D1, D0

S

A6 A5 A4 A3 A2 A1 A0

0

A

X

0

A

P

Auto-Increment options

Auto-Increment flag

START condition

R/W

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

STOP

condition

002aab418

(1) 16-pin version only.

(2) See Table 7 for register deﬁnition.

Fig 16. Write to a speciﬁc register

(1)

slave address

control register

MODE1 register

MODE2 register

(cont.)

S

A6 A5 A4 A3 A2 A1 A0

0

A

1

0

A

MODE1

register

selection

Auto-Increment

on all registers

acknowledge

from slave Auto-Increment on

START condition

R/W

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

SUBADR3 register

ALLCALLADR register

(cont.)

A

P

acknowledge

from slave

acknowledge

from slave

STOP

condition

002aab419

(1) 16-pin version only.

Fig 17. Write to all registers using the Auto-Increment feature

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

23 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

(1)

slave address

control register

PWM0 register

PWM1 register

(cont.)

A

S

A6 A5 A4 A3 A2 A1 A0

0

A

1

0

1

0

1

0

A

PWM0

register

selection

increment

START condition

R/W

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

on Individual

brightness

acknowledge

from slave

registers only

Auto-Increment on

PWM3 register

PWM2 register

PWM0 register

PWMx register

(cont.)

A

P

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

STOP

condition

002aab420

(1) 16-pin version only.

Fig 18. Multiple writes to Individual Brightness registers only using the Auto-Increment feature

ReSTART

condition

(1)

slave address

control register

slave address

data from MODE1 register

(cont.)

S

A6 A5 A4 A3 A2 A1 A0

0

A

1

0

A

Sr A6 A5 A4 A3 A2 A1 A0

1

A

MODE1

register

selection

Auto-Increment

on all registers

acknowledge

from slave Auto-Increment on

START condition

R/W

acknowledge

from slave

R/W

acknowledge

from master

acknowledge

from slave

data from

ALLCALLADR register

data from

MODE1 register

data from MODE2 register

data from PWM0

(cont.)

A

(cont.)

A

acknowledge

from master

acknowledge

from master

acknowledge

from master

acknowledge

from master

data from last read byte

(cont.)

A

P

not acknowledge STOP

from master condition

002aab423

(1) 16-pin version only.

Fig 19. Read all registers using the Auto-Increment feature

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

24 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

(1)

2

(2)

X

slave address

control register

new LED All Call I C address

sequence (A)

S

1

0

A1 A0

0

A

X

0

1

0

A

1

0

1

0

1

0

1

A

P

ALLCALLADR

START condition

R/W

acknowledge

from slave

acknowledge

from slave

register selection

acknowledge

from slave

Auto-Increment on

STOP

condition

(3)

the 16 LEDs are on at the acknowledge

LEDOUT register (LED fully ON)

2

LED All Call I C address

control register

sequence (B)

S

1

0

1

0

1

0

1

0

A

X

0

1

0

A

0

1

0

1

0

1

0

1

A

P

LEDOUT

register selection

START condition

R/W

acknowledge

from the

4 devices

acknowledge

from the

acknowledge

from the

4 devices

STOP

condition

4 devices

002aab424

(1) 10-pin version is used for this ﬁgure. Four PCA9633DP2s are used and the same sequence (A) (above) is sent to each of them.

A[1:0] = 00 to 11.

(2) ALLCALL bit in MODE1 register is equal to 1 for this example.

(3) OCH bit in MODE2 register is equal to 1 for this example.

Fig 20. LED All Call I²C-bus address programming and LED All Call sequence example

SWRST data

Byte 1 = A5h

SWRST data

Byte 2 = 5Ah

2

SWRST Call I C address

S

0

1

0

A

1

0

1

0

1

0

1

A

0

1

0

1

0

1

0

A

P

START condition

R/W

acknowledge

from slave(s)

acknowledge

from slave(s)

acknowledge

from slave(s)

PCA9633(s) is(are) reset.

Registers are set to default power-up values.

002aab425

Fig 21. Software Reset (SWRST) Call sequence

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

25 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

10. Application design-in information

5 V

12 V

V

= 2.5 V, 3.3 V or 5.0 V

DD

(1)

10 kΩ

2

I C-BUS/SMBus

MASTER

SDA

V

DD

SDA

SCL

LED0

SCL

LED1

LED2

OE

LED3

PCA9633

A0

A1

A2

A3

A4

A5

A6

V

SS

002aab286

I²C-bus address = 0010 101X.

All of the 4 LEDn outputs conﬁgurable as either open-drain or totem pole. Mixing of conﬁgurations is not possible.

(1) OE requires pull-up resistor if control signal from the master is open-drain.

Fig 22. Typical application

Question 1: What kind of edge rate control is there on the outputs?

• The typical edge rates depend on the output conﬁguration, supply voltage, and the

applied load. The outputs can be conﬁgured as either open-drain NMOS or totem pole

outputs. If the customer is using the part to directly drive LEDs, they should be using it

in an open-drain NMOS, if they are concerned about the maximum ISS and ground

bounce. The edge rate control was designed primarily to slow down the turn-on of the

output device; it turns off rather quickly (~1.5 ns). In simulation, the typical turn-on

time for the open-drain NMOS was ~14 ns (V_DD= 3.6 V; C_L= 50 pF; R_PU= 500 Ω).

Question 2: Is ground bounce possible?

• Ground bounce is a possibility, especially if all 16 outputs are changed at full current

(25 mA each). There is a fair amount of decoupling capacitance on chip (~50 pF),

which is intended to suppress some of the ground bounce. The customer will need to

determine if additional decoupling capacitance externally placed as close as

physically possible to the device is required.

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

26 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

Question 3: Can I really sink 400 mA through the single ground pin on the package and

will this cause any ground bounce problem due to the PWM of the LEDs?

• Yes, you can sink 400 mA through a single ground pin on the package. Although the

package only has one ground pin, there are two ground pads on the die itself

connected to this one pin. Although some ground bounce is likely, it will not disrupt the

operation of the part and would be reduced by the external decoupling capacitance.

Question 4: I can’t turn the LEDs on or off, but their registers are set properly. Why?

• Check the Mode Register 1 bit 4 SLEEP setting. The value needs to be 0 so that the

OSC is turn on. If the OSC is turned off, the LEDs cannot be turned on or off and also

can’t be dimmed or blinked.

Question 5: I’m using LEDs with integrated Zener diodes and the IC is getting very hot.

Why?

• The IC outputs can be set to either open-drain or push-pull and default to push-pull

outputs. In this application with the Zener diodes, they need to be set to open-drain

since in the push-pull architecture there is a low resistance path to GND through the

Zener and this is causing the IC to overheat. The PCA9632/33/34/35 ICs all power-up

in the push-pull output mode and with the logic state HIGH, so one of the ﬁrst things

that need to be done is to set the outputs to open-drain.

11. Limiting values

Table 19. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

Parameter

Conditions

Min

Max

+6.0

5.5

Unit

V

supply voltage

−0.5

V_I/O

voltage on an input/output pin

output current on pin LEDn

ground supply current

total power dissipation

storage temperature

ambient temperature

V

_SS− 0.5

V

I_O(LEDn)

I_SS

-

25

mA

mW

°C

-

100

400

+150

+85

P_tot

-

T_stg

−65

−40

T_amb

operating

°C

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

27 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

12. Static characteristics

Table 20. Static characteristics

V_DD= 2.3 V to 5.5 V; V_SS= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Supply

Conditions

Min

Typ

Max

Unit

V_DD

I_DD

supply voltage

supply current

2.3

-

5.5

V

operating mode; no load; f_SCL= 1 MHz

V_DD= 2.3 V

-

2.5

10

mA

V_DD= 3.3 V

V_DD= 5.5 V

I_stb

standby current

no load; f_SCL= 0 Hz; I/O = inputs; V_I= V_DD

V_DD= 2.3 V

-

2.3

2.9

11

µA

V

V_DD= 3.3 V

12

V_DD= 5.5 V

3.8

15.5

2.0

[1]

V_POR

power-on reset voltage

no load; V_I= V_DDor V_SS

1.70

Input SCL; input/output SDA

V_IL

V_IH

I_OL

LOW-level input voltage

HIGH-level input voltage

−0.5

0.7V_DD

20

-

+0.3V_DD

V

-

5.5

-

V

LOW-level output current V_OL= 0.4 V; V_DD= 2.3 V

V_OL= 0.4 V; V_DD= 5.0 V

-

mA

µA

pF

30

-

I_L

leakage current

V_I= V_DDor V_SS

V_I= V_SS

−1

-

+1

10

C_i

input capacitance

-

6

LED driver outputs

[2]

I_OL

LOW-level output current V_OL= 0.5 V; V_DD= 2.3 V

V_OL= 0.5 V; V_DD= 3.0 V

12

17

25

-

mA

-

V_OL= 0.5 V; V_DD= 4.5 V

-

I_OL(tot)

I_OH

total LOW-level output

current

V_OL= 0.5 V; V_DD= 4.5 V

100

HIGH-level output

current

open-drain; V_OH= V_DD

−50

-

+50

µA

V_OH

HIGH-level output

voltage

I_OH= −10 mA; V_DD= 2.3 V

I_OH= −10 mA; V_DD= 3.0 V

I_OH= −10 mA; V_DD= 4.5 V

1.6

2.3

4.0

-

V

-

V

-

V

C_o

output capacitance

2.5

5

pF

OE input

V_IL

V_IH

I_LI

LOW-level input voltage

HIGH-level input voltage

input leakage current

input capacitance

−0.5

2

-

+0.8

5.5

+1

V

-

V

−1

-

µA

pF

C_i

3.7

5

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

28 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

Table 20. Static characteristics …continued

V_DD= 2.3 V to 5.5 V; V_SS= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Address inputs

Conditions

Min

Typ

Max

Unit

V_IL

V_IH

I_LI

LOW-level input voltage

−0.5

0.7V_DD

−1

-

+0.3V_DD

V

HIGH-level input voltage

input leakage current

input capacitance

-

5.5

+1

5

V

-

µA

pF

C_i

-

3.7

[1] V_DDmust be lowered to 0.2 V in order to reset part.

[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 100 mA due to internal busing limits.

13. Dynamic characteristics

Table 21. Dynamic characteristics

Symbol Parameter

Conditions

Standard- mode

I²C-bus

Fast-mode

I²C-bus

Fast-mode

Plus I²C-bus

Unit

Min

0

Max

100

-

Min

0

Max

Min

0

Max

1000 kHz

[1]

f_SCL

t_BUF

SCL clock frequency

400

-

bus free time between a

STOP and START condition

4.7

1.3

0.5

-

µs

ns

t_HD;STA

t_SU;STA

hold time (repeated) START

condition

4.0

4.7

4.0

-

0.6

-

0.26

set-up time for a repeated

START condition

t_SU;STOset-up time for STOP

condition

t_HD;DAT

data hold time

0

-

3.45

-

0

-

0.9

-

0

[2]

[3]

t_VD;ACKdata valid acknowledge time

0.3

250

4.7

0.1

100

1.3

0.05

50

0.45 µs

t_VD;DAT

t_SU;DAT

t_LOW

data valid time

data set-up time

-

ns

LOW period of the SCL

clock

-

0.5

µs

t_HIGH

t_f

HIGH period of the SCL

clock

4.0

-

0.6

-

0.26

-

µs

ns

[5][6]

[4]

fall time of both SDA and

SCL signals

-

300

20 + 0.1C_b

300

50

-

120

50

t_r

rise time of both SDA and

SCL signals

1000 20 + 0.1C_b

[7]

t_SP

pulse width of spikes that

must be suppressed by the

input ﬁlter

50

-

[1] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held

LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.

[2] t_VD;ACK= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[3] t_VD;DAT= minimum time for SDA data out to be valid following SCL LOW.

[4] C_b= total capacitance of one bus line in pF.

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

29 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

[5] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V_ILof the SCL signal) in order to

bridge the undeﬁned region of SCL’s falling edge.

[6] The maximum t_ffor the SDA and SCL bus lines is speciﬁed at 300 ns. The maximum fall time (t_f) for the SDA output stage is speciﬁed at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum speciﬁed t_f.

[7] Input ﬁlters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

SDA

t

r

f

HD;STA

SP

BUF

t

LOW

SCL

t

SU;STO

HD;STA

SU;STA

t

SU;DAT

HD;DAT

HIGH

P

S

Sr

P

002aaa986

Fig 23. Deﬁnition of timing

START

condition

(S)

bit 7

MSB

(A7)

STOP

condition

(P)

bit 6

(A6)

bit 1

(D1)

bit 0

(D0)

acknowledge

(A)

protocol

t

HIGH

SU;STA

LOW

1 / f

SCL

SDA

t

BUF

f

t

r

t

SU;STO

t

HD;DAT

VD;DAT

VD;ACK

HD;STA

SU;DAT

002aab285

Rise and fall times refer to V_ILand V_IH

.

Fig 24. I²C-bus timing diagram

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

30 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

14. Test information

V

open

DD

V

SS

V

R

500 Ω

DD

L

V

O

I

PULSE

DUT

GENERATOR

C

50 pF

L

R

T

002aab880

R_L= Load resistor for LEDn. R_Lfor SDA and SCL > 1 kΩ (3 mA or less current).

C_L= Load capacitance includes jig and probe capacitance.

R_T= Termination resistance should be equal to the output impedance Z_oof the pulse generators.

Fig 25. Test circuitry for switching times

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

31 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

15. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

c

y

H

v

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.39

0.014 0.0075 0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig 26. Package outline SOT109-1 (SO16)

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

32 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm

SOT505-1

D

E

A

X

c

y

H

v

M

A

E

Z

5

8

A

(A )

2

A

3

A

1

pin 1 index

θ

L

p

L

1

4

detail X

e

w M

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

A

b

c

D

E

e

H

E

L

p

UNIT

v

w

y

Z

θ

1

2

3

p

max.

0.15

0.05

0.95

0.80

0.45

0.25

0.28

0.15

3.1

2.9

3.1

2.9

5.1

4.7

0.7

0.4

0.70

0.35

6°

0°

mm

1.1

0.65

0.25

0.94

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-04-09

03-02-18

SOT505-1

Fig 27. Package outline SOT505-1 (TSSOP8)

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

33 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm

SOT552-1

D

E

A

X

c

y

H

v

M

A

E

Z

6

10

A

(A )

2

A

3

A

1

pin 1 index

θ

L

p

L

1

5

detail X

e

w M

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

A

b

c

D

E

e

H

L

UNIT

v

w

y

Z

θ

1

2

3

p

E

p

max.

0.15

0.05

0.95

0.80

0.30

0.15

0.23

0.15

3.1

2.9

3.1

2.9

5.0

4.8

0.7

0.4

0.67

0.34

6°

0°

mm

1.1

0.5

0.25

0.95

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-07-29

03-02-18

SOT552-1

Fig 28. Package outline SOT552-1 (TSSOP10)

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

34 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig 29. Package outline SOT403-1 (TSSOP16)

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

35 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;

16 terminals; body 4 x 4 x 0.85 mm

SOT629-1

B

A

D

terminal 1

index area

A

1

E

c

detail X

e

1

C

1/2 e

y

e

v

M

b

C

A B

C

1

w

5

8

L

9

4

1

e

E

h

2

1/2 e

12

terminal 1

index area

16

13

X

D

h

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

1

e

2

y

D

E

L

v

w

y

1

h

max.

0.05 0.38

0.00 0.23

4.1

3.9

2.25

1.95

4.1

3.9

2.25

1.95

0.75

0.50

mm

0.05

0.1

1

0.2

0.65

1.95 1.95

0.1 0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-22

SOT629-1

- - -

MO-220

- - -

Fig 30. Package outline SOT629-1 (HVQFN16)

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

36 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

HVSON8: plastic thermal enhanced very thin small outline package; no leads;

8 terminals; body 3 x 3 x 0.85 mm

SOT908-1

0

1

2 mm

scale

X

D

B

A

E

A

1

c

detail X

terminal 1

index area

e

1

terminal 1

index area

C

M

v

C

A

B

e

b

y

w

C

1

4

L

exposed tie bar (4×)

E

h

exposed tie bar (4×)

8

5

D

h

DIMENSIONS (mm are the original dimensions)

(1)

A

max.

(1)

UNIT

A

b

E

e

y

c

D

E

L

v

w

y

1

h

1

h

0.05

0.00

0.3

0.2

3.1

2.9

2.25

1.95

3.1

2.9

1.65

1.35

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

1.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

05-09-26

05-10-05

SOT908-1

MO-229

Fig 31. Package outline SOT908-1 (HVSON8)

PCA9633_5

Product data sheet

Rev. 05 — 25 July 2008

37 of 43

PCA9633

NXP Semiconductors

4-bit Fm+ I²C-bus LED driver

16. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.

However, to be completely safe you must take normal precautions appropriate to handling

integrated circuits.

17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

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4-bit Fm+ I²C-bus LED driver

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

17.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 32) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 22 and 23

Table 22. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 23. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 32.

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4-bit Fm+ I²C-bus LED driver

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 32. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

18. Abbreviations

Table 24. Abbreviations

Acronym

CDM

DUT

Description

Charged-Device Model

Device Under Test

EMI

ElectroMagnetic Interference

ElectroStatic Discharge

Human Body Model

ESD

HBM

I²C-bus

LCD

Inter-Integrated Circuit bus

Liquid Crystal Display

LED

Light Emitting Diode

LSB

Least Signiﬁcant Bit

MM

Machine Model

MSB

Most Signiﬁcant Bit

NMOS

PCB

Negative-channel Metal-Oxide Semiconductor

Printed-Circuit Board

PMOS

PWM

RGB

Positive-channel Metal-Oxide Semiconductor

Pulse Width Modulation

Red/Green/Blue

RGBA

SMBus

Red/Green/Blue/Amber

System Management Bus

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19. Revision history

Table 25. Revision history

Document ID

PCA9633_5

Modiﬁcations:

Release date

Data sheet status

Change notice

Supersedes

20080725

Product data sheet

-

PCA9633_4

• Section 2 “Features”:

–

9^thbullet item: changed “up to 4 and 126 PCA9633 devices” to “up to 4 and 126 devices”

deleted (old) 12^thbullet item

–

• Section 7.1.1 “Regular I²C-bus slave address”: Remark re-written; added (new) 1^stand 2^ndbullet

items

• Figure 21 “Software Reset (SWRST) Call sequence”:

–

changed “Byte 1 = 0xA5” to “Byte 1 = A5h”

–

changed “Byte 2 = 0x5A” to “Byte 2 = 5Ah”

• Figure 25 “Test circuitry for switching times”: changed “GND” to “V_SS

”

PCA9633_4

PCA9633_3

PCA9633_2

20080304

20061220

20061114

20060123

Product data sheet

-

PCA9633_3

PCA9633_2

PCA9633_1

-

PCA9633_1

(9397 750 14614)

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Product data sheet

Rev. 05 — 25 July 2008

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4-bit Fm+ I²C-bus LED driver

20. Legal information

20.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

to result in personal injury, death or severe property or environmental

20.2 Deﬁnitions

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

20.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

20.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

I²C-bus — logo is a trademark of NXP B.V.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

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22. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

17

Soldering of SMD packages . . . . . . . . . . . . . . 38

Introduction to soldering. . . . . . . . . . . . . . . . . 38

Wave and reﬂow soldering . . . . . . . . . . . . . . . 38

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 38

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 39

17.1

17.2

17.3

17.4

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

18

19

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 40

Revision history . . . . . . . . . . . . . . . . . . . . . . . 41

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

20

Legal information . . . . . . . . . . . . . . . . . . . . . . 42

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 42

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42

20.1

20.2

20.3

20.4

7

7.1

7.1.1

7.1.2

7.1.3

7.1.4

7.2

Functional description . . . . . . . . . . . . . . . . . . . 8

Device addresses . . . . . . . . . . . . . . . . . . . . . . . 8

Regular I²C-bus slave address. . . . . . . . . . . . . 8

LED All Call I²C-bus address . . . . . . . . . . . . . . 9

LED Sub Call I²C-bus addresses . . . . . . . . . . . 9

Software Reset I²C-bus address . . . . . . . . . . . 9

Control register . . . . . . . . . . . . . . . . . . . . . . . . 10

Register deﬁnitions . . . . . . . . . . . . . . . . . . . . . 11

Mode register 1, MODE1 . . . . . . . . . . . . . . . . 12

Mode register 2, MODE2 . . . . . . . . . . . . . . . . 12

PWM registers 0 to 3, PWMx — Individual

21

22

Contact information . . . . . . . . . . . . . . . . . . . . 42

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.3

7.3.1

7.3.2

7.3.3

brightness control registers . . . . . . . . . . . . . . 13

Group duty cycle control, GRPPWM . . . . . . . 13

Group frequency, GRPFREQ . . . . . . . . . . . . . 14

LED driver output state, LEDOUT . . . . . . . . . 14

I²C-bus subaddress 1 to 3, SUBADRx . . . . . . 15

LED All Call I²C-bus address, ALLCALLADR. 15

Active LOW output enable input . . . . . . . . . . . 16

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 16

Software Reset . . . . . . . . . . . . . . . . . . . . . . . . 17

Using the PCA9633 with and without

7.3.4

7.3.5

7.3.6

7.3.7

7.3.8

7.4

7.5

7.6

7.7

external drivers . . . . . . . . . . . . . . . . . . . . . . . . 18

Individual brightness control with group

7.8

dimming/blinking. . . . . . . . . . . . . . . . . . . . . . . 20

8

Characteristics of the I²C-bus. . . . . . . . . . . . . 21

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

START and STOP conditions . . . . . . . . . . . . . 21

System conﬁguration . . . . . . . . . . . . . . . . . . . 21

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.1

8.1.1

8.2

8.3

9

Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 23

Application design-in information . . . . . . . . . 26

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27

Static characteristics. . . . . . . . . . . . . . . . . . . . 28

Dynamic characteristics . . . . . . . . . . . . . . . . . 29

Test information. . . . . . . . . . . . . . . . . . . . . . . . 31

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 32

Handling information. . . . . . . . . . . . . . . . . . . . 38

10

11

12

13

14

15

16

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 25 July 2008

Document identifier: PCA9633_5


型号：	PCA9633DP2,118
厂家：	NXP
描述：	PCA9633 - 4-bit Fm+ I2C-bus LED driver TSSOP 10-Pin PC 驱动光电二极管接口集成电路
文件：	总43页 (文件大小：229K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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