PCD5008 [NXP]
FLEX Pager Decoder; FLEX寻呼机解码器
| 型号： | PCD5008 |
| 厂家： | 
NXP |
| 描述： | FLEX Pager Decoder |
| 文件： | 总64页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCD5008
FLEX Pager Decoder
1998 Jun 17
Product specification
Supersedes data of 1997 Oct 27
File under Integrated Circuits, IC17
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
CONTENTS
8.6.7
Configuration of assigned frames and pager
collapse (ID = 20H to 27H)
Configuration of assigned phase
Call data packets
1
2
3
4
5
6
7
8
FEATURES
8.6.8
8.7
APPLICATIONS
8.7.1
8.7.2
8.7.3
8.7.4
8.7.5
8.7.6
General
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
Address packet (ID = 01H)
Vector packets (ID = 02H to 57H)
Numeric vector packet
Short message/tone-only vector packet
Hex/binary, alphanumeric, secure message
vectors
Short instruction vector
Message packets (ID = 03H to 57H)
Block Information Word (BIW) packet
(ID = 00H)
Message reception
FLEX signal structure
Message building
All frame mode (ID = 03H)
Temporary addresses
Message fragmentation
Message checksums
PINNING
FUNCTIONAL DESCRIPTION
8.7.7
8.7.8
8.7.9
8.1
General
8.2
Clocking, reset and start-up
Oscillator
Reset and start-up conditions
Serial peripheral interface (SPI)
General
8.2.1
8.2.2
8.3
8.8
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.8.7
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
SPI interconnect
SPI transfer initiated by the host
SPI transfer initiated by the decoder
SPI packet format
Message numbering
SPI timing
Host-to-decoder packets overview
Decoder-to-host packets overview
Configuration and synchronisation
General
9
LIMITING VALUES
10
11
12
13
14
15
DC CHARACTERISTICS
AC CHARACTERISTICS
SPI security algorithm
Configuration sequence
Configuration packet (ID = 01H)
Part ID packet (ID = FFH)
Checksum packet (ID = 00H)
Control packet (ID = 02H)
Operating the 1-minute timer
Status packet (ID = 7FH)
Receiver control interface
General
OSCILLATOR CHARACTERISTICS
THERMAL CHARACTERISTICS
HANDLING
TEST AND APPLICATION INFORMATION
15.1
15.2
15.3
15.3.1
15.3.2
Example application
System block diagram
FLEX encoding and decoding rules
FLEX encoding rules
FLEX decoding rules
Low battery detection
16
17
PACKAGE OUTLINE
SOLDERING
Receiver settings at reset
Receiver off state (ID = 10H)
Receiver warm-up sequences
Active receiver states
Forcing receiver lines (ID = 0FH)
Receiver shut-down sequence
Configuration of the FLEX CAPCODE
General
CAPCODE format
CAPCODE ranges
Address calculation
Phase and frame calculation
Configuration of user addresses
(ID = 78H, 80H to 8FH)
17.1
17.2
17.3
17.4
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
18
19
DEFINITIONS
LIFE SUPPORT APPLICATIONS
1998 Jun 17
2
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
1
FEATURES
3
GENERAL DESCRIPTION
• FLEX paging protocol signal processor
• 16 programmable user address words
• 16 fixed temporary addresses
This data sheet describes the operation of the PCD5008
integrated paging decoder. It is fully compatible with the
Motorola FLEXchip IC.
The PCD5008, also referred to as the decoder, simplifies
implementation of a FLEX paging device, by being able
to interface with several off-the-shelf paging receivers and
host microcontrollers/processors. Its primary function is to
process information received and demodulated from a
FLEX radio paging channel, select messages addressed
to the paging device and communicate the message
information to the host.
• 1600, 3200 and 6400 bits/s decoding
• Any-phase or single-phase decoding
• Uses standard serial peripheral interface (SPI) in slave
mode
• Allows low current power-down mode operation of host
processor
• Highly programmable receiver control
• Real-time clock time base
Motorola FLEXstack software, installed on the product
host processor, communicates with the PCD5008 and
interprets the codewords that are passed to the host.
• FLEX fragmentation and group messaging support
• Real-time clock over-the-air update support
• Compatible with synthesized receivers
• Low battery indication (external detector)
• Low cost LQFP32 plastic package
• Operates using a 76.8 kHz crystal
• Very low power consumption
The PCD5008 operates the paging receiver in an efficient
power consumption mode and enables the host to operate
in a low-power mode when no message is being received.
• Operates at low supply voltage.
2
APPLICATIONS
• Numeric FLEX pagers
• Alphanumeric FLEX pagers
• Remote metering
• Car security systems
• Personal digital assistants.
4
QUICK REFERENCE DATA
SYMBOL
VDD
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
supply voltage
1.8
−
2.2
3.6
−
V
IDD
supply current
see Sections 10 and 12
6.4
µA
°C
kHz
Tamb
fEXTAL
operating ambient temperature
external clock frequency
−25
−
+25
76.8
+70
−
5
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
PCD5008H
LQFP32 plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm
SOT358-1
1998 Jun 17
3
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
6
BLOCK DIAGRAM
EXTS0
12
11
3, 13
7, 29
V
V
, V
DD1 DD2
PCD5008
NOISE
DETECTOR
EXTS1
SYMBOL SYNC
, V
SS1 SS2
14
SYMCLK
4
8
TEST2
TEST3
RESET
LOBAT
EXTERNAL
CONTROL
UNIT
INTERNAL
CONTROL
UNIT
24
SYNC
CORRELATOR
10
2
OSCPD
5
6
XTAL
ERROR
CORRECTOR
CONTROL/STATUS
REGISTERS
76.8 kHz
OSCILLATOR
DE-INTERLEAVER
EXTAL
1
TOUT0
TOUT1
TOUT2
TOUT3
25
17
9
32
ADDRESS
COMPARATOR
LOCAL MESSAGE
FILTER
CLKOUT
CLOCK
SPI INTERFACE
RECEIVER CONTROL
SPI BUFFER
RAM 32 × 32
23 22 21 20 19 18 16 15
S0 S1 S2 S3 S4 S5 S6 S7
26 27 28 30 31
SS
READY
MOSI
SCK MISO
MGK259
Fig.1 Functional block diagram for PCD5008 pager decoder.
1998 Jun 17
4
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
7
PINNING
SYMBOL
PAD
PIN
I/O
COORDINATE
X/Y; note 1
DESCRIPTION
TOUT0
OSCPD
1
2
O
I
−1405/1088
−1405/816
3-state test output; note 2
internal oscillator power-down; connected to VSS when using the
internal oscillator, connected to VDD when using an external source
VDD1
3
−
I
−1405/563
−1405/306
−1405/76
supply voltage
TEST2
XTAL
EXTAL
VSS1
4
manufacturing test mode input pin; has to be connected to VSS
76.8 kHz crystal oscillator output
76.8 kHz crystal oscillator input or external clock input
ground supply
5
O
I
6
−1405/−404
−1405/−648
7
−
I
TEST3
TOUT3
LOBAT
EXTS1
EXTS0
VDD2
8
−1405/−1104 manufacturing test mode input pin; has to be connected to VSS
−1125/−1400 3-state test output; note 2
9
O
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
−863/−1400
−633/−1400
−398/−1400
134/−1400
569/−1400
829/−1400
1084/−1400
1405/−1093
1405/−718
1405/−398
1405/−93
low battery voltage detect input
I
most significant bit (MSB) of the symbol currently being decoded
least significant bit (LSB) of the symbol currently being decoded
supply voltage
I
−
O
O
O
O
O
O
O
O
O
O
I
SYMCLK
S7
recovered symbol clock output
receiver control output port, 3-state
receiver control output port, 3-state
3-state test output; note 2
S6
TOUT2
S5
receiver control output port, 3-state
receiver control output port, 3-state
receiver control output port, 3-state
receiver control output port, 3-state
receiver control output port, 3-state
receiver control output port, 3-state
active LOW reset input
S4
S3
S2
1405/202
S1
1405/502
S0
1405/812
RESET
TOUT1
READY
SS
1405/1114
1051/1400
721/1400
O
O
I
3-state test output; note 2
output driven LOW when the PCD5008 is ready for an SPI packet
slave select input for SPI communications
serial clock input for SPI communications
ground supply
404/1400
SCK
I
149/1400
VSS2
−
I
−100/1400
−516/1400
−789/1400
−1084/1400
MOSI
MISO
CLKOUT
data input for SPI communications
data output for SPI communications, 3-state
38.4 kHz clock output (derived from 76.8 kHz oscillator)
O
O
Notes
1. The pad coordinates are given in µm relating to the centre of the chip and are used in case of naked die delivery.
2. These test outputs may be either left unconnected or connected to VSS in the application.
1998 Jun 17
5
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
RESET
S0
TOUT0
OSCPD
1
2
3
4
5
6
7
8
24
23
V
22 S1
21 S2
20 S3
DD1
TEST2
XTAL
PCD5008H
EXTAL
19
18
17
S4
V
S5
SS1
TEST3
TOUT2
MGK257
Fig.2 Pin configuration.
The PCD5008 connects to any receiver capable of
providing a 2-bit digital signal. The PCD5008 operates the
paging receiver in an efficient power consumption mode.
The PCD5008 has 8 receiver control lines used for
warming up, operating and shutting down a receiver in
stages.
8
FUNCTIONAL DESCRIPTION
General
8.1
The PCD5008 simplifies implementation of a FLEX
paging device by interfacing with off-the-shelf components
such as a paging receiver and a microcontroller or
microprocessor (called a host). The PCD5008 is fully
compatible with FLEXstack software which provides a
complete, platform independent, software driver for the
PCD5008.
The PCD5008 has the ability to detect a battery-low signal
from an external detector during the receiver control
sequences.
The PCD5008 carries out the following functions:
• Synchronises to a FLEX data stream
The PCD5008 fully supports all non-roaming aspects of
the FLEX protocol (version G1.8), and can operate in
either single-phase or any-phase mode. The PCD5008
supports FLEX dynamic grouping, allowing up to
16 temporary addresses to be enabled simultaneously.
It is also capable of retrieving real time information from a
FLEX channel.
• Processes received, demodulated information
• Performs de-interleaving and error correction
• Selects calls addressed to the paging device using up to
16 programmable addresses
• Communicates the message information to the host.
1998 Jun 17
6
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
The PCD5008 interfaces to a host through a serial
peripheral interface (SPI). The host can then interpret the
message information in an appropriate manner (numeric,
alphanumeric, binary, etc.). This function is provided by
the FLEXstack software.
In this case the internal oscillator can be disabled by
pulling the OSCPD input pin HIGH.This reduces current
consumption and routes EXTAL directly to the internal
clock signal. When using a crystal, an external feedback
resistor and the load capacitances need to be connected
to pins EXTAL and XTAL (Fig.18). See Section 12 for the
recommended crystal parameters and the specification of
the oscillator transconductance to guarantee correct
start-up.
The PCD5008 enables the host to operate in a low power
mode when no message information for the paging device
is being received. It has a 38.4 kHz clock output capable
of driving other devices, and has a 1-minute timer that
offers low-power support for a real-time clock function on
the host. The host can use receiver control lines which are
not required by the receiver as expansion ports to control
other peripheral devices.
8.2.2
RESET AND START-UP CONDITIONS
The PCD5008 is reset by pulling the RESET input LOW.
After releasing the RESET by pulling it HIGH, the
PCD5008 counts 76800 clock cycles (typically 1 second)
before pulling READY LOW to indicate that the decoder is
ready for configuration via the SPI.
8.2
Clocking, reset and start-up
8.2.1
OSCILLATOR
See Fig.3 and Section 11 for the PCD5008 timing
specifications when power is applied.
The PCD5008 uses an inverting crystal oscillator.
The clock signal for the internal circuitry is derived via an
amplifier from the oscillator input pin EXTAL. Alternatively,
an external clock signal can be fed in at input pin EXTAL.
See Fig.4 and Section 11 for the PCD5008 timing
specifications when it is reset.
V
DD
t
strt(osc)
oscillator
RESET
READY
t
WUL(osc-READY)
t
t
MBK031
h(rst)
HL(RESET-READY)
Fig.3 Start-up timing.
1998 Jun 17
7
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
RESET
t
W(rst)
READY
t
HL(RESET-READY)
t
MBK033
LH(RESET-READY)
Fig.4 Reset timing.
8.3.2 SPI INTERCONNECT
8.3
Serial peripheral interface (SPI)
Connection on the PCD5008 consists of a READY pin and
4 SPI pins (SS, SCK, MOSI and MISO):
8.3.1
GENERAL
All data communication between the PCD5008 and the
host is done via the SPI using 32-bit data packets at data
rates up to 1 Mbits/s. SPI transfers are full-duplex and can
be initiated by either the host which acts as the SPI master
providing the data clock for packet transfer, or the
PCD5008 as an SPI slave.
READY: output signal; indicates that data is available
from the PCD5008
SS: SPI select; used as PCD5008 chip select
SCK: serial clock; output from the host used for clocking
data
The host can send packets to configure or control the
PCD5008 or a checksum packet to validate SPI
communication (Section 8.4.2). The PCD5008 buffers
data packets, relating to received data, into a 32 packet
transmit buffer. The PCD5008 can send either a status
packet, a part ID packet, or packets from the transmit
buffer. In the event of a buffer overflow, the PCD5008
stops decoding and clears the transmit buffer.
MOSI: master output slave input; data output from the
host
MISO: master input slave output; data output from the
PCD5008.
1998 Jun 17
8
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
4. The PCD5008 pulls the READY line HIGH, to indicate
that the transfer is complete.
8.3.3
SPI TRANSFER INITIATED BY THE HOST
The following steps occur when the host initiates an SPI
packet transfer, see Fig.5 for event timings:
5. The host waits until the READY line is pulled HIGH,
then de-selects the PCD5008 SPI by driving the
SS pin HIGH.
1. The host selects the PCD5008 by driving the
SS pin LOW.
6. The first 5 steps are repeated for each additional
packet.
2. The PCD5008 indicates that it is ready to start the
SPI transfer by driving the READY pin LOW.
3. The host clocks each of the 32 bits of the SPI packet
by pulsing SCK. Both the host and the PCD5008
sample data on the rising edge of SCK. Packets are
sent MSB first.
(1)
(5)
SS
READY
SCK
(2)
(4)
(3)
MOSI
D31
D31
D1 D0
D1 D0
D31
D31
D1 D0
D1 D0
D31
D31
D1 D0
D1 D0
Z
Z
Z
Z
o(off)
MISO
o(off)
o(off)
o(off)
MGK262
Numbers within parenthesis refer to sequence numbers, see Section 8.3.3.
Fig.5 Typical multiple SPI transfers initiated by the host.
3. The host clocks each of the 32 bits of the SPI packet
by pulsing SCK. Both the host and the PCD5008
sample data on the rising edge of SCK. Packets are
sent MSB first.
8.3.4
SPI TRANSFER INITIATED BY THE DECODER
The following steps occur when the PCD5008 initiates an
SPI packet transfer, see Fig.6 for event timings:
1. The PCD5008 initiates the SPI transfer by driving the
READY pin LOW.
4. The PCD5008 pulls the READY line HIGH, to indicate
that the transfer is complete.
2. If the PCD5008 is not already selected, the host
selects the PCD5008 SPI by driving the SS pin LOW.
5. The host may then either de-select the SPI interface of
the PCD5008 (Fig.7) by driving the SS pin HIGH or
maintain SS LOW to continue sending packets to the
PCD5008.
1998 Jun 17
9
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
(2)
(5)
SS
(1)
READY
SCK
(4)
(3)
MOSI
MISO
D31
D31
D1 D0
D1 D0
D31
D31
D1 D0
D1 D0
D31
D31
D1 D0
Z
Z
Z
Z
o(off)
D1 D0
o(off)
o(off)
o(off)
MGK263
Numbers within parenthesis refer to sequence numbers, see Section 8.3.4.
Fig.6 Typical multiple SPI transfers initiated by the PCD5008.
SS
READY
SCK
MOSI
MISO
D31
D31
D1 D0
D1 D0
D31
D31
D1 D0
D1 D0
D31
D31
D1 D0
D1 D0
Z
o(off)
MGK264
Fig.7 Multiple SPI transfers initiated by the PCD5008 with SS maintained LOW.
10
1998 Jun 17
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
8.3.5
SPI PACKET FORMAT
8.3.6
SPI TIMING
SPI data packets consist of an 8-bit ID (byte 3), followed
by 24 bits of information (byte 2 to byte 0). See Table 1,
note that bit 7 of byte 3 is the first bit on the bus.
See Fig.8 and Chapter 11 for the timing specifications of
the SPI.
Table 1 Packet bit assignments
BYTE
BIT 7
D31
BIT 6
D30
BIT 5
D29
BIT 4
D28
BIT 3
D27
BIT 2
D26
BIT 1
D25
BIT 0
D24
3
2
1
0
D23
D15
D7
D22
D14
D6
D21
D13
D5
D20
D12
D4
D19
D11
D3
D18
D10
D2
D17
D9
D16
D8
D1
D0
SS
t
SSH
READY
t
t
READYH
t
d(SS-READY)
t
LAG2
LEAD2
t
T
t
t
t
LEAD1
cy(SCK)
r
f
LAG1
SCK
t
SCKL
t
SCKH
Z
o(off)
MISO
D31
D0
t
t
t
o(dis)
t
ACC(o)
DOV
h(o)(D)
MOSI
D31
t
D0
t
MBK032
su(i)(D)
h(i)(D)
Fig.8 SPI timing.
1998 Jun 17
11
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
8.3.7
HOST-TO-DECODER PACKETS OVERVIEW
This section summarises the packets which can be sent from the host to the decoder.
Table 2 Host-to-decoder packet ID map
PACKET
ID (HEX)
TYPE
SECTION
00
01
02
03
checksum
8.4.6
configuration
control
8.4.4
8.4.7
8.8.3
−
all frame mode
04 to 0E
0F
reserved (host should never send)
receiver line control
8.5.7
8.5.4
8.5.5.3
8.5.5.3
8.5.5.3
8.5.5.3
8.5.5.3
8.5.6.2
8.5.6.2
8.5.6.2
8.5.6.2
8.5.8.1
8.5.8.1
−
10
receiver control configuration (off setting)
receiver control configuration (warm-up 1 setting)
receiver control configuration (warm-up 2 setting)
receiver control configuration (warm-up 3 setting)
receiver control configuration (warm-up 4 setting)
receiver control configuration (warm-up 5 setting)
receiver control configuration (3200 sps sync setting)
receiver control configuration (1600 sps sync setting)
receiver control configuration (3200 sps data setting)
receiver control configuration (1600 sps data setting)
receiver control configuration (shut-down 1 setting)
receiver control configuration (shut-down 2 setting)
special (ignored by decoder)
11
12
13
14
15
16
17
18
19
1A
1B
1C to 1F
20
frame assignment (frames 112 to 127)
frame assignment (frames 96 to 111)
8.6.7
8.6.7
8.6.7
8.6.7
8.6.7
8.6.7
8.6.7
8.6.7
−
21
22
frame assignment (frames 80 to 95)
23
frame assignment (frames 64 to 79)
24
frame assignment (frames 48 to 63)
25
frame assignment (frames 32 to 47)
26
frame assignment (frames 16 to 31)
27
frame assignment (frames 0 to 15)
28 to 77
78
reserved (host should never send)
user address enable
8.6.6
−
79 to 7F
80
reserved (host should never send)
user address assignment (user address 0)
user address assignment (user address 1)
user address assignment (user address 2)
user address assignment (user address 3)
user address assignment (user address 4)
user address assignment (user address 5)
8.6.6
8.6.6
8.6.6
8.6.6
8.6.6
8.6.6
81
82
83
84
85
1998 Jun 17
12
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
PACKET
TYPE
ID (HEX)
SECTION
86
user address assignment (user address 6)
user address assignment (user address 7)
user address assignment (user address 8)
user address assignment (user address 9)
user address assignment (user address 10)
user address assignment (user address 11)
user address assignment (user address 12)
user address assignment (user address 13)
user address assignment (user address 14)
user address assignment (user address 15)
reserved (host should never send)
8.6.6
87
8.6.6
8.6.6
8.6.6
8.6.6
8.6.6
8.6.6
8.6.6
8.6.6
8.6.6
−
88
89
8A
8B
8C
8D
8E
8F
90 to FF
8.3.8
DECODER-TO-HOST PACKETS OVERVIEW
This section summarises the packets which can be sent from the PCD5008 to the host (Table 3).
Table 3 Decoder-to-host packet ID map
PACKET
ID (HEX)
TYPE
SECTION
00
01
block information word
address
8.7.9
8.7.2
02 to 57
58 to 7E
7F
vector or message (ID is word number in frame)
8.7.3, 8.7.8
reserved
status
−
8.4.9
−
80 to FE
FF
reserved
part ID
8.4.5
1998 Jun 17
13
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
SPI transmit is disabled all decoding and timing functions
are unaffected. The SPI transmit can be enabled by
sending a checksum packet for which the checksum value
matches the checksum register.
8.4
Configuration and synchronisation
8.4.1
GENERAL
After a reset, all configuration data has to be (re)loaded
into the PCD5008 by the host using the SPI. PCD5008
features which do not change during operation are
configured using the configuration packet (Section 8.4.4),
the receiver control packets (Section 8.5) and the address
configuration packets (Section 8.6). PCD5008 features
which can be changed during operation are configured
using the control packet. The checksum packet ensures
proper communication between the host and the
PCD5008.
Any checksum packets sent when the SPI transmit is
enabled, are ignored by the PCD5008 irrespective of the
value of the checksum packet data bits. Thus when the
PCD5008 initiates an SPI transfer and the host has no
data to send, the host should send the checksum packet
so as not to disable the SPI transmit. The data in the
checksum packet could be a null packet (32 bit stream of
all zeros).
Sending a packet other than the checksum packet when
the SPI transmit is enabled causes the SPI transmit to be
disabled until a checksum packet is sent with the correct
value. Thus when the host re-configures the PCD5008
after a reset, the SPI transmit is disabled until the host
sends a checksum packet at the end of the configuration
data, with the checksum value equal to the result of
XORing together the data bits of each of the configuring
packets and the data bits of the part ID packet.
8.4.2
SPI SECURITY ALGORITHM
The PCD5008 provides a security algorithm to verify
correct SPI operation (Figs 9 and 10). The PCD5008
maintains a checksum register equal to the result of
XORing the 24 data bits of every packet it receives, except
the checksum packet 00H and special packets
1CH to 1FH. When the PCD5008 is reset, the internal
checksum register is initialized to the 24 bit part ID defined
in the part ID packet.
If the SPI transmit is enabled and there is data in the
transmit buffer, the PCD5008 initiates an SPI transfer
sending a packet from its transmit buffer. The PCD5008
sends the status packet (which is not buffered) when the
host initiates an SPI transfer and the transmit buffer is
empty.
Immediately following a reset and whenever the host
sends a packet other than a checksum packet, the
SPI output of status and data (SPI transmit) is disabled.
The PCD5008 then initiates SPI transfers continuously,
sending the part ID packet (Section 8.4.5). Note that when
32
32
32
PART ID REGISTER
32 × 32 DATA PACKET
FIFO TRANSMIT
BUFFER
32
MUX
SPI TRANSMIT REGISTER
MISO
STATUS REGISTER
MGK261
SPI
SECURITY
ALGORITHM
Fig.9 SPI transmit functional block diagram.
1998 Jun 17
14
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
reset
PCD5008 disables
SPI transmit
PCD5008 initializes
checksum register
to part ID value
PCD5008 initiates
part ID packet
PCD5008 waits for
SPI packet from host
Y
N
checksum packet?
PCD5008
SPI transmit
enabled?
PCD5008 disables
SPI transmit
Y
PCD5008 sets
N
checksum registers to
the XOR of the packet
data bits with the
packet data
matches checksum
register data?
N
checksum register bits
MGK260
Y
PCD5008 enables
SPI transmit
Fig.10 SPI security algorithm.
1998 Jun 17
15
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
5. At the end of each packet the PCD5008 pulls the
READY line HIGH, and then LOW again to indicate
that packet processing is complete.
8.4.3
CONFIGURATION SEQUENCE
A typical configuration and synchronisation sequence
would be as follows, see Fig.11 for event timings:
6. The host writes a control packet to enable FLEX
decoding in the PCD5008 (Section 8.4.7).
1. The PCD5008 is reset by the host.
2. After 1 second the PCD5008 interrupts the host to
read the part ID by pulling the READY line LOW.
7. The host writes a checksum packet to enable SPI data
output by the PCD5008 (Section 8.4.2).
3. The host pulls SS LOW at the start of each
SPI transfer and clocks out the part ID data.
8. On recognising a SYNC word, the PCD5008
synchronises to the channel.
4. The host configures the following aspects of PCD5008
operation:
9. The PCD5008 initiates an SPI transfer writing the
status packet, indicating that it is now in synchronous
mode.
a) General configuration (Section 8.4.4)
b) Receiver operation (Section 8.5)
c) FLEX CAPCODE configuration (Section 8.6).
The PCD5008 writes a part ID packet in response to
each incoming packet.
configuration packets
(addresses, receiver etc.)
SPI
(6)
(7)
control packet
checksum packet
HOST-TO-DECODER
(4)
(9)
partid packet
status packet
SPI
DECODER-TO-HOST
(4)
partid packet
(1)
RESET
(5)
(5)
(5)
(2)
READY
(3)
SS
(8)
FLEX DATASTREAM
SYNC
MBK097
Numbers within parenthesis refer to sequence numbers, see Section 8.4.3.
Fig.11 Typical configuration and synchronisation sequence.
1998 Jun 17
16
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
bit is set, the CLKOUT pin is driven HIGH. Note that
8.4.4
CONFIGURATION PACKET (ID = 01H)
setting and clearing this bit can cause pulses on the
CLKOUT pin that are less than one half the 38.4 kHz
period. Also note that when the clock output is enabled, the
CLKOUT pin always outputs the 38.4 kHz signal even
when the PCD5008 is in reset. Value after reset = 0.
The configuration packet defines a number of different
configuration options for the PCD5008. The PCD5008
ignores this packet when decoding is enabled,
i.e. the ON bit in the control packet is set (Table 11).
OFD: oscillator frequency difference (Tables 4 and 5).
These bits represent the maximum frequency difference
between the 76.8 kHz oscillator (accounting for ageing,
temperature variation, manufacturing tolerance etc.) and
the worst case transmitter bit rate (specified in FLEX as
±25 parts per million (ppm), see Section 15.3.1).
For example, if the transmitter tolerance is ±25 ppm and
the 76.8 kHz oscillator tolerance is ±140 ppm, the
transmitter-oscillator frequency difference is ±165 ppm
and OFD should be cleared (300 ppm max.). Value after
reset = 0. Note that configuring a smaller frequency
difference in this packet results in lower power
MTE: minute timer enable (Table 5). When this bit is set,
a status packet is sent at one minute intervals with the
minute time-out (MT) bit in the status packet set. When
this bit is clear, the internal 1-minute timer stops counting.
See Section 8.4.8 for details of 1-minute timer operation.
Value after reset = 0.
LBP: low battery polarity (Table 5). This bit defines the
polarity of the PCD5008’s LOBAT pin: When this bit is set,
a HIGH at input LOBAT represents a low battery condition.
The LB bit in the status packet is initialized to the inverse
(i.e. inactive) value of the LBP bit when the PCD5008 is
turned on (by setting the ON bit in the control packet).
When the PCD5008 is turned on, the first low battery
update in the status packet is sent to the host when a low
battery condition is detected on the LOBAT pin. Value
after reset = 0.
consumption due to higher receiver battery save ratios.
SME: synchronous mode enable (Table 5). When this bit
is set, a status packet is sent automatically whenever the
synchronous mode update (SMU) bit in the status packet
is set. This happens whenever a change occurs in the
synchronous mode (SM) status bit, which indicates that
the decoder is synchronized to a FLEX data stream.
The host can use the SM bit in the status packet as an
in-range/out-of-range indication. Value after reset = 0.
SP: signal polarity (Tables 5, 6 and 7). These bits set the
polarity of EXTS1 and EXTS0 input signals. The polarity of
the EXTS1 and EXTS0 bits is determined by the receiver
design. Value after reset = 0.
MOT: maximum off time (Table 5). When this bit is set, the
PCD5008 assumes that there can be up to 1 minute
between transmitted frames on the paging system. When
this bit is clear, the PCD5008 assumes that there can be
up to 4 minutes between transmitted frames on the paging
system. This setting is determined by the service provider.
Value after reset = 0.
Table 4 Maximum oscillator frequency difference
FREQUENCY DIFFERENCE
OFD1
OFD0
(ppm)
0
0
1
1
0
1
0
1
±300
±150
±75
±0
COD: clock output disable (Table 5). When this bit is clear,
a 38.4 kHz signal is output on the CLKOUT pin. When this
Table 5 Configuration packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OFD1
SP1
0
OFD0
SP0
0
0
0
0
0
0
SME
MOT
COD
MTE
LBP
1998 Jun 17
17
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
Table 6 Input signal polarity
8.4.5
PART ID PACKET (ID = FFH)
The part ID packet is output by the PCD5008 SPI
whenever the SPI transmit is disabled due to the
checksum feature.
SIGNAL POLARITY
EXTS1 EXTS0
normal normal
SP1
SP0
0
0
1
1
0
1
0
1
MDL: model (Table 8). The PCD5008 model value is 0.
normal
inverted
normal
CID: compatibility ID (Table 8). This value describes other
parts with the same model number, which are compatible
with this part. The PCD5008 compatibility value is 1.
Devices which implement a superset of PCD5008
functionality have MDL cleared and CID0 set.
inverted
inverted
inverted
Table 7 FLEX 4 level FSK modulation selection
FSK MODULATION
REV: revision (Table 8). This identifies the manufacturing
version of the PCD5008. For the PCD5008 the value is 6.
Compatible parts have values in the range 0 to 5.
EXTS1
EXTS0
AT SP = 0,0
(Hz)
1
1
0
0
0
1
1
0
+4800
+1600
−1600
−4800
8.4.6
CHECKSUM PACKET (ID = 00H)
See Table 9 for checksum packet bit assignment.
CV: checksum value (24 bits), see Section 8.4.2.
Table 8 Part ID packet bit assignments
BYTE
BIT 7
BIT 6
1
BIT 5
1
BIT 4
1
BIT 3
1
BIT 2
1
BIT 1
1
BIT 0
1
3
2
1
0
1
MDL1
CID7
REV7
MDL0
CID6
REV6
CID13
CID5
REV5
CID12
CID4
REV4
CID11
CID3
REV3
CID10
CID2
REV2
CID9
CID1
REV1
CID8
CID0
REV0
Table 9 Checksum packet bit assignments
BYTE
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0
3
2
1
0
CV23
CV15
CV7
CV22
CV14
CV6
CV21
CV13
CV5
CV20
CV12
CV4
CV19
CV11
CV3
CV18
CV10
CV2
CV17
CV9
CV1
CV16
CV8
CV0
1998 Jun 17
18
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
MTC: minute timer clear (Table 11). Setting this bit causes
8.4.7
CONTROL PACKET (ID = 02H)
the 1-minute timer to restart from 0 (Section 8.4.8).
The control packet defines a number of different control
bits for the PCD5008.
ON: turn on decoder (Table 11). When this bit is set, the
PCD5008 decodes FLEX signals. If this bit is cleared,
signal processing stops. However, to assure proper
operation, the PCD5008 requires that it be set into
asynchronous mode when turned off. To achieve that the
following sequence must be used:
FF: force frame 0 to 7 (Table 11). When set, each of these
bits forces the PCD5008 to decode one of the FLEX
frames 0 to 7 irrespective of the system collapse value (for
details of collapse values see Section 8.6.2). For example,
if the system collapse causes the PCD5008 to decode
frames 0, 32, 64 and 96, setting FF2 causes the PCD5008
to also decode FLEX frame 2. This may be used to
acquire transmitted time information. Value after reset = 0.
1. Send control packet with ON bit clear (decoder off)
2. Send control packet with ON bit set (decoder on)
3. Send control packet with ON bit clear (decoder off).
SPM: single phase mode (Table 11). When this bit is set,
the PCD5008 decodes only one of the transmitted phases.
When this bit is clear, the PCD5008 decodes all
transmitted phases. This value is determined by the
CAPCODE (Section 8.6). A change to this bit while the
PCD5008 is on does not take effect until the next block 0
of a frame. Value after reset = 0.
Timing between these steps is specified below and is
measured from the positive edge of the last clock of one
packet to the positive edge of the last clock of the next
packet.
• The minimum time between steps 1 and 2 is the greater
of 2 ms or the programmed shut-down time.
The programmed shut-down time is the sum of all of the
times programmed in the used receiver shut-down
settings packets.
PS: phase select (Tables 10 and 11). When the SPM bit is
set, these bits define which phase the PCD5008 shall
decode. This value is determined by the CAPCODE
(Section 8.6). A change to these bits, while the PCD5008
is on, does not take effect until the next block 0 of a frame.
Value after reset = 0.
• There is no maximum time between steps 1 and 2
• The minimum time between steps 2 and 3 is 2 ms
• The maximum time between steps 2 and 3 is the
programmed warm-up time minus 2 ms.
The programmed warm-up time is the sum of all the
times programmed in the used receiver warm-up
settings packets.
Table 10 Phase selection (PS bits)
DECODED PHASE (BASED ON
FLEX DATA RATE)
PS1
PS0
8.4.8
OPERATING THE 1-MINUTE TIMER
1600 bits/s 3200 bits/s 6400 bits/s
0
0
1
1
0
1
0
1
A
A
A
A
A
A
C
C
A
B
C
D
The PCD5008 provides a 1-minute timer which allows the
host to implement a time-of-day function while maintaining
low-power operation. The 1-minute timer is enabled using
the MTE bit in the configuration packet (Section 8.4.4).
When the 1-minute timer is enabled, a status packet is
sent at 1-minute intervals with the MT bit set
(Section 8.4.9). When the MTE bit is clear, the internal
1-minute timer stops counting. When the host sends a
control packet with MTC bit set, the 1-minute timer restarts
from 0. This allows accurate setting of a time-of-day
function.
SBI: send block information words (BIW) 2 to 4
(Table 11). When this bit is set, BIWs with time and date
information and BIWs received in error are sent to the host,
(Section 8.7.9). Value after reset = 0.
Table 11 Control packet bit assignments
BYTE
BIT 7
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
BIT 2
BIT 1
BIT 0
0
3
2
1
0
0
FF7
0
0
FF3
0
0
FF2
0
1
FF1
0
FF6
SPM
SBI
FF5
PS1
0
FF4
PS0
MTC
FF0
0
0
0
0
0
ON
1998 Jun 17
19
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
SMU: synchronous mode update (Table 12). This bit is set
if the SM bit has been updated in this packet. After the
PCD5008 has been turned on, this bit is set when the first
synchronization words are found (SM changes to 1) or
when the first synchronization search period (meaning the
receiver is active during this time) expires (SM stays 0),
after the PCD5008 is turned on. The latter condition gives
the host the option of assuming the paging device is in
range when it is turned on, and displaying out-of-range
only after the initial search period expires. After the initial
synchronous mode update, the SMU bit is set whenever
the PCD5008 switches from/to synchronous mode. The bit
is cleared when read. Changes in the SM bit due to turning
off the PCD5008 does not set the SMU bit. This bit is
initialized to 0 when the PCD5008 is reset.
8.4.9
STATUS PACKET (ID = 7FH)
The status packet contains various types of information
that the host may require and is sent to the host:
• Whenever the PCD5008 is polled and has no other data
to send
• On events for which the PCD5008 is configured to send
the status packet (Sections 8.4.4 and 8.4.7). In this
case, the PCD5008 prompts the host to read a status
packet for the following conditions:
– SMU bit in the status packet and the SME bit in the
configuration packet are set
– MT bit in the status packet and the MTE bit in the
configuration packet are set
– EOF bit in the status packet is set
– LBU bit in the status packet is set
– BOE bit in the status packet is set.
LB: low battery (Table 12). Set to the value last read from
the LOBAT pin. The host controls when the LOBAT pin is
read via the receiver control packets. This bit is initialized
to 0 at reset. It is also initialized to the inverse of the
LBP bit in the configuration packet, when the PCD5008 is
turned on, by setting the ON bit in the control packet.
FIV: frame information valid (Table 12). This bit is set,
when a valid frame information word has been received
since becoming synchronous to the system and the
f and c fields contain valid values. If this bit is clear, no
valid frame information words have been received since
the PCD5008 became synchronous to the system. This
value changes from 0 to 1 at the end of block 0 (Fig.17) of
the frame in which the first frame information word was
properly received. It is cleared when the PCD5008 goes
into asynchronous mode (see SM bit below). This bit is
initialized to 0 when the PCD5008 is reset and when the
PCD5008 is turned off by clearing the ON bit in the control
packet.
LBU: low battery update (Table 12). This bit is set if the
value on two consecutive reads of the LOBAT pin yielded
different results. The bit is cleared when read. The host
controls when the LOBAT pin is read via the receiver
control packets. Changes in the LB bit due to turning on
the PCD5008 do not cause the LBU bit to be set. This bit
is initialized to 0 when the PCD5008 is reset.
MT: minute time-out (Table 12). Set if one minute has
elapsed. The bit is cleared when read. This bit is initialized
to 0 when the PCD5008 is reset.
f: current frame number (Table 12). This value is updated
every frame regardless of whether the PCD5008 needs to
decode the frame. This value changes to its proper value
for a frame at the end of block 0 of the frame. The value of
these bits is not guaranteed when FIV is 0.
EOF: end of frame (Table 12). Set when the PCD5008 is
in all frame mode (AFM) (Section 8.8.3), and the end of
the frame has been reached. The PCD5008 is in the AFM
if the AFM enable counter is non-zero, if any temporary
address enabled (TAE) counter is non-zero (Section 8.8.3)
or if the FAF bit in the AFM packet is set. The bit is cleared
when read and initialized to 0 when the PCD5008 is reset.
c: current system cycle number (Table 12). This value is
updated every frame regardless of whether the PCD5008
needs to decode the frame. This value changes to its
proper value for a frame at the end of block 0 of the frame.
The value of these bits is not guaranteed when FIV is 0.
BOE: buffer overflow error (Table 12). Set when
information has been lost owing to slow host response
time. When the PCD5008 detects that its SPI transmit
buffer has overflowed, it clears the transmit buffer, turns off
decoding by clearing the ON bit in the control packet, and
sets this bit. The bit is cleared when read. This bit is
initialized to 0 when the PCD5008 is reset.
SM: synchronous mode (Table 12). This bit is set, when
the PCD5008 is synchronous to the system.
The PCD5008 sets this bit when the first synchronization
words are received. It clears this bit when synchronisation
to the FLEX signal is lost. This bit is initialized to 0 when
the PCD5008 is reset and when it is turned off by clearing
the ON bit in the control packet.
x: unused bits (Table 12). The value of these bits is not
guaranteed.
1998 Jun 17
20
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
corresponding FRS bit in the receiver line control packet is
set or the PCD5008 is turned on for the first time after a
reset (by setting the ON bit in the control packet). This
allows the designer to force the receiver control lines to the
receiver off setting with external pull-up or pull-down
resistors before the host can configure these settings in
the PCD5008.
8.5
Receiver control interface
8.5.1
GENERAL
The PCD5008 has 8 programmable receiver control lines,
S0 to S7. The host can program via SPI packets what
setting is applied to the receiver control lines, the duration
of warm-up and shut-down stages and the polling of the
LOBAT pin. This programmability allows the PCD5008 to
interface with many off-the-shelf receiver ICs. Note that
these packets are ignored when sent while decoding is
enabled (ON bit is set in the control packet).
8.5.4
RECEIVER OFF STATE (ID = 10H)
The receiver off state is configured by the receiver off
setting packet (Table 13), which defines the settings to be
applied when the PCD5008 decides to switch the
receiver off.
8.5.2
LOW BATTERY DETECTION
The PCD5008 can be configured to poll the LOBAT pin at
the end of every receiver control setting. This check can be
enabled or disabled for each receiver control setting. If the
poll is enabled for a setting, the pin is read just before the
PCD5008 activates the next setting on the receiver control
lines. The PCD5008 sends a status packet whenever the
value differs from the previous time that the LOBAT pin
was polled.
LBC: low battery check (Table 13). If this bit is set, the
PCD5008 checks the status of the LOBAT port just before
leaving the receiver off state. Value after reset = 0.
CLS: control line setting (Table 13). This is the value to be
output on the receiver control lines for the receiver off
state. Value after reset = 0.
ST: step time (Table 13). This sets the duration of the
warm-up off time. The setting is in steps of 625 µs. Valid
values are 625 µs (ST = 01H) to 159.375 ms (ST = FFH).
Value after reset = 01H.
8.5.3
RECEIVER SETTINGS AT RESET
The receiver control ports are 3-state outputs which are set
to high impedance when the PCD5008 is reset, until the
Table 12 Status packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
1
BIT 1
BIT 0
1
3
2
1
0
0
1
f6
1
f5
x
1
f4
1
f3
c3
x
1
f1
c1
x
FIV
SM
f2
f0
LB
LBU
x
c2
c0
SMU
x
MT
EOF
BOE
Table 13 Receiver off setting packet bit assignments
BYTE
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
1
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0
3
2
1
0
0
0
0
0
LBC
CLS3
ST3
0
0
0
CLS7
ST7
CLS6
ST6
CLS5
ST5
CLS4
ST4
CLS2
ST2
CLS1
ST1
CLS0
ST0
1998 Jun 17
21
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
If it exceeds 160 ms, the PCD5008 executes the receiver
shut-down sequence 160 ms after the start of the warm-up
off time. If the sum of all of the used warm-up times and the
warm-up off times is less than 160 ms, the receiver
remains in the 1600 sps sync setting or the 3200 sps sync
setting from the end of the last used warm-up setting until
valid signals are expected (160 ms after the start of the
warm-up off time). Figure 12 shows the receiver warm-up
sequence while decoding, when all warm-up settings are
enabled.
8.5.5
RECEIVER WARM-UP SEQUENCES
8.5.5.1
Normal receiver warm-up sequence
The PCD5008 allows for up to 6 steps associated with
warming up the receiver. When the PCD5008 turns on the
receiver while decoding, it starts the warm-up sequence
160 ms before it requires valid signals at the EXTS1 and
EXTS0 input pins.
1. The PCD5008 leaves the receiver control lines in the
off state for the programmed warm-up off time.
2. The first warm-up setting, if enabled, is applied to the
receiver control lines for the amount of time
programmed for that setting.
8.5.5.2
First receiver warm-up sequence
When the PCD5008 is turned on by setting the ON bit in
the control packet, the receiver warm-up sequence differs
from the sequence described in Section 8.5.5.1. After the
ON bit is set no receiver warm-up off time is applied,
instead the PCD5008 immediately begins to apply the
receiver warm-up settings. When a disabled warm-up
setting is found, the decoder applies 3200 sps sync setting
to the receiver control lines. The decoder then expects
valid signals after the 3200 sps sync warm-up time.
Figure 13 shows the receiver warm-up sequence when the
PCD5008 is first turned on and when all warm-up settings
are enabled.
3. Subsequent warm-up settings are applied to the
receiver control lines for their corresponding time until
a disabled warm-up setting is found.
4. At the end of the last used warm-up setting, the
1600 symbols per second (sps) sync setting or the
3200 sps sync setting is applied to the receiver control
lines depending on the PCD5008 current state.
The PCD5008 must be configured such that the sum of all
of the used warm-up times and the warm-up off time does
not exceed 160 ms.
160 ms
warm up
off time
warm up
time 1
warm up
time 2
warm up
time 3
warm up
time 4
warm up
time 5
receiver
control
line setting
warm up
setting 1
warm up
setting 2
warm up
setting 3
warm up
setting 4
warm up
setting 5
1600 sps or 3200 sps
sync setting
off
possible
possible
possible
possible
possible
possible
EXTS1 & EXTS0
LOBAT
check
LOBAT
check
LOBAT
check
LOBAT
check
LOBAT
check
LOBAT signals are expected
check to be valid here
MGK265
Fig.12 Receiver warm-up sequence while decoding.
3200 sps sync
warm up
time
warm up
time 1
warm up
time 2
warm up
time 3
warm up
time 4
warm up
time 5
receiver
control
line setting
warm up
setting 1
warm up
setting 2
warm up
setting 3
warm up
setting 4
warm up
setting 5
3200 sps
sync setting
off
possible
LOBAT
check
possible
LOBAT
check
possible
LOBAT
check
possible
LOBAT
check
possible
LOBAT
check
possible
LOBAT signals are expected
check to be valid here
EXTS1 & EXTS0
MGK266
Fig.13 First receiver warm-up sequence after turning decoding on.
22
1998 Jun 17
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
ST: step time (Table 15). This sets the duration time for
receiver warm-up until the next receiver state. The setting
is in 625 µs steps and valid values are:
8.5.5.3
Receiver warm-up setting packets
(ID = 11H to 15H)
CLS: control line setting (Table 15). This is the value to be
output on the receiver control lines (S0 to S7) for this
receiver warm-up state. Value after reset = 0.
625 µs (ST = 01H) to 79.375 ms (ST = 7FH).
Value after reset = 01H.
SE: step enable (Table 15). The receiver setting is
enabled when the bit is set. If the bit is cleared then that
step in the receiver warm-up sequence is disabled and all
following steps are ignored. Value after reset = 0.
s: setting number, see Tables 14 and 15 for the s names
and values and location in the receiver warm-up packet.
LBC: low battery check (Table 15). If this bit is set, the
PCD5008 checks the status of the LOBAT port just before
leaving this receiver warm-up state. Value after reset = 0.
Table 14 Receiver warm-up setting numbers
s3
0
s2
s1
s0
SETTING NAME
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
warm-up 1
warm-up 2
warm-up 3
warm-up 4
warm-up 5
0
0
0
0
Table 15 Receiver warm-up setting packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
SE
CLS7
0
0
0
0
0
1
0
s3
s2
0
s1
0
s0
0
LBC
CLS3
ST3
CLS6
ST6
CLS5
ST5
CLS4
ST4
CLS2
ST2
CLS1
ST1
CLS0
ST0
1998 Jun 17
23
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
8.5.6
ACTIVE RECEIVER STATES
8.5.6.1
General
In addition to the warm-up and shut-down states, the PCD5008 has four active receiver states. When these settings are
applied to the receiver control lines, the PCD5008 is decoding the EXTS1 and EXTS0 input signals. The timing of these
signals and their duration depends on the FLEX data stream. Because of this, there is no time setting associated with
these settings (with the exception of the 3200 sps sync setting).
The four settings are as follows:
1600 sps sync setting: applied when the PCD5008 searches for a 1600 sps signal.
3200 sps sync setting: applied when the PCD5008 searches for a 3200 sps signal.
1600 sps data setting: applied after the PCD5008 has found the C or C sync word in the sync 2 section of a
1600 sps frame.
3200 sps data setting: applied after the PCD5008 has found the C or C sync word in the sync 2 section of a
3200 sps frame.
Figure 14 shows some examples of how these settings are used in the PCD5008.
TM
FLEX
frame
info
block 10
sync 1
sync 2
block 0
signal
receiver
control
line setting
example #1
1600 sps data or 3200 sps data
or last used warm up setting
1600 sps
sync setting
3200 sps
sync setting
3200 sps
data setting
possible
LOBAT
check
possible
LOBAT
check
possible
LOBAT
check
receiver
control
line setting
example #2
1600 sps data or 3200 sps data
or last used warm up setting
1600 sps
sync setting
1600 sps
data setting
MGK268
possible
LOBAT
check
possible
LOBAT
check
Fig.14 Examples of receiver control transitions.
1998 Jun 17
24
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
8.5.6.2
Receiver on setting packets (ID = 16H to 19H)
Table 16 s names and values
LBC: low battery check (Table 17). If this bit is set, the
PCD5008 checks the status of the LOBAT port just before
leaving this receiver sync setting state. Value after
reset = 0.
s3
s2
s1
s0
SETTING NAME
0
1
1
1
0
0
1
0
0
1
0
1
1600 sps sync
3200 sps data
1600 sps data
CLS: control line setting (Table 17). This is the value to be
output on the receiver control lines for this receiver
sync setting state. Value after reset = 0.
8.5.7
FORCING RECEIVER LINES (ID = 0FH)
This packet (Table 19) enables host control over the
receiver control line (S0 to S7) settings in all modes except
reset. In reset, the receiver control lines are high
impedance.
ST: step time (Table 17). This sets the waiting time, before
expecting good signals at EXTS1 and EXTS0 at the end of
the warm-up sequence, after turning decoding on.
The setting is in steps of 625 µs. Valid values are:
625 µs (ST = 01H) to 79.375 ms (ST = 7FH). Value after
reset = 01H.
FRS: force receiver setting (Table 19). Setting a bit causes
the associated CLS bit in this packet to override the
internal receiver control settings on the corresponding
receiver control line. Clearing a bit returns control of the
corresponding receiver control line to the PCD5008. Value
after reset = 0.
LBC: low battery check (Table 18). If this bit is set, the
PCD5008 checks the status of the LOBAT port just before
leaving this receiver on state. Value after reset = 0.
CLS: control line setting (Table 18). This is the value to be
output on the receiver control lines (S0 to S7) for this
receiver on state. Value after reset = 0.
CLS: control line setting (Table 19). This bit setting is
applied to the corresponding receiver control line if the
associated FRS bit is set in this packet. Value after
reset = 0.
s: setting number, see Tables 16 and 18 for the s names
and values and location in the receiver on setting packet.
Table 17 3200 sps sync setting packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
LBC
CLS3
ST3
CLS7
0
CLS6
ST6
CLS5
ST5
CLS4
ST4
CLS2
ST2
CLS1
ST1
CLS0
ST0
Table 18 Receiver on setting packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
s3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
0
0
0
0
0
1
0
s2
0
s1
0
s0
0
LBC
CLS3
0
CLS7
0
CLS6
0
CLS5
0
CLS4
0
CLS2
0
CLS1
0
CLS0
0
Table 19 Receiver line control packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
FRS7
CLS7
FRS6
CLS6
FRS5
CLS5
FRS4
CLS4
FRS3
CLS3
FRS2
CLS2
FRS1
CLS1
FRS0
CLS0
1998 Jun 17
25
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
LBC: low battery check (Table 21). If this bit is set, the
PCD5008 checks the status of the LOBAT port just before
leaving this receiver shut-down state. Value after
reset = 0.
8.5.8
RECEIVER SHUT-DOWN SEQUENCE
The PCD5008 allows up to 3 steps associated with
shutting down the receiver. When the PCD5008 decides to
turn off the receiver, the first shut-down setting, if enabled,
is applied to the receiver control lines for the
corresponding shut-down time. At the end of the last used
shut-down time, the receiver off setting is applied to the
receiver control lines. If the first shut-down setting is not
enabled, the PCD5008 switches directly from the
receiver on to the receiver off setting.
CLS: control line setting (Table 21). This is the value to be
output on the receiver control lines (S0 to S7) for this
receiver shut-down state. Value after reset = 0.
ST: step time (Table 21). This sets the duration time for
receiver shut-down, until the next receiver state.
The setting is in steps of 625 µs. Valid values are
625 µs (ST = 01H) to 39.375 ms (ST = 3FH). Value after
reset = 01H.
Figure 15 shows the receiver shut-down sequence when
all shut-down settings are enabled. If the receiver is on or
being warmed up when the decoder is turned off (by
clearing the ON bit in the control packet), the PCD5008
immediately executes the receiver shut-down sequence.
If the PCD5008 is executing the shut-down sequence
when turned on (with the ON bit in the control packet set)
the PCD5008 completes the shut-down sequence before
starting the warm-up sequence.
s: setting number, see Tables 20 and 21 for the s names
and values and location in the receiver shut-down packet.
Table 20 s names and values
s
0
1
SETTING NAME
shut-down 1
shut-down 2
8.5.8.1
Receiver shut-down setting packets
(ID = 1A to 1BH)
SE: step enable (Table 21). The receiver setting is
enabled when the bit is set. If the bit is cleared then that
step in the receiver shut-down sequence is disabled and
all following steps are ignored. Value after reset = 0.
Table 21 Receiver shut-down stages
BYTE
BIT 7
BIT 6
BIT 5
0
BIT 4
1
BIT 3
BIT 2
0
BIT 1
1
BIT 0
s
3
2
1
0
0
SE
CLS7
0
0
0
1
0
0
LBC
CLS3
ST3
0
0
0
CLS6
0
CLS5
ST5
CLS4
ST4
CLS2
ST2
CLS1
ST1
CLS0
ST0
shut down
time 1
shut down
time 2
receiver
control
line setting
1600 sps or 3200 sps
sync or data setting
shut down
setting 1
shut down
setting 2
off
MGK267
possible
possible
possible
LOBAT
check
LOBAT
check
LOBAT
check
Fig.15 Receiver shut-down sequence.
1998 Jun 17
26
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
When the FLEX standard pager collapse value of 4
(battery cycle of 16 frames) is used, the pager collapse
field can be omitted.
8.6
Configuration of the FLEX CAPCODE
8.6.1
GENERAL
A CAPCODE specifies a decoder address, the collapse
value of the address and whether single-phase, any-phase
or all-phase address. The PCD5008 supports
single-phase and any-phase operation. The FLEX
protocol provides a standard mechanism to derive phase
and frame in which an address should be transmitted.
If this mechanism is not used, a CAPCODE also specifies
the phase and frame assigned to the address.
The collapse value is a number between 0 and 7 and
defines how often the decoding device looks for messages
on the FLEX channel. For a given collapse value b, the
decoding device looks in every 2b frames. Thus an
address with an assigned base frame of 3 and a collapse
value of 5 typically looks for messages in frame 3 and
every 32 frames thereafter (i.e. frames 3, 35, 67 and 99).
8.6.2
CAPCODE FORMAT
The FLEX CAPCODE consist of a series of decimal and
alphabetic fields, see Fig.16 for the field definitions.
Frame field, optional 3 digit decimal
CAPCODE type, mandatory
field, represents the frame number if
standard frame and phase
embedding rules are not used.
alphabetic character, indicates rules
for deriving phase and frame from
address field.
P 1 2 2 5 U 2 2 3 4 5 5 0 1 2 1
Roaming capability, optional
alphabetic character 'P'
indicates no roaming capabilities.
Pager collapse (battery cycle),
optional 1 digit decimal field
(mandatory if frame number
field is included) indicates pager
collapse value.
Address field, mandatory 7, 9 or 10 digit
decimal field, contains the information from
which the BCH address codewords for this
CAPCODE are derived.
MBK096
Fig.16 CAPCODE format.
1998 Jun 17
27
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
A long CAPCODE represents addresses situated
8.6.3
CAPCODE RANGES
above 2101248 subdivided into categories
(uncoordinated, global, country) to allow different
allocation schemes to coexist.
A CAPCODE represents user addresses ranging
from 1 to 5370810366. A short CAPCODE can have
address values below 2031615 and are represented in the
data stream by a single address codeword. Some short
addresses have been reserved for special purposes:
information service addresses, network addresses,
temporary (group) addresses and operator messaging
addresses.
Table 22 defines the address usage assignment.
All addresses not listed in this table are not defined and
reserved for future use.
Table 22 CAPCODE assignment table
CAPCODE ADDRESS VALUE
DESCRIPTION
from
to
0000000000
illegal
0000000001
0001933313
0001998849
0002009088
0002025472
0002029568
0002029584
0002029600
0002031615
0002101249
0102101251
0402101251
1075843073
2149584897
3223326721
3923326751
4280000001
4285000001
4290000001
4291000001
0001933312
0001998848
0002009087
0002025471
0002029567
0002029583
0002029599
0002031614
0002101248
0102101250
0402101250
1075843072
2149584896
3223326720
3923326750
4280000000
4285000000
4290000000
4291000000
4297068542
short addresses
illegal
reserved for future use
Information service addresses
network addresses
temporary addresses
operator messaging addresses
reserved for future use
invalid, not used
long address set 1-2 uncoordinated
long address set 1-2 country; note 1
long address set 1-2 global; note 2
long address set 1-3 global; note 2
long address set 1-4 global; note 2
long address set 2-3 country; note 1
long address set 2-3 reserved
long address set 2-3 information service, global; notes 2 and 3
long address set 2-3 information service, country; notes 1 and 3
long address set 2-3 information service, world-wide; notes 3 and 4
reserved for future use
Notes
1. Country: the addresses are coordinated within each country and with countries along borders.
2. Global: address is coordinated to be unique world-wide.
3. Information service: currently, the rules governing the use of these addresses are not defined.
4. World-wide: 1000 addresses are assigned to each country for world-wide use.
1998 Jun 17
28
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
8.6.4
ADDRESS CALCULATION
Table 23 Address word range definitions
Address codeword values generally do not coincide with
(part of) the user address as specified in the CAPCODE.
To find the address codewords corresponding to a user
address a conversion has to be done (Table 24). The type
of conversion depends on the CAPCODE range in which
the user address is located. Note that addresses are
transmitted LSB first (differently to POCSAG).
TYPE
HEX VALUE
000000
Idle word (illegal address)
Long address 1
000001 to 008000
008001 to 1E0000
1E0001 to 1E8000
1E8001 to 1F0000
1F0001 to 1F27FF
Short address
Long address 3
Long address 4
Short addresses, are transmitted in a single address
codeword where as long addresses are transmitted in two
consecutive address codewords. The first codeword of a
long address contains the lower part of the address, the
second codeword the upper part. By combining two long
address codewords from different banks 6 long address
ranges are created: 1 to 2, 1 to 3, 1 to 4, 2 to 3, 2 to 4 and
3 to 4. Ranges 2 to 4 and 3 to 4 are as yet undefined and
reserved.
Short address (reserved)
Information service address 1F2800 to 1F67FF
Network address
1F6800 to 1F77FF
1F7800 to 1F780F
Temporary address
Operator messaging address 1F7810 to 1F781F
Short address (reserved)
Long address 2
1F7820 to 1F7FFE
1F7FFF to 1FFFFE
1FFFFF
Idle word (illegal address)
Table 24 describes how to calculate the 21 bit address
codeword which is transmitted over the air.
Table 24 Address word calculation
LOWER ADDRESS CODEWORD;
UPPER ADDRESS CODEWORD;
TYPE
notes 1, 2 and 3
notes 1, 3 and 4
Short address
CAPCODE + 8000
note 5
Long address,
range 1 to 2; note 6
1 + ((CAPCODE − 1F9001) MOD 8000)
1FFFFF − ((CAPCODE − 1F9001) DIV 8000)
Long address,
ranges 1 to 3 and
1 to 4
1 + ((CAPCODE − 1F9001) MOD 8000)
1D8000 + ((CAPCODE − 1F9001) DIV 8000)
Long address,
range 2 to 3
1F7FFF + ((CAPCODE − 1F8FFF) MOD 8000) 1C8000 + ((CAPCODE − 1F8FFF) DIV 8000)
Notes
1. All numbers are in hexadecimal format.
2. The MOD operator gives the remainder of an integer division.
3. CAPCODE refers to the value of the address field in a FLEX CAPCODE.
4. The DIV operator is the integer division.
5. A short address consists of a single codeword.
6. The upper codeword range in bank 2 is used from the highest address downwards, i.e. the lowest value of the
CAPCODE produces a codeword value of 1FFFFEH.
1998 Jun 17
29
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
8.6.5
PHASE AND FRAME CALCULATION
The standard rules for extracting phase and base frame
from the user address are (phase numbers 0 to 3
correspond to phases A to D):
The method for specifying the phase and base frame of a
pager is specified in the CAPCODE type:
Phase number = ((Address − Offset) DIV 4) MOD 4
Frame = ((Address − Offset) DIV 16) MOD 128
• The phase, base frame are extracted by standard rules
from the user address field in the CAPCODE
(CAPCODE types A to L).
where DIV is the integer division and MOD is the
remainder of an integer division.
• The phase is indicated by the CAPCODE type
(Table 25) and the base frame is specified in the frame
field of the CAPCODE (CAPCODE types U to Z).
For a CAPCODE which does not use the standard rules for
extracting phase and base frame
For easy allocation of (up to 4) consecutive CAPCODEs
having the same phase and frame, an offset in the
range 0 to 3 is subtracted from the user address for the
purposes of phase and frame extraction. The offset is
determined by the CAPCODE type.
(CAPCODE types U to Z) the 3-digit frame
field 000 to 127 and a single digit decimal pager
collapse 0 to 5 can precede the CAPCODE type. When
these fields are not included, the paging device or the
subscriber database must be accessed to determine the
assigned frame and collapse value.
Table 25 Frame and phase extraction for different CAPCODE types
CAPCODE TYPE
PAGER TYPE
single-phase
FRAME/PHASE EXTRACTION
standard rules; Offset: 0
A
B
C
D
E
F
G
H
I
single-phase
single-phase
single-phase
any-phase
standard rules; Offset: 1
standard rules; Offset: 2
standard rules; Offset: 3
standard rules; Offset: 0
any-phase
standard rules; Offset: 1
any-phase
standard rules; Offset: 2
any-phase
standard rules; Offset: 3
all-phase; note 1
all-phase; note 1
all-phase; note 1
all-phase; note 1
single-phase
single-phase
single-phase
single-phase
any-phase
standard rules; Offset: 0
J
standard rules; Offset: 1
K
L
standard rules; Offset: 2
standard rules; Offset: 3
U
V
W
X
Y
Z
no frame extraction rules, phase-A
no frame extraction rules, phase-B
no frame extraction rules, phase-C
no frame extraction rules, phase-D
no frame extraction rules, any-phase
no frame extraction rules, all-phase
all-phase; note 1
Note
1. All-phase decoding is not defined in FLEX G1.8 and, therefore, is not supported by the PCD5008.
1998 Jun 17
30
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
LA: long address (Table 26). When this bit is set, the
address is configured as a long address. Both words of a
long address must have this bit set.
8.6.6
CONFIGURATION OF USER ADDRESSES
(ID = 78H, 80H TO 8FH)
The PCD5008 has 16 user address locations which can be
programmed as long or short, and configured as priority
and/or tone-only. After a reset all address locations are
disabled. Short addresses occupy a single location, long
addresses occupy two locations. The first word of a long
address must be in an even address location and the
second word must be in the address index immediately
following the first word. Address location containing long
addresses of the 2-3 and 2-4 set (Section 8.6.3) must
follow any address locations programmed as long
addresses of the 1-2, 1-3 and 1-4 set.
TOA: tone-only address (Table 26). When this bit is set,
the PCD5008 considers this address a tone-only address
and does not decode a vector word when the address is
received. Both words of a long, tone only address must
have this bit set.
A: address word (Table 26). This is the 21 bit value of the
address word (A20 = MSB). Valid FLEX messaging
addresses must be used. For the conversion from a
CAPCODE (Section 8.6.4).
UAE: user address enable (Table 27). When a bit is set,
the corresponding user address location is enabled. When
it is cleared, the corresponding user address location is
disabled. UAE0 corresponds to the user address location
configured using a packet ID of 80H and UAE15
corresponds to the user address location configured using
a packet ID of 8FH. In some instances, if an invalid
FLEX messaging address is programmed, it is not
detected even when the address is enabled. Value after
reset = 0.
User addresses are programmed using the address
assignment packets, and are enabled and disabled using
the address enable packet. To allow easy reprogramming
of user addresses without disrupting normal operation, the
host can send address assignment packets while the
PCD5008 is on. In this case, the host must disable the user
address location(s) by clearing the corresponding user
address enable (UAE) bit in the UAE packet before
changing any of the bits in the corresponding address
assignment packet.
a: address location (Table 26). This specifies which
address location is being configured. A zero in this field
corresponds to address index zero (AI = 0) in the address
packet received from the PCD5008 when an address is
detected (Section 8.7.2).
Table 26 Address assignment packet bit assignments (ID = 80H to 8FH)
BYTE
BIT 7
1
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
a3
BIT 2
a2
BIT 1
a1
BIT 0
a0
3
2
1
0
0
LA
TOA
A13
A5
A20
A12
A4
A19
A11
A3
A18
A10
A2
A17
A9
A16
A8
A15
A7
A14
A6
A1
A0
Table 27 Address enable packet bit assignments (ID = 78H)
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
UAE15
UAE7
UAE14
UAE6
UAE13
UAE5
UAE12
UAE4
UAE11
UAE3
UAE10
UAE2
UAE9
UAE1
UAE8
UAE0
1998 Jun 17
31
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
AF: assigned frame (Table 29). If a bit is set, the PCD5008
decodes the associated FLEX frame and scans its
contents for enabled addresses. Value after reset = 0.
8.6.7
CONFIGURATION OF ASSIGNED FRAMES AND PAGER
COLLAPSE (ID = 20H TO 27H)
The assigned frame and collapse value determine the
frames in which the decoding device typically looks for
messages (other system factors can cause the decoding
device to look in other frames in addition to the typical
frames).
Table 28 Frame assignment ranges
f2
f1
f0
AF15
AF0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
frame 127
frame 111
frame 95
frame 79
frame 63
frame 47
frame 31
frame 15
frame 112
frame 96
frame 80
frame 64
frame 48
frame 32
frame 16
frame 0
The PCD5008 must be configured explicitly to receive all
required frames by setting the associated assigned
frame (AF) bits. For each enabled CAPCODE these are
the base frame and the associated frames implied by the
pager collapse value. For example if the PCD5008 has
one enabled address and it is assigned to base frame 3
with a collapse value of 4, the AF bits for
frames 3, 19, 35, 51, 67, 83, 99 and 115 should be set
and the AF bits for all other frames should be cleared.
There are 8 frame assignment packets each capable of
assigning a range of 16 consecutive frame numbers.
8.6.8
CONFIGURATION OF ASSIGNED PHASE
The assigned phase is required only for single-phase
devices. It determines the phase (A, B, C, or D) in which
the messages are received. For details of phase
calculation see Section 8.6.5. For details of programming
the assigned phase see Section 8.4.7.
f: frame range, see Table 29 for location in the frame
assignment packet and Table 28 for the AFs and values.
The value determines which 16 frames out of a range
of 128 correspond to the 16 AF bits in the packet. At least
one of these bits must have been set when the PCD5008
is turned on by setting the ON bit in the control packet.
Value after reset = 0.
Table 29 Frame assignment packet bit assignments
BYTE
BIT 7
BIT 6
0
BIT 5
1
BIT 4
0
BIT 3
0
BIT 2
f2
BIT 1
f1
BIT 0
f0
3
2
1
0
0
0
0
0
0
0
0
0
0
AF15
AF7
AF14
AF6
AF13
AF5
AF12
AF4
AF11
AF3
AF10
AF2
AF9
AF1
AF8
AF0
1998 Jun 17
32
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
TOA: tone-only address (Table 30). Set this bit if the
8.7
Call data packets
address was programmed in the PCD5008 as a tone-only
address. No vector word is sent for tone-only addresses.
8.7.1
GENERAL
The PCD5008 sends data extracted from the
FLEX signal to the host in SPI packets using the
following packet types:
WN: word number of vector (2 to 87 decimal) (Table 30).
The location of the vector within this frame for the detected
address. This value is invalid for this packet if the TOA bit
is set.
• BIW packets which contain data transmitted in BIWs
• Address packets which indicate that a call has been
detected and give additional information about call
attributes
x: unused bits (Table 30). The value of these bits is not
guaranteed.
• Vector packets which indicate the call type and indicate
which message word numbers (WN) are associated
with the call
8.7.3
VECTOR PACKETS (ID = 02H TO 57H)
Information from vector codewords in received calls is sent
to the host in vector packets. For any address packet sent
to the host (except tone-only addresses), a corresponding
vector packet is always sent.
• Message packets which contain the information
contained within the message codewords of a call.
For more information about the function of these packets
within the FLEX datastream see Section 8.8.
The ID of the vector packet is the word number where the
vector word was received in the frame. The host must
associate vector packets with a call by searching for an
address packet previously received on the same phase
and with WN bits which match the ID of the vector packet.
8.7.2
ADDRESS PACKET (ID = 01H)
Information from address codewords in received calls is
sent to the host in address packets. If less than 3 bit errors
are detected in a received address word and it matches an
enabled address assigned to the PCD5008, the address
packet is sent to the host processor. The address packet
contains the call address, the location in the datastream of
the associated vector, and other miscellaneous call data.
The vector type of a vector packet indicates the format of
a call as one of:
• Numeric (3 types)
• Short message/tone-only
• Hex/binary
• Alphanumeric
PA: priority address (Table 30). This bit is set if the
address was received as a priority address.
• Secure message
• Short instruction.
p: phase (Table 30). This is the phase on which the
address was detected (0 = A, 1 = B, 2 = C and 3 = D).
The numeric, hex/binary, alphanumeric, and secure
message vector packets indicate the location and number
of message word packets in the message field. If more
than two bit errors are detected in the vector word (via
BCH calculations, parity calculations, check character
calculations, or value validation) the e bit is set and the
message words are not sent.
LA: long address (Table 30). This bit is set if the address
was programmed in the PCD5008 as a LA.
AI: address index (Table 30). This index identifies which
address was detected. Valid values are 00H to 0FH,
corresponding to the 16 programmable address words
and 80H to 8FH, corresponding to the 16 temporary
addresses (Section 8.8.4). For long addresses, the
address packet is only sent once with AI referring to the
second word of the address.
Table 30 Address packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
0
p1
0
p0
0
0
x
0
x
0
x
1
x
PA
LA
AI7
TOA
AI6
WN6
AI5
WN5
AI4
WN4
AI3
WN3
AI2
WN2
AI1
WN1
AI0
WN0
1998 Jun 17
33
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
n: number of message words in the message (Table 31),
including the second vector word for long addresses,
(000 = 1 word message, 001 = 2 word message, etc.).
For long addresses, the first message word is located in
the word location that immediately follows the associated
vector.
8.7.4
NUMERIC VECTOR PACKET
WN: word number of vector (2 to 87 decimal) (Table 31).
WN describes the location of the vector word in the frame.
e: error (Table 31). Set if more than 2 bit errors are
detected in the word, if the check character calculation fails
after error correction has been performed, or if the vector
value is determined to be invalid.
b: word number of message start in the message field
(3 to 87 decimal) (Table 31). For long addresses, the word
number indicates the location of the second message
word.
p: phase (Table 31). This is the phase on which the vector
was found (0 = A, 1 = B, 2 = C and 3 = D).
x: unused bits (Table 31). The value of these bits is not
K: first check bits of the message checksum
guaranteed.
(Table 31 and Section 8.8.6).
V: vector type identifier (Table 32).
Table 31 Numeric vector packet bit assignments
BYTE
BIT 7
BIT 6
WN6
p1
BIT 5
WN5
p0
BIT 4
WN4
x
BIT 3
WN3
x
BIT 2
WN2
V2
BIT 1
WN1
V1
BIT 0
WN0
V0
3
2
1
0
0
e
x
x
K3
K2
K1
K0
n2
n1
n0
b6
b5
b4
b3
b2
b1
b0
Table 32 Numeric vector definitions
V2
0
V1
1
V0
1
TYPE
DESCRIPTION
standard numeric
No special formatting of characters is specified.
1
0
0
special format numeric
Formatting of the received characters is predetermined by
special rules in the host (e.g. inserting spaces and dashes).
1
1
1
numbered numeric
Received information is numbered by the service provider to
indicate all messages have been properly received.
1998 Jun 17
34
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
t: message type (Tables 33 and 34). These bits define the
8.7.5
SHORT MESSAGE/TONE-ONLY VECTOR PACKET
meaning of the d bits in this packet.
V: vector type identifier, these bits set to 010 for a
x: unused bits (Table 33). The value of these bits is not
short message/tone-only vector (Table 33).
guaranteed.
WN: word number of vector (2 to 87 decimal) (Table 33).
d: data bits whose definition depends on the value of t in
this packet according to Table 34. Note that if this vector is
received on a long address and the e bit in this packet is
not set, the decoder sends a message packet from the
word location immediately following the vector packet.
Except for the short message on a non-network address
(t = 0), all messages bits in the message packet are
unused and should be ignored.
WN describes the location of the vector word in the frame.
e: error (Table 33). Set if more than 2 bit errors are
detected in the word, if the check character calculation fails
after error correction has been performed, or if the vector
value is determined to be invalid.
p: phase (Table 33). This is the phase on which the vector
was found (0 = A, 1 = B, 2 = C and 3 = D).
Table 33 Short message/tone-only vector packet bit assignments
BYTE
BIT 7
BIT 6
WN6
p1
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
e
WN5
p0
WN4
x
WN3
x
WN2
V2
WN1
V1
WN0
V0
x
x
d11
d3
d10
d2
d9
d8
d7
d6
d5
d4
d1
d0
t1
t0
Table 34 Short message/tone-only vector definitions
t1
0
0
1
t0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
DESCRIPTION
0
1
0
c3
s8
s1
c2
s7
s0
c1
s6
c0
s5
b3
s4
b2
s3
b1
s2
b0
s1
a3
s0
a2
a1
a0
first 3 numeric characters; note 1
S2 S1 S0 8 sources (S) and 9 unused bits (s)
R0 N5 N4 N3 N2 N1 N0 S2 S1 S0 8 sources (S), message retrieval
flag (R), message number (N) and
2 unused bits (s)
1
1
spare message type
Note
1. For long addresses, an extra 5 characters are sent in the message packet immediately following the vector packet.
1998 Jun 17
35
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
b: word number of message start in the message field
(Table 36). Valid values are 3 to 87 decimal.
8.7.6
HEX/BINARY, ALPHANUMERIC AND SECURE
MESSAGE VECTORS
x: unused bits (Table 36). The value of these bits is not
V: vector type identifier (Table 35).
guaranteed.
WN: word number of vector (2 to 87 decimal) (Table 36).
Note that for long addresses, the first message packet is
sent from the word location immediately following the word
location of the vector packet. The b bits indicate the
second message word in the message field if one exists.
WN describes the location of the vector word in the frame.
e: error (Table 36). Set if more than 2 bit errors are
detected in the word, if the check character calculation fails
after error correction has been performed, or if the vector
value is determined to be invalid.
Table 35 Non-numeric vector definitions
p: phase (Table 36). This is the phase on which the vector
was found (0 = A, 1 = B, 2 = C and 3 = D).
V2
0
V1
0
V0
0
TYPE
secure
n: number of message words in this frame (Table 36),
including the first message word that immediately follows
a long address vector. Valid values are 1 to 85 decimal.
1
0
1
alphanumeric
hex/binary
1
1
0
Table 36 Hex/binary, alphanumeric and secure message vector packet bit assignments
BYTE
BIT 7
BIT 6
WN6
p1
BIT 5
WN5
p0
BIT 4
WN4
x
BIT 3
WN3
x
BIT 2
WN2
V2
BIT 1
WN1
V1
BIT 0
WN0
V0
3
2
1
0
0
e
x
x
n6
n5
n4
n3
n2
n1
n0
b6
b5
b4
b3
b2
b1
b0
1998 Jun 17
36
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
i: instruction type (Tables 37 and 38). These bits define
8.7.7
SHORT INSTRUCTION VECTOR
the meaning of the d bits in this packet.
V: these bits are set 001 for a short instruction vector.
x: unused bits (Table 37). The value of these bits is not
guaranteed.
WN: word number of vector (2 to 87 decimal) (Table 37).
WN describes the location of the vector word in the frame.
d: data bits whose definition depend on the value of the
i bits in this packet according to Table 38. Note that if this
vector is received on a long address and the e bit in this
packet is not set, the decoder sends a message packet
immediately following the vector packet. All message bits
in the message packet are unused and should be ignored.
e: error (Table 37). Set if more than 2 bit errors are
detected in the word, if the check character calculation fails
after error correction has been performed, or if the vector
value is determined to be invalid.
p: phase (Table 37). This is the phase on which the vector
was found (0 = A, 1 = B, 2 = C and 3 = D).
Table 37 Short instruction vector packet bit assignments
BYTE
BIT 7
BIT 6
WN6
p1
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
e
WN5
p0
WN4
x
WN3
x
WN2
V2
WN1
V1
WN0
V0
x
x
d10
d2
d9
d8
d7
d6
d5
d4
d3
d1
d0
i2
i1
i0
Table 38 Short instruction vector definitions
i2
i1
i0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
DESCRIPTION
0
0
0
a3
a2
a1
a0
f6
f5
f4
f3
f2
f1
f0 temporary address assignment,
note 1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
reserved
reserved
reserved
reserved
reserved
reserved
reserved for test
Note
1. Assigned temporary address index a and associated frame number f (Section 8.8.4).
1998 Jun 17
37
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
Only codewords containing the numeric message are to
be transmitted. The space character CH is used to fill any
unused 4-bit characters in the last word and zeros to fill
any remaining partial characters. The checksum includes
only the codewords comprising the shortened message,
along with the space and fill characters used to fill in the
last word.
8.7.8
MESSAGE PACKETS (ID = 03H TO 57H)
General
8.7.8.1
The message field follows the vector field in the FLEX
protocol. It contains the message data, checksum
information, and may contain fragment and message
numbers (Sections 8.8.7 and 8.8.5). If the error bit of a
vector word is not set and the vector word indicates that
there are message words associated with the page, the
message words are sent in message packets to the host.
Table 39 Standard and alternate numeric character sets;
Peoples Republic of China (ROC) option ‘on’
and ‘off’
The ID of the message packet is the word number where
the message word was received in the frame.
CHARACTER
B3
B2
B1
B0
WN: word number of message word (3 to 87 decimal)
(Table 40). WN describes the location of the message
word in the frame.
ROC ‘on’ ROC ‘off’
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
e: error (Table 40). Set if more than 2 bit errors are
detected in the word.
2
2
3
3
p: phase (Table 40). This is the phase on which the vector
was found (0 = A, 1 = B, 2 = C and 3 = D).
4
4
5
5
i: these are the information bits of the message word
(Table 40). The definition of these i bits depends on the
vector type and which word of the message is being
received.
6
6
7
7
8
8
9
9
8.7.8.2
Numeric Message
A
Spare
FLEX numeric messages are encoded using the
4-bit BCD encoded characters sets described in Table 39.
Characters are placed in codewords along with additional
information about the message as described in
Tables 41 and 42 and the following definitions. The 4-bit
numeric characters of the message are designated as
letters a, b, c, d, ... z, A, B etc.
B
Space
C
U
Space
−
]
D
E
[
Table 40 Message packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
WN5
p0
BIT 4
WN4
i20
BIT 3
WN3
i19
BIT 2
BIT 1
WN1
i17
BIT 0
WN0
i16
3
2
1
0
0
e
WN6
p1
WN2
i18
i15
i7
i14
i13
i12
i11
i10
i9
i8
i6
i5
i4
i3
i2
i1
i0
1998 Jun 17
38
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
K: least significant 2 bits of 6 bit message checksum
(Tables 41 and 42), most significant 4 bits are in the
vector word. See Section 8.8.6 for a description of
message checksums.
S: special format, (Table 42). In the numbered message
format, when this bit is set, a special display format should
be used. Spaces and dashes, specified by the host, are
inserted into the received message to ease reading of the
message. This feature may avoid the transmission of an
additional word on the channel. The actual format is
undefined in FLEX and may be determined by the
manufacturer.
N: message number (Table 42). See Section 8.8.7 for a
description of message numbering.
R: message retrieval flag (Table 42). When this bit is set,
the pager expects this message to be numbered.
See Section 8.8.7 for a description of message
numbering.
Table 41 Standard (V = 011) or special format (V = 100) 4, 10, 15, 20, 25, 31, 36, or 41 characters
MESSAGE
WORD
i0
i1
i2
i3
i4
i5
i6
i7
i8
i9 i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20
1st
2nd
3rd
4th
5th
6th
7th
8th
K4 K5 a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 d0 d1 d2 d3 e0 e1 e2
e3 f0 f1 f2 f3 g0 g1 g2 g3 h0 h1 h2 h3 i0 i1 i2 i3 j0 j1 j2 j3
k0 k1 k2 k3 l0 l1 l2 l3 m0 m1 m2 m3 n0 n1 n2 n3 o0 o1 o2 o3 q0
q1 q2 q3 r0 r1 r2 r3 s0 s1 s2 s3 t0 t1 t2 t3 u0 u1 u2 u3 v0 v1
v2 v3 w0 w1 w2 w3 y0 y1 y2 y3 z0 z1 z2 z3 A0 A1 A2 A3 B0 B1 B2
B3 C0 C1 C2 C3 D0 D1 D2 D3 E0 E1 E2 E3 F0 F1 F2 F3 G0 G1 G2 G3
H0 H1 H2 H3 I0
I1
I2
I3 J0 J1 J2 J3 V0 V1 V2 V3 L0 L1 L2 L3 M0
M1 M2 M3 O0 O1 O2 O3 P0 P1 P2 P3 Q0 Q1 Q2 Q3 T0 T1 T2 T3 U0 U1
Table 42 Numbered (V = 111) 2, 8, 13, 18, 23, 29, 34, or 39 numeric characters
MESSAGE
WORD
i0
i1
i2
i3
i4
i5
i6
i7
i8
i9 i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20
1st
2nd
3rd
4th
5th
6th
7th
8th
K4 K5 N0 N1 N2 N3 N4 N5 R0 S0 a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2
c3 d0 d1 d2 d3 e0 e1 e2 e3 f0 f1 f2 f3 g0 g1 g2 g3 h0 h1 h2 h3
i0 i1 i2 i3 j0 j1 j2 j3 k0 k1 k2 k3 l0 l1 l2 l3 m0 m1 m2 m3 n0
n1 n2 n3 o0 o1 o2 o3 q0 q1 q2 q3 r0 r1 r2 r3 s0 s1 s2 s3 t0 t1
t2 t3 u0 u1 u2 u3 v0 v1 v2 v3 w0 w1 w2 w3 y0 y1 y2 y3 z0 z1 z2
z3 A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 C2 C3 D0 D1 D2 D3 E0 E1 E2 E3
F0 F1 F2 F3 G0 G1 G2 G3 H0 H1 H2 H3 I0 I1 I2 I3 J0 J1 J2 J3 V0
V1 V2 V3 L0 L1 L2 L3 M0 M1 M2 M3 O0 O1 O2 O3 P0 P1 P2 P3 Q0 Q1
1998 Jun 17
39
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
Where symbolic characters (e.g. Chinese, Kanji etc.) are
being transmitted, special rules for fragment and message
termination are defined in Section 8.8.5.1.
8.7.8.3
Alphanumeric Message
FLEX alphanumeric messages are encoded using the
7-bit encoded alphanumeric character set defined in
Table 43. Characters are placed in codewords along with
additional information about the message as described in
Tables 44 and 45 and the following definitions. The 7-bit
characters of the message are designated lower case
letters a, b, c, d, etc.
Each 7-bit field, starting with the second character of the
second word in the message (first character of the second
word in all remaining fragments), represents standard
ASCII (ISO 646-1983E) characters with options for certain
international characters.
Alphanumeric messages can be sent as fragments.
See Section 8.8.5 for a description of message
fragmentation.
Control characters that are not acted upon by the pager
are ignored in the display process (do not require display
space) but are stored in memory for possible download to
an external device. The ASCII character ETX (03H) should
be used to fill any unused 7-bit characters in a word.
Table 43 FLEX alphanumeric character set
MOST SIGNIFICANT 3 BITS OF CHARACTER (HEX)
LEAST SIGNIFICANT 4 BITS
OF CHARACTER (HEX)
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
NUL
SOH
STX
ETX
EOT
ENQ
ACK
BEL
BS
DLE
DC1
DC2
DC3
DC4
NAK
SYN
ETB
CAN
EM
SP
!
0
1
2
3
4
5
6
7
8
9
:
@
A
B
C
D
E
F
P
Q
R
S
T
U
V
W
X
Y
Z
[
‘
a
b
c
d
e
f
p
q
r
“
#
$
%
&
’
s
t
u
v
w
x
y
z
{
G
H
I
g
h
i
(
TAB
LF
)
SUB
ESC
FS
*
J
j
VT
+
,
;
K
L
k
l
FF
<
=
>
?
\
CR
GS
-
M
N
O
]
m
n
o
}
~
SO
RS
.
^
SI
US
/
_
DEL
1998 Jun 17
40
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
K: 10-bit fragment checksum (Tables 44 and 45).
See Section 8.8.6 for a description of message checksum.
R: message retrieval flag (Table 44). When this bit is set,
the pager expects this message to be numbered.
See Section 8.8.7 for a description of message
numbering.
C: 1-bit message continued flag (Tables 44 and 45).
When this bit is set, fragments of this message are to be
expected in following frames. See Section 8.8.5 for a
description of message fragmentation.
S: 7-bit signature field (Table 44). The signature is defined
to be the 1’s complement of the binary sum over the total
message (all fragments). 7 bits at a time are taken (on
alpha character boundary) starting with the first 7 bits
directly following the signature field, a6a5a4a3a2a1a0,
b6b5b4b3b2b1b0, etc. The 7 LSBs of the result are
transmitted as the message signature.
F: 2-bit message fragment number (Tables 44 and 45).
This is a modulo 3 message fragment number which is
incremented by 1 in successive message fragments.
See Section 8.8.5 for a description of message
fragmentation.
U, V: fragmentation control bits (Table 45). This field exists
in all fragments except the first fragment. It is used to
support character position tracking in each fragment when
symbolic characters (character made up of 1, 2 or 3
ASCII characters) are transmitted using the alphanumeric
message type. The default value is 0,0.
N: message number (Tables 44 and 45). See
Section 8.8.7 for a description of message numbering.
M: 1-bit mail drop flag (Table 44). When this bit is set, it
indicates the message is to be stored in a special area in
memory and is written over existing data automatically in
that memory space.
See Section 8.8.5.1 for a description of fragment control.
Table 44 Vector type V = 101 first fragment
MESSAGE
WORD
i0
i1
i2
i3
i4
i5
i6
i7
i8
i9 i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20
1st
2nd
3rd
4th
5th
...
K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 C0 F0 F1 N0 N1 N2 N3 N4 N5 R0 M0
S0 S1 S2 S3 S4 S5 S6 a0 a1 a2 a3 a4 a5 a6 b0 b1 b2 b3 b4 b5 b6
c0 c1 c2 c3 c4 c5 c6 d0 d1 d2 d3 d4 d5 d6 e0 e1 e2 e3 e4 e5 e6
f0
i0
f1
i1
f2
i2
f3
i3
f4
i4
f5
i5
f6 g0 g1 g2 g3 g4 g5 g6 h0 h1 h2 h3 h4 h5 h6
i6 j0 j1 j2 j3 j4 j5 j6 k0 k1 k2 k3 k4 k5 k6
nth
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
Table 45 Vector type V = 101 other fragments
MESSAGE
WORD
i0
i1
i2
i3
i4
i5
i6
i7
i8
i9 i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20
1st
2nd
3rd
4th
5th
...
K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 C0 F0 F1 N0 N1 N2 N3 N4 N5 U0 V0
a0 a1 a2 a3 a4 a5 a6 b0 b1 b2 b3 b4 b5 b6 c0 c1 c2 c3 c4 c5 c6
d0 d1 d2 d3 d4 d5 d6 e0 e1 e2 e3 e4 e5 e6 f0
g0 g1 g2 g3 g4 g5 g6 h0 h1 h2 h3 h4 h5 h6 i0
f1
i1
l1
f2
i2
l2
f3
i3
l3
f4
i4
l4
f5
i5
l5
f6
i6
l6
j0
j1
j2
j3
j4
j5
j6 k0 k1 k2 k3 k4 k5 k6 l0
nth
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
1998 Jun 17
41
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
R: message retrieval flag (Table 46). When this bit is set,
the pager expects this message to be numbered.
See Section 8.8.7 for a description of message
numbering.
8.7.8.4
Hex/binary message
FLEX hexadecimal/binary messages may be encoded
using any word size (blocking length) in the
range 1 to 16 bits. Words are placed in codewords along
with additional information about the message as
described in Tables 46 and 47 and these definitions.
The message data in Tables 46 and 47 have blocking
lengths of 4 bits; words are designated lower case letters
a, b, c, d etc.
s: 5 bit field reserved for future use (Table 46).
Default value = 00000.
M: 1 bit mail drop flag, see Table 46. When this bit is set,
the message is to be stored in a special area in memory to
overwrite existing data in the same memory space.
Hexadecimal/binary messages can be sent as fragments.
See Section 8.8.5 for a description of message
D: 1 bit display direction field (Table 46). D = 0 display left
to right, D = 1 display right to left (valid only when data sent
as characters i.e. blocking length not equal 0001).
fragmentation. Messages and message fragments are
terminated, or interrupted in the case of a non-terminating
fragment, on the last full character boundary in the last
codeword. Unused bits are cleared if the last valid data bit
is logic 1, or set if the last valid data bit is logic 0. If the
terminating fragment exactly fills its last codeword, an
additional codeword is sent to indicate the location of the
last character. This codeword is filled with logic 0s if the
last valid data bit is logic 1 and filled with logic 1s if the last
valid data bit is logic 0.
B: 4 bit blocking length (Table 46). Indicates bits per
character. B3B2B1B0 = 0001 = 1 bit per character
(binary/transparent data), 1111 = 15 bits per character,
0000 = 16 bits per character. Data with a blocking length
other than 1 is assumed to be displayed on a character by
character basis (default value = 0001). Note: Tables 46
and 47 show B = 4 bit blocking length.
S: 8 bit signature field (Table 46). The 1’s complement of
the binary sum, taken 8 bits at a time, over the total
message prior to formatting into fragments. The first 8 bits
following the signature field are summed with the following
8 bits, b3b2b1b0a3a2a1a0 + d3d2d1d0c3c2c1c0, etc.
continuing to the last valid data bit in the last word of the
last fragment (the sum does not include termination bits).
The 8 LSBs of the result are inverted (1’s complement)
and transmitted as the message signature.
Fields K to N make up the first word of a message and the
first word of every fragment in a long message.
K: 12 bit fragment checksum (Tables 46 and 47).
See Section 8.8.6 for a description of message
checksums.
C: 1 bit message continued flag (Tables 46 and 47).
When this bit is set, fragments of this message are to be
expected in following frames. See Section 8.8.5 for a
description of message fragmentation.
8.7.8.5
Secure message
F: 2 bit message fragment number (Tables 46 and 47).
This is a modulo 3 message fragment number which is
incremented by 1 in successive message fragments.
See Section 8.8.5 for a description of message
fragmentation.
FLEX secure messages are encoded using the 7-bit
FLEX alphanumeric character set (Section 8.7.8.3).
These characters are placed in codewords along with
additional information about the message as described in
Table 48 and the following definitions. In Table 48, 7-bit
characters of the message are designated lower case
letters a, b, c, d etc.
N: message number (Tables 46 and 47).
See Section 8.8.7 for a description of message
numbering.
Secure messages follow the same fragmentation and
termination rules as alphanumeric messages
(Section 8.7.8.3).
H: 1 bit header message flag (Table 46). It is a header
message only when this bit is set, otherwise it is a data
message. A header message is a displayable tag
associated with a non-displayable data message.
The header message (which is sent first) and the data
message, both have the same message number.
K: 10 bit fragment checksum (Table 48).
See Section 8.8.6 for a description of message
checksums.
C: 1 bit message continued flag (Table 48). When this bit
is set, fragments of this message are to be expected in
following frames. See Section 8.8.5 for a description of
message fragmentation.
The second codeword of the first fragment of a hex/binary
message contains fields R to S. These fields are only
transmitted in the first fragment of a message.
1998 Jun 17
42
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
F: 2 bit message fragment number (Table 48). This is a
modulo 3 message fragment number which is
incremented by 1 in successive message fragments.
See Section 8.8.5 for a description of message
fragmentation.
N: message number (Table 48). See Section 8.8.7 for a
description of message numbering.
s: spare bits (Table 48), are not used and are set to 0.
Table 46 Vector type V = 110 first fragment
MESSAGE
WORD
i0
i1
i2
i3
i4
i5
i6
i7
i8
i9 i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20
1st
2nd
3rd
4th
5th
6th
...
K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 C0 F0 F1 N0 N1 N2 N3 N4 N5
R0 M0 D0 H0 B0 B1 B2 B3 s0 s1 s2 s3 s4 S0 S1 S2 S3 S4 S5 S6 S7
a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 d0 d1 d2 d3 e0 e1 e2 e3 f0
f1
k2 k3 l0
q3 r0 r1 r2 r3 s0 s1 s2 s3 t0
f2
f3 g0 g1 g2 g3 h0 h1 h2 h3 i0
l1 l2 l3 m0 m1 m2 m3 n0 n1 n2 n3 o0 o1 o2 o3 q0 q1 q2
t1 t2 t3 u0 u1 u2 u3 v0 v1 v2 v3
i1
i2
i3
j0
j1
j2
j3 k0 k1
nth
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
Table 47 Vector type V = 110 all other fragments
MESSAGE
WORD
i0
i1
i2
i3
i4
i5
i6
i7
i8
i9 i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20
1st
2nd
3rd
4th
5th
...
K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 C0 F0 F1 N0 N1 N2 N3 N4 N5
a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 d0 d1 d2 d3 e0 e1 e2 e3 f0
f1
k2 k3 l0
q3 r0 r1 r2 r3 s0 s1 s2 s3 t0
f2
f3 g0 g1 g2 g3 h0 h1 h2 h3 i0
l1 l2 l3 m0 m1 m2 m3 n0 n1 n2 n3 o0 o1 o2 o3 q0 q1 q2
t1 t2 t3 u0 u1 u2 u3 v0 v1 v2 v3
i1
i2
i3
j0
j1
j2
j3 k0 k1
nth
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
Table 48 Vector type V = 000 all fragments
MESSAGE
WORD
i0
i1
i2
i3
i4
i5
i6
i7
i8
i9 i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20
1st
2nd
3rd
4th
5th
...
K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 C0 F0 F1 N0 N1 N2 N3 N4 N5 s0 s1
a0 a1 a2 a3 a4 a5 a6 b0 b1 b2 b3 b4 b5 b6 c0 c1 c2 c3 c4 c5 c6
d0 d1 d2 d3 d4 d5 d6 e0 e1 e2 e3 e4 e5 e6 f0
g0 g1 g2 g3 g4 g5 g6 h0 h1 h2 h3 h4 h5 h6 i0
f1
i1
l1
f2
i2
l2
f3
i3
l3
f4
i4
l4
f5
i5
l5
f6
i6
l6
j0
j1
j2
j3
j4
j5
j6 k0 k1 k2 k3 k4 k5 k6 l0
nth
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
1998 Jun 17
43
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
and refers to the actual time at the leading edge of the first
bit of sync 1 of frame 0 of the current cycle.
See Tables 50, 51, 52 and 53 and the following bit
definitions of the time related BIWs.
8.7.9
BLOCK INFORMATION WORD (BIW) PACKET
(ID = 00H)
The FLEX protocol allows systems to transmit time
information using block information words. The information
carried in a BIW depends on the BIW word format
(Table 49). The first BIW of each phase, carrying
information about the frame structure, is used internally by
the PCD5008 and is never transmitted to the host.
e: error (Table 49). Set if more than 2 bit errors are
detected in the word or if the check character calculation
fails after error correction has been performed.
p: phase (Table 49), is the phase on which the BIW was
found (0 = A, 1 = B, 2 = C and 3 = D).
The PCD5008 can be configured to send all time and date
BIWs (BIW001, BIW010 and BIW101) to the host by
setting the SBI bit in the control packet, see Section 8.4.7.
When the SBI bit is set and a BIW is received with an
uncorrectable number of bit errors, the PCD5008 sends
the BIW to the host indicating that the codeword was
received in error (regardless of the BIW word format).
The PCD5008 does not support decoding of vector and
message words associated with the data/system
message BIW101.
x: unused bits (Table 49). Their value is not guaranteed.
f: word format type (Table 49). The value of these bits
modify the meaning of the s bits in this packet as described
in Tables 50, 51 and 52. If the e bit is not set, this field is
one of 001, 010 or 101.
s: BIW information bits (Table 49). The definition of these
bits depend on the f bits in this packet.
m: month field (Table 50). 0001 to 1100 binary
correspond to January to December in month order.
System providers supporting local time transmissions are
required to transmit at least one time related BIW in each
phase transmitted in frame 0, cycle 0. The time
d: day field (Table 50). 00001 to 11111 binary correspond
to 1 to 31 days in the month.
transmitted is the local time for the transmitted time zone
Table 49 BIW packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0
3
2
1
0
0
e
0
p1
x
p0
x
x
f2
f1
f0
x
s13
s5
s12
s4
s11
s3
s10
s2
s9
s8
s7
s6
s1
s0
Table 50 Month/day/year BIW definitions
f2
f1
f0
s13
s12
s11
s10
s9
s8
s7
s6
s5
s4
s3
s2
s1
s0
0
0
1
m3
m2
m1
m0
d4
d3
d2
d1
d0
Y4
Y3
Y2
Y1
Y0
Table 51 Second/minute/hour BIW definitions
f2
f1
f0
s13
s12
s11
s10
s9
s8
s7
s6
s5
s4
s3
s2
s1
s0
0
1
1
S2
S1
S0
M5
M4
M3
M2
M1
M0
H4
H3
H2
H1
H0
Table 52 Accurate seconds/daylight savings time/time zone; system message BIW definitions
f2
f1
f0 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0
S2 S1 S0 L0 z4 z3 z2 z1 z0
DESCRIPTION
system message; note 1
1
0
1
x
0
1
0
X
Note
1. When the s3s2s1s0 field is 0100 or 0101, then s4 to s13 are defined as above, when the s3s2s1s0 field does not have
one of these values, the system message does not contain time related information and is not sent to the host.
1998 Jun 17
44
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
Y: year field (Table 50). This represents the year with
modulo 32 arithmetic. 00000 to 11111 binary representing
years 1994 to 2025 and 2026 to 2057.
S: accurate seconds (Table 52). This field provides a more
accurate seconds reference and can be used to adjust the
seconds to within 1 second. This field represents the time
that should be added to the coarse seconds in 1⁄64 minute
increments.
S: seconds field (Table 51). This represents a coarse
value of the seconds field. These bits represent the
seconds in 1⁄8 minute (7.5 s) increments.
L: daylight savings time (Table 52). When this bit is set,
the time being transmitted is local standard time. When it
is clear, the time being transmitted is daylight savings time.
000 to 111 binary correspond to 0 to 52.5 seconds.
M: minute field (Table 51). 000000 to 111011 binary
correspond to 0 to 59 minutes.
z: time zone (Table 52). These bits indicate the time zone
for the time which is being transmitted. The offset
from GMT is the offset for local standard time. Table 53
describes the values for z.
H: hour field (Table 51). 00000 to 10111 binary
correspond to 0 to 23 hours.
Table 53 Time zone values
z4
z3
z2
z1
z0
TIME ZONE
z4
z3
z2
z1
z0
TIME ZONE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GMT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
reserved
GMT + 01:00h
GMT + 02:00h
GMT + 03:00h
GMT + 04:00h
GMT + 05:00h
GMT + 06:00h
GMT + 07:00h
GMT + 08:00h
GMT + 09:00h
GMT + 10:00h
GMT + 11:00h
GMT + 12:00h
GMT + 03:30h
GMT + 04:30h
GMT + 05:30h
GMT + 05:45h
GMT + 06:30h
GMT + 09:30h
GMT − 03:30h
GMT − 11:00h
GMT − 10:00h
GMT − 09:00h
GMT − 08:00h
GMT − 07:00h
GMT − 06:00h
GMT − 05:00h
GMT − 04:00h
GMT − 03:00h
GMT − 02:00h
GMT − 01:00h
1998 Jun 17
45
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
The synchronization portion consists of: a first sync signal
at 1600 bps; a frame information word having the frame
number 0 to 127 (7 bits) and the cycle number
0 to 14 (4 bits); and a second sync signal at the data rate
of the interleaved portion.
8.8
Message reception
8.8.1
FLEX SIGNAL STRUCTURE
The FLEX signal transmitted on the radio channel (see
Fig.17) consists of a series of four minute cycles, each
cycle having 128 frames at 1.875 seconds per frame.
A pager may be assigned to process any number of the
frames. Battery saving is performed for frames which are
not assigned. The FLEX signal can assign additional
frames to the pager using collapse, fragmentation,
temporary addressing or carry-on information within the
FLEX signal.
The block information field contains BIWs. These can be
used for determining time and date information and certain
paging system information.
The address field contains addresses assigned to paging
devices. Addresses are used to identify information sent to
individual paging devices and/or groups of paging devices.
Information in the FLEX signal may indicate that an
address is a priority address. An address may be either a
short (one word) address or a long (two word) address.
An address may be a tone-only address in which case
there is no additional information associated with the
address. If an address is not a tone-only address, then
there is an associated vector word in the vector field.
Information in the FLEX signal indicates the location of
the vector word in the vector field associated with the
address. A pager may perform battery saving at the end of
the address field when its address(es) is not detected.
Each FLEX frame has a synchronization portion followed
by an eleven block data portion, each block lasting
160 milliseconds. The synchronization portion indicates
the rate at which the data portion is transmitted,
1600, 3200 or 6400 bits per second (bps). The 1600 bps
rate is transmitted at 1600 symbols per second (sps)
using 2 level FSK modulation and consists of a single
phase of information at 1600 bps, phase-A. The 3200 bps
rate is transmitted at either 1600 sps using 4 level FSK
modulation or 3200 sps using 2 level FSK modulation and
consists of two concurrent phases of information at
1600 bps, phase-A and phase-C. The 6400 bps rate is
transmitted at 3200 sps using 4 level FSK modulation and
consists of four concurrent phases of information at
1600 bps (phase-A, -B, -C and -D).
The vector field consists of a series of vector words.
Depending upon the type of message, a vector word (or
words in the case of a long address) may either contain all
of the information necessary for the message, or indicate
the location of message words in the message field
comprising the message information. Short addresses
have one associated vector word in the vector field. Long
addresses have one associated vector word in the vector
field directly followed by the first message codeword of the
call.
Each block has eight interleaved words per phase, thus
there are 88 codewords (numbered 0 to 87) per phase in
every frame. Each word has information contained within
an error correcting code which allows for bit error
correction and detection. The 88 words in each phase are
organized into a block information field, an address field, a
vector field, a message field, and an idle field.
The boundaries between the fields are independent of the
block boundaries. Furthermore, at 3200 and 6400 bps,
the information in one phase is independent of the
information in a concurrent phase, and the boundaries
between the fields of one phase are unrelated to the
boundaries between the fields in a concurrent phase.
The message field consists of a series of information
words containing message information. The message
information may be formatted in ASCII, BCD or binary
depending upon the message type.
1998 Jun 17
46
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
15 cycles (1 hour)
cycle 0
frame 0
sync
cycle 1
cycle 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cycle 13
cycle 14
1 cycle (4 minutes) = 128 frames
frame 1
frame 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . frame 126
frame 127
1 frame (1.875 seconds) = sync + 11 blocks
block 0
block 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . block 9
block 10
sync (115 ms)
frame info
interleaved block (160 ms)
sync 1
sync 2
8 × 32 bits @ 1600 bps
2 - level FM
16 × 32 bits @ 3200 bps 2 or 4 level FM
32 × 32 bits @ 6400 bps
8 + 32 bits @ 1600 bps
4 - level FM
MGK469
48 + 32 bits @ 3200 bps (25 ms)
128 + 32 bits @ 6400 bps
32 bits @ 1600 bps (20 ms)
112 bits @ 1600 bps (70 ms)
Fig.17 FLEX signal structure.
1998 Jun 17
47
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
Tables 54 and 55 show an example of receiving three
messages (possibly portions of fragmented or group
messages), and two BIW packets in the first two blocks of
a 2 phase 3200 bps FLEX frame in case of an
any-phase pager. Table 54 shows the block number, word
number and word content of both phase-A and phase-C
(subscripts indicate the call number). In a 6400 bps
FLEX frame, there would be four phases: A, B, C and D;
in a 1600 bps signal there would be only phase-A.
Table 55 shows the sequence of packets transmitted to
the host.
8.8.2
MESSAGE BUILDING
The PCD5008 sends data from the FLEX signal to the
host in packets. Data is transmitted one block at a time,
and one phase at a time. For a 2 phase transmission,
information in block 0 phase-A is converted into packets
and sent to the host, then information in block 0 phase-C
is sent to the host followed by information in
block 1 phase-A and then information in block 1 phase-C
etc. Codewords for different calls may therefore be
interleaved, so the host must use the phase and word
number embedded in each packet to associate that packet
with a particular call.
Table 55 PCD5008 packet sequence
The phase and word number of the vector packet provides
a unique key which allows the host to associate all the data
for a particular call within a frame. The host must then use
information embedded in the vector word to calculate what
message word locations are associated with the vector.
PACKET WORD
PACKET PHASE
COMMENT
note 1
TYPE
address
address
vector
NO.
1
2
3
A
A
A
7
8
7
note 1
pointer to
phase-A
word 9
Table 54 FLEX transmission sequence
BLOCK WORD
PHASE-A
PHASE-C
4
5
6
C
C
C
BIW
BIW
n.a.
n.a.
10
note 2
note 2
note 1
0
1
2
BIW1; note 1
addr; note 2
addr; note 2
addr1
BIW1; note 1
BIW
long
address
BIW
3
addr; note 2
addr; note 2
long addr3 (cw 1)
long addr3 (cw 2)
addr; note 2
vect; note 2
vect; note 2
vect3; note 3
7
A
vector
8
pointer to
phase-A
word 12
0
4
addr2
5
6
vect; note 2
vect; note 2
vect1
8
A
A
A
A
A
A
A
C
message
9
mess1 (cw 1)
mess1 (cw 2)
mess1 (cw 3)
mess2 (cw 1)
mess2 (cw 2)
mess2 (cw 3)
mess2 (cw 4)
7
9
message 10
message 11
message 12
message 13
message 14
message 15
8
vect2
10
11
12
13
14
15
9
mess1 (cw 1)
mess1 (cw 2)
mess1 (cw 3)
10
11
mess3 (cw 1);
note 4
1
12
mess2 (cw 1)
mess2 (cw 2)
mess2 (cw 3)
mess2 (cw 4)
mess; note 2
mess; note 2
mess3 (cw 2)
mess3 (cw 3)
vector
10
pointer to
phase-A
word 14
13
14
15
16
17
18
C
C
C
message 11
message 14
message 15
mess3 (cw 1)
mess3 (cw 2)
mess3 (cw 3)
Notes
1. Phases begin with BIW1, which is not sent to the host.
2. Codewords not addressed to the pager.
Notes
1. Word number in an address is that of the
corresponding vector.
3. Vector for long address indicates the location of the
second and third message words.
2. BIW sent if BIW reception enabled by SBI bit in the
control packet.
4. For long addresses, the first message word
immediately follows the vector.
1998 Jun 17
48
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
counter. AFM remains active until the host determines that
no further data can be sent to it outside programmed
frames, i.e:
8.8.3
ALL FRAME MODE (ID = 03H)
The FLEX protocol requires pagers to be capable of
receiving data in frames other than pagers’ programmed
frames and frames implied by collapse values. This is
achieved in the PCD5008 by all frame mode (AFM) which
is required to implement the following features:
• The TAE counters are all zero indicating that no further
temporary message data is expected
• The AFM counter is zero indicating that no further data
is expected for fragmented messages
• Fragmented messages Section 8.8.5)
• Temporary addresses (Section 8.8.4).
• The FAF bit is clear.
Both the AFM counter and the TAE counters can only be
incremented internally by the PCD5008 and can only be
decremented by the host via AFM packet. Neither the
TAE counters nor the AFM counter can be incremented
past the value 127 (it does not roll-over) or decremented
past the value 0. The TAE counters and the AFM counter
are cleared on a reset and when the decoder is turned off.
The PCD5008 enters AFM automatically and when
in AFM, it decodes every FLEX frame irrespective of
whether it is a programmed frame. In AFM the PCD5008
sends a status packet with the end-of-frame (EOF) bit set
at the end of every frame. In addition the host can force
AFM by sending an AFM packet with the force all frame
mode (FAF) bit set.
DAF: decrement all frame mode counter, see Table 56.
Setting this bit decrements the AFM counter by one. If a
packet is sent with this bit clear, the AFM counter is not
affected. Value after reset = 0.
The PCD5008 contains a number of counters which are
used to track the number of active calls requiring AFM.
These consist of an AFM counter for tracking the number
of active fragmented messages and 16 temporary address
enable (TAE) counters which count the number of times
each temporary address has been enabled. These
counters are automatically incremented when a
corresponding vector is received, i.e.:
FAF: force all frame mode, see Table 56. Setting this bit
forces the PCD5008 to enter AFM. If this bit is clear, the
PCD5008 may or may not be in AFM depending on the
status of the AFM counter and the TAE counters. This
functionality may be useful in acquiring transmitted time
information. Value after reset = 0.
• A short instruction vector indicating a temporary address
has been assigned to this pager
• A vector indicating a message for this pager with a
format which allows fragmentation.
DTA: decrement temporary address enable counter, see
Table 56. When a bit in this word is set, the corresponding
TAE counter is decremented by one. When a bit is clear,
the corresponding TAE counter is not affected. When a
TAE counter reaches zero, the temporary address is
disabled. Value after reset = 0.
The host must determine when no further data can be
received for a message associated with a temporary
address, or a fragmented message, and send an
AFM packet, see Table 56, to decrement the appropriate
Table 56 All frame mode packet bit assignments
BYTE
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
1
BIT 0
1
3
2
1
0
DAF
DTA15
DTA7
FAF
0
0
0
0
0
0
DTA14
DTA6
DTA13
DTA5
DTA12
DTA4
DTA11
DTA3
DTA10
DTA2
DTA9
DTA1
DTA8
DTA0
1998 Jun 17
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Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
3. The host examines the vector packet to identify
8.8.4
TEMPORARY ADDRESSES
which TA is assigned and the frame in which the TA is
expected.
FLEX allows dynamic group calls in which a common
message is sent to a group of paging devices. This is
achieved by assigning the same temporary address (TA)
to each pager in the group using the pagers’ personal
addresses and the short instruction vector. The short
instruction vector causes the TA to be active in the next
occurrence of a specific frame (if the designated frame is
equal to the present frame the host is to interpret this as
the next occurrence of this frame in the following cycle).
4. The PCD5008 continues to decode all of the frames
and passes any address information, vector
information and message information to the host
followed by a status packet indicating the end of each
frame and the current frame number.
5. The host processes data packets received while the
PCD5008 is in AFM. It uses the AFM packet to
decrement the appropriate TA counter when no further
data can be expected for the corresponding TA. This
occurs when:
FLEX specifies sixteen TAs which remain valid for one
message starting in the specified frame and remaining
valid throughout the following frames to the completion of
the message. The FLEX protocol restricts the placement
of TAs such that once assigned to a specific frame they
cannot occur in the FLEX transmission before that
frame.
a) The TA is not found in the assigned frame.
b) The TA is found in the frame it was assigned and
was not a fragmented message.
c) The TA is found in the assigned frame was a
fragmented message and the rules for message
fragmentation (Section 8.8.5) indicate that no
further data can be expected. In this case the host
must send an AFM packet with both the DAF and
the appropriate DTA bits set in order to terminate
both the fragmented message and the TA.
The PCD5008 uses AFM (Section 8.8.3) to allow the
reception of TAs outside programmed frames.
The sequence for the host and the PCD5008 to operate
a TA is:
1. The PCD5008 receives an address codeword followed
by a vector codeword with
6. The above operation is repeated for every enabled TA.
V2V1V0 = 001 and I2I1I0 = 000 indicating a short
instruction vector which assigns a TA to this pager.
2. The PCD5008 passes the address and vector
codeword to the host as packets and increments the
corresponding TA counter and enters AFM.
1998 Jun 17
50
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
If the fragmented message was received on a
temporary address, then the appropriate DTA bit
should also be set in the AFM packet.
8.8.5
MESSAGE FRAGMENTATION
The FLEX frame length limits the maximum number of
message codewords that can be associated with an
address codeword. Messages longer than 84 codewords
must be sent as several fragments. The PCD5008
uses AFM (Section 8.8.3) to allow the reception of
fragmented messages.
b) If this is the first fragment of a fragmented message
(C is set and no fragmented messages are in
progress for this address and message number),
then the host does not decrement the AFM counter
and expects further fragments to be received for
this address in subsequent frames.
The fragments of a message are sent in sequence. Each
fragment contains a checksum character to detect errors
in the fragment, a message number to identify which
message the fragment is a part, and the continue bit which
either indicates that more fragments are in queue or that
the last fragment has been received. Each fragment also
contains a fragment number starting with 3 for the first
fragment and then incremented through the
c) If this is the second or subsequent fragment of a
fragmented message and further fragments will
follow, (C is set and a fragmented message is in
progress for this address and message number),
then the host decrements the AFM counter by
sending an AFM packet to the PCD5008 with the
DAF bit set.
sequence 0, 1 or 2 in subsequent fragments. This allows
the detection of missing fragments.
d) If this is the last fragment of a fragmented
message, (C is clear and a fragmented message is
in progress for this address and message number),
then the host decrements the AFM counter by 2,
sending 2 AFM packets to the PCD5008 with the
DAF bit set. If the fragmented message was
received on a TA, then one of these AFM packets
should also have the appropriate DTA bit set.
Message fragments may not be separated by more than
32 frames (1 minute) or 128 frames (4 minutes), as
indicated by the service provider. During the reception of a
fragmented message, the PCD5008 examines every
frame for additional fragments until the last fragment is
encountered or the host determines that more than
32 or 128 frames have elapsed since the reception of the
previous message fragment.
4. If, on receiving a status packet, the host determines
that more than 32 or 128 frames have elapsed since
the reception of a fragment for a fragmented message
then the host decrements the AFM counter by sending
an AFM packet to the PCD5008 with the DAF bit set.
If the fragmented message was received on a TA, then
the appropriate DTA bit should also be set in the
AFM packet.
The sequence for the host and the PCD5008 to receive a
fragmented message is as follows:
1. The PCD5008 receives an address codeword followed
by a vector indicating one of:
a) Secure (vector type = 000)
b) Alphanumeric (vector type = 101)
c) Hexadecimal/binary (vector type = 110).
5. When no fragmented messages are in progress
(the AFM counter = 0) and no TAs are pending
(all TA counters = 0) and the FAF bit is clear in the
AFM packet, the PCD5008 leaves AFM.
The PCD5008 passes the address, vector and
message codewords to the host as packets and
increments its internal AFM counter and enters AFM.
As an alternative to the above scheme, the host may
choose to decrement the AFM counter at the end of the
entire message by decrementing it once for each fragment
received. This method is limited to a maximum of
127 fragments.
2. While in AFM, the PCD5008 decodes all of the frames
passing any address, vector and message information
to the host followed by a status packet indicating the
end of each frame and the current frame number.
3. Every time the host receives a secure, alphanumeric
or hexadecimal/binary vector packet, it inspects the
message continued flag (C) in the first message
packet:
Tables 57 and 58 show examples of message reception
with and without message fragmentation.
a) If this is not a fragmented message (C is clear and
no fragmented messages are in progress for this
address and message number), then the host
decrements the AFM counter by sending an
AFM packet to the PCD5008 with the DAF bit set.
1998 Jun 17
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Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
Table 57 Alphanumeric message without fragmentation
PACKET
AFM
PHASE
COMMENT
COUNTER
NUMBER
TYPE
1st
2nd
3rd
4th
address 1
vector 1
message
AFM
A
A
A
0
1
1
0
address 1 is received
vector = alphanumeric type
message word received; C bit = 0; no more fragments are expected
host writes AFM packet to the PCD5008 with the DAF bit = 1
Table 58 Alphanumeric message with fragmentation
PACKET
AFM
PHASE
COMMENT
COUNTER
NUMBER
TYPE
1st
2nd
3rd
address 1
vector 1
A
A
A
0
1
1
address 1 is received
vector = alphanumeric type
message
message word received; C bit = 1;
message is fragmented, more expected
4th
5th
6th
7th
status
1
1
2
2
end of frame indication (EOF = 1)
address 1 is received
address 1
vector 1
message
B
B
B
vector = alphanumeric type
message word received; C bit = 1;
message is fragmented, more expected
8th
9th
AFM
1
1
1
2
2
1
0
host writes AFM packet to the PCD5008 with the DAF bit = 1
end of frame indication (EOF = 1)
status
10th
11th
12th
13th
14th
address 1
vector 1
message
AFM
A
A
A
address 1 is received
vector = alphanumeric type
message word received; C bit = 0; no more fragments are expected
host writes AFM packet to the PCD5008 with the DAF bit = 1
host writes AFM packet to the PCD5008 with the DAF bit = 1
AFM
1998 Jun 17
52
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
codeword are added to form a binary sum. The message
checksum is the 1’s complement of the LSBs of the
binary sum, where the number of bits taken is determined
by the message type (Section 8.7.8).
8.8.5.1
Fragmentation of non-7-bit character sets
FLEX alphanumeric messages can be used to send
symbolic characters like Chinese, Kanji, etc. In this case
several ASCII characters are used to represent each
symbolic character. Enhanced fragmentation (EF) rules
are provided by FLEX to allow character positions within
a fragment to be determined in the event of missing
fragments under poor signal conditions:
In the case of the 6-bit message checksum used in
numeric messages, a binary sum is first calculated as
described above. The binary sum is then truncated to its
8 LSBs, then the 2 MSBs are shifted right by 6 bits and
added to the least significant 6 bits to form a new
binary sum. The 6 LSBs of this new sum are taken and
1’s complemented to form the 6-bit message checksum.
1. The pager must remove <NUL> characters from the
end of fragments (where they are used as fill
characters) so that the displayed message is not
affected. To determine character boundaries,
<NUL> (00H) characters in all other positions must be
considered a result of channel errors. This allows each
fragment to end with a complete character and does
not disrupt pagers which do not follow all the EF rules.
8.8.7
MESSAGE NUMBERING
FLEX messages may be numbered (Section 8.7.8), in
this case the system controller assigns message numbers
(for each paging address separately) starting at 0 and
progressing up to a maximum of 63 in numerical order.
The maximum roll-over number is defined in the pager
code plug to accommodate values set in the system
infrastructure. When message numbers are not received
in order, the subscriber should assume a message has
been missed. When a message number is missed, the
subscriber or the pager may determine the missing
message number(s) allowing a request to be made for
retrieval.
2. The last fragment of a message containing symbolic
characters is completed by filling unused character
positions with <ETX> (03H) characters or
<NUL> characters. When a message ends at exactly
the last character position of the last BCH codeword,
no additional <ETX> is required.
3. The U and V bits (Table 45) which aid decoding, are
available in all fragments following the initial fragment.
In the first fragment the message starts in the default
character mode (U and V = 10). For subsequent
fragments the definition of the U and V field is as
shown in Table 59. When the U and V field is 00,
characters may be split between fragments. When the
U and V field is not 00, each fragment starts on a
character boundary with the character mode defined
as in Table 59.
Messages which can be received out of sequence are
indicated by clearing the message retrieval flag R.
Messages with R cleared number should not be included
in the missed message calculation.
In case of fragmented messages, this number is also used
to identify fragments of the same message. Multiple
messages to the same address must have separate
message numbers.
8.8.6
MESSAGE CHECKSUMS
FLEX provides a message checksum facility for
alphanumeric, numeric, hex/binary, and secure
Table 59 Fragmentation control bit definitions
U0 V0
DEFINITION
messages. The checksum is calculated by summing the
information bits of each codeword in the message or
message fragment (including control information and
termination characters and bits in the last message
codeword). Information bits of each codeword are broken
into three groups as indicated in Table 60. Bits i0, i8 and i16
are the LSBs of each group and bit i0 is the first bit of the
codeword to be transmitted. The 3 groups are for each
0
0
0
1
EF not supported in controller
reserved (for a second alternate character
mode)
1
1
0
1
default character mode start position 1
alternate character mode start position 1
Table 60 Bit groups for message checksums
i0
i1
i2
i3
i4
i5
i6
i7
i8
i9
i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20
group 2 group 3
group 1
1998 Jun 17
53
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
9
LIMITING VALUES
In accordance with the absolute maximum rating system (IEC 134).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
note 1
MIN.
MAX.
UNIT
VDD
IDD
II
−0.5
−
+5.0
50
V
supply current
mA
mA
mA
V
DC input current (any input)
DC output current (any output)
input voltages (all inputs)
total power dissipation
−10
−10
−0.5
−
+10
IO
+10
VI
note 2
VDD + 0.5
300
Ptot
PO
Tamb
Tstg
mW
mW
°C
power dissipation per output
operating ambient temperature
storage temperature
−
10
−25
−65
+70
+150
°C
Notes
1. VDD1 and VDD2 respectively VSS1 and VSS2 must be connected at the same potential.
2. VI(max) = 5.0 V.
10 DC CHARACTERISTICS
Tamb = −25 to +70 °C; VDD = 2.2 V; f = 76.8 kHz; unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD
supply voltage
1.8
2.2
4.2
4.4
3.6
V
IDD(stby)
IDD
standby supply current
operating supply current
on = 0; note 1
on = 1; note 2
−
−
10
µA
µA
−
Digital inputs: OSCPD, TEST2, TEST3, RESET, LOBAT, EXTS0, EXTS1, SS and MOSI
VIL
VIH
ILI
LOW-level input voltage
−
−
−
−
0.2VDD
V
HIGH-level input voltage
0.8VDD
−
V
LOW/HIGH-level input leakage current
−
1
µA
Digital outputs: MISO, READY, CLKOUT, SYMCLK and S0 to S7
VOL
VOH
ILO
LOW-level output voltage
HIGH-level output voltage
Isink = 0.8 mA
−
0.1
0.4
V
Isource = −0.8 mA
V
DD − 0.4 VDD − 0.1 −
V
LOW/HIGH-level output leakage current 3-state outputs
−
−
1
µA
Notes
1. External clock signal (frequency = 76.8 kHz, amplitude = VSS to VDD) at pin EXTAL; OSCPD = HIGH;
test inputs = LOW; other inputs = HIGH; outputs unconnected (note that any additional capacitive load at
pin CLKOUT increases the supply current); SPI transmit enabled; to obtain the supply current of an application with
a crystal connected as in Fig.18, a typical oscillator current of 2 µA needs to be added to this value
(see Chapter 12); Tamb = 25 °C.
2. As note 1, but PCD5008 configured via SPI and synchronous to a typical FLEX data stream (collapse value = 4),
Tamb = 25 °C.
1998 Jun 17
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Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
11 AC CHARACTERISTICS
Tamb = −25 to +70 °C, VDD = 1.8 to 3.6 V, fEXTAL = 76.8 kHz, maximum load capacitance = 50 pF connected to any
digital output; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Reset timing
tW(rst)
RESET pulse width
200
−
−
−
1
−
ns
ns
s
tLH(RESET-READY) RESET LOW to READY HIGH
200
−
tHL(RESET-READY) RESET HIGH to READY LOW stable 76.8 kHz clock
−
Start-up timing
tstrt(osc)
th(rst)
oscillator start-up time
RESET hold time
see Fig.18
−
1
−
−
−
−
s
200
−
−
ns
T
s
tHL(RESET-READY) RESET HIGH to READY LOW note 1
76800
1
tWUL(osc-READY)
oscillator warmed up to
READY LOW
−
SPI timing
fSCK
operating frequency
cycle time
0
−
−
−
−
−
1
MHz
ns
Tcy(SCK)
tLEAD1
1000
200
200
−
−
select lead time
−
ns
tLAG1
de-select lag time
SS-to-READY delay time
−
ns
td(SS-READY)
previous packet did not program
an address word; note 2
80
µs
previous packet programmed an
address word; note 2
−
−
420
µs
tREADYH
tLEAD2
tLAG2
tsu(i)(D)
th(i)(D)
tACC(o)
to(dis)
tDOV
READY HIGH time
READY lead time
READY lag time
MOSI data setup time
MOSI data hold time
MISO access time
MISO disable time
MISO data valid time
MISO data hold time
SS HIGH time
50
200
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
−
200
−
200
200
0
−
200
300
200
−
−
−
th(o)(D)
tSSH
0
200
300
300
−
−
tSCKH
tSCKL
tr
SCK HIGH time
−
SCK LOW time
−
SCK rise time
10% to 90% VDD
10% to 90% VDD
1
tf
SCK fall time
−
1
Notes
1. T is one period of the 76.8 kHz clock source. Note that from power-up, the oscillator start-up time can influence the
availability and period of clock strobes. This can affect the RESET HIGH to READY LOW timing.
2. When the host re-programs an address word with a host-to-decoder packet ID > 7FH, there is an added delay before
the PCD5008 is ready for another packet.
1998 Jun 17
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Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
12 OSCILLATOR CHARACTERISTICS
Tamb = −25 to +70 °C; note 1.
SYMBOL
PARAMETER
external capacitor at pin EXTAL
external capacitor at pin XTAL
external feedback resistor
oscillator transconductance
CONDITIONS
note 1
MIN.
TYP. MAX. UNIT
C1
−
15
−
pF
pF
MΩ
µS
µS
µA
C2
note 1
−
15
−
Rf
note 1
−
10
−
gm(osc)
VDD = 1.8 V
9.4
−
19.6
22.6
2
−
VDD = 3.6 V
50
−
Iosc
oscillator operating supply current
VDD = 2.2 V; note 2
−
Notes
1. Designed for quartz crystal type: SEIKO VTC200 or equivalent; parameters: f = 76800Hz, RS = 35 kΩ (max.),
CL = (C1//C2) + Cstray = 8 to 12 pF, C0 = crystal shunt capacitance = 0.8 pF (typ.),
Cf = typical parasitic pin capacitance = 2 pF; maximum overall frequency tolerance (including transmitter)
is 300 ppm (Section 8.4.4).
2. Extracted from evaluations under conditions as in Fig.18; this value is strongly dependent on external conditions
(load and parasitic capacitances).
13 THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
VALUE
UNIT
thermal resistance from junction to ambient in free air
80
K/W
14 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
1998 Jun 17
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Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
15 TEST AND APPLICATION INFORMATION
15.1 Example application
DC/DC
CONVERTER
V
V
sup
DD
10 µF
100 nF
KEYPAD
OSCPD,
TEST2, TEST3
V
, V
DD1 DD2
SYMCLK
READY, SS, SCK,
CLKOUT
RECEIVER
MOSI, MISO
FRONT-END
5
MICROCONTROLLER
P83CL881
PCD5008
RESET
S0 to S7
IF AND
4-LEVEL
DEMODULATOR
EXTS0, EXTS1
2
I C-bus
TOUT0 to
TOUT3
2
LOBAT
EEPROM
EXTAL
15 pF
XTAL
15 pF
V
, V
SS1 SS2
LCD
DRIVER
76.8 kHz
LCD
MBK030
10 MΩ
Fig.18 Example application.
1998 Jun 17
57
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
15.2 System block diagram
PAGING RECEIVER
RF RECEIVER
BATTERY
LOW DETECTOR
HOST
MICROPROCESSOR
battery low
indication
receiver
control
lines
reset
USER INTERFACE
API
8
PCD5008
demodulator
data
serial
peripheral
interface
INTEGRATED
IF AMPLIFIER &
DEMODULATOR
TM
FLEXstack SOFTWARE
2
SPI INTERFACE
5
MBK098
76.8 kHz crystal
Fig.19 System block diagram.
1998 Jun 17
58
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
• Enhanced message fragmenting for symbolic character
transmission requires that the encoder track character
boundaries within each fragment in order to avoid
character splitting.
15.3 FLEX encoding and decoding rules
The encoding and decoding rules identify the minimum
requirements which must be met by the paging device,
paging terminal or other encoding equipment to properly
format a FLEX data stream for RF transmission and to
successfully decode it.
• Message numbering as an optional feature is offered by
some carriers and available on an individual subscriber
basis.
15.3.1 FLEX ENCODING RULES
• Message numbers must be assigned sequentially in
ascending order.
The FLEX encoding rules are as follows:
• Message number sequences must be separately
maintained for each individual and radio group address.
• The stability of the encoder clock used to establish time
positions of FLEX frames must be no worse than
±25 ppm (including worst case temperature and aging
effects).
• Message numbers are not used (retrieval message
number disabled) in conjunction with a dynamic group
address.
• A maximum of 2 occurrences of an identical individual or
radio group address is allowed in any frame for
unfragmented messages. This rule applies across all
phases in a multi-phase frame. For example, for
decoding devices that support any-phase addressing,
an any-phase address may appear at once in two
different phases in a single multi-phase frame.
• When a missed message is re-transmitted from
message retrieval storage, the message must have
R = 0 to avoid creating an out of sequence message
which may cause the pager to indicate a missed
message.
15.3.2 FLEX DECODING RULES
• Once an individual or radio group address is used to
begin transmitting a fragmented message, that same
address must not be used to start a new fragmented
transmission until the first fragmented transmission has
been completed.
The FLEX decoding rules are as follows:
• FLEX decoding devices may implement either
single-phase addressing or any-phase addressing.
• FLEX decoding devices that support the numeric
vector type (V2V1V0 = 011) must also support the short
message vector (V2V1V0 = 010) with the message
type (t1t0) set to 00.
• For the duration of time that an individual or radio group
address is being used to send a fragmented message,
that same address must not appear more than once in
any frame to send an unfragmented message.
• FLEX decoding devices that support the alphanumeric
vector type (V2V1V0 = 101) must support the numeric
vector type (V2V1V0 = 011) and the short message
vector (V2V1V0 = 010) with the message type (t1t0)
set to 00, FLEX paging devices that implement
any-phase and support the alphanumeric vector type
(V2V1V0 = 101) must also support the short instruction
vector (V2V1V0 = 001) with the instruction type (i2i1i0)
set to 000.
• Once a specific dynamic group address (temporary
address) is assigned to a group, it must not be reused
until its associated message has been transmitted in its
entirety. Given this constraint, the same dynamic group
address can only appear once in any frame.
• A dynamic group address cannot be used to set up a
second dynamic group.
• Messages using any of the three defined numeric
vectors (V2V1V0 = 011, 100 and 111) cannot be
fragmented, and thus must be completely contained in a
single frame.
• FLEX decoding devices must be capable of decoding
frames at all of the following combinations of data rate
and modulation mode. They are: 1600 bps 2 level;
3200 bps 2 level; 3200 4 level and 6400 bps 4 level.
• Fragments of the same message must be sent at a
frequency of at least 1 every 32 frames (i.e. at least
once a minute) or 1 every 128 frames (i.e. at least once
every 4 minutes) as specified by the service provider.
• FLEX decoding devices must be designed to tolerate
4 minute fragment separation times.
1998 Jun 17
59
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
16 PACKAGE OUTLINE
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm
SOT358-1
c
y
X
A
24
17
25
16
Z
E
e
H
E
A
E
(A )
3
2
A
A
1
w M
p
θ
b
L
p
pin 1 index
L
32
9
detail X
1
8
e
Z
D
v M
A
w M
b
p
D
B
H
v M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.4 0.18 7.1
0.3 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.9
0.5
0.9
0.5
mm
1.60
0.25
0.8
1.0
0.2 0.25 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-19
97-08-04
SOT358 -1
1998 Jun 17
60
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
If wave soldering cannot be avoided, for LQFP
17 SOLDERING
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
17.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
17.2 Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
17.4 Repairing soldered joints
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
17.3 Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
CAUTION
Wave soldering is NOT applicable for all LQFP
packages with a pitch (e) equal or less than 0.5 mm.
1998 Jun 17
61
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
18 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
19 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Jun 17
62
Philips Semiconductors
Product specification
FLEX Pager Decoder
PCD5008
NOTES
1998 Jun 17
63
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For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
435102/1200/02/pp64
Date of release: 1998 Jun 17
Document order number: 9397 750 03705
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