PCD5041HZ-T [NXP]
IC TELECOM, CORDLESS, BURST MODE CONTROLLER, PQFP80, Cordless Telephone IC;
| 型号： | PCD5041HZ-T |
| 厂家： | 
NXP |
| 描述： | IC TELECOM, CORDLESS, BURST MODE CONTROLLER, PQFP80, Cordless Telephone IC 控制器 |
| 文件： | 总28页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCD5041
DECT burst mode controller
1996 Oct 31
Objective specification
Supersedes data of October 1992
File under Integrated Circuits, IC17
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
CONTENTS
FEATURES
2
3
4
5
6
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
6.1
Internal bus and data memory
Internal Bus
Data Memory
Clock generation and correction
Programmable communication controller and
program memory
6.1.1
6.1.2
6.2
6.3
6.3.1
6.3.2
6.4
PCC
PCC functions
Speech interface
6.4.1
6.4.2
6.4.3
6.5
12-slot mode
Muting
Local call
RF interface
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.5.10
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.7
Serial receiver
Serial transmitter
Seamless handover
RF control signals
Synthesizer programming
RSSI measurement
Local call switching
Data synchronization
Ciphering machine
Comparator/data slicer on PCD5041HZ
Microcontroller Interface
Function of the microcontroller interface
Microcontroller interrupts
Watchdog
Power-down
Survey of registers
7
LIMITING VALUES
CHARACTERISTICS
PACKAGE OUTLINES
SOLDERING
8
9
10
10.1
10.2
10.3
10.4
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
11
12
DEFINITIONS
LIFE SUPPORT APPLICATIONS
1996 Oct 31
2
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
1
FEATURES
2
GENERAL DESCRIPTION
• On-chip pre-programmed Communication Controller
with embedded firmware for implementation of Traffic
Bearer Control (TBC), MAC message handling,
scanning, and control of the device’s other functional
units.
The PCD5041 DECT Burst Mode Controller (BMC) is a
custom IC that performs the DECT Physical Layer and
MAC Layer time-critical functions, for use in DECT
handset products which comply with the following
standards (and updates):
• Portable Part (PP) modes
• TDMA frame (de)multiplexing
• Encryption
• DECT CI part 2: Physical layer (DE/RES 3001-2)
• DECT CI part 3 : Medium Access Control layer
(DE/RES 3001-3)
• DECT CI part 7: Security features for DECT
(DE/RES 3001-7)
• Scrambling
• CRC generation and checking
• Beacon transmission control (by P00 packets)
• DECT CI part 9: Public Access Profile
(DE/RES 3001-9).
• On-chip comparator for receive data slicer function (only
available in the LQFP80 package)
The PCD5041 has interfaces to:
• ADPCM CODECs in the handset mode
• Switches up to12 active speech channels from speech
• A radio transceiver; the interface is fully decoded, and
interface to 1152 kbit/s. radio interface, and vice versa
includes power-down signals
• Dual channel speech/data capability
• An external microcontroller.
• Received Signal Strength Indication (RSSI)
measurement, with on-chip 6-bits peak/hold detector
The PCD5041 is designed to be connected to an ADPCM
CODEC (Philips’ PCD5032, for example) and an
80C51-type microcontroller. Other microcontrollers (e.g.
68000) and CODECs can also be supported.
• Quality control report
• Digital Phase Locked Loop (DPLL)
• Synchronization (handset to active bearer, base station
to cluster of RFPs)
• Seamless handover procedure
• Fast (hardware) and slow (software) mute function
• 1 kbyte extended RAM memory
• On-chip crystal oscillator (13.824 MHz)
• Programmable microcontroller clock frequency
• Programmable interrupts
• Watchdog with two programmable time-outs
• Low power consumption in standby mode
• Low supply voltage (2.7 to 5.5 V)
• SACMOS technology.
3
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
PCD5041H
QFP64
SOT319-2
plastic quad flat package; 64 leads (lead length 1.95 mm); body
14 × 20 × 2.8 mm
PCD5041HZ
1996 Oct 31
SOT315-1
LQFP80 plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm
3
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
4
BLOCK DIAGRAM
PCD5041
TIMING, CONTROL,
CLOCK
DECT
BURST MODE
CONTROLLER
GENERATION
internal
bus
to CODEC/
Highway
SPEECH
INTERFACE
DATA MEMORY
2 kbyte RAM
3-wire synthesizer
interface
PROGRAMMABLE
COMMUNICATION
CONTROLLER (PCC)
RF INTERFACE
Rx/Tx data
PCC
8051/68000
interface
MICROCONTROLLER
INTERFACE
PROGRAM MEMORY
4 kbyte ROM
MBH705
Fig.1 Block diagram.
5
PINNING (see Figs 2 and 3)
PIN
SYMBOL
TYPE(2)
DESCRIPTION
QFP64
LQFP80(1)
AD0 to AD7
1 to 8
80, 1, and
3 to 7
I/O
address/Data bus
ALE
9
10
9
11
I
I
address latch enable
CS
chip select (active LOW)
address bus
A8 to A10
VDD1
13 to 11
14
14 to 12
15
I
P
O
positive supply 1
PROC_CLK
15
16
microcontroller clock; programmable from fCLK/64 to fCLK,
where fCLK is the crystal oscillator frequency
VSS1
16
17
18
19
20
17
20
21
22
23
P
I
negative supply 1
XTAL1
XTAL2
VSS2
crystal oscillator input
O
P
O
crystal oscillator output
negative supply
RESET_OUT
watchdog timer output; intended to reset the external
microcontroller when expired
RD
21
22
23
24
25
26
I
I
read (active LOW)
write (active LOW)
WR
RDY
O
ready signal (active LOW), to initiate wait states in the
microcontroller (open drain)
1996 Oct 31
4
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
PIN
SYMBOL
TYPE(2)
DESCRIPTION
QFP64
LQFP80(1)
INT
24
25
26
27
−
27
29
31
32
33
O
O
interrupt (active LOW)
100 Hz frame timer
negative supply 3
CLK100
VSS3
DO
P
O
3-state data output on the speech interface
FS3
I/O
8 kHz framing signal to ADPCM CODEC 1 output, for simple
base + handset, otherwise 8 kHz framing input
FS1
FS4
FS2
28
−
34
35
36
I/O
I/O
O
8 kHz framing signal to ADPCM CODEC 1 output, for simple
base + handset, otherwise 8 kHz framing input
8 kHz framing signal to ADPCM CODEC 1 output, for simple
base + handset, otherwise 8 kHz framing input
29
8 kHz framing signal to ADPCM CODEC 2 in the base station
mode
DI
30
31
37
38
I
data input on the speech interface
DCK
O
simple base + handset; 1152 kHz data clock (output),
otherwise 2048 kHz data clock (input) signal
CLK3
32
39
O
3.456 MHz clock (nominal value, used to adjust system
timing)
ANT_SW
33
34
35
36
37
38
39
40
41
43
44
45
46
47
O
O
O
I
selects one of two antennas
T_ENABLE
T_POWER_RMP
RMT_STAT
SYNTH_LOCK
VSS4
Transmitter Enable (active LOW)
Transmitter Power Ramp control
serial 8-bit data can be read in for each slot; REMote radio
lock indication from synthesizer
negative supply 4
I
P
O
REF_CLK
reference frequency for the synthesizer, i.e. the crystal
oscillator clock fCLK
VDD2
40
41
42
43
44
45
46
47
48
48
49
51
52
53
54
55
56
57
P
O
O
O
O
O
O
O
I
positive supply 2
S_ENABLE
S_CLK
synthesizer enable
clock signal, to be used with S_DATA
serial data to the synthesizer
synthesizer power-down control
VCO bandswitch control signal
control signal for dual synthesizer schemes
serial output data to transmitter
S_DATA
S_POWER_DWN
VCO_BND_SW
1200 HZ
T_DATA
SET_OFF_IN
switches off the crystal oscillator, and prevents all RF signals
from becoming active
TEST1
49
50
58
60
I
I
selects various test modes.; normal operation set to 0
RSSI_AN
analog signal (for basic DECT systems), peak signal strength
measured after a lowpass filter
TEST2
TEST3
R_DATA
51
52
53
−
I
I
I
selects various test modes; normal operation set to 0
selects various test modes; normal operation set to 0
receive data
61
63
1996 Oct 31
5
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
PIN
SYMBOL
TYPE(2)
DESCRIPTION
QFP64
LQFP80(1)
R_ENABLE
R_POWER_DWN
COMP_NE
SLICE_CTR
COMP_OUT
VDD3
54
55
−
64
65
66
67
68
69
70
71
72
73
74
76
77
78
79
O
O
I
receiver enable (active LOW)
receiver power-down
digital input comparator not_enable (active LOW)
slice time constant control
56
−
O
O
P
P
I
digital comparator output
57
58
−
positive supply 3
VSS5
negative supply 5
COMP_INM
VREF
analog comparator input negative
reference input for the A/D converter
analog input positive
59
−
I
COMP_INP
VDD(RAM)
I
60
61
62
63
64
P
I/O
I
power supply for data RAM
SYNCPORT
RESET
in the base station the signal is the SYNCPORT
BMC master reset signal
MEM_SEL
EN_WATCHDOG
I
selects PCC program memory at microcontroller interface
I
enable watchdog input; when HIGH, the watchdog timer of
the BMC is enabled
Notes
1. Un-referenced pins for the LQFP80 package are not connected. FS3, FS4 and the comparator signals are only
available in the LQFP80 package.
2. All signals which are input or I/O, and which can be floating, need to be pulled up to VDD or down to VSS in order to
protect the device against cross-currents. Exceptions are VREF and RSSI_AN, which do not have to be protected.
1996 Oct 31
6
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ALE
CSN
AD10
AD9
AD8
1
2
51 TEST2
50 RSSI_AN
49
3
TEST1
48 SET_OFF_IN
4
5
47
46
T_DATA
1200_Hz
6
7
45 VCO_BND_SW
8
44 S_POWER_DWN
9
43
S_DATA
10
11
12
13
14
15
16
17
18
19
PCD5041H
42 S_CLK
41
S_ENABLE
V
40
DD2
39 REF_CLK
V
V
38
37
36
SS4
DD1
PROC_CLK
SYNTH_LOCK
RMT_STAT
V
SS1
35 T_POWER_RMP
XTAL1
XTAL2
34
T_ENABLE
V
33 ANT_SW
SS2
MBH706
Fig.2 Pin configuration, PCD5041H (QFP64 package).
7
1996 Oct 31
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
AD1
n.c.
1
2
60 RSSI_AN
59 n.c.
TEST1
AD2
AD3
AD4
AD5
AD6
AD7
ALE
n.c.
3
58
57
SET_OFF_IN
4
5
56 T_DATA
55 1200_Hz
6
VCO_BND_SW
7
54
53
S_POWER_DWN
8
9
52 S_DATA
S_CLK
10
11
12
51
50 n.c.
PCD5041HZ
CSN
AD10
S_ENABLE
49
48
47
46
45
44
43
42
41
V
AD9 13
DD2
REF_CLK
AD8
DD1
14
15
16
17
V
V
SS4
PROC_CLK
SYNTH_LOCK
RMT_STAT
V
SS1
T_POWER_RMP
n.c. 18
n.c.
19
20
n.c.
T_ENABLE
XTAL1
MBH707
Fig.3 Pin configuration, PCD5041HZ (LQFP80 package).
8
1996 Oct 31
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
6
FUNCTIONAL DESCRIPTION (see Fig.1)
6.2
Clock generation and correction (see Fig.4)
The PCD5041 has dedicated hardware blocks containing
logic for time-critical functions requiring bit or byte-time
accuracy. Other functions requiring only slot-time
accuracy are performed by software in the Programmable
Communication Controller (PCC). This approach offers
maximum flexibility during prototyping.
The device has an on-chip 13.824 MHz crystal oscillator.
From this source, a few frequencies are derived for internal
and external use. Frequencies generated for external use
are:
• 13.824 MHz for the synthesizer reference
(pin REF_CLK). This output is only provided if the
synthesizer power-down control (output on
pin S_POWER_DWN) is not selected.
6.1
Internal bus and data memory
6.1.1
INTERNAL BUS
• 0.144 to 13.824 MHz for the microcontroller clock
(pin PROC_CLK)
The function of the internal bus is:
• 3.456 MHz for the ADPCM CODEC (pin CLK3)
• 1200 Hz (pin 1200_HZ) for dual synthesizer switching
• 100 Hz (pin CLK100) indicates start of frame.
• To provide access for all functional blocks to the
common data memory
• To provide access for the microcontroller-interface and
the PCC to all other functional blocks.
Nominally, the frequency on pin CLK3 is 3.456 MHz. This
frequency is obtained by dividing the crystal frequency by
4. Sometimes, the crystal frequency will be divided by 3
or by 5, to synchronize the combination of the ADPCM
CODEC and the device to an external source. For the
handset application, the PCD5041 can be synchronized to
the incoming radio channel, using the ‘slot
All functional blocks (speech-interface, RF-interface,
microcontroller-interface and PCC) can autonomously use
the internal bus to communicate with the common data
memory.
A bus controller is used to handle the bus priority
mechanism. When several blocks request access
simultaneously, the request with the highest priority is
handled first.
synchronization’ event of one active channel, so the
handset is locked to one base station.
6.1.2
DATA MEMORY
A large part of the data memory is used for the bit rate
adaptation between the DECT radio interface and the
speech interface. The data memory also acts as the main
communication interface between the external
microprocessor and the PCC.
In a handset, the device uses only 1 kbyte of the common
data memory. The remaining 1 kbyte can be used by the
microcontroller as an extended data memory for the higher
layer software. The microcontroller is not aware of the fact
that it is sharing the memory with the PCD5041. From the
microcontroller’s point of view, the PCD5041’s
microcontroller-interface plus the common data memory
behave as a standard RAM device.
1996 Oct 31
9
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
13.824 MHz system clock
2
6.912 MHz system clock
4 (±1)
clock corrections in this level
3.456 MHz system
clock for ADPCM codec
unless disabled PCD5041's mode register
3
1152 kHz
system/bit clock
bit counter
144
480
24
slot counter
slot counter
FSx signals
(8 kHz)
100 Hz
frame sync
COMPARATOR
'SYNC' event
16
MBH708
Fig.4 Internal clocking scheme of the PCD5041.
6.3
Programmable communication controller and
6.4
Speech interface
program memory
The speech interface block performs the following
functions:
6.3.1
PCC
• Connection to a 1152 kbit/s interface in a handset and a
simple base station in the so called ‘12 slot mode’
The PCC is a RISC-type controller and is used to control
functions which are slot-time accurate. It is well suited for
bit manipulation, and runs at a clock frequency of
6.912 MHz (equivalent to 3.4Mips). After finishing a task, it
switches to a power saving state, from which it returns
after a pre-programmed time.
• Autonomous storing/fetching of ADPCM speech data
in/from the PCD5041’s common data memory, using
internal addressing logic
• Muting of speech data
• Local call.
6.3.2
PCC FUNCTIONS
The most important functions of the PCC are to:
6.4.1
12-SLOT MODE
• Perform the appropriate actions on received messages:
PMID and FMID checking, RFPI checking, TBC
handling
This is the normal operating mode for the PCD5041.
The 12-slot mode is selected if up to 4 ADPCM CODECs
are connected to the PCD5041, where the PCD5041 is the
master of these CODECs. In a handset, or in a simple
base stations which is connected with up to 4 analog lines
to the public network, the PCD5041 is master of the
CODECs. Each CODEC is connected with a separate
framing reference signal (FS1 to FS4) to the PCD5041.
In the QFP64 package, 2 framing signals FS1 and FS2
are available, whereas in the LQFP80 package 4 framing
signals can be used (FS1 to FS4). When more CODECs
• Prepare A-field messages for transmission
• Prepare the RF-interface for the coming slot
• Perform the procedures for RSSI and set-up scan,
maintain scan counters and timers, assemble the RSSI
field in the common data memory
• Filter events and indicate them to the microcontroller by
interrupt.
1996 Oct 31
10
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
are to be connected, the FS5 to FS12 signals have to be
generated externally. When using the framing signals
FS1 to FS4, no interface logic is required when using the
PCD5032 ADPCM CODEC.
6.5
RF interface
Most of the functions performed by the RF interface are
under control of the PCC. Specifically, the processing of
non-speech data and the programming of functions and
registers is done via the PCC.
A speech-slot control table is used to determine where to
store/fetch speech data for transmission and reception.
The hardware speech-interface is capable of addressing
the right speech buffer for the relevant speech slot, and will
maintain a counter carrying the offset to the correct
stored/fetched address.
6.5.1
SERIAL TRANSMITTER
The serial receiver processes the data, which comes from
the RF section, and which is already filtered by the
synchronization part. The data is latched, using the
recovered data clock.
6.4.2
MUTING
The serial receiver will collect the complete A-field and
B-field and store it in the common data memory. Before the
A-field is received, the A-field start address is programmed
by the PCC. Upon reception of A-field nibbles, the address
is updated by the serial receiver. Meanwhile, the PCC will
program the B-field start address.
Due to various reasons the quality of the incoming speech
data may be degraded significantly. By muting the speech
data, these disturbances are not audible (or are less
audible) to the user. The PCD5041 performs two types of
muting:
• Fast muting
• Slow muting.
In Fig.6 the data flow in the serial receiver is shown. Note
that almost no decoding of messages is required. Only the
header of the A-field needs to be decoded to check if a
ciphered message is being received or transmitted, which
requires the ciphering to be switched on in the A-field also.
Fast muting, which is performed by the PCD5041
automatically, is nothing more than a repetition of the
previously received frame (80 speech samples) to the
ADPCM CODEC. It is issued if no Sync word was
detected. Slow muting is issued by the microcontroller,
after having detected a degradation of quality. A slow mute
is implemented as a continuous ‘0000’ nibble transmission
to the ADPCM CODEC, until slow mute is released.
6.5.2
SERIAL RECEIVER
The serial transmitter performs the reverse of the receiver
functions. Several blocks used in the receiver are also
used in the transmitter. Amongst these are the
CRC-generators, the scrambler, and the address
registers. Figure 7 shows the serial transmitter structure.
6.4.3
LOCAL CALL
A local call option is implemented, in order to loopback
data from one CODEC to another CODEC, and vice versa,
see Fig.5.
By transmitting the X-CRC twice, the Z-field is transmitted.
The handling of the address registers is the same for the
transmitter. Transmission of the synchronization sequence
(S-field) is done using the same method as the A-field and
B-field. The S-field is stored in the common data memory
and will be fetched by the transmitter, just before
transmission.
handbook, halfpage
Two additional functions are not shown in Fig.7:
0
1
0
1
DO
• In the handset the data in the serial transmitter may be
advanced by a programmable number of bit periods.
This is done to compensate for the delay in the RF
section
• The transmitted data can be inverted (using a switch in
the PCD5041 mode register), in order to connect the
PCD5041 to VCOs requiring negative modulation.
0
1
0
1
DI
speech slots
speech buffer
pair
MBH710
Fig.5 Local call switching on speech interface.
1996 Oct 31
11
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
DATA MEMORY
DATA MEMORY READ CONTROL
nibble-parallel
bit-serial
ok
DE-CIPHER
DE-CIPHER
CIPHER
CONTROL
R-CRC
other
cs
MUX
MUX
Bprotect
ok
Cs-DEC.
UNSCRAMBLE
ok
R-CRC
X-CRC
A-MAP
B-MAP
D-MAP
D32
MBH737
D00
Fig.6 Serial receiver structure.
DATA MEMORY
DATA MEMORY READ CONTROL
nibble-parallel
bit-serial
CIPHER
CIPHER
CIPHER
CONTROL
R-CRC
other
cs
MUX
MUX
Bprotect
Cs-DEC.
UNSCRAMBLE
R-CRC
X-CRC
A-MAP
B-MAP
D-MAP
D32
MBH736
D00
Fig.7 Serial transmitter structure.
12
1996 Oct 31
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
To program various types of synthesizers, a 3-byte shift
register is present. Three data formats are supported:
8, 16 or 24 bit words can be selected. The transfer of data
from a frequency table in the common data memory to the
shift register is under control of the PCC.
6.5.3
SEAMLESS HANDOVER
Seamless handover guarantees that when speech
information is switched from one slot to another, no speech
samples are lost, added or displaced. Seamless handover
is achieved in the RF interface by:
• Using a look-up table containing the correct start
addresses of the B-fields in the data memory
6.5.6
RSSI MEASUREMENT (see Fig.8)
The RSSI measurement in the PCD5041 RF-interface
block is done in 3 parts: a peak/hold detector, a 6-bit A/D
converter, and an RSSI control unit, which controls the
peak/hold detector and the A/D converter. Once per slot
time, a sample is fetched by the PCC and saved in the
appropriate area of the common data memory.
• The RF receive and transmit blocks move data to/from
the data memory block in 4-bit nibbles.
6.5.4
RF CONTROL SIGNALS
The timing of the control signals to the RF section is fixed,
but such that an RF delay between 1.5 and 7 µs can be
tolerated. Only the transmitter ramp signal and the
synthesizer enable are programmable within certain limits.
If the radio receiver is active in a particular time slot, the
RSSI value will automatically be measured in that slot.
Adjustment to the RSSI_AN input level can be made with
VREF.
6.5.5
SYNTHESIZER PROGRAMMING
To program a synthesizer, a 3-wire serial interface is used.
The signals on this interface are:
• S_ENABLE (enable)
• S_CLK (clock)
• S_DATA (data).
RF-INTERFACE
VREF
internal
bus
6
RSSI_AN
RSSI
CTRL
(HW)
RSSI
PROCESSING
(SW in PCC)
6-BIT
A/D
PEAK
HOLD
RSSI_AN
RSSI value
filtered width
= 30 µs
start_AD
write in memory
RSSI_CTR
(τ =10 to 40 µs)
MBH711
Fig.8 RSSI measurement path.
1996 Oct 31
13
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
Bit synchronization is done using a Digital PLL (DPLL),
with an oversampling factor of 12, i.e. the DPLL is running
at 12 times the data rate. The output from the DPLL is a
receive clock signal (RxC), which acts as the enable for a
20-bit shift register.
6.5.7
LOCAL CALL SWITCHING (see Fig.9)
The PCD5041 provides a local call switching function in
the base station. It stores incoming speech nibbles in the
common data memory, in the area reserved for that
particular receive slot. Then, during the transmit phase, it
passes the start pointer of the same data memory area to
the transmit block. Thus, the speech data is echoed to the
other user. To handle quality degradation for local calls, a
mute can be performed at the RF side of the speech buffer.
Sync word detection is achieved by checking the incoming
data pattern with the expected synchronization field
pattern, using a correlator.
The correlator has a programmable threshold, so it can
accept bit errors in the sync field pattern up to the
threshold level. Furthermore, the correlator window is
programmable. This means that ‘SlotSync’, which
indicates the slot synchronization event, can be detected
only during a certain period (the time window).
6.5.8
DATA SYNCHRONIZATION (see Fig.10)
The data synchronization is done in 2 phases:
• Bit synchronization
• Sync word detection.
RF slots
Rx1
Rx2
Tx1
Tx2
MBH712
speech buffers
in data memory
Fig.9 Local call switching on the RF-side.
13.824 MHz
filtered
R×C
DPLL
EN
D
data in
R_DATA
(1152 kbits/s)
20-BIT SHIFT
REGISTER
FILTER
XOR
Q0 to Q15
Q16 to Q19
base/handset
to serial
receiver logic
threshold
SYNC
CHECK
(1010)
CORRELATOR
(E98A)
correlator
window
MBH713
SlotSync
DPLL_sync
Fig.10 Schematic of the receiver synchronization part.
14
1996 Oct 31
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
The ‘DPLL_sync’ indication should only be used, when
‘SlotSync’ is active. It indicates that the last 4 bits of the
pre-amble field (the training sequence) are received
correctly, and thus indicates that the DPLL was in lock
(synchronized) in time. If the ‘SlotSync’ is active, and the
‘DPLL_sync’ is not, then a sliding interferer might have
been detected.
automatically by the cipher machine. The contents of the
memory space where IV and key are found, are the
responsibility of the PCC, and the external
microprocessor.
6.5.10 COMPARATOR/DATA SLICER ON PCD5041HZ
The PCD5041HZ contains a comparator/data slicer.
The comparator is a stand-alone circuit. No connections
other than power supply are made internally. The
comparator can be used as a data slicer for the receiver
input. The delay requirements listed in Chapter 8 were
derived from this application. Another use of the
comparator is in a successive approximation A/D
converter to indicate battery low-voltage condition, or in a
power-on-reset circuit.
If ‘SlotSync’ is not detected, effectively no data is received
in that slot. This implies a ‘fast mute’ because speech data
received in the previous frame is not destroyed.
6.5.9
CIPHERING MACHINE
The description of the cipher machine is subject to
confidentiality. The specification of its algorithms are
delivered by ETSI under the terms of a Non-Disclosure
Agreement.
When the signal COMP_NE is LOW the comparator is
enabled. When COMP_NE is HIGH the comparator is
disabled, and the circuit consumes no power. If the
comparator is used as a data slicer for the receiver input,
the R_DATA is connected to COMP_OUT, the COMP_NE
is connected to R_ENABLE, both connection are done
externally. The pin COMP_INP is connected to the RF
mixer. A proper bias voltage (from the slicer time constant
control circuit) is connected to COMP_INM. Another use of
the comparator is in a successive approximation A/D
converter for battery voltage detection.
The cipher machine is under control of the TBC, which is
implemented in the PCC. The cipher machine generates
2 fields of ciphering bits:
• A_cipher (40 bits) for A-field messages (ciphers tail
only)
• B_cipher (320 bits) for speech in B-field.
The transmitted ciphered bits are then:
• A_ciphered: = A XOR A_cipher
• B_ciphered: = B XOR B_cipher.
The pins are protected against ESD damaging, with a
protection diode to the positive and negative supply rail.
The input pin COMP_NE has a pull-up resistor which
keeps the comparator in power-down mode by default.
On reception by the peer end point, deciphering consists
of the same operation thanks to the synchronous
generation of A_cipher and B_cipher.
handbook, halfpage
KEY
A_cipher
64 BITS
handbook, halfpage
COMP_INP
(40 bits)
CIPHER
MACHINE
COMP_OUT
COMP_INM
B_cipher
KEY
MBH715
(320 bits)
64 BITS
COMP_NE
MBH714
Fig.12 Circuit schematic of the comparator/data
slicer.
Fig.11 Cipher machine and its sources.
The cipher machine is time-multiplexed on a slot basis.
Initially, the Initialisation Vector (IV) and the key must be
loaded into the cipher machine. Transfer of the IV and key
from the common data area to the cipher machine is done
1996 Oct 31
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Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
6.6
Microcontroller Interface
6.6.3
WATCHDOG
The PCD5041 is equipped with a watchdog timer, which
generates a reset towards an external device (e.g. a
microcontroller) after time-out. Two (fixed) time-out
periods can be programmed; 1.25 s and 82 s.
The watchdog function can be disabled by using the
EN_WATCHDOG input pin.
6.6.1
FUNCTION OF THE MICROCONTROLLER INTERFACE
The microcontroller interface will provide the following
services.
• Direct interface to processors which have an
INTEL-8051 compatible interface
• General interface to processors that can handle ‘wait
states’ e.g. 68000-family; in this case glue logic is
required
6.6.4
POWER-DOWN
The PCC may switch off the 6.912 MHz internal clock, to
enter a power saving mode. All blocks, running on this
clock are then switched off (i.e. RF-interface, cipher block,
speech interface, PCC). This is called the power-down
state, and is only used in the handset mode.
• Processor clock signal of which the frequency is
programmable in order to adjust instantaneously
processor performance to processor work load
• A programmable interrupt register
• A watchdog timer with time-out periods of
1.25 or 82 seconds, depending on the programming.
The 13.824 MHz clock is never switched off. The Timing
Control, microcontroller interface, and Bus Controller keep
running, in order to remain synchronous with a base
station, and to keep the wake-up circuitry active. During
power-down the external microcontroller has still access to
the common data area.
The microcontroller can address the PCD5041 as any
other RAM memory connected to the microcontroller bus.
By writing the ‘Interface-Mode Register’, the
microcontroller can select the interface mode and its own
clock frequency.
6.7
Survey of registers
6.6.2
MICROCONTROLLER INTERRUPTS
For a survey of all addresses occupied refer to
Tables 1 and 2. Some of the address locations are used
differently for read and write. The addresses 000 to 7DF
are occupied by RAM memory, while the upper 32 bytes
are assigned to the hardware registers. A part of the RAM
memory is allocated for use by the RF block, cipher block,
and the speech interface.
The function of microcontroller Interrupts is to make
optimal use of the microcontroller’s processing power, and
to achieve optimal cooperation between time-critical tasks
and less time-critical tasks both executed in software.
Three registers are available to handle interrupts. These
are:
• Interrupt Event Register
• Interrupt Enable Register
• Interrupt Reset Register.
These registers are to be regarded together.
Corresponding bits in these registers relate to one and the
same event. Bits in the Interrupt Event Register are set by
the PCC and are to be reset by the external processor by
writing ‘1’s in the corresponding bits in the Interrupt Reset
Register. The mask in the Interrupt Enable Register
enables the interrupt if corresponding events do occur.
1996 Oct 31
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Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
Table 1 Hardware register addresses
Table 2 Fixed RAM locations
ADDRESS
WRITE
READ
ADDRESS
ENTRY
7E0
7E1
7E2
7E3
7E4
7E5
7E6
7E7
7E8
7E9
7EA
7EB
7EC
7ED
7EE
7EF
7F0
7F1
7F2
7F3
7F4
7F5
7F6
7F7
7F8
7F9
7FA
7FB
7FC
7FD
7FE
7FF
−
−
−
−
740 to 747
748 to 74F
750 to 757
758 to 75F
760 to 767
768 to 76F
770 to 777
778 to 77F
780 to 787
788 to 78F
790 to 797
798 to 79F
7A0 to 7A7
7A8 to 7AA
7AB
cipher key vector #0
S-DATA1
cipher key vector #1
cipher key vector #2
cipher key vector #3
cipher key vector #4
cipher key vector #5
cipher key vector #6
cipher key vector #7
cipher key vector #8
cipher key vector #9
cipher key vector #10
cipher key vector #11
cipher init vector
S-DATA2
S-DATA3
RMT-STAT
−
RF-STATUS
B-field-shift
−
B-field-loc.
−
A-field-loc.
−
window-wide-off
window-wide-on
window-narrow-off
window-narrow-on
T-power-rmp-on
synth-off
−
−
−
−
−
−
not used
RF-control-port
slot-cnt-off
sync-status
slot-counter-copy
RSSI
XZ field buffer
7AC to 7AF
7B0 to 7BB
7BC to 7BF
7C0 to 7DF
S-field buffer
frame-cnt-ref
sync-ref-preset
bit-counter-preset
frame-counter
slot-counter
sync-control
BMC-mode
cipher-slot-control-table
not used
bit-counter-copy 1
bit-counter-copy 2
frame-counter
slot-counter
sync-control
BMC-mode
speech-slot-control-table
correlator-threshold measure
watchdog-1
watchdog-2
−
−
−
−
−
−
interrupt-event
interrupt-enable
interrupt-reset
controller mode
interrupt-event
interrupt-enable
−
controller mode
1996 Oct 31
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Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
7
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER
VDD
MIN.
−0.5
MAX.
+6.5
UNIT
supply voltage
V
V
VI
all input voltages
DC input current
DC output current
total power dissipation
−0.5
−10
−10
−
VDD + 0.5
+10
II
mA
mA
mW
mW
mA
mA
°C
IO
+10
Ptot
PO
IDD
ISS
Tstg
Tj
+500
30
power dissipation per output
supply current
−
−100
−100
−55
−
+130
+130
+100
90
ground current
storage temperature range
operating junction temperature
°C
8
CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
General
Tamb
VDD
operating ambient temperature
supply voltage
−25
2.7
1.0
−
−
+70
5.5
VDD
12
°C
V
−
−
6
1
−
VDD(ret)
IDD
RAM retention voltage
operating supply current
standby supply current
clock input duty cycle
V
note 1
note 2
mA
mA
%
IDD(stb)
−
3
All inputs LOW except WRN;
XTAL1 running at 14 MHz
45
55
Digital I/O
VIL
LOW level input voltage
LOW level output voltage
HIGH level input voltage
HIGH level output voltage
input leakage current
0
−
−
−
−
0.3VDD
0.3VDD
VDD
V
VOL
VIH
0
V
0.7VDD
0.7VDD
V
VOH
ILI
VDD
V
1.0
µA
mA
IO(source)
output source current
VDD = 3.6 V;
0.4 V ≤VO ≤ VDD − 0.4 V
2.0
2.0
5.0
5.0
−
IO(sink)
output sink current
VDD = 3.6 V;
−
mA
0.4 V ≤VO ≤ VDD − 0.4 V
IRDYN(sink)
RDYN output sink current
VDD = 3.6 V; VO = 0.4 V
VDD = 5.0 V; VO = 0.4 V
n = 1 to 32
2.0
−
5.0
6.0
n × 64
8
−
−
−
−
mA
mA
kHz
kHz
fDCK
fFS1
DCK input frequency
FS1 input frequency
−
−
1996 Oct 31
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Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Oscillator (inputs XTAL1 and XTAL2)
gm
RF
transconductance
VDD = 2.7 V
VDD = 3.6 V
0.6
−
−
−
−
mS
mS
kΩ
−
1.6
feedback resistance
200
500
RSSI Peak detector (6-bit linear A-D converter, for RSSI measurement on input RSSI_AN)
Vi(RSSI_AN)
input level
0
−
VDD
VREF
VDD
−
V
Vconv(RSSI_AN) voltage conversion range
0
−
V
Vi(VREF)
Zi(VREF)
VREF input voltage
1.0
−
3.0
50
V
VREF input impedance
during power-down high
impedance
kΩ
tconv
conversion time
18.4
−
−
µs
integral non-linearity
differential non-linearity
input impedance RSSI_AN
−
−
−
−
4
LSB
LSB
MΩ
note 3
0.2
1
1.5
−
Zi(RSSI_AN)
PCD5041HZ comparator characteristics
IDD(stb)(comp) supply current (standby)
IDD(idle)(comp) supply current (idle)
note 4
−
10
135
350
−
−
−
−
1
−
−
µA
µA
µA
µA
pF
kΩ
VDD = 3.0 V; note 4
VDD = 3.0 V; note 4
note 5
−
IDD(1MHz)
ILI(comp)
Ci
supply current (1 MHz)
input leakage current
input capacitance
pullup resistance
input common mode range
max. input offset voltage
propagation delay
delay difference
−
−
note 5
−
10
200
−
Rpu
note 6
−
Vcm
note 7
1.0
−
V
DD − 0.5 V
Vos
note 8
5
−
mV
ns
ns
V
tpd
note 9
−
100
10
−
200
−
∆tpd
note 8 and 9
IO = 2 mA
IO = 2 mA
CL = 50 pF
CL = 50 pF
−
VOL(comp)
VOH(comp)
tr
output level LOW
output level HIGH
output rise time
−
0.4
−
V
−
−
−
DD − 0.4 −
V
15
15
−
−
ns
ns
µs
tf
output fall time
−
ten
enable time
8
1996 Oct 31
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Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
Notes to the characteristics
1. VDD = 3.0 V; fclk =13.824 MHz; no external load; one speech link active (under typical conditions).
2. VDD = 3.0 V; fclk =13.824 MHz; no external load; after reset.
3. Maximum differential non-linearity at supply voltage 5.5 V and VREF = 1 V.
4. Supply current IDD(stb)(comp) flows when COMP_NE is HIGH.
Supply current IDD(idle)(comp) flows when the comparator is in active mode (COMP_NE is LOW). It is the DC current
of the comparator when it is not switching, and V(COMP_INP) < V(COMP_INM).
The active mode supply current IDD(1MHz) includes the output pulse rate of 1 MHz.
5. For input pins COMP_INP, COMP_INM, COMP_NE.
6. For input pin COMP_NE.
7. The minimum input common mode voltage will be measured at DC levels with, COMP_INM at 1 V DC ±30 mV.
The same goes for the maximum input common mode voltage at (VDD − 0.5V).
8. These values are not tested in production, and are based upon theoretical estimates and laboratory tests.
9. The propagation delay tpd is measured from the time the differential input voltage equals the offset voltage, to the
50% point of the output transition. The initial differential input voltage is 100 mV and the propagation delay is
specified for an input overdrive of 30 mV, and a load capacitance of 50 pF. tpd is valid for both the positive and
negative going output transition. The maximum value is valid for the total ranges of temperature, supply voltage and
common mode input voltage. The worst case operation conditions are at the minimum supply voltage, the lowest
operating temperature and the minimum input common mode voltage. The delay difference ∆tpd gives the difference
between tpd for the rising output transition and tpd for the falling output transition and is valid for all operating
conditions. The test method to check the maximum delay difference is by measuring the RMS voltage of the output
signal.
1996 Oct 31
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Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
9
PACKAGE OUTLINES
QFP64: plastic quad flat package;
64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
SOT319-1
y
X
A
51
33
52
32
Z
E
e
Q
A
2
H
A
E
(A )
3
E
A
1
θ
w M
p
L
p
pin 1 index
b
L
20
64
detail X
1
19
w M
Z
v
M
M
D
A
b
p
e
D
B
H
v
B
D
0
5
scale
10 mm
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
D
E
p
D
max.
7o
0o
0.36 2.87
0.10 2.57
0.50 0.25 20.1 14.1
0.35 0.13 19.9 13.9
24.2 18.2
23.6 17.6
1.0 1.43
0.6 1.23
1.2
0.8
1.2
0.8
mm
3.3
0.25
1
1.95
0.2
0.2
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT319-1
1996 Oct 31
21
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SOT315-1
y
X
A
60
41
Z
61
40
E
e
Q
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
L
pin 1 index
80
21
detail X
1
20
Z
D
v
M
A
e
w M
b
p
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
4o
0o
0.16 1.5
0.04 1.3
0.25 0.18 12.1 12.1
0.13 0.12 11.9 11.9
14.15 14.15
13.85 13.85
0.7 0.70
0.3 0.58
1.45 1.45
1.05 1.05
mm
1.6
0.25
0.5
1.0
0.2 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-03-24
95-12-19
SOT315-1
1996 Oct 31
22
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
If wave soldering cannot be avoided, the following
conditions must be observed:
10 SOLDERING
10.1 Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions:
• Do not consider wave soldering LQFP packages
LQFP48 (SOT313-2), LQFP64 (SOT314-2) or
LQFP80 (SOT315-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
• Do not consider wave soldering QFP packages
QFP52 (SOT379-1), QFP100 (SOT317-1),
QFP100 (SOT317-2), QFP100 (SOT382-1) or
QFP160 (SOT322-1).
10.2 Reflow soldering
Reflow soldering techniques are suitable for all LQFP and
QFP packages.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
10.4 Repairing soldered joints
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
10.3 Wave soldering
Wave soldering is not recommended for LQFP or QFP
packages. This is because of the likelihood of solder
bridging due to closely-spaced leads and the possibility of
incomplete solder penetration in multi-lead devices.
1996 Oct 31
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Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
11 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
12 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Oct 31
24
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
NOTES
1996 Oct 31
25
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
NOTES
1996 Oct 31
26
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
NOTES
1996 Oct 31
27
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
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Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Belgium: see The Netherlands
Brazil: see South America
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 247 9145, Fax. +7 095 247 9144
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500
Colombia: see South America
Czech Republic: see Austria
Slovakia: see Austria
Slovenia: see Italy
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 1949
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580/xxx
South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730
Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722
Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444
Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,
Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
Middle East: see Italy
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
647021/00/01/pp28
Date of release: 1996 Oct 31
Document order number: 9397 750 01291
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