PCE84C486PN [NXP]
IC 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDIP32, Microcontroller;
| 型号： | PCE84C486PN |
| 厂家： | 
NXP |
| 描述： | IC 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDIP32, Microcontroller 微控制器和处理器 外围集成电路 电视 光电二极管 时钟 |
| 文件： | 总36页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCE84C486; PCE84C487
Microcontrollers for digital
auto-sync and VST TV controller
applications
1996 Feb 21
Objective specification
File under Integrated Circuits, IC14
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync
and VST TV controller applications
PCE84C486;
PCE84C487
CONTENTS
14
LIMITING VALUES
15
16
17
18
DC CHARACTERISTICS
AC CHARACTERISTICS
PACKAGE OUTLINES
SOLDERING
1
FEATURES
1.1
1.2
General
Special
2
3
4
5
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAMS
18.1
18.2
Introduction
SDIP
19
20
21
DEFINITIONS
PINNING INFORMATION
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
5.1
5.2
Pinning
Pin description
6
RESET
6.1
6.2
6.3
6.4
6.5
External reset using the RESET pin
Power-on-reset
Watchdog Timer reset
Reset trip level
Reset status
7
ANALOG (DC) CONTROL
7.1
7.2
7.3
7.4
6 and 7-bit PWM outputs
8-bit PWM outputs
14-bit PWM output (PWM8)
A typical PWM output application
8
ANALOG-TO-DIGITAL CONVERTER (ADC)
8.1
8.2
Conversion algorithm
A typical application for keypad detection
9
I2C-BUS INTERFACE
8-BIT COUNTER (T3)
WATCHDOG TIMER (WDT)
OUTPUT PORTS
10
11
12
12.1
13
Mask options
DERIVATIVE REGISTERS
1996 Feb 21
2
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
1
FEATURES
General
2
GENERAL DESCRIPTION
The PCE84C486 and PCE84C487 are low-cost
microcontrollers and have been designed for use with
auto-sync monitors, handling mode detection, digital
control and Voltage Synthesized Tuning (VST). These
microcontrollers have no on-chip OSD function.
1.1
• CMOS 8-bit CPU (enhanced 8048 CPU) with 4 kbytes
system ROM and 128 bytes system RAM
• One 8-bit timer/event counter (T1) and one 8-bit counter
(T3) triggered by external input
The term PCE84C48X is used throughout this data sheet
to refer to both devices. Differences between the
PCE84C486 and the PCE84C487 are highlighted
throughout the document.
• Three single level vectored interrupt sources: external
(INTN), counter/timer and I2C-bus
• 2 directly testable inputs T0 and T1
The PCE84C48X is a member of the 84CXXX CMOS
microcontroller family. The device uses the PCE84CXX
processor core and has 4 kbytes of ROM and 128 bytes of
RAM. I/O requirements are catered for with 11 general
purpose bidirectional I/O lines (the PCE84C487 has 12)
plus 12 function combined I/O lines (the PCE84C487 has
16). Nine PWM analog outputs (the PCE84C487 has 13)
are available for analog control purposes and also a two
channel 4-bit ADC. The device has an 8-bit counter (T3),
for use in pulse counting applications and also an 8-bit
timer/counter (T1) with programmable clock. A Watchdog
timer, a master-slave I2C-bus interface and 2 directly
testable lines are also available on-chip.
• On-chip oscillator clock frequency: 1 to 10 MHz
• On-chip Power-on-reset with low power detector
• The PCE84C486 has eleven quasi-bidirectional I/O
lines, the PCE84C487 has twelve. The configuration of
each I/O line individually selected by mask option
• Idle and Stop modes for reduced power consumption
• Operating temperature: −25 to +85 °C
• Operating voltage: 4.5 to 5.5 V
• Packages: SDIP32 for the PCE84C486; SDIP42 for the
PCE84C487.
1.2
Special
The block diagram of the PCE84C486 is shown in Fig.1;
the block diagram of the PCE84C487 is shown in Fig.2.
• Master-slave I2C-bus interface
• Four 6-bit Pulse Width Modulated outputs
• Four 7-bit Pulse Width Modulated outputs
• Four 8-bit Pulse Width Modulated outputs (PCE84C487
only)
• One 14-bit Pulse Width Modulated output
• Two 4-bit Analog-to-Digital Converter (ADC) channels
• 14 derivative I/O ports
• Watchdog Timer.
3
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
SOT232-1
SOT270-1
PCE84C486
PCE84C487
SDIP32
SDIP42
plastic shrink dual in-line package; 32 leads (400 mil)
plastic shrink dual in-line package; 42 leads (600 mil)
1996 Feb 21
3
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
4
BLOCK DIAGRAMS
GM9C12
a n d b l p a g e w i d t h
1996 Feb 21
4
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
GM9C13
a n d l l p a g e w i d t h
1996 Feb 21
5
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
5
PINNING INFORMATION
Pinning
5.1
handbook, halfpage
DP20/SDA
1
2
3
4
5
6
7
8
9
42 DP07/PWM7
41 DP12/ADC2
40 INTN/T0
39 T1
P10/SCL
P11
DP13/PWM8
P12
handbook, halfpage
DP20/SDA
1
2
3
4
5
6
7
8
9
32 DP07/PWM7
31 DP12/ADC2
30 INTN/T0
29 T1
P10/SCL
38 RESET
P11
n.c.
37 n.c.
DP13/PWM8
T3
36 XTAL2(OUT)
35 XTAL1(IN)
34 DP27/PWM13
P12
T3
28 RESET
DP24/PWM10
P14
27 XTAL2(OUT)
26 XTAL1(IN)
P14
P00
P01
P00 10
RSTO 11
P01 12
33 V
DD
25 V
DD
PCE84C486
32 EMU
PCE84C487
24 DP00/PWM0
23 DP01/PWM1
22 DP02/PWM2
21 DP03/PWM3
20 DP04/PWM4
19 DP05/PWM5
18 DP06/PWM6
17 DP11/ADC1
31 DP00/PWM0
30 DP01/PWM1
29 DP26/PWM12
28 DP02/PWM2
27 n.c.
P02 10
P03 11
P04 12
P05 13
P06 14
P07 15
P02 13
DP25/PWM11 14
P03 15
n.c. 16
P04 17
26 DP03/PWM3
25 DP04/PWM4
24 DP05/PWM5
23 DP06/PWM6
22 DP11/ADC1
P05 18
V
16
SS
P06 19
MGC904
P07 20
V
21
SS
MGC905
Fig.3 Pin configuration - PCE84C486.
Fig.4 Pin configuration - PCE84C487.
1996 Feb 21
6
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
5.2
Pin description
Table 1 SDIP32 package
SYMBOL
PIN
DESCRIPTION
DP20/SDA
1
Derivative port line 20 or I2C-bus data line.
P10/SCL
2
Port line 10 or I2C-bus clock line or emulation input DXWR.
Port line 11 or emulation input DXRD.
Derivative I/O port 13 or PWM8 output.
Port line 12 or emulation input DXALE.
8-bit counter input (Schmitt trigger).
Port line 14 or emulation output DXINT.
General I/O port lines.
P11
3
DP13/PWM8
4
P12
5
6
T3
P14
7
P00 to P07
8 to 15
16
VSS
Ground pin.
DP11/ADC1
17
Derivative I/O port 11 or ADC Channel 1input.
DP00/PWM0 to DP07/PWM7
24 to 18, 32 Derivative I/O ports or 6 and 7-bit PWM outputs.
VDD
25
26
27
28
29
30
31
Power supply.
XTAL1 (IN)
XTAL2 (OUT)
RESET
Oscillator input pin for system clock.
Oscillator output pin for system clock.
Reset input; active LOW input initializes device.
Direct testable pin or event counter input.
External interrupt or direct testable pin.
Derivative I/O port 12 or ADC Channel 2 input.
T1
INTN/T0
DP12/ADC2
1996 Feb 21
7
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
Table 2 SDIP42 package
SYMBOL
PIN
DESCRIPTION
DP20/SDA
P10/SCL
P11
1
2
3
4
5
6
7
Derivative port line 20 or I2C-bus data line.
Port line 10 or I2C-bus clock line or emulation input DXWR.
Port line 11 or emulation input DXRD.
Derivative I/O port 13 or PWM8 output.
Port line 12 or emulation input DXALE.
Not connected.
DP13/PWM8
P12
n.c.
T3
8-bit counter input (Schmitt trigger).
DP24/PWM10 to DP27/PWM13
P14
8, 14, 29, 34 Derivative I/O ports or 8-bit PWM outputs.
Port line 14 or emulation output DXINT.
9
10, 12, 13, 15, General I/O port lines.
17, 18, 19, 20
P00 to P07
RSTO
11
Used for emulation purposes only. This active HIGH output is the
result of the OR operation carried out internally on the RESET
input and the Watchdog Timer reset line.
n.c.
16
21
22
Not connected.
VSS
Ground pin.
DP11/ADC1
Derivative I/O port 11 or ADC channel 1 input.
DP04/PWM4 to DP07/PWM7
25, 24, 23, 42 Derivative I/O ports or 6-bit PWM outputs.
27 Not connected.
31, 30, 28, 26 Derivative I/O ports or 7-bit PWM outputs.
n.c.
DP00/PWM0 to DP03/PWM3
EMU
32
33
35
36
37
38
39
40
41
Emulation mode control input, normally LOW.
Power supply.
VDD
XTAL1 (IN)
XTAL2 (OUT)
n.c.
Oscillator input pin for system clock.
Oscillator output pin for system clock.
Not connected.
RESET
T1
Reset input; active LOW input initializes device.
Direct testable pin or event counter input.
External interrupt or direct testable pin.
Derivative I/O port 12 or ADC Channel 2 input.
INTN/T0
DP12/ADC2
1996 Feb 21
8
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
6
RESET
6.4
Reset trip level
To initialize the microcontroller to a defined state a reset
operation is performed. A reset can be generated in three
ways:
The RESET trip voltage level for both the PCE84C486 and
PCE84C487 is masked to 1.3 V.
6.5
Reset status
• applying an external signal to the RESET pin
• via Power-on-reset circuitry
• Derivative Registers reset status; see Table 8 for details
• Program Counter 00H
• by the Watchdog Timer.
• Memory Bank 0
6.1
External reset using the RESET pin
• Register Bank 0
An active LOW signal from an external logic device will
reset the device. The signal must be maintained long
enough to allow VDD to reach its fxtal-dependent minimum
operating voltage.
• Stack Pointer 00H
• All interrupts disabled
• Timer/event counter 1 stopped and cleared
• Timer pre-scaler modulo-32 (PS = 0)
• Timer flag cleared
6.2
Power-on-reset
A Power-on-reset can be generated using an external RC
circuit. To avoid overload of the internal diode, an external
diode should be added in parallel if CRESET ≥ 2.2 µF.
The RC circuit is shown in Fig.5.
• Serial I/O interface disabled (ESO = 0) and in slave
receiver mode
• Idle and Stop mode cleared.
6.3
Watchdog Timer reset
An overflow of the Watchdog Timer will cause the device
to be reset. The operation of the Watchdog Timer is
described in Chapter 12.
handbook, halfpage
V
DD
R
RESET
internal reset
(
100 kΩ)
RESET
C
RESET
V
SS
PCA84C8XX
MLC259
Fig.5 External components for RESET pin.
1996 Feb 21
9
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
The maximum repetition frequency (fPWM) of the 6 and
7-bit PWM outputs is shown below.
7
ANALOG (DC) CONTROL
The PCE84C486 has nine Pulse Width Modulated outputs
(PWM0 to PWM8) and the PCE84C487 has thirteen Pulse
Width Modulated outputs (PWM0 to PWM8 and
PWM10 to PWM13). These outputs are used for analog
control purposes e.g. brightness, contrast, H-shift, V-shift,
H-width, V-size, pin-cushion, trapezium, R (or G or B) gain
control, sound volume etc. Each PWM output generates a
pulse pattern with a programmable duty cycle.
fxtal
For the 6-bit PWM outputs: fPWM
For the 7-bit PWM outputs: f PWM
=
=
---------
192
fxtal
---------
384
7.2
8-bit PWM outputs
The PWM outputs are specified below:
The block diagram for the 8-bit PWM outputs is shown in
Fig.8.
• PWM0 to PWM3: 4 PWM outputs with 7-bit resolution
• PWM4 to PWM7: 4 PWM outputs with 6-bit resolution
• PWM8: 1 PWM output with 14-bit resolution
The 8-bit PWM outputs PWM10 to PWM13 (only available
with the PCE84C487) share the same pins as Derivative
Port lines DP24 to DP27, respectively. Selection of the pin
function as either a PWM output or a Derivative Port line is
achieved using the appropriate PWMnE bit in the
PWME2 Register (see Table 8). In the PCE84C486 the
contents of the PWME2 register should be set so that
these PWM outputs are disabled (i.e 00H).
• PWM10 to PWM13: 4 PWM outputs with 8-bit
resolution.
The 6 and 7-bit PWM outputs are described in Section 7.1;
the 8-bit PWM outputs are described in Section 7.2 and
the 14-bit PWM output is described in Section 7.3. A
typical PWM output application is described in Section 7.4.
The polarity of the 8-bit PWM outputs is programmable
and is selected by the P8LVL bit in the CON2 Register.
7.1
6 and 7-bit PWM outputs
The duty cycle of each 8-bit PWM output is dependent
upon the programmable contents of its associated data
latch (PWM10 to PWM13 Registers respectively). As the
clock frequency of each PWM circuit is fxtal, the pulse
width of the pulse generated can be calculated as shown
below.
The block diagram for the 6 and 7-bit PWM outputs is
shown in Fig.6.
Pulse Width Modulated outputs PWM0 to PWM7 share
the same pins as Derivative Port lines DP00 to DP07,
respectively. Selection of the pin function as either a PWM
output or a Derivative Port line is achieved using the
appropriate PWMnE bit in the PWME1 Register (see
Table 8).
(PWMn)
Pulse width =
------------------------
fxtal
The polarity of the 6 and 7-bit PWM outputs is
programmable and is selected by the P7LVL or the P6LVL
bit in the CON2 Register (see Table 8). The state of the
P7LVL bit determines the polarity of the 7-bit PWMs; the
state of the P6LVL bit determines the polarity of the 6-bit
PWMs.
Where (PWMn) is the decimal value held in the data latch.
The maximum repetition frequency (fPWM) of the 8-bit
PWM outputs is shown below.
fxtal
f PWM
=
---------
256
The duty cycle of each PWM output is dependent upon the
programmable contents of its associated data latch
(PWM0 to PWM7 Registers respectively). As the clock
frequency of each PWM circuit is 1⁄3 × fxtal, the pulse width
of the pulse generated can be calculated as shown below.
An 8-bit PWM output is driven HIGH when the value held
in its data latch is 00H. This is different to the 6 and 7-bit
PWM outputs which are driven LOW when their data
latches contain 00H.
3 × (PWMn)
Pulse width =
---------------------------------
fxtal
Where (PWMn) is the decimal value held in the data latch.
1996 Feb 21
10
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
internal data bus
DP0x data
I/O
f
xtal
3
6 or 7-BIT PWM DATA LATCH
P6LVL/P7LVL
PWMnE
Q
6 or 7-BIT DAC PWM
CONTROLLER
DP0x/PWMx
Q
MLC069
Fig.6 Block diagram for 6 and 7-bit PWMs.
f
xtal
3
64
or
1
2
3
m
m + 1
m + 2
64
or
1
128
128
00
01
m
63
or
127
MLC261
decimal value PWM data latch
Fig.7 Typical non-inverted output pulse patterns for 6 or 7-bit PWM outputs.
11
1996 Feb 21
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
DP2x data
I/O
f
8-BIT PWM DATA LATCH
P8LVL
osc
PWMnE
Q
Q
8-BIT DAC PWM
CONTROLLER
DP2x/PWMx
MGC907
Fig.8 Block diagram for 8-bit PWMs.
f
osc
256
1
2
3
m
m + 1
m + 2
256
1
00
01
m
256
MGC908
decimal value PWM data latch
Fig.9 Typical non-inverted output pulse patterns for 8-bit PWM outputs.
12
1996 Feb 21
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
7.3
14-bit PWM output (PWM8)
7.3.1
COARSE ADJUSTMENT
The 14-bit PWM output can be used to generate the
Automatic Frequency Control (AFC) signal used in VST
applications.
An active HIGH pulse is generated in every subperiod; the
pulse width being determined by the contents of PWM8H.
The coarse output (OUT1) is LOW at the start of each
subperiod and will remain LOW until the time
PWM8 shares the same pin as Derivative Port line DP13.
Selection of the pin function as either a PWM output or as
a Derivative Port line is achieved using the PWM8E bit in
Register 22.
[3 ⁄ fxtal × (PWM8H + 1) ] has elapsed. The output will
then go HIGH and remain HIGH until the start of the next
subperiod. The coarse pulse width may be calculated as
shown below.
The Block diagram for the 14-bit PWM output is shown in
Fig.10 and comprises:
3
--------
fxtal
Pulse duration = (127 – PWM8H) ×
• Two 7-bit latches: PWM8L (Register 18) and PWM8H
7.3.2
FINE ADJUSTMENT
(Register 19)
• 14-bit data latch (PWMREG)
• 14-bit counter
Fine adjustment is achieved by generating an additional
pulse in specific subperiods. The pulse is added at the
start of the selected subperiod and has a pulse width of
3/fxtal. The contents of PWM8L determine in which
subperiods a fine pulse will be added. It is the logic 0 state
of the value held in PWM8L that actually selects the
subperiods. When more than one bit is a logic 0 then the
subperiods selected will be a combination of those
subperiods specified in Table 3. For example, if
• Coarse pulse controller
• Fine pulse controller
• Mixer.
Data is loaded into the 14-bit data latch (PWMREG) from
the two 7-bit data latches (PWM8H and PWM8L) when
PWM8L is written to. The contents of PWMREG determine
the active time of the PWM8 output. The upper seven bits
of PWMREG are used by the coarse pulse controller and
determine the coarse pulse width; the lower seven bits are
used by the fine pulse controller and determine in which
subperiods fine pulses will be added. The outputs OUT1
and OUT2 of the coarse and fine pulse controllers are
‘ORED’ in the mixer to give the PWM8 output. The polarity
of the PWM8 output is programmable and is selected by
the P8LVL bit in Register 23.
PWM8L = 111 1010 then this is a combination of:
• PWM8L = 111 1110: subperiod 64 and
• PWM8L = 111 1011: subperiods 16, 48, 80 and 112.
Pulses will be added in subperiods 16, 48, 64, 80 and 112.
This example is illustrated in Fig.13.
When PWM8L holds 111 1111 fine adjustment is inhibited
and the PWM8 output is determined only by the contents
of PWM8H.
As the 14-bit counter is clocked by 1⁄3 × fxtal, the repetition
times of the coarse and fine pulse controllers may be
calculated as shown below.
Table 3 Additional pulse distribution
PWM8L
ADDITIONAL PULSE IN SUBPERIOD
64
111 1110
111 1101
111 1011
111 0111
110 1111
101 1111
011 1111
384
fxtal
Coarse controller repetition time: tsub
=
---------
32 and 96
16, 48, 80 and 112
49152
----------------
fxtal
Fine controller repetition time: t r =
8, 24, 40, 56, 72, 88, 104 and 120
4, 12, 20, 28, 36, 44, 52...116 and 124
2, 6, 10, 14, 18, 22, 26, 30...122 and 126
1, 3, 5, 7, 9, 11, 13, 15, 17...125 and 127
Figure 11 shows typical PWM8 outputs, with coarse
adjustment only, for different values held in PWM8H. Note
that the PWM8 coarse controller output is the same as the
7-bit PWM outputs except the polarity is reversed.
Figure 12 shows typical PWM8 outputs, with coarse and
fine adjustment, after the coarse and fine pulse controller
outputs have been ‘ORED’ by the mixer.
1996 Feb 21
13
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
Internal data bus
‘MOV instruction’
PWM8L
PWM8H
7
7
DATA LOAD
TIMING PULSE
LOAD
PWMREG
7
7
COARSE 7-BIT
PWM
FINE PULSE
GENERATOR
OUT1
OUT2
MIXER
polarity
control bit
Q
Q
PWM8 output
P14LVL
Q14 to 8
Q7 to 1
f
= f
14-BIT COUNTER
tdac xtal
3
MGC909
Fig.10 14-bit PWM Block diagram.
14
1996 Feb 21
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
f
xtal
3
127
0
1
2
m
m + 1
m + 2
127
0
1
00
01
m
127
MLC263
decimal value PWM8H data latch
Fig.11 Non-inverted PWM8 output patterns - Coarse adjustment only.
f
xtal
3
127
0
1
2
m
m + 1
m + 2
127
0
1
00
01
m
127
MLC262
decimal value PWM8H data latch
Fig.12 Non-inverted PWM8 output patterns - Coarse and Fine adjustment.
15
1996 Feb 21
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
t
r
t
t
t
t
t
t
t
t
t
sub0
sub16
sub32
sub48
sub64
sub80
sub96
sub112
sub127
111 1110
111 1011
111 1010
PWM8L
MLC755
Fig.13 Fine adjustment output (OUT2).
7.4
A typical PWM output application
A typical PWM application is shown in Fig.14. R1 and C1
form an integration network the time constant of which
should be at least 5 times greater than the repetition period
of the PWM output pattern. In order to smooth a changing
PWM output a high value of C1 should be chosen. The
value of C1 will normally be in the range 1 to 10 µF. The
potential divider chain formed by R2 and R3 is used only
when the output voltage is to be offset. The output voltages
for this application are calculated using
supply
voltage
handbook, halfpage
R2
R3
R1
analog
output
PWMn
PCE84C48X
Equations (1) and (2).
R3 × supply voltage
C1
Vmax
=
(1)
----------------------------------------------------
R1 × R2
R3 +
----------------------
V
R1 + R2
SS
R1 × R3
---------------------
R1 + R3
MGD136
× supply voltage
V min
=
(2)
------------------------------------------------------------------
R1 × R3
R2 +
----------------------
R1 + R3
The loop from the PWM pin through R1 and C1 to VSS will
radiate high frequency energy pulses. In order to limit the
effect of this unwanted radiation source, the loop should
be kept short and a high value of R1 selected. The value
of R1 will normally be in the range 3.3 to 100 kΩ. It is good
practice to avoid sharing VSS with the return leads of other
sensitive signals.
Fig.14 Typical PWM output circuit.
1996 Feb 21
16
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
The ADC channel selector is controlled by the ADCS1 and
ADCS0 bits in Register 20. The channels are selected as
shown in Table 5.
8
ANALOG-TO-DIGITAL CONVERTER (ADC)
The two-channel ADC comprises a 4-bit Digital-to-Analog
Converter (DAC); a comparator; an analog channel
selector and control circuitry. As the digital input to the 4-bit
DAC is loaded by software (a subroutine in the program),
it is known as a software ADC. The block diagram is shown
in Fig.15.
Table 5 Selection of ADC channel
ADCS1
ADCS0
CHANNEL SELECTED
0
0
1
1
0
1
0
1
not allowed
ADC1
The ADC inputs ADC1 and ADC2 share the same pins as
Derivative Port lines DP11 and DP12 respectively.
Selection of the pin function as either an ADC input or as
a Derivative Port line is achieved using bits ADCE1 and
ADCE2 in Register 22. When ADCEn = 1, the ADC
function is enabled.
ADC2
not allowed
8.1
Conversion algorithm
There are many algorithms available to achieve the ADC
conversion. The algorithm described below and shown in
Fig.16 uses an iteration process.
The 4-bit DAC analog output voltage (Vref) is determined
by the decimal value of the data held in bits DAC0 to DAC3
of Register 20. Vref is calculated as shown in Equation (3)
and Table 4 lists the Vref values assuming VDD = 5 V.
1. Enable and then select the ADC channel for
conversion. Channel selection is achieved using bits
ADCS1 and ADCS0 in Register 20.
V
Vref
=
DD × (DAC value + 1)
(3)
----------
16
2. Set the digital input to the DAC to 1000. The digital
input to the DAC is selected using bits DAC3 to DAC0
in Register 20.
When the analog input voltage is higher than Vref, the
COMP bit in Register 20 will be HIGH.
3. Determine the result of the compare operation. This is
achieved by reading the COMP bit in Register 20
using the instruction MOV A, D20H. If COMP = 1; the
analog input voltage is higher than the reference
voltage (Vref). If COMP = 0; the analog input voltage is
lower than the reference voltage (Vref).
Table 4 Selection of Vref
DAC3
DAC2
DAC1
DAC0
Vref (V)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.3125
0.6250
0.9375
1.2500
1.5625
1.8750
2.1875
2.5000
2.8125
3.1250
3.4375
3.7500
4.0625
4.3750
4.6875
5.0000
4. If COMP = 1; then the analog input voltage is higher
than the reference voltage (Vref) and therefore the
digital input to the DAC needs to be increased. Set the
input to the DAC to 1100.
5. If COMP = 0; then the analog input voltage is lower
than the reference voltage (Vref) and therefore the
digital input to the DAC needs to be decreased. Set the
input to the DAC to 0100.
6. Determine the result of the compare operation by
reading the COMP bit in Register 20.
1996 Feb 21
17
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
7. For the DAC = 1100 case
9. The operations detailed in 6, 7 and 8 above are
repeated and each time the digital input to the DAC is
changed accordingly; as dictated by the state of the
COMP bit. The complete process is shown in Fig.16.
Each time the DAC input is changed the number of
values which the analog input can take is reduced by
half. In this manner the actual analog value is honed
into. The value of the analog input (VA) is determined
using Equation (4):
If COMP = 1; then the analog input voltage is still
greater than Vref and therefore the digital input to the
DAC needs to be increased again. Set the input to the
DAC to 1110.
If COMP = 0; then the analog input voltage is now less
than Vref and therefore the digital input to the DAC
needs to be decreased. Set the input to the DAC to
1010
V
VA
=
DD × (DAC value + 1)
(4)
8. For the DAC = 0100 case
----------
16
If COMP = 1; then the analog input voltage is now
greater than Vref and therefore the digital input to the
DAC needs to be increased. Set the input to the DAC
to 0110.
As the conversion time of each compare operation is
greater than 6 µs but less than 9 µs; a NOP instruction is
recommended to be used in between the instructions that
change the value of Vref; select the ADC channel and read
the COMP bit.
If COMP = 0; then the analog input voltage is still lower
than Vref and therefore the digital input to the DAC
needs to be decreased again. Set the input to the DAC
to 0010.
Internal bus
DERIVATIVE PORT
SELECTOR
EN1
EN2
DP11/ADC1
ADC
COMP bit
+
−
CHANNEL
SELECTOR
COMPARATOR
EN
V
‘MOV A, D20’
instruction
to read COMP bit
ref
DP12/ADC2
ENABLE
SELECTOR
Channel selection
ADCS1 ADCS0
4-BIT DAC
ADCE1 ADCE2
DAC3
DAC2
DAC1
DAC0
ADC enable selection
MGD263
DAC value selection
Fig.15 Block diagram of 2 channel ADC.
1996 Feb 21
18
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
LM0C73
a n d b o o k , f u l l p a g e w
1996 Feb 21
19
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
The input voltage generated by the operation of any key
(ignoring the effect of the 100 kΩ resistor) can be
calculated as follows:
8.2
A typical application for keypad detection
The ADC channels of the PCE84C48X can be used in
keypad applications to detect and identify the operation of
individual keys. The circuit for a 14-key application is
shown in Fig.17.
(n – 0.5)
VADCn
=
× V DD
-----------------------
16
When no key is depressed the input voltage at the ADC
input pin will be greater than 15⁄16VDD and if the DAC value
selected is 1110 then the COMP bit will be HIGH. When
any key is depressed the input voltage at the ADC input pin
will change, and as each key will generate its own unique
input voltage, this can be measured by the ADC channel
and the actual key depressed can then be identified.
Where n is the key number and can take any integer value
in the range 1 to 14.
The input voltage at the ADC input will be influenced by the
tolerance of the resistors and the length of the cable
connecting the keypad to the monitor. In the worse case
situation this may reduce the number of keys that can be
uniquely detected and identified.
handbook, halfpage
V
DD
100 kΩ
key 14
5 kΩ
2 kΩ
ADCx
1 µF
key 13
PCE84C486
PCE84C487
2 kΩ
2 kΩ
1 kΩ
key 2
key 1
V
SS
14 key matrix
MGC910
Fig.17 A typical ADC application for keypad detection.
1996 Feb 21
20
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
I2C-BUS INTERFACE
If the rising and falling edges of the input pulse are less
than 30 ns then the minimum pulse width that the T3 input
will recognise is 3/fosc + 100 ns. If the system clock is
10 MHz then the minimum pulse width is 400 ns. In some
display modes, the active pulse width of the Hsync signal
can be less than 400 ns; in this situation some external
application circuitry may be required.
9
The PCE84C48X has an on-chip I2C-bus interface that
can be used in master or slave mode. Full details of the
I2C-bus are given in the document “The I2C-bus and how
to use it”. This document may be ordered using the code
9398 393 40011.
The I2C-bus interface lines SDA and SCL share the same
pins as port lines DP20 and P10 respectively. Selection of
the pin function as either an I2C-bus line or a port line is
achieved using the SDAE and SCLE bits in Derivative
Register 22. Only port Option 2 is available for both of
these pins.
t
H
handbook, halfpage
0.9 V
DD
10 8-BIT COUNTER (T3)
0.1 V
DD
The main application for this counter is in the frequency
measurement of the Hsync signal.
t
t
r
f
t
t
f
r
The block diagram of the 8-bit counter is shown in Fig.22.
A Schmitt trigger is used at the input for noise rejection and
also to shape the input signal into a square wave. The T3
input is sampled at a frequency of 1⁄3 × fosc by the sample
clock which synchronizes the internal T3 clock and the
read operation of Derivative Register 24. The rising edge
of the input increments the ripple counter by 1.
0.9 V
0.1 V
DD
DD
MGC719
t
L
The contents of T3 may be read using the instruction
MOV A, D24H. As soon as the data is read, the counter is
reset to zero. A counter overflow or Power-on-reset also
resets the counter contents to zero.
Fig.18 T3 input waveform.
CK
SYNCHRONISATION
T3
8-BIT COUNTER
CIRCUIT
RESET
Q0 to Q7
sample clock
Power-on-reset
T3 COUNTER
EMU
CONTROL CIRCUIT
READ D24H
Data bus
MGC717
Fig.19 Block diagram of the 8-bit counter (T3).
21
1996 Feb 21
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
The maximum time period (tp) which the counter may run
and not cause a reset operation, is calculated as shown
below.
11 WATCHDOG TIMER (WDT)
The purpose of the Watchdog Timer is to reset the
microcontroller, within a reasonable period of time, if it
enters an erroneous processor state. Erroneous processor
states can be caused by noise or RFI.
tp
=
× 2 22
1
--------
fosc
The Watchdog Timer consists of a 23-bit counter which is
clocked at a frequency of fosc. During a Power-on-reset the
contents of the counter are cleared. The counter contents
are then incremented by ‘1’ every oscillator clock cycle.
If the maximum count is exceeded, the counter overflows
and the microcontroller is reset. In order to prevent a
counter overflow and its resulting reset operation, the user
program must clear the contents of the Watchdog Timer
before its maximum count is exceeded. During normal
processing, the contents of the Watchdog Timer are
In the Idle mode the oscillator is still running and the
Watchdog Timer remains active. In the Stop mode
however, the oscillator is stopped and the operation of the
Watchdog Timer is halted but its contents are retained.
Therefore, it may be advisable for the user to clear the
contents of the Watchdog Timer before the Stop mode is
entered, in order to avoid an unexpected reset operation
after the device is woken-up.
The operational voltage range of the Watchdog Timer is
2 to 5.5 V.
cleared by writing a logic 1 to Derivative Register 45H (this
is a dummy register).
f
CLK
osc
23-BIT COUNTER
RESET
Q22
WR45H
on-chip RESET
Power-on-reset
MGC906
Fig.20 The Watchdog Timer.
1996 Feb 21
22
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
12 OUTPUT PORTS
Each I/O port line may be individually configured using one
of three mask options. The three I/O mask options are
specified below:
Option 1 Standard input/output with switched pull-up
current source; this is shown in Fig.24.
Option 2 Input/output with open-drain output; this is
shown in Fig.25.
Option 3 Push-pull output; this is shown in Fig.26.
The state of each output port after a Power-on-reset can
also be selected using the mask options. All port mask
options are given in Section 13.1.
WRITE PULSE
OUTL/ORL/ANL/MOV
V
DD
constant
current
TR2
source
100 µA typ.
TR3
DATA BUS
D
D
SQ
SLAVE
SQ
MQ
MASTER
I/O PORT
LINE
TR1
V
SS
ORL/ANL/MOV
MLA696
IN/MOV
Fig.21 Standard I/O with pull-up transistor source (Option 1).
1996 Feb 21
23
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
WRITE PULSE
OUTL/ORL/ANL
V
DD
DATA BUS
D
D
MQ
SQ
SLAVE
SQ
MASTER
I/O PORT
LINE
TR1
V
SS
ORL/ANL
MLA697
IN
Fig.22 Open-drain I/O without pull-up transistor (Option 2).
WRITE PULSE
OUTL / ORL / ANL
V
DD
TR2
constant
current
source
DATA BUS
D
D
SQ
SLAVE
SQ
MQ
100 µA typ.
MASTER
OUTPUT
LINE
TR1
V
SS
ORL / ANL
MLB998
IN
Fig.23 Push-pull output with pull-up transistor (Option 3).
24
1996 Feb 21
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
12.1 Mask options
Table 7 Port options - PCE84C487
Table 6 lists the port mask options available for the
PCE84C486; Table 7 lists the port mask options available
for the PCE84C487.
OPTION
PORT PIN
CONFIGURATION
10 1, 2 or 3
12 1, 2 or 3
RESET STATE
P00
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH
Table 6 Port options - PCE84C486
P01
P02
13 1, 2 or 3
15 1, 2 or 3
17 1, 2 or 3
18 1, 2 or 3
19 1, 2 or 3
20 1, 2 or 3
OPTION
PORT PIN
P03
CONFIGURATION
RESET STATE
P04
P00
8
9
1, 2 or 3
1, 2 or 3
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH
P05
P01
P06
P02
10 1, 2 or 3
11 1, 2 or 3
12 1, 2 or 3
13 1, 2 or 3
14 1, 2 or 3
15 1, 2 or 3
P07
P03
P10
2
3
5
9
1, 2 or 3
1, 2 or 3
1, 2 or 3
1, 2 or 3
P04
P11
P05
P12
P06
P14
P07
DP00
DP01
DP02
DP03
DP04
DP05
DP06
DP07
DP11
DP12
DP13
DP20
DP24
DP25
DP26
DP27
31 1, 2 or 3
30 1, 2 or 3
28 1, 2 or 3
26 1, 2 or 3
25 1, 2 or 3
24 1, 2 or 3
23 1, 2 or 3
42 1, 2 or 3
22 1, 2 or 3
41 1, 2 or 3
P10
2
3
5
7
1, 2 or 3
1, 2 or 3
1, 2 or 3
1, 2 or 3
P11
P12
P14
DP00
DP01
DP02
DP03
DP04
DP05
DP06
DP07
DP11
DP12
DP13
DP20
24 1, 2 or 3
23 1, 2 or 3
22 1, 2 or 3
21 1, 2 or 3
20 1, 2 or 3
19 1, 2 or 3
18 1, 2 or 3
32 1, 2 or 3
17 1, 2 or 3
31 1, 2 or 3
4
1
8
1, 2 or 3
2
1, 2 or 3
HIGH or LOW
HIGH or LOW
HIGH or LOW
HIGH or LOW
14 1, 2 or 3
29 1, 2 or 3
34 1, 2 or 3
4
1
1, 2 or 3
2
1996 Feb 21
25
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
13 DERIVATIVE REGISTERS
The PCE84C486 has 22 Derivative Registers and the PCE84C487 has 26 Derivative Registers. Both devices have one
dummy register associated with the Watchdog Timer; this resides at address 45H. The Derivative Port I/O registers are
located at addresses 00 to 05H. When DP0TR, DP1TR and DP2TR are read the data is read directly from the pin.
However, when DP0R, DP1R and DP2R are read the data is read from the port latch (see Figs 24 to 26 for the port
configuration).
As the PCE84C486 has no 8-bit PWM outputs the PWME2 Register (address 44H) is not used and its contents must be
set to 00H. Registers PWME2, PWM10 to PWM13 and the 4 MSBs of Registers DP2TR and DP2R are only available in
the PCE84C487.
Table 8 Register map (see note 1)
ADDR
(HEX)
REG
7
6
5
4
3
2
1
0
R/W
00
DP0TR
DP07
DP06
(X)
DP05
(X)
DP04
(X)
DP03
(X)
DP02
(X)
DP01
(X)
DP00
(X)
R
(terminal) (X)
DP1TR
(terminal) (X)
01
02
03
04
05
10
11
12
13
14
15
16
17
18
19
−
−
(X)
−
(X)
−
(X)
DP13
(X)
DP12
(X)
DP11
(X)
−
R
DP2TR
(terminal) (X)
DP27
DP26
(X)
DP25
(X)
DP24
(X)
−
(X)
−
(X)
−
(X)
DP20
(X)
R
DP0R
(latch)
DP07
(1)
DP06
(1)
DP05
(1)
DP04
(1)
DP03
(1)
DP02
(1)
DP01
(1)
DP00
(1)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DP1R
(latch)
−
(X)
−
(X)
−
(X)
−
(X)
DP13
(1)
DP12
(1)
DP11
(1)
−
(1)
DP2R
(latch)
DP27
(1)
DP26
(1)
DP25
(1)
DP24
(1)
−
(X)
−
(X)
−
(X)
DP20
(1)
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8L
PWM8H
−
(X)
PWM06
(0)
PWM05
(0)
PWM04
(0)
PWM03
(0)
PWM02
(0)
PWM01
(0)
PWM00
(0)
−
(X)
PWM16
(0)
PWM15
(0)
PWM14
(0)
PWM13
(0)
PWM12
(0)
PWM11
(0)
PWM10
(0)
−
(X)
PWM26
(0)
PWM25
(0)
PWM24
(0)
PWM23
(0)
PWM22
(0)
PWM21
(0)
PWM20
(0)
−
(X)
PWM36
(0)
PWM35
(0)
PWM34
(0)
PWM33
(0)
PWM32
(0)
PWM31
(0)
PWM30
(0)
−
(X)
−
(X)
PWM45
(0)
PWM44
(0)
PWM43
(0)
PWM42
(0)
PWM41
(0)
PWM40
(0)
−
(X)
−
(X)
PWM55
(0)
PWM54
(0)
PWM53
(0)
PWM52
(0)
PWM51
(0)
PWM50
(0)
−
(X)
−
(X)
PWM65
(0)
PWM64
(0)
PWM63
(0)
PWM62
(0)
PWM61
(0)
PWM60
(0)
−
(X)
−
(X)
PWM75
(0)
PWM74
(0)
PWM73
(0)
PWM72
(0)
PWM71
(0)
PWM70
(0)
−
(X)
PWM86L PWM85L PWM84L PWM83L PWM82L PWM81L PWM80L RW
(0) (0) (0) (0) (0) (0) (0)
PWM86H PWM85H PWM84H PWM83H PWM82H PWM81H PWM80H RW
(0) (0) (0) (0) (0) (0) (0)
−
(X)
1996 Feb 21
26
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
ADDR
(HEX)
REG
7
6
5
4
3
2
1
0
R/W
20
ADCCN
−
(X)
ADCS1
(0)
ADCS0
(0)
DAC3
(0)
DAC2
(0)
DAC1
(0)
DAC0
(0)
COMP(2) RW
(0)
21
22
23
24
40
41
42
43
44
PWME1 PWM7E PWM6E PWM5E PWM4E PWM3E PWM2E PWM1E PWM0E RW
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
CON1
CON2
T3CON
PWM8E SCLE
SDAE
(0)
ADCE2
(0)
ADCE1
(0)
0(3)
−
(X)
−
(X)
RW
RW
R
(0)
(0)
−
−
−
(X)
−
(X)
P8LVL
(0)
P14LVL
(0)
P7LVL
(0)
P6LVL
(0)
(X)
(X)
T3B7
(0)
T3B6
(0)
T3B5
(0)
T3B4
(0)
T3B3
(0)
T3B2
(0)
T3B1
(0)
T3B0
(0)
PWM10 PWM107 PWM106 PWM105 PWM104 PWM103 PWM102 PWM101 PWM100 RW
(0) (0) (0) (0) (0) (0) (0) (0)
PWM117 PWM116 PWM115 PWM114 PWM113 PWM112 PWM111( PWM110 RW
(0) (0) (0) (0) (0) (0) 0) (0)
PWM12 PWM127 PWM126 PWM125 PWM124 PWM123 PWM122 PWM121 PWM120 RW
(0) (0) (0) (0) (0) (0) (0) (0)
PWM13 PWM137 PWM136 PWM135 PWM134 PWM133 PWM132 PWM131 PWM130 RW
PWM11
(0)
(0)
(0)
(0)
(0)
PWM13E PWM12E PWM11E PWM10E RW
(0) (0) (0) (0)
(0)
(0)
(0)
PWME2
−
(X)
−
(X)
−
(X)
−
(X)
Notes
1. Values within parethesis show the bit state after a reset operation. ‘X’ denotes an undefined state.
2. This bit is Read only.
3. This bit must be set to logic 0.
14 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 34)
SYMBOL
VDD
PARAMETER
MIN.
−0.3
MAX.
+8.0
UNIT
supply voltage
V
V
VI
input voltage on any pin with respect to ground (VSS
maximum source current for all port lines
maximum sink current for all port lines
total power dissipation
)
−0.3
−
VDD + 0.3
−10.0
30.0
IOH
IOL
mA
mA
W
−
Ptot
Tamb
Tstg
−
1
operating ambient temperature
−25
−55
+85
°C
storage temperature
+125
°C
1996 Feb 21
27
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
15 DC CHARACTERISTICS
VDD = 5 V ±10%; VSS = 0 V; Tamb = −25 to +85 °C; all voltages with respect to VSS; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Supply
VDD
IDD
operating supply voltage
4.5
5.0
5
5.5
10
7
V
operating supply current
fxtal = 10 MHz; VDD = 5 V
−
mA
mA
mA
mA
mA
V
fxtal = 6 MHz; VDD = 5 V
−
3.5
3
Stop; fxtal = 10 MHz
Stop; fxtal = 6 MHz
−
6
−
1.5
−
4
ILU
latch-up current for all pins
Power-on-reset voltage level
50
0.7
−
VPOR
1.3
1.9
Ports P0; P1; DP0; DP1 and DP2 inputs
VIL
VIH
ILI
LOW level input voltage
HIGH level input voltage
input leakage current
0
−
−
−
0.3VDD
VDD
V
0.7VDD
V
VSS < VI < VDD
−
±10
µA
Port P0 outputs
VOL
IOH1
LOW level output voltage
HIGH level pull-up output source current
VDD = 5 V; IOL = 10 mA
VDD = 5 V; VO = 0.7VDD
−
−
1.2
V
−40
−
−100
−
µA
µA
mA
V
DD = 5 V; VO = VSS
−140 −400
IOH2
HIGH level push-pull output source current VDD = 5 V; VO = VDD − 0.4 V −3.0
−7.0
−
DP00/PWM0 to DP07/PWM7; DP24/PWM10 to DP27/PWM13 as derivative ports
IOL
LOW level output sink current
VDD = 5 V; VOL = 0.4 V
VDD = 5 V; VO = 0.7VDD
5.0
−40
−
12.0
−
−
mA
µA
IOH1
HIGH level pull-up output source current
−100
V
DD = 5 V; VO = VSS
−140 −400
µA
IOH2
HIGH level push-pull output source current VDD = 5 V; VO = VDD − 0.4 V −3.0
−7.0
−
mA
DP00/PWM0 to DP07/PWM7; DP24/PWM10 to DP27/PWM13 as PWM outputs
IOL
LOW level output sink current
VDD = 5 V; VOL = 0.4 V
VDD = 5 V; VO = 0.7VDD
VDD = 5 V; VO = VSS
0.7
−40
−
1.5
−
−
mA
µA
IOH1
HIGH level pull-up output source current
−100
−140 −400
µA
IOH2
HIGH level push-pull output source current VDD = 5 V; VO = VDD − 0.4 V −0.7
−1.5
−
mA
P10 to P12 and P14 outputs
IOL
LOW level output sink current
HIGH level pull-up output source current
VDD = 5 V; VOL = 0.4 V
VDD = 5 V; VO = 0.7VDD
5.0
−40
−
12.0
−
−
mA
µA
IOH1
−100
V
DD = 5 V; VO = VSS
−140 −400
µA
IOH2
HIGH level push-pull output source current VDD = 5 V; VO = VDD − 0.4 V −3.0
−7.0
−
mA
DP20/SDA and DP21/SCL outputs
IOL
LOW level output sink current
VDD = 5 V; VOL = 0.4 V
VDD = 5 V; VO = 0.7VDD
3.0
−40
−
−
−
−
mA
µA
IOH1
HIGH level pull-up output source current
−100
V
DD = 5 V; VO = VSS
−140 −400
−7.0
µA
IOH2
HIGH level push-pull output source current VDD = 5 V; VO = VDD − 0.4 V −3.0
−
mA
1996 Feb 21
28
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
DP13/PWM8 as PWM8 output
IOL
LOW level output sink current
HIGH level pull-up output source current
VDD = 5 V; VOL = 0.4 V
VDD = 5 V; VO = 0.7VDD
1.4
3.0
−
−
mA
µA
IOH1
−40
−100
V
DD = 5 V; VO = VSS
−
−140 −400
µA
IOH2
HIGH level push-pull output source current VDD = 5 V; VO = VDD − 0.4 V −1.4
−3.0
−
mA
DP11/ADC1 or DP12/ADC2 as derivative output ports
IOL
LOW level output sink current
VDD = 5 V; VOL = 0.4 V
VDD = 5 V; VO = 0.7VDD
VDD = 5 V; VO = VSS
5.0
−40
−
12.0
−
−
mA
µA
IOH1
HIGH level pull-up output source current
−100
−140 −400
µA
IOH2
HIGH level push-pull output source current VDD = 5 V; VO = VDD − 0.4 V −3.0
−7.0
−
mA
TEST/EMU; RESET; INTN/T0; T1 and T3
VIL
VIH
ILI
LOW level input voltage
HIGH level input voltage
input leakage current
0
−
−
−
0.3VDD
VDD
V
0.7VDD
−1.0
V
VSS < VI < VDD
+1.0
µA
16 AC CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
fxtal
Crystal oscillator frequency
Option 1: gm = 0.4 mS
Option 2: gm = 1.2 mS
PXE resonator frequency
Option 2: gm = 1.2 mS
VDD = 5 V; Tamb = −25 to +85 °C
1
4
−
−
6
MHz
MHz
10
fPXE
VDD = 5 V; Tamb = −25 to +85 °C
VDD = 5 V; Tamb = −25 to +85 °C
1
−
5
MHz
pF
Cxtal1
Cxtal2
tT3
external capacitance at XTAL1 (IN)
pin (PXE resonator)
−
30
100
external capacitance at XTAL2 (OUT) VDD = 5 V; Tamb = −25 to +85 °C
pin (PXE resonator)
−
30
100
pF
minimum pulse width period at T3
input
rising or falling edge of T3
pulse < 30 ns
0.4
−
−
µs
Analog-to-Digital (software) Converter
VAI
DP11/ADC1 or DP12/ADC2
VSS
−
VDD
V
comparator analog input voltage
VAE
conversion error range
−
−
−
−
±1⁄2
LSB
TAFC
conversion time (from any change in
ADC input i.e. channel select, voltage
level or enable/disable)
7
µs
1996 Feb 21
29
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
17 PACKAGE OUTLINES
SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)
SOT232-1
D
M
E
A
2
A
A
L
1
c
(e )
w M
e
Z
1
b
1
M
H
b
32
17
pin 1 index
E
1
16
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
2
max.
(1)
(1)
Z
1
w
UNIT
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.
max.
1.3
0.8
0.53
0.40
0.32
0.23
29.4
28.5
9.1
8.7
3.2
2.8
10.7
10.2
12.2
10.5
mm
4.7
0.51
3.8
1.778
10.16
0.18
1.6
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT232-1
1996 Feb 21
30
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)
SOT270-1
D
M
E
A
2
A
L
A
1
c
e
(e )
1
w M
Z
b
1
M
H
b
42
22
pin 1 index
E
1
21
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
2
max.
(1)
(1)
Z
1
w
UNIT
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.
max.
1.3
0.8
0.53
0.40
0.32
0.23
38.9
38.4
14.0
13.7
3.2
2.9
15.80
15.24
17.15
15.90
mm
5.08
0.51
4.0
1.778
15.24
0.18
1.73
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
90-02-13
95-02-04
SOT270-1
1996 Feb 21
31
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
18 SOLDERING
18.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
18.2 SDIP
18.2.1 SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
18.2.2 REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
1996 Feb 21
32
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
19 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
20 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
21 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Feb 21
33
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
NOTES
1996 Feb 21
34
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
NOTES
1996 Feb 21
35
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© Philips Electronics N.V. 1996
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457021/1100/01/pp36
Date of release: 1996 Feb 21
9397 750 00676
Document order number:
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