PCF2103EU [NXP]

LCD controllers/drivers; LCD控制器/驱动器


型号：	PCF2103EU
厂家：	NXP
描述：	LCD controllers/drivers LCD控制器/驱动器驱动器控制器 CD
文件：	总56页 (文件大小：303K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

PCF2103 family

LCD controllers/drivers

1998 May 11

Product speciﬁcation

File under Integrated Circuits, IC12

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

CONTENTS

8.7

Set CGRAM address

8.8

8.9

8.10

8.11

Set DDRAM address

FEATURES

Read busy flag and address counter

Write data to CGRAM or DDRAM

Read data from CGRAM or DDRAM

Extended function set instructions and features

New instructions

Icon control

APPLICATIONS

GENERAL DESCRIPTION

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING

8.12

8.12.1

8.12.2

8.12.3

8.12.4

8.12.5

8.12.6

8.12.7

FUNCTIONAL DESCRIPTION

Screen configuration

Display configuration

Reducing current consumption

7.1

7.2

LCD bias voltage generator

Oscillator

7.3

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.13

7.14

7.15

External clock

Power-on reset

Power-down mode

Registers

Busy flag

Address Counter (AC)

Display Data RAM (DDRAM)

Character Generator ROM (CGROM)

Character Generator RAM (CGRAM)

Cursor control circuit

Timing generator

INTERFACE TO MICROCONTROLLER

9.1

9.2

9.2.1

9.2.2

9.2.3

Parallel interface

I²C-bus interface

Characteristics of the I²C-bus

I²C-bus protocol

Definitions

LIMITING VALUES

HANDLING

DC CHARACTERISTICS

AC CHARACTERISTICS

TIMING CHARACTERISTICS

APPLICATION INFORMATION

LCD row and column drivers

Reset function

INSTRUCTIONS

8.1

8.2

8.3

8.3.1

8.3.2

8.4

8.4.1

8.4.2

8.4.3

8.5

Clear display

Return home

Entry mode set

I/D

15.1

8-bit operation, 1-line display using internal

reset

4-bit operation, 1-line display using internal

reset

8-bit operation, 2-line display

I²C-bus operation, 1-line display

15.2

15.3

15.4

Display control (and partial power-down mode)

Cursor or display shift

Function set

DL (parallel mode only)

BONDING PAD LOCATIONS

DEFINITIONS

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I²C COMPONENTS

8.6

8.6.1

8.6.2

8.6.3

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

FEATURES

• Single-chip LCD controller/driver

• 2-line display of up to 12 characters + 120 icons,

or 1-line display of up to 24 characters + 120 icons

• 5 × 7 character format plus cursor; 5 × 8 for kana

(Japanese syllabary) and user defined symbols

APPLICATIONS

• Icon mode: reduced current consumption while

displaying icons only⁽¹⁾

• Telecom equipment

• Portable instruments

• Point-of-sale terminals.

• Icon blink function

• On-chip:

– Generation of intermediate LCD bias voltages

GENERAL DESCRIPTION

– Oscillator requires no external components

(external clock also possible)

The PCF2103 family is a low power CMOS LCD controller

and driver, designed to drive a dot matrix LCD display of

2 line by 12 or 1 line by 24 characters with 5 × 8 dot

format. All necessary functions for the display are provided

in a single chip, including on-chip generation of LCD bias

voltages, resulting in a minimum of external components

and lower system current consumption. The PCF2103

interfaces to most microcontrollers via a 4 or 8-bit bus or

via the 2-wire I²C-bus. The chip contains a character

generator and displays alphanumeric and kana

• Display data RAM: 80 characters

• Character generator ROM: 240, 5 × 8 characters

• Character generator RAM: 16, 5 × 8 characters;

3 characters used to drive 120 icons, 6 characters used

if icon blink feature is used in application

• 4 or 8-bit parallel bus and 2-wire I²C-bus interface

• CMOS compatible

• 18 row, 60 column outputs

(Japanese) characters. The letter ‘X’ in PCF2103X

characterizes the built-in character set. Various character

sets can be manufactured on request.

• Mux rates 1 : 18 (for normal operation) and 1 : 2

(for icon-only mode)

• Uses common 11 code instruction set (extended)

• Logic supply voltage range, V_DD− V_SS= 1.8 to 5.5 V;

chip may be driven with two battery cells

• Display supply voltage range, V_LCD− V_SS= 2.2 to 6.5 V

• Very low current consumption (20 to 120 µA):

– Icon mode: <25 µA

– Power-down mode: <2.5 µA.

(1) Icon mode is used to save current. When only icons

are displayed, a much lower operating voltage V_LCD

can be used and the switching frequency of the LCD

outputs is reduced. In most applications it is possible

to use V_DDas V_LCD

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME

DESCRIPTION

VERSION

PCF2103EU/2/F2

−

chip with bumps in tray

−

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

BLOCK DIAGRAM

C1 to C60

R1 to R18

handbook, full pagewidth

COLUMN DRIVERS

ROW DRIVERS

BIAS

VOLTAGE

GENERATOR

LCD

DATA LATCHES

SHIFT REGISTER 18-BIT

SHIFT REGISTER 5 × 12-BIT

OSC

OSCILLATOR

CURSOR AND DATA CONTROL

CHARACTER

GENERATOR

ROM

GENERATOR

RAM (128 × 5)

(CGRAM)

(CGROM)

16 CHARACTERS

240 CHARACTERS

TIMING

GENERATOR

DISPLAY DATA RAM

(DDRAM)

80 CHARACTERS/BYTES

DISPLAY

ADDRESS

COUNTER

ADDRESS COUNTER

(AC)

INSTRUCTION

DECODER

PCF2103

DATA

(DR)

INSTRUCTION

BUSY

FLAG

POWER-ON

RESET

I/O BUFFER

MGL259

SCL

SDA

DB4 to DB7

DB0 to DB3/SA0

R/W

Fig.1 Block diagram.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

PINNING

SYMBOL

DIE PAD

DESCRIPTION

V_DD

supply voltage

OSC

oscillator/external clock input

power-down pad input

test pad (connected to V_SS

ground

)

V_SS

V_LCD

V_LCDinput; note 1

R9 to R16

R18

7 to 14

LCD row driver outputs 9 to 16

LCD row driver output 18

C60 to C1

16 to 23, 26 to 50, LCD column driver outputs 60 to 1

53 to 77, 80, 81

R8 to R1

R17

82 to 89

LCD row driver outputs 8 to 1

LCD row driver output 17

I²C-bus serial clock input

I²C-bus serial data input/output

data bus clock input

SCL

SDA

R/W

DB7

DB6

DB5

DB4

DB3/SA0

DB2

DB1

DB0

read/write input

bit of bi-directional data bus

100

101

102

103

bit of bi-directional data bus/I²C-bus address pin

bit of bi-directional data bus

Note

1. This is the voltage used for the generation of LCD bias levels.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

Table 1 Pin functions; note 1

NAME

FUNCTION

DESCRIPTION

RS selects the register to be accessed for read and write; there is an internal pull-up

on this pin

RS = 0 selects the instruction register for write and the busy flag and address

counter for read

RS = 1 selects the data register for both read and write

R/W

read/write

R/W selects either the read (R/W = 1) or write (R/W = 0) operation; there is an

internal pull-up on this pin

data bus clock

pin E is set HIGH to signal the start of a read or write operation; data is clocked in or

out of the chip on the negative edge of the clock

DB7 to DB0 data bus

the bi-directional, 3-state data bus transfers data between the system controller and

the PCF2103; DB7 may be used as the busy ﬂag, signalling that internal operations

are not yet completed; in 4-bit operations the 4 higher order lines DB7 to DB4 are

used; DB3 to DB0 must be left open-circuit; there is an internal pull-up on each of the

data lines

C1 to C60

R1 to R18

V_LCD

column driver

outputs

these pins output the data for columns

row driver

outputs

these pins output the row select waveforms to the display; R17 and R18 drive the

icons

LCD power

supply

positive power supply for the liquid crystal display

OSC

oscillator

when the on-chip oscillator is used this pin must be connected to V_DD; an external

clock signal, if used, is input at this pin

SCL

SDA

SA0

serial clock line input for the I²C-bus clock signal

serial data line

address pin

I/O for the I²C-bus data line

the hardware sub-address line is used to program the device sub-address for two

different PCF2103s on the same I²C-bus

test pad

must be connected to V_SS; not user accessible

power-down pad PD selects chip power-down mode; for normal operation PD = 0

Note

1. When the I²C-bus is used, the parallel interface pin E must be defined as E = 0. In I²C-bus read mode DB7 to DB0

should be connected to V_DDor left open-circuit.

a) When the parallel bus is used, pins SCL and SDA must be connected to V_SSor V_DD; they may not be left

unconnected.

b) If the 4-bit interface is used without reading out from the PCF2103 (i.e. R/W is set permanently to logic 0), the

unused ports DB0 to DB3 can either be set to V_SSor V_DDinstead of leaving them open.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

FUNCTIONAL DESCRIPTION

LCD bias voltage generator

7.1

The intermediate bias voltages for the LCD display are generated on-chip. This removes the need for an external

resistive bias chain and significantly reduces the system current consumption. The optimum value of V_LCDdepends on

the multiplex rate, the LCD threshold voltage (V_th) and the number of bias levels and is given by the relationships given

in Tables 2 and 3. Using a 5-level bias scheme for 1 : 18 maximum rate allows V_LCD<5 V for most LCD liquids.

Table 2 Optimum/maximum values for V_OP(off pixels start darkening; V_off= V_th)

MUX RATE

1 : 18

NUMBER OF LEVELS

V_on/V_th

1.272

2.236

V_OP/V_th

V_OP(typical; for V_th= 1.4 V)

3.7

5.2 V

3.9 V

1 : 2

2.283

Table 3 Minimum values for V_OP(on pixels clearly visible; V_on> V_th)

MUX RATE

1 : 18

NUMBER OF LEVELS

V_on/V_th

1.12

V_OP/V_th

3.2

V_OP(typical; for V_th= 1.4 V)

4.6 V

2.1 V

1 : 2

1.2

1.5

During power-down, the whole chip is being reset and will

restart with a clear display after power-down. Therefore,

the whole chip has to be initialized after a power-down as

after an initial power-up.

7.2

Oscillator

The on-chip oscillator provides the clock signal for the

display system. No external components are required and

pin OSC must be connected to V_DD

7.6

Registers

7.3 External clock

The PCF2103 has two 8-bit registers, an Instruction

Select signal (RS) determines which register will be

accessed. The instruction register stores instruction codes

such as ‘display clear’ and ‘cursor shift’, and address

information for the Display Data RAM (DDRAM) and

Character Generator RAM (CGRAM). The instruction

controller. The data register temporarily stores data to be

read from the DDRAM and CGRAM. When reading, data

from the DDRAM or CGRAM corresponding to the address

in the instruction register is written to the data register prior

to being read by the ‘read data’ instruction.

If an external clock is to be used, it is input at the OSC pin.

The resulting display frame frequency is given by

f_osc

f_frame

------------

3072

Only in the power-down state is the clock allowed to be

stopped (OSC connected to V_SS), otherwise the LCD is

frozen in a DC state.

7.4

Power-on reset

The on-chip power-on reset block initializes the chip after

power-on or power failure. This is a synchronous reset and

requires 3 oscillator cycles to be executed. Afterwards, a

clear display is initiated.

7.7

Busy ﬂag

The busy flag indicates the internal status of the PCF2103.

Logic 1 indicates that the chip is busy and further

instructions will not be accepted. The busy flag is output at

pin DB7 when RS = 0 and R/W = 1. Instructions should

only be written after checking that the busy flag is logic 0

or waiting for the required number of cycles.

7.5

Power-down mode

The chip can be put into power-down mode where all static

currents are switched off (no internal oscillator, no bias

level generation, all LCD outputs are internally connected

to V_SS) when PD = 1.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

7.8

Address Counter (AC)

7.11 Character Generator RAM (CGRAM)

The address counter assigns addresses to the DDRAM

and CGRAM for reading and writing and is set by the

commands ‘set CGRAM address’ and ‘set DDRAM

address’. After a read/write operation the address counter

is automatically incremented or decremented by 1.

The address counter contents are output to the bus

(DB6 to DB0) when RS = 0 and R/W = 1.

Up to 16 user defined characters may be stored in the

CGRAM. Some CGRAM characters (see Fig.14) are also

used to drive icons (6 if icons blink and both icon rows are

used in application; 3 if no blink but both icon rows are

used in application; 0 if no icons are driven by the icon

rows). The CGROM and CGRAM use a common address

space, of which the first column is reserved for the

CGRAM (see Fig.6). Figure 7 shows the addressing

principle for the CGRAM.

7.9

Display Data RAM (DDRAM)

The DDRAM stores up to 80 characters of display data

represented by 8-bit character codes. RAM locations

which are not used for storing display data can be used as

general purpose RAM. The basic RAM-to-display

addressing scheme is shown in Fig.2. With no display shift

the characters represented by the codes in the first

24 RAM locations starting at address 00 in line 1 are

displayed. Figures 3 and 4 show the display mapping for

right and left shift respectively.

7.12 Cursor control circuit

The cursor control circuit generates the cursor (underline

and/or cursor blink as shown in Fig.5) at the DDRAM

address contained in the address counter. When the

address counter contains the CGRAM address the cursor

will be inhibited.

7.13 Timing generator

When data is written to or read from the DDRAM

wrap-around occurs from the end of one line to the start of

the next line. When the display is shifted each line wraps

around within itself, independently of the others. Thus all

lines are shifted and wrapped around together.

The address ranges and wrap-around operations for the

various modes are shown in Table 4.

The timing generator produces the various signals

required to drive the internal circuitry. Internal chip

operation is not disturbed by operations on the data buses.

7.14 LCD row and column drivers

The PCF2103 contains 18 row and 60 column drivers,

which connect the appropriate LCD bias voltages in

sequence to the display in accordance with the data to be

displayed. R17 and R18 drive the icon rows.

7.10 Character Generator ROM (CGROM)

The Character Generator ROM (CGROM) generates

240 character patterns in 5 × 8 dot format from 8-bit

character codes. Figure 6 shows the character set that is

currently implemented.

The bias voltages and the timing are selected

automatically when the number of lines in the display is

selected. Figures 8, 9 and 10 show typical waveforms.

Unused outputs should be left unconnected.

Table 4 Address space and wrap-around operation

READ/WRITE

WRAP-AROUND⁽¹⁾

DISPLAY SHIFT

WRAP-AROUND⁽²⁾

MODE

ADDRESS SPACE

1 × 24

2 × 12

00H to 4FH

00H to 27H; 40H to 67H

4FH to 00H

27H to 40H; 67H to 00H

4FH to 00H

27H to 00H; 67H to 40H

Notes

1. Moves to next line.

2. Stays within line.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

non-displayed DDRAM addresses

display

handbook, full pagewidth

position

22 23 24

DDRAM

address

00 01 02 03 04

15 16 17 18 19

4C 4D 4E 4F

1-line display

non-displayed DDRAM address

10 11 12

00 01 02 03 04

09 0A 0B 0C 0D

24 25 26 27

line 1

line 2

DDRAM

address

10 11 12

40 41 42 43 44

49 4A 4B 4C 4D

64 65 66 67

MGE991

2-line display

Fig.2 DDRAM-to-display mapping: no shift.

display

position

handbook, halfpage

22 23 24

14 15 16

4F 00 01 02 03

DDRAM

address

1-line display

10 11 12

08 09 0A

line 1

line 2

27 00 01 02 03

DDRAM

address

10 11 12

48 49 4A

67 40 41 42 43

MGE992

2-line display

Fig.3 DDRAM-to-display mapping: right shift.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

display

handbook, halfpage

position

22 23 24

16 17 18

01 02 03 04 05

DDRAM

address

1-line display

10 11 12

0A 0B 0C

line 1

line 2

01 02 03 04 05

DDRAM

address

10 11 12

4A 4B 4C

41 42 43 44 45

MGE993

2-line display

Fig.4 DDRAM-to-display mapping: left shift.

MGA801

cursor

5 x 7 dot character font

alternating display

cursor display example

blink display example

Fig.5 Cursor and blink display examples.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

handbook, full pagewidth

upper

4 bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

lower

4 bits

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111

MGD689

Fig.6 Character set ‘E’ in CGROM.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

character codes

(DDRAM data)

CGRAM

address

character patterns

(CGRAM data)

character code

(CGRAM data)

handbook, full pagewidth

higher

order

bits

lower

order

bits

higher

order

bits

lower

order

bits

higher

order

bits

lower

order

bits

character

pattern

example 1

cursor

position

character

pattern

example 2

MGE995

Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.

CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with

the cursor. Data in the 8th position will appear in the cursor position.

Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in Fig.6.

As shown in Figs 6 and 7, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds

to selection for display.

Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ command. Bit 6 can be set using the ‘set DDRAM address’ command in

the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘read busy flag and address

counter’ command; see Table 7.

Fig.7 Relationship between CGRAM addresses and data and display patterns.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

frame n

frame n + 1

state 1 (ON)

state 2 (OFF)

handbook, full pagewidth

LCD

V /V

ROW 1

ROW 9

ROW 2

COL1

LCD

V /V

LCD

V /V

LCD

V /V

LCD

V /V

COL2

0.5V

0.25V

0 V

state 1

−0.25V

−0.5V

−V

0.5V

0.25V

0 V

state 2

−0.25V

−0.5V

−V

MGE996

Fig.8 Typical LCD waveforms; character mode.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

frame n

frame n + 1

handbook, full pagewidth

only icons are

driven (MUX 1 : 2)

LCD

2/3

1/3

ROW 17

ROW 18

LCD

2/3

1/3

LCD

2/3

1/3

ROW 1 to 16

LCD

2/3

1/3

COL 1

ON/OFF

LCD

2/3

1/3

COL 2

COL 3

COL 4

/ON

OFF

LCD

2/3

1/3

ON/ON

LCD

2/3

1/3

OFF/OFF

MGE997

Fig.9 Mux 1 : 2 LCD waveforms; icon mode.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

handbook, full pagewidth

frame n

frame n + 1

PIXEL

state 1 (ON)

state 2 (OFF)

2/3 V

1/3 V

R17

state 1

COL 1 -

ROW 17

R18

R1-16

−1/3 V

−2/3 V

−V

state 3 (OFF)

2/3 V

1/3 V

state 2

COL 2 -

ROW 17

−1/3 V

−2/3 V

−V

2/3 V

1/3 V

state 3

COL 1 -

ROW 1 to 16

−1/3 V

−2/3 V

−V

MGE998

V_ON(rms)= 0.745 V_OP

V_OFF(rms)= 0.333 V_OP

V_ON

D =

= 2.23

-------------

V_OFF

Fig.10 Mux 1 : 2 LCD waveforms; icon mode.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

7.15 Reset function

The PCF2103 automatically initializes (resets) when power is turned on. The reset executes a ‘clear display’ instruction,

requiring 165 oscillator cycles. After the reset the chip has the state shown in Table 5.

Table 5 State after reset

STEP

INSTRUCTION

clear display

RESET STATE (BIT/REGISTER)

RESET STATE (DESCRIPTION)

entry mode set

I/D = 1

S = 0

D = 0

C = 0

B = 0

DL = 1

M = 0

H = 0

+1 (increment)

no shift

display control

display off

cursor off

cursor character blink off

8-bit interface

1-line display

normal instruction set

function set

default address pointer to DDRAM; the Busy Flag (BF) indicates the busy state (BF = 1) until initialization

ends; the busy state lasts 2 ms; the chip may also be initialized by software; see Tables 16 and 17

icon control

IM, IB = 00

icons/icon blink disabled

default conﬁgurations

display/screen conﬁguration

I²C-bus interface reset

L, P, Q = 000

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

In normal use, instructions that perform data transfer with

internal RAM are used most frequently. However,

automatic incrementing by 1 (or decrementing by 1) of

internal RAM addresses after each data write lessens the

microcontroller program load. The display shift in particular

can be performed concurrently with display data write,

enabling the designer to develop systems in minimum time

with maximum programming efficiency.

INSTRUCTIONS

Only two PCF2103 registers, the Instruction Register (IR)

and the Data Register (DR) can be directly controlled by

the microcontroller. Before internal operation, control

information is stored temporarily in these registers to allow

interface to various types of microcontrollers which

operate at different speeds or to allow interface to

peripheral control ICs. The format for instructions when

I²C-bus control is used is shown in Table 6. The PCF2103

operation is controlled by the instructions given in Table 7

together with their execution time. Details are explained in

subsequent sections.

During internal operation, no instruction other than the

‘read busy flag and address counter’ instruction will be

executed. Because the busy flag is set to logic 1 while an

instruction is being executed, the user should verify that

the busy flag is at logic 0 before sending the next

instruction or wait for the maximum instruction execution

time, as given in Table 7. An instruction sent while the

busy flag is logic 1 will not be executed.

Instructions are of 4 types, those that:

1. Designate PCF2103 functions such as display format,

data length, etc.

2. Set internal RAM addresses

3. Perform data transfer with internal RAM

4. Others.

Table 6 Instruction set for I²C-bus commands

CONTROL BYTE

COMMAND BYTE

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 note 1

I²C-BUS COMMANDS

Co RS

Note

1. R/W is set together with the slave address.

1998 May 11

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Table 7 Instruction set with parallel bus commands; note 1

REQUIRED

INSTRUCTION RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

H = 0 or 1

DESCRIPTION

CLOCK

CYCLES

NOP

no operation

Function set

sets interface Data Length (DL) and number of

display lines (M); extended instruction set control

(H)

Read busy ﬂag

and address

counter

reads the Busy Flag (BF) indicating internal

operating is being performed and reads address

counter contents

Read data

Write data

read data

write data

reads data from CGRAM or DDRAM

writes data from CGRAM or DDRAM

H = 0

Clear display

clears entire display and sets DDRAM address 0

in address counter

165

Return home

Entry mode set

Display control

sets DDRAM address 0 in address counter; also

returns shifted display to original position; DDRAM

contents remain unchanged

I/D

sets cursor move direction and speciﬁes shift of

display; these operations are performed during

data write and read

sets entire display on/off (D), cursor on/off (C) and

blink of cursor position character (B); D = 0

(display off) puts chip into power-down mode

Cursor/display

shift

S/C R/L

A_CG

moves cursor and shifts display without changing

DDRAM contents

Set CGRAM

address

sets CGRAM address; bit 6 is to be set by the

command ‘set DDRAM address’; look at the

description of the commands

Set DDRAM

address

A_DD

sets DDRAM address

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REQUIRED

INSTRUCTION RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

H = 1

DESCRIPTION

CLOCK

CYCLES

Reserved

do not use

−

Screen

set screen conﬁguration

conﬁguration

Display

set display conﬁguration

conﬁguration

Icon control

Reserved

set icon mode (IM), icon blink (IB)

do not use

−

do not use

Note

1. X = don’t care.

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

Table 8 Speciﬁcation of mnemonics used in Table 7

BIT

LOGIC 0

LOGIC 1

I/D

decrement

display freeze

display off

cursor off

increment

display shift

display on

cursor on

cursor character blink off: character at cursor

position does not blink

cursor character blink on: character at cursor

position blinks

S/C

R/L

cursor move

left shift

display shift

right shift

4 bits

8 bits

use basic instruction set

use extended instruction set

L (ignored, left/right screen: standard connection

left/right screen: mirrored connection

(as in PCF2116);

if M = 1)

(as in PCF2114);

1st 12 characters of 24: columns are from 1 to 60; 1st 12 characters of 24: columns are from 1 to 60;

2nd 12 characters of 24: columns are from 1 to 60 2nd 12 characters of 24: columns are from 60 to 1

column data: left to right (as in PCF2116);

column data is displayed from 1 to 60

column data: right to left;

column data is displayed from 60 to 1

row data: top to bottom (as in PCF2116);

row data is displayed from 1 to 16 and icon row

data is in 17 and 18

row data: bottom to top;

row data is displayed from 16 to 1 and icon

row data is in 18 and 17

character mode; full display

icon blink disabled

icon mode; only icons displayed

icon blink enabled

1-line by 24 display

2-line by 12 display

C₀

last control byte; see Table 6

another control byte follows after data/command

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

R/W

DB7

DB6

DB5

DB4

IR7

IR6

IR5

IR4

IR3

IR2

IR1

IR0

AC3

AC2

AC1

AC0

DR7

DR6

DR5

DR4

DR3

AC6

AC5

AC4

DR2

DR1

DR0

busy flag and

address counter read

data register

read

instruction

write

MGA804

Fig.11 4-bit transfer example.

R/W

internal

DB7

internal operation

not

busy

IR7

IR3

AC3

busy

instruction

write

busy flag

check

busy flag

check

instruction

write

MGA805

IR7 and IR3: instruction 7th and 3rd bit.

AC3: address counter 3rd bit.

D7 and D3: data 7th and 3rd bit.

Fig.12 An example of 4-bit data transfer timing sequence.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

R/W

internal

internal operation

busy

not

busy

data

busy

data

DB7

instruction

write

busy flag

check

busy flag

check

busy flag

check

instruction

write

MGA806

Fig.13 Example of busy flag checking timing sequence.

8.1

Clear display

8.3

Entry mode set

‘Clear display’ writes character code 20H into all DDRAM

addresses (the character pattern for character code 20H

must be a blank pattern), sets the DDRAM address

counter to logic 0 and returns display to its original position

if it was shifted. Thus, the display disappears and the

cursor or blink position goes to the left edge of the display.

Sets entry mode I/D = 1 (increment mode). S of entry

mode does not change.

8.3.1

I/D

When I/D = 1 (0) the DDRAM or CGRAM address

increments (decrements) by 1 when data is written into or

read from the DDRAM or CGRAM. The cursor or blink

position moves to the right when incremented and to the

left when decremented. The cursor underline and cursor

character blink are inhibited when the CGRAM is

accessed.

The instruction ‘clear display’ requires extra execution

time. This may be allowed by checking the Busy Flag (BF)

or by waiting until the 165 clock cycles have elapsed.

The latter must be applied where no read-back options are

foreseen, as in some Chip-On-Glass (COG) applications.

8.3.2

When S = 1, the entire display shifts either to the right

(I/D = 0) or to the left (I/D = 1) during a DDRAM write. Thus

it looks as if the cursor stands still and the display moves.

The display does not shift when reading from the DDRAM,

or when writing into or reading out of the CGRAM. When

S = 0 the display does not shift.

8.2

Return home

‘Return home’ sets the DDRAM address counter to logic 0

and returns display to its original position if it was shifted.

DDRAM contents do not change. The cursor or blink

position goes to the left of the first display line. I/D and S of

entry mode do not change.

1998 May 11

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Product speciﬁcation

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PCF2103 family

The Address Counter (AC) content does not change if the

only action performed is shift display, but increments or

decrements with the ‘cursor shift’.

8.4

Display control (and partial power-down mode)

8.4.1

The display is on when D = 1 and off when D = 0. Display

data in the DDRAM are not affected and can be displayed

immediately by setting D to logic 1.

8.6

Function set

8.6.1

DL (PARALLEL MODE ONLY)

When the display is off (D = 0) the chip is in partial

power-down mode:

Sets interface data width. Data is sent or received in bytes

(DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4)

when DL = 0. When 4-bit width is selected, data is

transmitted in two cycles using the parallel bus. In a 4-bit

application DB3 to DB0 should be left open-circuit (internal

pull-ups). Hence in the first ‘function set’ instruction after

power-on N and H are set to logic 1. A second

• The LCD outputs are connected to V_SS

• Bias generator is turned off.

3 oscillator cycles are required after sending the

‘display off’ instruction to ensure all outputs are at V_SS

afterwards OSC can be stopped. If the oscillator is running

during partial power-down mode (‘display off’) the chip can

still execute instructions. Even lower current consumption

is obtained by inhibiting the oscillator (OSC = V_SS).

‘function set’ must then be sent (2 nibbles) to set N and H

to their required values.

‘Function set’ from the I²C-bus interface sets the DL bit to

logic 1.

To ensure I_DD< 2 µA the parallel bus pins DB7 to DB0

should be connected to V_DD; RS and R/W to V_DDor left

open-circuit and PD to V_DD. Recovery from power-down

mode: put PD back to logic 0, if necessary put OSC back

to V_DDand send a ‘display control’ instruction with D = 1 to

enable the display again.

8.6.2

Chooses either 1-line by 24 display (M = 0) or 2-line by

12 display (M = 1).

8.6.3

8.4.2

When H = 0 the chip can be programmed via the standard

11 instruction codes used in the PCF2116 and other LCD

controllers.

The cursor is displayed when C = 1 and inhibited when

C = 0. Even if the cursor disappears, the display functions

I/D, etc. remain in operation during display data write.

The cursor is displayed using 5 dots in the 8th line (see

Fig.5).

When H = 1 the extended range of instructions will be

used. These are mainly for controlling the display

configuration and the icons.

8.4.3

8.7

Set CGRAM address

The character indicated by the cursor blinks when B = 1.

The cursor character blink is displayed by switching

between display characters and all dots on with a period of

‘Set CGRAM address’ sets bits 5 to 0 of the CGRAM

address A_CGinto the address counter (binary A[5] to A[0]).

Data can then be written to or read from the CGRAM.

f_osc

approximately 1 s, with f_BLINK

----------------

Attention: the CGRAM address uses the same address

(binary A[6] to A[0]). With the ‘set CGRAM address’

command, only bits 5 down to 0 are set. Bit 6 can be set

using the ‘set DDRAM address’ command first, or by using

the auto-increment feature during CGRAM write.

All bits 6 to 0 can be read using the

52224

The cursor underline and the cursor character blink can be

set to display simultaneously.

8.5

Cursor or display shift

‘Cursor/display shift’ moves the cursor position or the

display to the right or left without writing or reading display

data. This function is used to correct a character or move

the cursor through the display. In 2-line displays, the

cursor moves to the next line when it passes the last

position (40) of the line. When the displayed data is shifted

repeatedly all lines shift at the same time; displayed

characters do not shift into the next line.

‘read busy flag and address counter’ command.

When writing to the lower part of the CGRAM, ensure that

bit 6 of the address is not set (e.g. by an earlier DDRAM

write or read action).

1998 May 11

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Product speciﬁcation

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PCF2103 family

8.8

Set DDRAM address

8.12 Extended function set instructions and

features

‘Set DDRAM address’ sets the DDRAM address A_DDinto

the address counter (binary A[6] to A[0]). Data can then be

written to or read from the DDRAM.

8.12.1 NEW INSTRUCTIONS

H = 1 sets the chip into alternate instruction set mode.

8.9

Read busy ﬂag and address counter

8.12.2 ICON CONTROL

‘Read busy flag and address counter’ reads the Busy Flag

(BF) and Address Counter (AC). BF = 1 indicates that an

internal operation is in progress. The next instruction will

not be executed until BF = 0, so BF should be checked

before sending another instruction.

The PCF2103 can drive up to 120 icons. See Fig.14 for

CGRAM to icon mapping.

8.12.3 IM

When IM = 0 the chip is in character mode. In character

mode characters and icons are driven (mux 1 : 18).

At the same time, the value of the address counter

expressed in binary A[6] to A[0] is read out. The address

counter is used by both CGRAM and DDRAM, and its

value is determined by the previous instruction.

When IM = 1 the chip is in icon mode. In icon mode only

the icons are driven (mux 1 : 2).

8.10 Write data to CGRAM or DDRAM

8.12.4 IB

‘Write data’ writes binary 8-bit data D[7] to D[0] to the

CGRAM or the DDRAM.

Icon blink control is independent of the cursor/character

blink function.

Whether the CGRAM or DDRAM is to be written into is

determined by the previous ‘set CGRAM address’ or ‘set

DDRAM address’ command. After writing, the address

automatically increments or decrements by 1, in

accordance with the entry mode. Only bits D[4] to D[0] of

CGRAM data are valid, bits D[7] to D[5] are ‘don’t care’.

When IB = 0 icon blink is disabled. Icon data is stored in

CGRAM character 0 to 2 (3 × 8 × 5 = 120 bits for

120 icons).

When IB = 1 icon blink is enabled. In this case each icon is

controlled by two bits. Blink consists of two half phases

(corresponding to the cursor on and off phases called even

and odd phases hereafter).

8.11 Read data from CGRAM or DDRAM

Icon states for the even phase are stored in CGRAM

characters 0 to 2 (3 × 8 × 5 = 120 bits for 120 icons).

These bits also define the icon state when the icon blink is

not used.

‘Read data’ reads binary 8-bit data D[7] to D[0] from the

CGRAM or DDRAM.

The most recent ‘set address’ command determines

whether the CGRAM or DDRAM is to be read.

Icon states for the odd phase are stored in CGRAM

character 4 to 6 (another 120 bits for the 120 icons). When

icon blink is disabled CGRAM characters 4 to 6 may be

used as normal CGRAM characters.

The ‘read data’ instruction gates the content of the Data

goes LOW again, internal operation increments (or

decrements) the AC and stores RAM data corresponding

to the new AC into the DR.

It should be noted that there are only three instructions that

update the Data Register (DR). These are:

• ‘set CGRAM address’

• ‘set DDRAM address’

• ‘read data’ from CGRAM or DDRAM.

Other instructions (e.g. ‘write data’, ‘cursor/display shift’,

‘clear display’, ‘return home’) do not modify the data

1998 May 11

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PCF2103 family

Table 9 Blink effect for icons and cursor character blink

PARAMETER

Cursor underline

EVEN PHASE

ODD PHASE

off

Cursor character blink

Icons

block (all on)

normal (display character)

state 1: CGRAM characters 0 to 2

state 2: CGRAM characters 4 to 6

display:

COL 1 to 5

COL 6 to 10

COL 56 to 60

handbook, full pagewidth

ROW 17 –

ROW 18 –

56 57 58 59 60

61 62 63 64 65

block of 5 columns

66 67 68 69 70

116 117 118 119 120

MGE999

icon no.

handbook, full pagewidth

phase

ROW/COL

character codes

CGRAM address

CGRAM data

icon view

MSB

LSB MSB

LSB

1-5

6-10

11-15

even

17/1-5

17/6-10

17/11-15

56-60

61-65

even

17/56-60

18/1-5

116-120

1-5

even

18/56-60

17/1-5

odd (blink)

116-120

odd (blink) 18/56-60

MGG001

CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off.

Data in character codes 0 to 2 define the icon states when icon blink is disabled or during the even phase when icon blink is enabled.

Data in character codes 4 to 6 define the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled).

Fig.14 CGRAM-to-icon mapping.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

8.12.5 SCREEN CONFIGURATION

INTERFACE TO MICROCONTROLLER

Parallel interface

The default value for L is logic 0. In the event of L = 0 the

two halves of a split screen are connected in a standard

way i.e. column 1/61, 2/62 to 60/120. In the event of L = 1

the two halves of a split screen are connected in a mirrored

way i.e. column 1/120, 2/119 to 60/61. This allows single

layer PCB or glass layout.

9.1

The PCF2103 can send data in either two 4-bit operations

or one 8-bit operation and can thus interface to 4-bit or

8-bit microcontrollers.

In 8-bit mode data is transferred as 8-bit bytes using the

8 data lines DB7 to DB0. Three further control lines E, RS

and R/W are required; see Table 1.

8.12.6 DISPLAY CONFIGURATION

The default value for P and Q is logic 0. P = 1 mirrors the

column data whereas Q = 1 mirrors the row data.

In 4-bit mode data is transferred in two cycles of 4 bits

each using pins DB7 to DB4 for transaction. The higher

order bits (corresponding to DB7 to DB4 in 8-bit mode) are

sent in the first cycle and the lower order bits (DB3 to DB0

in 8-bit mode) in the second. Data transfer is complete

after two 4-bit data transfers. Note that two cycles are also

required for the busy flag check. 4-bit operation is selected

by instruction. See Figs 11 to 14 for examples of bus

protocol.

8.12.7 REDUCING CURRENT CONSUMPTION

Reducing current consumption can be achieved by one of

the options mentioned in Table 10.

Table 10 Reducing current consumption

ORIGINAL MODE

ALTERNATIVE MODE

In 4-bit mode pins DB3 to DB0 must be left open-circuit.

They are pulled up to V_DDinternally.

Character mode

Display on

icon mode (control bit IM)

display off (control bit D)

1998 May 11

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PCF2103 family

9.2

I²C-bus interface

9.2.2

I²C-BUS PROTOCOL

Before any data is transmitted on the I²C-bus, the device

which should respond is addressed first. The addressing is

always carried out with the first byte transmitted after the

start procedure. The I²C-bus configuration for the different

PCF2103 read and write cycles is shown in Figs 20 to 21.

The slow down feature of the I²C-bus protocol (receiver

holds SCL low during internal operations) is not used in the

PCF2103.

9.2.1

CHARACTERISTICS OF THE I²C-BUS

The I²C-bus is for bidirectional, two-line communication

between different ICs or modules. The two lines are a

serial data line (SDA) and a Serial Clock Line (SCL).

Both lines must be connected to a positive supply via a

pull-up resistor. Data transfer may be initiated only when

the bus is not busy.

Each byte of eight bits is followed by an acknowledge bit.

The acknowledge bit is a HIGH-level signal put on the bus

by the transmitter during which time the master generates

an extra acknowledge related clock pulse. A slave receiver

which is addressed must generate an acknowledge after

the reception of each byte. Also a master receiver must

generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter.

9.2.3

DEFINITIONS

• Transmitter: the device which sends the data to the bus

• Receiver: the device which receives the data from the

bus

• Master: the device which initiates a transfer, generates

clock signals and terminates a transfer

• Slave: the device addressed by a master

The device that acknowledges must pull down the SDA

line during the acknowledge clock pulse, so that the SDA

line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times

must be taken into consideration). A master receiver must

signal an end of data to the transmitter by not generating

an acknowledge on the last byte that has been clocked out

of the slave. In this event the transmitter must leave the

data line HIGH to enable the master to generate a STOP

condition.

• Multi-master: more than one master can attempt to

control the bus at the same time without corrupting the

message

• Arbitration: procedure to ensure that, if more than one

master simultaneously tries to control the bus, only one

is allowed to do so and the message is not corrupted

• Synchronization: procedure to synchronize the clock

signals of two or more devices.

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Philips Semiconductors

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PCF2103 family

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

SDA

SCL

MGA807

Fig.15 System configuration.

handbook, full pagewidth

SDA

SCL

data line

stable;

data valid

change

of data

allowed

MBC621

Fig.16 Bit transfer.

handbook, full pagewidth

SDA

SCL

STOP condition

START condition

MBC622

Fig.17 Definition of START and STOP conditions.

handbook, full pagewidth

DATA OUTPUT

BY TRANSMITTER

not acknowledge

acknowledge

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

clock pulse for

acknowledgement

START

condition

MBC602

Fig.18 Acknowledgement on the I²C-bus.

1998 May 11

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ahdnbok,uflapegwidt

acknowledgement

from PCF2103

1 RS CONTROL BYTE

DATA BYTE

0 RS CONTROL BYTE

1 byte

DATA BYTE

A P

slave address

2n ≥ 0 bytes

n ≥ 0 bytes

R/W Co

update

data pointer

MGL250

PCF2103

slave address

R/W

Fig.19 Master transmits to slave receiver; write mode.

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acknowledgement

(1)

1 RS CONTROL BYTE A

DATA BYTE

0 RS CONTROL BYTE

1 byte

DATA BYTE

slave address

2n 0 bytes

n ≥ 0 bytes

R/W

acknowledgement

no acknowledgement

SLAVE

ADDRESS

DATA BYTE

n bytes

last byte

R/W

update

data pointer

MGG003

data pointer

(1) Last data byte is a dummy byte (may be omitted).

Fig.20 Master reads after setting word address; write word address, set RS; ‘read data’.

Philips Semiconductors

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PCF2103 family

dbook, full pagewidth

acknowledgement

from PCF2103

acknowledgement

from master

no acknowledgement

from master

SLAVE

ADDRESS

DATA BYTE

last byte

n bytes

R/W

update

data pointer

MGL251

Fig.21 Master reads slave immediately after first byte; read mode (RS previously defined).

dbook, full pagewidth

SDA

LOW

BUF

SCL

SDA

SU;DAT

HD;STA

HIGH

HD;DAT

SU;STA

MGA728

SU;STO

Fig.22 I²C-bus timing diagram.

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PCF2103 family

10 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL

PARAMETER

MIN.

MAX.

+6.5

UNIT

V_DD

supply voltage

−0.5

V_LCD

V_I(1)

V_I(2)

V_O

LCD supply voltage

+7.5

input voltage on pins OSC, RS, R/W, E and DB7 to DB0 −0.5

input voltage on pins SCL and SDA −0.5

output voltage on pins R1 to R18, C1 to C60 and V_LCD−0.5

V_DD+ 0.5

+6.5

V_LCD+ 0.5

+10

I_I

DC input current

−10

−50

−

°C

I_O

DC output current

+10

I_DD, I_SSand I_LCD

V_DD, V_SSor V_LCDcurrent

total power dissipation

power dissipation per output

storage temperature

+50

P_tot

400

P/out

T_stg

−

100

−65

+150

11 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is

desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).

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PCF2103 family

12 DC CHARACTERISTICS

V_DD= 1.8 to 5.5 V; V_SS= 0 V; V_LCD= 2.2 to 6.5 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.

UNIT

Supplies

V_DD

V_LCD

I_SS

supply voltage

1.8

−

5.5

LCD supply voltage

supply current

2.2

−

6.5

120

note 1

µA

V_DD= 3 V; V_LCD= 5 V;

notes 1 and 2

−

icon mode; V_DD= 3 V;

V_LCD= 2.5 V;

notes 1 and 2

−

µA

power-down mode;

V_DD= 3 V; V_LCD= 2.5 V;

DB7 to DB0,

RS and R/W = 1;

OSC = 0; PD = 1; note 1

V_POR

Logic

V_IL

power-on reset voltage

note 3

−

1.3

1.6

LOW-level input voltage on

pins T1, E, RS, R/W,

−

0.3V_DD

DB7 to DB0 and SA0

V_IH

HIGH-level input voltage on

pins T1, E, RS, R/W,

0.7V_DD

−

V_DD

DB7 to DB0 and SA0

V_IL(PD)

V_IH(PD)

V_IL(OSC)

LOW-level input voltage on

pin PD

−

0.2V_DD

V_DD

HIGH-level input voltage on

pin PD

0.8V_DD

LOW-level input voltage on

pin OSC

V_DD− 1.5 V

V_IH(OSC)

I_OL(DB)

HIGH-input voltage on pin OSC

_DD− 0.1 −

V_DD

LOW-level output current on

pins DB7 to DB0

V_OL= 0.4 V; V_DD= 5 V

V_OH= 4 V; V_DD= 5 V

V_I= V_SS

1.6

−

I_OH(DB)

I_pu

HIGH-level output current on

pins DB7 to DB0

−1

−8

0.12

−

µA

pull-up current on

pins DB7 to DB0

0.04

−1

I_L

leakage current on pins OSC, E, V_I= V_DDor V_SS

RS, R/W, DB7 to DB0 and SA0

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

I²C-bus

SDA AND SCL

V_IL

V_IH

I_L

LOW-level input voltage

HIGH-level input voltage

input leakage current

input capacitance

−

0.3V_DD

5.5

0.7V_DD

V_I= V_DDor V_SS

−1

−

µA

C_i

note 4

I_OL

LOW-level output current

pin SDA

V_OL= 0.4 V; V_DD= 5 V

−

LCD outputs

R_o(ROW)

R_o(COL)

V_bias(tol)

row output resistance on

pins R1 to R18

note 5

note 6

−

kΩ

column output resistance on

pins C1 to C60

bias tolerance on

130

pins R1 to R18 and C1 to C60

Notes

1. LCD outputs are open-circuit; inputs at V_DDor V_SS; bus inactive.

2. T_amb= 25 °C; f_osc= 200 kHz.

3. Resets all logic when V_DD< V_POR; 3 oscillator clock cycles required.

4. Tested on sample basis.

5. Resistance of output terminals (R1 to R18 and C1 to C60) with a load current of 20 µA; outputs measured one at a

time.

6. LCD outputs open-circuit.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

13 AC CHARACTERISTICS

V_DD= 1.8 to 5.5 V; V_SS= 0 V; V_LCD= 2.2 − 6.5 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

SYMBOL

f_fr(LCD)

f_osc

f_osc(ext)

t_OSCST

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

147

UNIT

LCD frame frequency (internal clock)

oscillator frequency (not available at any pin)

external clock frequency

V_DD= 5.0 V

140

−

250

−

450

300

kHz

µs

oscillator start-up time after PD going from

logic 1 to logic 0

200

Bus timing characteristics: parallel interface; note 1

WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2103); see Fig.23

T_en(cy)

t_W(en)

t_su(A)

t_h(A)

enable cycle time

enable pulse width

address set-up time

address hold time

data set-up time

data hold time

500

220

−

t_su(D)

t_h(D)

READ OPERATION (READING DATA FROM PCF2103 TO MICROCONTROLLER); see Fig.24

T_en(cy)

t_W(en)

t_su(A)

t_h(A)

enable cycle time

enable pulse width

address set-up time

address hold time

data delay time

500

220

−

t_d(D)

150

100

t_h(D)

data hold time

Timing characteristics: I²C-bus interface; note 1

f_SCL

SCL clock frequency

−

400

−

kHz

µs

t_LOW

t_HIGH

t_SU;DAT

t_HD;DAT

t_r

SCL clock LOW period

SCL clock HIGH period

data set-up time

1.3

0.6

100

−

data hold time

−

SCL and SDA rise time

SCL and SDA fall time

capacitive bus line load

set-up time for a repeated START condition

START condition hold time

set-up time for STOP condition

tolerable spike width on bus

−

300

400

−

t_f

−

C_B

−

t_SU;STA

t_HD;STA

t_SU;STO

t_SW

0.6

−

Note

1. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to

V_ILand V_IHwith an input voltage swing of V_SSto V_DD

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

14 TIMING CHARACTERISTICS

handbook, full pagewidth

su(A)

h(A)

R/W

W(en)

h(A)

su(D)

h(D)

DATA

VALID

DB0 to DB7

MGL252

en(cy)

Fig.23 Parallel bus write operation sequence; writing data from microcontroller to PCF2103.

handbook, full pagewidth

su(A)

h(A)

R/W

W(en)

h(A)

d(D)

h(D)

DATA

VALID

DB0 to DB7

MGL253

en(cy)

Fig.24 Parallel bus read operation sequence; reading data from PCF2103 to microcontroller.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

15 APPLICATION INFORMATION

handbook, full pagewidth

P20

R17, R18

R/W

P21

2 × 12 CHARACTER

LCD DISPLAY

PLUS 120 ICONS

R1 to R16

P22

P80CL51

PCF2103

C1 to C60

P17 to P10

DB7 to DB0

MGL254

Fig.25 Direct connection to 8-bit microcontroller; 8-bit bus.

handbook, full pagewidth

R17, R18

P10

P11

P12

R/W

2 × 12 CHARACTER

LCD DISPLAY

PLUS 120 ICONS

R1 to R16

P80CL51

PCF2103

C1 to C60

P17 to P14

DB7 to DB4

MGL255

Fig.26 Direct connection to 8-bit microcontroller; 4-bit bus.

handbook, full pagewidth

R17, R18

OSC

2 × 12 CHARACTER

LCD DISPLAY

PLUS 120 ICONS

R1 to R16

LCD

PCF2103

100

LCD

100

C1 to C60

DB7 to DB0

RS R/W

MGL256

Fig.27 Application example using parallel interface.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

DD DD

handbook, full pagewidth

DB3/SAO

R17, R18

OSC

2 × 12 CHARACTER

LCD DISPLAY

PLUS 120 ICONS

R1 to R16

LCD

100

PCF2103

LCD

100

C1 to C60

SCL SDA

DB3/SAO

R17, R18

OSC

1 × 24 CHARACTER

LCD DISPLAY

PLUS 120 ICONS

R1 to R16

LCD

100

PCF2103

LCD

100

C1 to C60

SCL SDA

MASTER TRANSMITTER

PCF84C81A; P80CL410

MGL257

Fig.28 Application using I²C-bus interface.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

Since the display shift operation changes display position

only and DDRAM contents remain unchanged, display

data entered first can be displayed when the ‘return home’

operation is performed.

15.1 4-bit operation, 1-line display using internal

reset

The program must set functions prior to 4-bit operation;

Table 11 shows an example. When power is turned on,

8-bit operation is automatically selected and the PCF2103

attempts to perform the first write as an 8-bit operation.

Since nothing is connected to DB0 to DB3, a rewrite is

then required. However, since one operation is completed

in two accesses of 4-bit operation, a rewrite is required to

set the functions (see Table 11 step 3). Thus, DB4 to DB7

of the ‘function set’ are written twice.

15.3 8-bit operation, 2-line display

For a 2-line display, the cursor automatically moves from

the first to the second line after the 40th digit of the first line

has been written. Thus, if there are only 8 characters in the

first line, the DDRAM address must be set after the eighth

character is completed (see Table 6). It should be noted

that both lines of the display are always shifted together;

data does not shift from one line to the other.

15.2 8-bit operation, 1-line display using internal

reset

15.4 I²C-bus operation, 1-line display

Table 12 shows an example of a 1-line display in 8-bit

operation. The PCF2103 functions must be set by the

‘function set’ instruction prior to display. Since the DDRAM

can store data for 80 characters, the RAM can be used for

advertising displays when combined with display shift

operation.

A control byte is required with most commands

(see Table 15).

Table 11 4-bit operation, 1-line display example; using internal reset

STEP

INSTRUCTION

DISPLAY

OPERATION

power supply on (PCF2103 is initialized by

the internal reset circuit)

initialized; no display appears

function set

R/W DB7 DB6 DB5 DB4

sets to 4-bit operation; in this instance operation

is handled as 8-bit by initialization and only this

instruction completes with one write

function set

sets to 4-bit operation, selects 1-line display and

V_LCD= V₀; 4-bit operation starts from this point

and resetting is needed

display on/off control

turns on display and cursor; entire display is

blank after initialization

entry mode set

sets mode to increment the address by 1 and to

shift the cursor to the right at the time of write to

the DD/CGRAM; display is not shifted

‘write data’ to CGRAM/DDRAM

writes ‘P’; the DDRAM has already been selected

by initialization at power-on; the cursor is

incremented by 1 and shifted to the right

1998 May 11

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Table 12 8-bit operation, 1-line display example; using internal reset (character set ‘A’)

STEP

INSTRUCTION

DISPLAY

OPERATION

initialized; no display appears

power supply on (PCF2103 is initialized by the internal reset

function)

function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

sets to 8-bit operation, selects 1-line display

display mode on/off control

turns on display and cursor; entire display is blank after

initialization

entry mode set

sets mode to increment the address by 1 and to shift the

cursor to the right at the time of the write to the

DD/CGRAM; display is not shifted

‘write data’ to CGRAM/DDRAM

writes ‘P’; the DDRAM has already been selected by

initialization at power-on; the cursor is incremented by 1

and shifted to the right

‘write data’ to CGRAM/DDRAM

PH_

writes ‘H’

7 to 11

‘write data’ to CGRAM/DDRAM

PHILIPS_

HILIPS _

writes ‘S’

entry mode set

sets mode for display shift at the time of write

‘write data’ to CGRAM/DDRAM

writes space

writes ‘M’

‘write data’ to CGRAM/DDRAM

ILIPS M_

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STEP

INSTRUCTION

‘write data’ to CGRAM/DDRAM

DISPLAY

OPERATION

MICROKO

ICROKO

writes ‘O’

cursor/display shift

shifts only the cursor position to the left

writes ‘C’ correction; the display moves to the left

shifts the display and cursor to the right

shifts only the cursor to the right

writes ‘M’

cursor/display shift

‘write data’ to CGRAM/DDRAM

cursor/display shift

MICROKO

MICROCO_

cursor/display shift

‘write data’ to CGRAM/DDRAM

ICROCOM_

return home

PHILIPS M

returns both display and cursor to the original position

(address 0)

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Table 13 8-bit operation, 1-line display and icon example; using internal reset (character set ‘A’)

STEP

INSTRUCTION

DISPLAY

OPERATION

initialized; no display appears

power supply on (PCF2103 is initialized by the internal reset

function)

function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

sets to 8-bit operation, selects 1-line display

display mode on/off control

turns on display and cursor; entire display is blank after

initialization

entry mode set

sets mode to increment the address by 1 and to shift the

cursor to the right at the time of the write to the

DD/CGRAM; display is not shifted

set CGRAM address

sets the CGRAM address to position of character 0; the

CGRAM is selected

‘write data’ to CGRAM/DDRAM

writes data to CGRAM for icon even phase; icons appear

set CGRAM address

sets the CGRAM address to position of character 4; the

CGRAM is selected

‘write data’ to CGRAM/DDRAM

writes data to CGRAM for icon odd phase

function set

sets H = 1

icons blink

sets H = 0

icon control

function set

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STEP

INSTRUCTION

DISPLAY

OPERATION

set DDRAM address

sets the DDRAM address to the ﬁrst position; DDRAM is

selected

‘write data’ to CGRAM/DDRAM

writes ‘P’; the cursor is incremented by 1 and shifted to

the right

‘write data’ to CGRAM/DDRAM

PH_

writes ‘H’

17 to 20

return home

PHILIPS

returns both display and cursor to the original position

(address 0)

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Table 14 8-bit operation, 2-line display example; using internal reset

STEP

INSTRUCTION

DISPLAY

OPERATION

initialized; no display appears

power supply on (PCF2103 is initialized by the internal reset

function)

function set

sets to 8-bit operation; selects 2-line display and voltage

generator off

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

display on/off control

turns on display and cursor; entire display is blank after

initialization

entry mode set

sets mode to increment the address by 1 and to shift the

cursor to the right at the time of write to the CG/DDRAM;

display is not shifted

‘write data’ to CGRAM/DDRAM

writes ‘P’; the DDRAM has already been selected by

initialization at power-on; the cursor is incremented by 1

and shifted to the right

6 to 10

‘write data’ to CGRAM/DDRAM

writes ‘S’

PHILIPS_

set DDRAM address

sets DDRAM address to position the cursor at the head of

the 2nd line

PHILIPS

‘write data’ to CGRAM/ DDRAM

writes ‘M’

PHILIPS

14 to 19

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STEP

INSTRUCTION

‘write data’ to CGRAM/DDRAM

DISPLAY

OPERATION

writes ‘O’

PHILIPS

MICROCO_

‘write data’ to CGRAM/DDRAM

sets mode for display shift at the time of write

PHILIPS

MICROCO_

‘write data’ to CGRAM/DDRAM

writes ‘M’; display is shifted to the left; the ﬁrst and second

lines shift together

HILIPS

ICROCOM_

return home

returns both display and cursor to the original position

(address 0)

PHILIPS

MICROCOM

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Table 15 Example of I²C-bus operation; 1-line display (using internal reset, assuming SA0 = V_SS; note 1)

STEP

INSTRUCTION

DISPLAY

OPERATION

initialized; no display appears

I²C-bus start

slave address for write

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack

during the acknowledge cycle SDA will be pulled-down by the

PCF2103

send a control byte for ‘function set’

Co RS

Ack

control byte sets RS for following data bytes

function set

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

selects 1-line display; SCL pulse during acknowledge cycle

starts execution of instruction

display on/off control

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

turns on display and cursor; entire display shows character 20H

(blank in ASCII-like character sets)

entry mode set

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

sets mode to increment the address by 1 and to shift the cursor

to the right at the time of write to the DDRAM or CGRAM; display

is not shifted

I²C-bus start

for writing data to DDRAM, RS must be set to 1; therefore a

control byte is needed

slave address for write

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack

send a control byte for ‘write data’

Co RS

Ack

‘write data’ to DDRAM

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

writes ‘P’; the DDRAM has been selected at power-up; the

cursor is incremented by 1 and shifted to the right

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STEP

INSTRUCTION

‘write data’ to DDRAM

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

DISPLAY

OPERATION

writes ‘H’

PH_

12 to 15

‘write data’ to DDRAM

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

writes ‘S’

PHILIPS_

(optional I²C-bus stop) I²C-bus start + slave address

for write (as step 8)

control byte

Co RS

Ack

PHILIPS_

return home

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

sets DDRAM address 0 in address counter (also returns shifted

display to original position; DDRAM contents unchanged); this

instruction does not update the Data Register (DR)

PHILIPS

I²C-bus start

slave address for read

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack

during the acknowledge cycle the content of the DR is loaded

into the internal I²C-bus interface to be shifted out; in the

previous instruction neither a ‘set address’ nor a ‘read data’ has

been performed; therefore the content of the DR was unknown;

R/W has to be set to logic 1 while still in I²C-bus write mode

PHILIPS

control byte for read

Co RS

Ack

DDRAM content will be read from following instructions

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STEP

INSTRUCTION

DISPLAY

OPERATION

‘read data’: 8 × SCL + master acknowledge; note 2

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

8 × SCL; content loaded into interface during previous

acknowledge cycle is shifted out over SDA; MSB is DB7; during

master acknowledge content of DDRAM address 01 is loaded

into the I²C-bus interface

PHILIPS

‘read data’: 8 × SCL + master acknowledge; note 2

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

8 × SCL; code of letter ‘H’ is read ﬁrst; during master

acknowledge code of ‘I’ is loaded into the I²C-bus interface

PHILIPS

‘read data’: 8 × SCL + no master acknowledge; note 2

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

no master acknowledge; after the content of the I²C-bus

interface register is shifted out no internal action is performed;

no new data is loaded to the interface register, Data Register

(DR) is not updated, Address Counter (AC) is not incremented

and cursor is not shifted

I²C-bus stop

PHILIPS

Notes

1. X = don’t care.

2. SDA is left at high-impedance by the microcontroller during the read acknowledge.

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Table 16 Initialization by instruction, 8-bit interface (note 1)

STEP

DESCRIPTION

power-on or unknown state

wait 2 ms after V_DDrises above V_POR

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction

function set (interface is 8 bits long)

wait 2 ms

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction

function set (interface is 8 bits long)

wait more than 40 µs

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction

function set (interface is 8 bits long)

BF can be checked after the following instructions; when BF is not checked,

the waiting time between instructions is the speciﬁed instruction time

(see Table 4)

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 function set (interface is 8 bits long); specify the number of display lines

display off

clear display

entry mode set

I/D

Initialization ends

Note

1. X = don’t care.

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Table 17 Initialization by instruction, 4-bit interface; not applicable for I²C-bus operation

STEP

Power-on or unknown state

DESCRIPTION

Wait 2 ms after V_DDrises above V_POR

R/W

DB7

DB6

DB5

DB4 BF cannot be checked before this instruction

function set (interface is 8 bits long)

Wait 2 ms

R/W

DB7

DB6

DB5

DB4 BF cannot be checked before this instruction

function set (interface is 8 bits long)

Wait 40 µs

R/W

DB7

DB6

DB5

DB4 BF cannot be checked before this instruction

function set (interface is 8 bits long)

BF can be checked after the following instructions; when BF is not checked, the waiting time

between instructions is the speciﬁed instruction time (see Table 4)

R/W

DB7

DB6

DB5

DB4 function set (set interface to 4 bits long)

interface is 8 bits long

function set (interface is 4 bits long)

specify number of display lines

display off

clear display

entry mode set

I/D

Initialization ends

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

16 BONDING PAD LOCATIONS

handbook, full pagewidth

78 77 76 75 74 73 72 71 70

69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

C28(dummy)

C28

C2(dummy)

R17

C29

C30

C31

C32

C33

C34

C35

C36

C37

C38

C39

C40

C41

C42

C43

C44

C45

C46

C47

C48

C49

SCL

≈ 3.18

SDA

R/W

DB7

DB6

DB5

DB4

100

101

102

103

104

DB3

DB2

C50

DB1

C51

DB0

C52

C52(dummy)

DB0(dummy)

105

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

≈ 2.99 mm

MGL258

Fig.29 Bonding pad locations.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

Table 18 Bonding pad locations (dimensions in µm).

All x/y coordinates are referenced to centre of

chip (see Fig.29)

SYMBOL

C40

PAD

SYMBOL

PAD

1344

1262

1172

1082

992

−2

V_DD(dummy) 105

−1228

−1414

C39

C38

C37

C36

C35

C34

C33

C32

C31

C30

C29

C28

V_DD

OSC

−1048

−958

−868

−778

−688

−516

−349

−259

−169

−79

−1414

−1254

−1164

−1074

−948

178

268

358

448

V_SS

V_LCD

538

628

718

R10

R11

R12

R13

R14

R15

R16

R18

C60

C59

C58

C57

C56

C55

C54

C53

808

898

1070

1160

1250

1414

101

C28 (dummy) 51

C27 (dummy) 52

191

281

C27

C26

C25

C24

C23

C22

C21

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

371

461

551

902

641

805

731

715

821

625

911

535

1001

1091

1181

1344

445

355

C53 (dummy) 24

C52 (dummy) 25

265

175

C52

C51

C50

C49

C48

C47

C46

C45

C44

C43

C42

C41

−5

−95

−812

−185

−275

−446

−536

−626

−716

−806

−896

−722

−632

−542

−452

−362

−272

−182

−92

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

Table 19 Bump speciﬁcations

SYMBOL

PAD

PARAMETER

SPECIFICATION

UNIT

−986

1414

1303

1213

1123

1033

943

Bump variant

Type

−

−1076

−1166

−1344

1335

galvanic; pure

aurum

−

C3 (dummy)

C2 (dummy)

Bump width

Bump length

Bump height

60 ±6

90 ±6

17.5 ±5

µm

Height difference in one

die

853

Convex deformation

Pad size; aluminium

µm

763

80 × 100

673

Passivation opening CBB 46 × 76

583

Wafer thickness

Minimum pitch

380 ±25

493

403

R17

SCL

SDA

313

131

−9

−195

−289

−382

−476

−572

−668

−765

−861

−957

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

100

101

102

103

−1054

−1150

−1240

−1405

1405

DB0 (dummy) 104

Rec. Pat. C1

Rec. Pat. C2

−1335

−1340

Rec. Pat. F

−1397

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

17 DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

18 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

19 PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

1998 May 11

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2103 family

NOTES

1998 May 11

Philips Semiconductors – a worldwide company

Argentina: see South America

Middle East: see Italy

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Tel. +31 40 27 82785, Fax. +31 40 27 88399

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Fax. +43 160 101 1210

Tel. +64 9 849 4160, Fax. +64 9 849 7811

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

Norway: Box 1, Manglerud 0612, OSLO,

220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Belgium: see The Netherlands

Brazil: see South America

Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,

Tel. +359 2 689 211, Fax. +359 2 689 102

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,

Tel. +48 22 612 2831, Fax. +48 22 612 2327

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,

Tel. +1 800 234 7381

Portugal: see Spain

Romania: see Italy

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. +7 095 755 6918, Fax. +7 095 755 6919

Colombia: see South America

Czech Republic: see Austria

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. +65 350 2538, Fax. +65 251 6500

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. +45 32 88 2636, Fax. +45 31 57 0044

Slovakia: see Austria

Slovenia: see Italy

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. +358 9 615800, Fax. +358 9 61580920

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,

Tel. +27 11 470 5911, Fax. +27 11 470 5494

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

South America: Al. Vicente Pinzon, 173, 6th floor,

04547-130 SÃO PAULO, SP, Brazil,

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Tel. +55 11 821 2333, Fax. +55 11 821 2382

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Spain: Balmes 22, 08007 BARCELONA,

Tel. +30 1 4894 339/239, Fax. +30 1 4814 240

Tel. +34 93 301 6312, Fax. +34 93 301 4107

Hungary: see Austria

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,

Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,

Tel. +91 22 493 8541, Fax. +91 22 493 0966

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. +41 1 488 2741 Fax. +41 1 488 3263

Indonesia: PT Philips Development Corporation, Semiconductors Division,

Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,

Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,

Tel. +66 2 745 4090, Fax. +66 2 398 0793

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Tel. +90 212 279 2770, Fax. +90 212 282 6707

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

Tel. +1 800 234 7381

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Uruguay: see South America

Vietnam: see Singapore

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. +381 11 625 344, Fax.+381 11 635 777

For all other countries apply to: Philips Semiconductors,

Internet: http://www.semiconductors.philips.com

International Marketing & Sales Communications, Building BE-p, P.O. Box 218,

5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

SCA60

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

415106/1200/01/pp56

Date of release: 1998 May 11

Document order number: 9397 750 02649

PCF2103EU [NXP]

相关型号：

PCF2103EU/2

PCF2103EU/2/F2

PCF2103EU/F2

PCF2103FAMILY

PCF2104C

PCF2104CU

PCF2104CU/12

PCF2104CU/2

PCF2104CU/2

PCF2104CU/2

PCF2104CU/7

PCF2104CU/7