PCF210AA [NXP]
SPI Real time clock/calendar Time keeping application; SPI实时时钟/日历计时的应用
| 型号： | PCF210AA |
| 厂家： | 
NXP |
| 描述： | SPI Real time clock/calendar Time keeping application |
| 文件： | 总63页 (文件大小：828K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCF2123
SPI Real time clock/calendar
Rev. 5 — 27 April 2011
Product data sheet
1. General description
The PCF2123 is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low power
applications. Data is transferred serially via a Serial Peripheral Interface (SPI-bus) with a
maximum data rate of 6.25 Mbit/s. An alarm and timer function is also available providing
the possibility to generate a wake-up signal on an interrupt pin. An offset register allows
fine tuning of the clock.
2. Features and benefits
Real time clock provides year, month, day, weekday, hours, minutes, and seconds
based on a 32.768 kHz quartz crystal
Low backup current while running: typical 100 nA at VDD = 2.0 V and Tamb = 25 °C
Resolution: seconds to years
Watchdog functionality
Freely programmable timer and alarm with interrupt capability
Clock operating voltage: 1.1 V to 5.5 V
3 line SPI-bus with separate, but combinable data input and output
Serial interface at VDD = 1.6 V to 5.5 V
1 second or 1 minute interrupt output
Integrated oscillator load capacitors for CL = 7 pF
Internal Power-On Reset (POR)
Open-drain interrupt and clock output pins
Programmable offset register for frequency adjustment
3. Applications
Time keeping application
Battery powered devices
Metering
High duration timers
Daily alarms
Low standby power applications
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21.
PCF2123
NXP Semiconductors
SPI Real time clock/calendar
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
PCF2123BS/1
PCF2123TS/1
HVQFN16
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 3 × 3 × 0.85 mm
SOT758-1
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
PCF2123U/5GA/1
PCF2123U/10AA/1
PCF2123U/12AA/1
PCF2123U/12HA/1
wire bond die
wire bond die
WLCSP12
12 bonding pads[1]
12 bonding pads[2]
wafer level chip size package; 12 bumps[3]
wafer level chip size package; 12 bumps[3]
PCF2123U/10
PCF2123U/10
PCF2123U/12
PCF2123U/12
WLCSP12
[1] Unsawn wafer.
[2] Sawn 6 inch wafer on Film Frame Carrier (FFC) for 6 inch wafer, see Figure 37 on page 53.
[3] Sawn 6 inch wafer with gold bumps on Film Frame Carrier (FFC) for 8 inch wafer, see Figure 38 on page 53.
5. Marking
Table 2.
Marking codes
Type number
Marking code
123
PCF2123BS/1
PCF2123TS/1
PCF2123
PC2123-1
PC2123-1
PC2123-1
PC2123-1
PCF2123U/5GA/1
PCF2123U/10AA/1
PCF2123U/12AA/1
PCF2123U/12HA/1
PCF2123
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 27 April 2011
2 of 63
PCF2123
NXP Semiconductors
SPI Real time clock/calendar
6. Block diagram
OSCI
CLKOE
C
OSCI
OSCILLATOR
32.768 kHz
DIVIDER
CLOCK OUT
CLKOUT
OSCO
C
OSCO
MONITOR
OFFSET FUNCTION
Offset_register
0Dh
TIMER FUNCTION
Timer_clkout
TEST
0Eh
0Fh
V
DD
Countdown_timer
V
SS
CONTROL
Control_1
Control_2
00h
01h
POWER ON
RESET
TIME
02h
03h
04h
05h
06h
07h
08h
Seconds
Minutes
Hours
WATCH
DOG
Days
Weekdays
Months
Years
SDO
SDI
SCL
CE
SPI
INTERFACE
ALARM FUNCTION
Minute_alarm
Hour_alarm
INT
INTERRUPT
09h
0Ah
0Bh
0Ch
R
pd
Day_alarm
PCF2123
Weekday_alarm
013aaa223
Fig 1. Block diagram of PCF2123
PCF2123
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 27 April 2011
3 of 63
PCF2123
NXP Semiconductors
SPI Real time clock/calendar
7. Pinning information
7.1 Pinning
terminal 1
index area
1
2
3
4
12
11
10
9
OSCO
TEST
INT
CLKOUT
CLKOE
SCL
1
2
3
4
5
6
7
14
OSCI
OSCO
n.c.
V
DD
PCF2123BS
13
12
11
10
9
CLKOUT
CLKOE
n.c.
CE
SDI
TEST
INT
PCF2123TS
SCL
CE
SDI
001aai550
V
8
SDO
SS
Transparent top view
001aai551
For mechanical details, see Figure 30 on page 45.
Top view. For mechanical details, see Figure 31 on
page 46.
Fig 2. Pin configuration for HVQFN16 (PCF2123BS/1) Fig 3. Pin configuration for TSSOP14 (PCF2123TS/1)
6
5
4
V
DD
OSCI
7
8
CLKOUT
CLKOE
OSCO
PCF2123U
TEST
INT
9
3
2
SCL
SDI
10
11
12
CE
V
SS
1
SDO
001aai544
Viewed from active side. For mechanical details, see Figure 33 on page 48 and Figure 34 on
page 49.
Fig 4. Pin configuration for PCF2123Ux (bare die)
PCF2123
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 27 April 2011
4 of 63
PCF2123
NXP Semiconductors
SPI Real time clock/calendar
7.2 Pin description
Table 3.
Symbol Pin
HVQFN16
(PCF2123BS/1) (PCF2123TS/1) (bare die)
Pin description
Description
TSSOP14
PCF2123Ux
OSCI
OSCO
n.c.
16
1
7
8
-
oscillator input; high-impedance node; minimize wire length
between quartz and package
1
2
oscillator output; high-impedance node; minimize wire length
between quartz and package
6, 7, 14, 15
2
3, 11
4
do not connect and do not use as feed through; connect to
VDD if floating pins are not allowed
TEST
9
test pin; not user accessible; connect to VSS or leave floating
(internally pulled down)
INT
CE
3
5
6
7
8
10
11
12[2]
interrupt output (open-drain; active LOW)
chip enable input (active HIGH) with internal pull down
ground
4
5[1]
VSS
SDO
8
1
serial data output, push-pull; high-impedance when not
driving; can be connected to SDI for single wire data line
SDI
9
9
2
3
4
5
6
serial data input; may float when CE is inactive
serial clock input; may float when CE is inactive
CLKOUT enable or disable pin; enable is active HIGH
clock output (open-drain)
SCL
10
10
12
13
14
CLKOE 11
CLKOUT 12
VDD
13
supply voltage; positive or negative steps in VDD may affect
oscillator performance; recommend 100 nF decoupling close
to the device (see Figure 29)
[1] The die paddle (exposed pad) is wired to VSS and should be electrically isolated.
[2] The substrate (rear side of the die) is wired to VSS and should be electrically isolated.
PCF2123
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 27 April 2011
5 of 63
PCF2123
NXP Semiconductors
SPI Real time clock/calendar
8. Functional description
The PCF2123 contains 16 8-bit registers with an auto-incrementing address counter, an
on-chip 32.768 kHz oscillator with two integrated load capacitors, a frequency divider
which provides the source clock for the Real Time Clock (RTC), a programmable clock
output, and a 6.25 Mbit/s SPI-bus. An offset register allows fine tuning of the clock.
All 16 registers are designed as addressable 8-bit parallel registers although not all bits
are implemented.
• The first two registers (memory address 00h and 01h) are used as control registers.
• The memory addresses 02h through 08h are used as counters for the clock function
(seconds up to years). The registers Seconds, Minutes, Hours, Days, Weekdays,
Months, and Years are all coded in Binary Coded Decimal (BCD) format. When one of
the RTC registers is written or read the contents of all counters are frozen. Therefore,
faulty writing or reading of the clock and calendar during a carry condition is
prevented.
• Addresses 09h through 0Ch define the alarm condition.
• Address 0Dh defines the offset calibration.
• Address 0Eh defines the clock out and timer mode.
• Address registers 0Eh and 0Fh are used for the countdown timer function. The
countdown timer has four selectable source clocks allowing for countdown periods in
the range from 244 μs up to four hours. There are also two pre-defined timers which
can be used to generate an interrupt once per second or once per minute. These are
defined in register Control_2 (01h).
8.1 Low power operation
Minimum power operation will be achieved by reducing the number and frequency of
switching signals inside the IC, i.e., low frequency timer clocks and a low frequency
CLKOUT will result in lower operating power. A second prime consideration is the series
resistance Rs of the quartz used.
8.1.1 Power consumption with respect to quartz series resistance
The series resistance acts as a loss element. Low Rs will reduce current consumption
further.
PCF2123
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© NXP B.V. 2011. All rights reserved.
Product data sheet
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PCF2123
NXP Semiconductors
SPI Real time clock/calendar
001aai558
250
(1)
I
DD
(nA)
210
170
130
90
50
0
20
40
60
80
100
(2)
Rs (kΩ)
Configuration: CLKOUT disabled, VDD = 3 V, timer clock set to 1⁄60 Hz.
(1) IDD (nA) minimum power mode.
(2) Maximum value for RS is 100 kΩ.
Fig 5. IDD with respect to quartz RS
8.1.2 Power consumptions with respect to timer mode
Four source clocks are possible for the timer. The 4.096 kHz source clock will add the
greatest part to the power consumption. The selection of 64 Hz, 1 Hz, or 1⁄60 Hz will be
almost indistinguishable and add very little.
001aai559
400
(1)
I
DD
(nA)
300
(2)
(3)
200
100
0
0
2
4
6
V
DD
(V)
Configuration: CLKOUT disabled, quartz RS = 15 kΩ.
(1) IDD (nA) minimum power mode.
(2) Timer clock = 4 kHz.
(3) Timer clock = 64 Hz, 1 Hz, 1⁄60 Hz.
Fig 6. IDD with respect to timer clock selection
PCF2123
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 27 April 2011
7 of 63
PCF2123
NXP Semiconductors
SPI Real time clock/calendar
8.2 Register overview
16 registers are available. The time registers are encoded in the Binary Coded Decimal
(BCD) format to simplify application use. Other registers are either bit-wise or standard
binary.
Table 4.
Bit positions labelled as - are not implemented and will return a 0 when read. The bit position labelled as -- is not implemented
and will return a 0 or 1 when read. Bit positions labelled with N should always be written with logic 0[1]
Registers overview
.
Address Register name
Bit
7
6
5
4
3
2
1
0
Control and status registers
00h
01h
Control_1
Control_2
EXT_TEST
MI
N
STOP
MSF
SR
N
12_24
TF
CIE
AIE
N
SI
TI_TP
AF
TIE
Time and date registers
02h
03h
04h
Seconds
Minutes
Hours
OS
--
SECONDS (0 to 59)
MINUTES (0 to 59)
-
-
AMPM
HOURS (1 to 12) in 12 h mode
HOURS (0 to 23) in 24 h mode
DAYS (1 to 31)
05h
06h
07h
08h
Days
-
-
-
-
-
-
Weekdays
Months
Years
-
-
-
-
WEEKDAYS (0 to 6)
MONTHS (1 to 12)
YEARS (0 to 99)
Alarm registers
09h
0Ah
Minute_alarm
AE_M
MINUTE_ALARM (0 to 59)
AMPM HOUR_ALARM (1 to 12) in 12 h mode
Hour_alarm
AE_H
-
HOUR_ALARM (0 to 23) in 24 h mode
DAY_ALARM (1 to 31)
0Bh
0Ch
Day_alarm
AE_D
AE_W
-
-
Weekday_alarm
-
-
-
WEEKDAY_ALARM (0 to 6)
Offset register
0Dh
Offset_register
MODE
OFFSET[6:0]
Timer registers
0Eh
0Fh
Timer_clkout
-
COF[2:0]
TE
-
CTD[1:0]
Countdown_timer COUNTDOWN_TIMER[7:0]
[1] Except in the case of software reset, see Section 8.3.1.1.
PCF2123
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 27 April 2011
8 of 63
PCF2123
NXP Semiconductors
SPI Real time clock/calendar
8.3 Control registers
8.3.1 Register Control_1
Table 5.
Control_1 - control and status register 1 (address 00h) bit description
Bit
Symbol
Value
Description
Reference
7
EXT_TEST
0[1]
normal mode
Section 8.10
1
external clock test mode
unused
6
5
N
-
-
STOP
0[1]
the RTC source clock runs
the RTC clock is stopped;
Section 8.11
1
RTC divider chain flip-flops are
asynchronously set to logic 0;
CLKOUT at 32.768 kHz, 16.384 kHz or
8.192 kHz is still available
4
SR
0[1]
1
no software reset
initiate software reset[2];
Section 8.3.1.1
this register will always return a 0 when
read
3
2
N
-
unused
-
-
12_24
0[1]
24 hour mode is selected
12 hour mode is selected
no correction interrupt generated
1
1
CIE
0[1]
1
Section 8.9
interrupt pulses will be generated at every
correction cycle
0
N
-
unused
-
[1] Default value.
[2] For a software reset, 01011000 (58h) must be sent to register Control_1 (see Section 8.3.1.1).
8.3.1.1 Reset
A reset is automatically generated at power-on. A reset can also be initiated with the
software reset command. It is generally recommended to make a software reset after
power-on.
A software reset can be initiated by setting the bits 6, 4 and 3 in register Control_1 logic 1
and all other bits logic 0 by sending the bit sequence 01011000 (58h), see Figure 7. If this
bit sequence is not correct, the software reset instruction will be ignored to protect the
device from accidently being reset. When sending the software instruction, the other bits
are not written.
PCF2123
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© NXP B.V. 2011. All rights reserved.
Product data sheet
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PCF2123
NXP Semiconductors
SPI Real time clock/calendar
R/W
addr 00
software reset 58
HEX
HEX
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
1
0
0
0
0
0
1
0
1
1
0
0
0
SCL
CE
(1)
internal
reset signal
001aai562
(1) When CE is inactive, the interface is reset.
Fig 7. Software reset command
After reset, the following mode is entered:
• 32.768 kHz on pin CLKOUT active
• 24 hour mode is selected
• Offset register is set to 0
• No alarms set
• Timer disabled
• No interrupts enabled
Table 6.
Register reset values
Bits labeled as - are not implemented. Bits labeled as X are undefined at power-on and unchanged
by subsequent resets.
Address Register name
Bit
7
0
0
1
-
6
0
0
X
X
-
5
0
0
X
X
X
X
-
4
0
0
X
X
X
X
-
3
0
0
X
X
X
X
-
2
1
0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Control_1
Control_2
Seconds
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
Minutes
Hours
-
Days
-
-
Weekdays
Months
-
-
-
-
-
X
X
X
X
X
-
X
X
X
X
X
-
Years
X
1
1
1
1
0
-
X
X
-
X
X
X
X
-
Minute_alarm
Hour_alarm
Day_alarm
Weekday_alarm
Offset_register
Timer_clkout
Countdown_timer
-
-
0
0
X
0
0
X
0
0
X
0
0
X
-
1
1
X
X
X
X
PCF2123
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 27 April 2011
10 of 63
PCF2123
NXP Semiconductors
SPI Real time clock/calendar
8.3.2 Register Control_2
Table 7.
Control_2 - control and status register 2 (address 01h) bits description
Bit
Symbol
Value
0[1]
1
Description
Reference
7
MI
minute interrupt is disabled
minute interrupt is enabled
second interrupt is disabled
second interrupt is enabled
no minute or second interrupt generated
Section 8.6.3
6
5
SI
0[1]
1
MSF
0[1]
1
flag set when minute or second interrupt
generated;
flag must be cleared to clear interrupt
when TI_IP = 0
4
3
TI_TP
AF
0[1]
1
0[1]
interrupt pin follows timer flags
interrupt pin generates a pulse
no alarm interrupt generated
Section 8.7.2
Section 8.5.5
1
flag set when alarm triggered;
flag must be cleared to clear interrupt
no countdown timer interrupt generated
2
TF
0[1]
1
Section 8.6.4
flag set when countdown timer interrupt
generated;
flag must be cleared to clear interrupt
when TI_IP = 0
1
0
AIE
TIE
0[1]
1
0[1]
no interrupt generated from the alarm flag Section 8.7.3
interrupt generated when alarm flag set
no interrupt generated from the countdown Section 8.7.2
timer
1
interrupt generated by the countdown timer
[1] Default value.
PCF2123
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 27 April 2011
11 of 63
PCF2123
NXP Semiconductors
SPI Real time clock/calendar
8.4 Time and date function
The majority of the registers are coded in the Binary Coded Decimal (BCD) format. BCD is
used to simplify application use. An example is shown for the seconds in Table 9.
8.4.1 Register Seconds
Table 8.
Bit
Seconds - seconds register (address 02h) bit description
Symbol
Value
Place value Description
7
OS
0
1[1]
-
-
clock integrity is guaranteed
clock integrity is not guaranteed;
oscillator has stopped or has
been interrupted
6 to 4 SECONDS
3 to 0
0 to 5
0 to 9
ten’s place actual seconds coded in BCD
format, see Table 9
unit place
[1] Default value.
Table 9.
Seconds coded in BCD format
Seconds value Upper-digit (ten’s place)
(decimal)
Digit (unit place)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
01
02
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
1
:
0
1
0
:
09
10
:
0
0
:
0
0
:
0
0
:
0
1
:
1
0
:
0
0
:
0
0
:
1
0
:
58
59
0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
1
8.4.1.1 OS flag
The PCF2123 includes a flag (OS in register Seconds, see Table 8) which is set whenever
the oscillator is stopped (see Figure 8 and Figure 9). The flag will remain set until cleared
by software. If the flag cannot be cleared, then the PCF2123 oscillator is not running. This
method can be used to monitor the oscillator and to determine if the supply voltage has
reduced to the point where oscillation fails.
main supply
V
DD
battery operation
V
OSC(MIN)
t
001aai561
Fig 8. OS set by failing VDD
PCF2123
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Product data sheet
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PCF2123
NXP Semiconductors
SPI Real time clock/calendar
OS = 1 and flag can not be cleared
OS = 1 and flag can be cleared
V
DD
oscillation
OS flag
OS flag set when
oscillation stops
OS flag cleared
by software
t
oscillation now stable
001aai553
Fig 9. OS flag
The oscillator may be stopped, for example, by grounding one of the oscillator pins, OSCI
or OSCO. The oscillator is also considered to be stopped during the time between
power-on and stable crystal resonance. This time may be in the range of 200 ms to 2 s
depending on crystal type, temperature and supply voltage. At power-on the OS flag is
always set.
8.4.2 Register Minutes
Table 10. Minutes - minutes register (address 03h) bit description
Bit
Symbol
Value
-
Place value Description
- unused
7
-
6 to 4 MINUTES
3 to 0
0 to 5
0 to 9
ten’s place actual minutes coded in BCD
format
unit place
8.4.3 Register Hours
Table 11. Hours - hours register (address 04h) bit description
Bit
Symbol
Value
Place value Description
7 to 6
-
-
-
unused
12 hour mode[1]
5
AMPM
0
-
-
indicates AM
indicates PM
1
4
HOURS
0 to 1
0 to 9
ten’s place actual hours in 12 hour mode
coded in BCD format
3 to 0
unit place
24 hour mode[1]
5 to 4 HOURS
3 to 0
0 to 2
0 to 9
ten’s place actual hours in 24 hour mode
coded in BCD format
unit place
[1] Hour mode is set by the 12_24 bit in register Control_1.
PCF2123
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© NXP B.V. 2011. All rights reserved.
Product data sheet
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PCF2123
NXP Semiconductors
SPI Real time clock/calendar
8.4.4 Register Days
Table 12. Days - days register (address 05h) bit description
Bit
Symbol
Value
-
Place value Description
- unused
7 to 6
-
5 to 4 DAYS[1]
0 to 3
0 to 9
ten’s place actual day coded in BCD format
unit place
3 to 0
[1] The PCF2123 compensates for leap years by adding a 29th day to February if the year counter contains a
value which is exactly divisible by 4, including the year 00.
8.4.5 Register Weekdays
Table 13. Weekdays - weekdays register (address 06h) bit description
Bit
Symbol
Value
-
Description
7 to 3
-
unused
2 to 0 WEEKDAYS
0 to 6
actual weekday values, see Table 14
Table 14. Weekday assignments
Day[1]
Bit
2
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
Sunday
0
Monday
Tuesday
Wednesday
Thursday
Friday
0
0
0
1
1
Saturday
1
[1] Definition may be re-assigned by the user.
8.4.6 Register Months
Table 15. Months - months register (address 07h) bit description
Bit
Symbol
-
Value
-
Place value Description
- unused
7 to 5
4
MONTHS
0 to 1
0 to 9
ten’s place actual month coded in BCD
format, see Table 16
3 to 0
unit place
PCF2123
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© NXP B.V. 2011. All rights reserved.
Product data sheet
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NXP Semiconductors
SPI Real time clock/calendar
Table 16. Month assignments in BCD format
Month
Upper-digit
(ten’s place)
Digit (unit place)
Bit 4
0
Bit 3
0
Bit 2
Bit 1
0
Bit 0
1
January
February
March
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
April
0
0
0
0
May
0
0
0
1
June
0
0
1
0
July
0
0
1
1
August
September
October
November
December
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
1
0
1
0
8.4.7 Register Years
Table 17. Years - years register (08h) bit description
Bit
Symbol
Value
0 to 9
0 to 9
Place value Description
7 to 4 YEARS
3 to 0
ten’s place actual year coded in BCD format
unit place
8.4.8 Setting and reading the time
Figure 10 shows the data flow and data dependencies starting from the 1 Hz clock tick.
1 Hz tick
SECONDS
MINUTES
12_24 hour mode
HOURS
DAYS
LEAP YEAR
CALCULATION
WEEKDAY
MONTHS
YEARS
001aaf901
Fig 10. Data flow of the time function
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During read/write operations, the time counting circuits (memory locations 02h through
08h) are blocked.
This prevents
• Faulty reading of the clock and calendar during a carry condition
• Incrementing the time registers during the read cycle
After this read/write access is completed, the time circuit is released again and any
pending request to increment the time counters that occurred during the read/write access
is serviced. A maximum of 1 request can be stored; therefore, all accesses must be
completed within 1 second (see Figure 11).
t < 1 s
data bus
COMMAND
DATA
DATA
DATA
chip enable
013aaa222
Fig 11. Access time for read/write operations
As a consequence of this method, it is very important to make a read or write access in
one go, that is, setting or reading seconds through to years should be made in one single
access. Failing to comply with this method could result in the time becoming corrupted.
As an example, if the time (seconds through to hours) is set in one access and then in a
second access the date is set, it is possible that the time may increment between the two
accesses. A similar problem exists when reading. A roll over may occur between reads
thus giving the minutes from one moment and the hours from the next. Therefore it is
advised to read all time and date registers in one access.
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8.5 Alarm function
When one or more of these registers are loaded with a valid minute, hour, day, or
weekday and its corresponding alarm enable bit (AE_x) is logic 0, then that information
will be compared with the current minute, hour, day, and weekday.
8.5.1 Register Minute_alarm
Table 18. Minute_alarm - minute alarm register (address 09h) bit description
Bit
Symbol
Value
Place value Description
7
AE_M
0
1[1]
-
-
minute alarm is enabled
minute alarm is disabled
6 to 4 MINUTE_ALARM
3 to 0
0 to 5
0 to 9
ten’s place minute alarm information coded in
BCD format
unit place
[1] Default value.
8.5.2 Register Hour_alarm
Table 19. Hour_alarm - hour alarm register (address 0Ah) bit description
Bit
Symbol
Value
Place value Description
7
AE_H
0
1[1]
-
-
-
hour alarm is enabled
hour alarm is disabled
unused
6
-
-
12 hour mode[2]
5
AMPM
0
-
-
indicates AM
indicates PM
1
4
HOUR_ALARM
0 to 1
0 to 9
ten’s place hour alarm information coded in
BCD format when in 12 hour
3 to 0
unit place
mode
24 hour mode[2]
5 to 4 HOUR_ALARM
3 to 0
0 to 2
0 to 9
ten’s place hour alarm information coded in
BCD format when in 24 hour
unit place
mode
[1] Default value.
[2] Hour mode is set by the 12_24 bit in register Control_1.
8.5.3 Register Day_alarm
Table 20. Day_alarm - day alarm register (address 0Bh) bit description
Bit
Symbol
Value
Place value Description
7
AE_D
0
1[1]
-
-
-
day alarm is enabled
day alarm is disabled
unused
6
-
-
5 to 4 DAY_ALARM
3 to 0
0 to 3
0 to 9
ten’s place day alarm information coded in
BCD format
unit place
[1] Default value.
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8.5.4 Register Weekday_alarm
Table 21. Weekday_alarm - weekday alarm register (address 0Ch) bit description
Bit
Symbol
Value
Description
7
AE_W
0
weekday alarm is enabled
weekday alarm is disabled
unused
1[1]
-
6 to 3
-
2 to 0 WEEKDAY_ALARM
0 to 6
weekday alarm information coded in BCD
format
[1] Default value.
8.5.5 Alarm flag
By clearing the MSB, AE_x (Alarm Enable), of one or more of the alarm registers the
corresponding alarm condition(s) are active. When an alarm occurs, AF (register
Control_2, see Table 7) is set logic 1. The asserted AF can be used to generate an
interrupt (INT). The AF is cleared using the interface.
check now signal
example
AE_M
AE_M = 1
MINUTE ALARM
=
1
MINUTE TIME
0
AE_H
HOUR ALARM
=
HOUR TIME
(1)
set alarm flag AF
AE_D
DAY ALARM
=
DAY TIME
AE_W
WEEKDAY ALARM
=
013aaa088
WEEKDAY TIME
(1) Only when all enabled alarm settings are matching.
It’s only on increment to a matched case that the alarm flag is set, see Section 8.5.5.
Fig 12. Alarm function block diagram
The registers at addresses 09h through 0Ch contain alarm information. When one or
more of these registers is loaded with minute, hour, day, or weekday, and its
corresponding Alarm Enable bit (AE_x) is logic 0, then that information is compared with
the current minute, hour, day, and weekday. When all enabled comparisons first match,
the Alarm Flag (AF) is set logic 1.
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The generation of interrupts from the alarm function is controlled via bit AIE (register
Control_2, see Table 7). If bit AIE is enabled, the INT pin follows the condition of bit AF. AF
will remain set until cleared by the interface. Once AF has been cleared, it will only be set
again when the time increments to match the alarm condition once more. Alarm registers
which have their AE_x bit logic 1 are ignored.
Generation of interrupts from the alarm function is described in Section 8.7.3.
minutes counter
minute alarm
AF
44
45
45
46
INT when AIE = 1
001aaf903
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 13. Alarm flag timing
Figure 13, Table 22, and Table 23 show an example for clearing bit AF, but leaving bit
MSF and bit TF unaffected. The flags are cleared by a write command, therefore bits 7, 6,
4, 1 and 0 must be written with their previous values. Repeatedly re-writing these bits has
no influence on the functional behavior.
To prevent the timer flags being overwritten while clearing bit AF, logic AND is performed
during a write access. A flag is cleared by writing logic 0 whilst a flag is not cleared by
writing logic 1. Writing logic 1 will result in the flag value remaining unchanged.
Table 22. Flag location in register Control_2
Register
Bit
7
6
5
4
3
2
1
0
Control_2
-
-
MSF
-
AF
TF
-
-
Table 23 shows what instruction must be sent to clear bit AF. In this example, bit MSF and
bit TF are unaffected.
Table 23. Example to clear only AF (bit 3) in register Control_2
Register
Bit
7
6
5
4
3
2
1
0
Control_2
-
-
1
-
0
1
-
-
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8.6 Timer functions
The countdown timer has four selectable source clocks allowing for countdown periods in
the range from 244 μs to 4 h 15 min. There are also two pre-defined timers which can be
used to generate an interrupt once per second or once per minute. For periods greater
than 4 hours, the alarm function can be used. Registers 01h, 0Eh and 0Fh are used to
control the timer function and output.
8.6.1 Register Timer_clkout
Table 24. Timer_clkout - timer control register (address 0Eh) bit description
Bit
Symbol
Value
Description
Reference
-
7
-
-
unused
[1]
6 to 4 COF[2:0]
CLKOUT control
Section 8.8
Section 8.6.4
3
TE
0
countdown timer is disabled
countdown timer is enabled
unused
1
2
-
-
1 to 0 CTD[1:0]
00
01
10
11[2]
4.096 kHz countdown timer source clock
64 Hz countdown timer source clock
1 Hz countdown timer source clock
1
⁄60 Hz countdown timer source clock
[1] Values of COF[2:0] see Table 35.
[2] Default value.
8.6.2 Register Countdown_timer
Table 25. Countdown_timer - countdown timer register (address 0Ah) bit description
Bit
Symbol
Value
Description
Reference
7 to 0 COUNTDOWN_TIMER[7:0]
0h to FFh
countdown period in seconds:
Section 8.6.4
n
CountdownPeriod =
--------------------------------------------------------------
SourceClockFrequency
where n is the countdown value
8.6.3 Minute and second interrupt
The minute and second interrupts (bits MI and SI) are pre-defined timers for generating
periodic interrupts. The timers can be enabled independently from one another. However,
a minute interrupt enabled on top of a second interrupt will not be distinguishable since it
will occur at the same time; see Figure 14.
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seconds counter
minutes counter
58
59
59
11
00
12
00
01
INT when SI enabled
MSF when SI enabled
INT when only MI enabled
MSF when only MI enabled
001aaf905
In this example, TI_TP is set to logic 1 resulting in 1⁄64 Hz wide interrupt pulse and the MSF flag is
not cleared after an interrupt.
Fig 14. INT example for MI and SI
Table 26. Effect of bits MI and SI on INT generation
Minute interrupt (bit MI) Second interrupt (bit SI) Result
0
1
0
1
0
0
1
1
no interrupt generated
an interrupt once per minute
an interrupt once per second
an interrupt once per second
The minute and second flag (bit MSF) is set logic 1 when either the seconds or the
minutes counter increments according to the currently enabled interrupt. The flag can be
read and cleared by the interface. The status of bit MSF does not affect the INT pulse
generation. If the MSF flag is not cleared prior to the next coming interrupt period, an INT
pulse will still be generated.
The purpose of the flag is to allow the controlling system to interrogate the PCF2123 and
identify the source of the interrupt, i.e., minute or second, countdown timer or alarm.
Table 27. Effect of MI and SI on MSF
Minute interrupt (bit MI) Second interrupt (bit SI) Result
0
1
0
0
MSF never set
MSF set when minutes counter
increments
0
1
1
1
MSF set when seconds counter
increments
MSF set when seconds counter
increments
The duration of both of these timers will be affected by the register Offset_register (see
Section 8.9). Only when the Offset_register has the value 00h the periods will be
consistent.
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8.6.4 Countdown timer function
The 8-bit countdown timer at address 0Fh is controlled by the register Timer_clkout at
address 0Eh. The register Timer_clkout selects one of 4 source clock frequencies for the
timer (4.096 kHz, 64 Hz, 1 Hz, or 1⁄60 Hz) and enables or disables the timer.
Table 28. Bits CTD0 and CTD1 for timer frequency selection and countdown timer
durations
CTD[1:0] Timer source clock Delay
frequency[1]
Minimum timer duration
n = 1
Maximum timer duration
n = 255
00
01
10
11
4.096 kHz
64 Hz
1 Hz[2]
244 μs
15.625 ms
1 s
62.256 ms
3.984 s
255 s
1
⁄
60 Hz[2]
60 s
4 h 15 min
[1] When not in use, CTD must be set to 1⁄60 Hz for power saving.
[2] Time periods can be affected by correction pulses.
Remark: Note that all timings which are generated from the 32.768 kHz oscillator are
based on the assumption that there is 0 ppm deviation. Deviation in oscillator frequency
will result in deviation in timings. This is not applicable to interface timing.
The timer counts down from a software-loaded 8-bit binary value, n. Loading the counter
with 0 stops the timer. Values from 1 to 255 are valid. When the counter reaches 1, the
countdown timer flag (bit TF) will be set and the counter automatically re-loads and starts
the next timer period. Reading the timer will return the current value of the countdown
counter (see Figure 15).
countdown value, n
xx
03
timer source clock
countdown counter
xx
03
02
01
03
02
01
03
02
01
03
TE
TF
INT
n
n
duration of first timer period after
enable may range from n − 1 to n + 1
001aaf906
In this example it is assumed that the timer flag is cleared before the next countdown period
expires and that the pin INT is set to pulsed mode.
Fig 15. General countdown timer behavior
If a new value of n is written before the end of the current timer period, then this value will
take immediate effect. NXP does not recommend changing n without first disabling the
counter (by setting bit TE = 0). The update of n is asynchronous to the timer clock,
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therefore changing it without setting bit TE = 0 may result in a corrupted value loaded into
the countdown counter which results in an undetermined countdown period for the first
period. The countdown value n will, however, be correctly stored and correctly loaded on
subsequent timer periods.
When the countdown timer flag is set, an interrupt signal on INT will be generated
provided that this mode is enabled. See Section 8.7.2 for details on how the interrupt can
be controlled.
When starting the timer for the first time, the first period will have an uncertainty which is a
result of the enable instruction being generated from the interface clock which is
asynchronous from the timer source clock. Subsequent timer periods will have no such
delay. The amount of delay for the first timer period will depend on the chosen source
clock, see Table 29.
Table 29. First period delay for timer counter value n
Timer source clock
4.096 kHz
Minimum timer period
Maximum timer period
n + 1
n
64 Hz
n
n + 1
1 Hz
(n − 1) + 1⁄64 Hz
(n − 1) + 1⁄64 Hz
n + 1⁄64 Hz
n + 1⁄64 Hz
1
⁄60 Hz
At the end of every countdown, the timer sets the countdown timer flag (bit TF). Bit TF
may only be cleared by software. The asserted bit TF can be used to generate an
interrupt (INT). The interrupt may be generated as a pulsed signal every countdown
period or as a permanently active signal which follows the condition of bit TF. Bit TI_TP is
used to control this mode selection and the interrupt output may be disabled with bit TIE,
see Table 7.
When reading the timer, the current countdown value is returned and not the initial
value n. Since it is not possible to freeze the countdown timer counter during read back, it
is recommended to read the register twice and check for consistent results.
Timer source clock frequency selection of 1 Hz and 1⁄60 Hz will be affected by the
Offset_register. The duration of a program period will vary according to when the offset is
initiated. For example, if a 100 s timer is set using the 1 Hz clock as source, then some
100 s periods will contain correction pulses and therefor be longer or shorter depending
on the setting of the Offset_register. See Section 8.9 to understand the operation of the
Offset_register.
8.6.5 Timer flags
When a minute or second interrupt occurs, bit MSF is set logic 1. Similarly, at the end of a
timer countdown or alarm event, bit TF or AF are set logic 1. These bits maintain their
value until overwritten by software. If both countdown timer and minute or second
interrupts are required in the application, the source of the interrupt can be determined by
reading these bits. To prevent one flag being overwritten while clearing another a logical
AND is performed during a write access. A flag is cleared by writing logic 0 whilst a flag is
not cleared by writing logic 1. Writing logic 1 will result in the flag value remaining
unchanged.
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Three examples are given for clearing the flags. Clearing the flags is made by a write
command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values.
Repeatedly re-writing these bits has no influence on the functional behavior.
Table 30. Flag location in register Control_2
Register
Bit
7
6
5
4
3
2
1
0
Control_2
-
-
MSF
-
AF
TF
-
-
Table 31, Table 32, and Table 33 show what instruction must be sent to clear the
appropriate flag.
Table 31. Example to clear only TF (bit 2) in register Control_2
Register
Bit
7
6
5
4
3
2
1
0
Control_2
-
-
1
-
1
0
-
-
Table 32. Example to clear only MSF (bit 5) in register Control_2
Register
Bit
7
6
5
4
3
2
1
0
Control_2
-
-
0
-
1
1
-
-
Table 33. Example to clear both TF and MSF (bit 2 and bit 5) in register Control_2
Register
Bit
7
6
5
4
3
2
1
0
Control_2
-
-
0
-
1
0
-
-
Clearing the alarm flag (bit AF) operates in exactly the same way, see Section 8.5.5.
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8.7 Interrupt output
An active LOW interrupt signal is available at pin INT. Operation is controlled via the bits
of register Control_2. Interrupts may be sourced from four places: second and minute
timer, countdown timer, alarm function or offset function.
With bit TI_TP, the timer generated interrupts can be configured to either generate a pulse
or to follow the status of the interrupt flags (bits TF and MSF). Correction interrupt pulses
are always 1⁄128 second long. Alarm interrupts always follow the condition of AF.
SI
to interface:
read MSF
MSF: MINUTE
SECOND FLAG
SI MI
SECONDS COUNTER
MINUTES COUNTER
SET
0
1
PULSE
GENERATOR 1
CLEAR
TRIGGER
CLEAR
MI
from interface:
clear MSF
INT
TI_TP
TE
to interface:
read TF
TF: TIMER
TIE
COUNTDOWN COUNTER
SET
0
1
PULSE
GENERATOR 2
CLEAR
TRIGGER
CLEAR
E.G.AIE
from interface:
0
1
clear TF
AIE
CIE
to interface:
read AF
AF: ALARM
FLAG
set alarm
flag, AF
SET
CLEAR
from interface:
clear AF
PULSE
GENERATOR 3
offset circuit: add/substract
1/64 Hz pulse
TRIGGER
CLEAR
from interface:
set CIE
001aai555
When bits SI, MI, TIE, AIE, and CIE are all disabled, pin INT will remain high-impedance.
Fig 16. Interrupt scheme
Remark: Note that the interrupts from the four sources are wired-OR, meaning they will
mask one another (see Figure 16).
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8.7.1 Minute and second interrupts
The pulse generator for the minute and second interrupt operates from an internal 64 Hz
clock and consequently generates a pulse of 1⁄64 second in duration.
If the MSF flag is cleared before the end of the INT pulse, then the INT pulse is shortened.
This allows the source of a system interrupt to be cleared immediately it is serviced, i.e.,
the system does not have to wait for the completion of the pulse before continuing; see
Figure 17. Instructions for clearing MSF are given in Section 8.6.5.
seconds counter
MSF
58
59
INT
(1)
SCL
8th clock
instruction
CLEAR INSTRUCTION
001aaf908
(1) Indicates normal duration of INT pulse (bit TI_TP = 1)
Fig 17. Example of shortening the INT pulse by clearing the MSF flag
The timing shown for clearing bit MSF in Figure 17 is also valid for the non-pulsed
interrupt mode i.e. when bit TI_TP = 0, INT may be shortened by setting both MI and SI or
MSF to logic 0.
8.7.2 Countdown timer interrupts
The generation of interrupts from the countdown timer is controlled via bit TIE.
The pulse generator for the countdown timer interrupt also uses an internal clock, but this
time it is dependent on the selected source clock for the countdown timer and on the
countdown value n. As a consequence, the width of the interrupt pulse varies (see
Table 34).
Table 34. INT operation (bit TI_TP = 1)
Source clock (Hz)
INT period (s)
n = 1[1]
n > 1
1
1
4096
64
⁄
⁄
8192
4096
1
1
⁄
⁄
128
64
1
1
1
⁄
⁄
64
64
1
1
1
⁄
⁄
⁄
60
64
64
[1] n = loaded countdown value. Timer stopped when n = 0.
If the TF flag is cleared before the end of the INT pulse, then the INT pulse is shortened.
This allows the source of a system interrupt to be cleared immediately it is serviced, i.e.,
the system does not have to wait for the completion of the pulse before continuing (see
Figure 18). Instructions for clearing MSF can be found in Section 8.6.5.
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countdown counter
01
n
CDTF
INT
(1)
SCL
8th clock
instruction
CLEAR INSTRUCTION
001aaf909
(1) Indicates normal duration of INT pulse (bit TI_TP = 1).
Fig 18. Example of shortening the INT pulse by clearing the TF flag
The timing shown for clearing bit TF in Figure 18 is also valid for the non-pulsed interrupt
mode, i.e., when bit TI_TP = 0; INT may be shortened by setting bit TIE to logic 0.
8.7.3 Alarm interrupts
The generation of interrupts from the alarm function is controlled via bit AIE (see Table 7).
If bit AIE is enabled, the INT pin follows the condition of bit AF. Clearing bit AF will
immediately clear INT. No pulse generation is possible for alarm interrupts (see
Figure 19).
minute counter
minute alarm
AF
44
45
45
INT
SCL
8th clock
instruction
CLEAR INSTRUCTION
001aaf910
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 19. AF timing
8.7.3.1 Correction pulse interrupts
Interrupt pulses generated by correction events can be shortened by writing logic 1 to bit
CIE in register Control_1.
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8.8 Clock output
A programmable square wave is available at pin CLKOUT. Operation is controlled by the
COF[2:0] bits in the register Timer_clkout. Frequencies of 32.768 kHz (default) down to
1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge
pump, or for calibration of the oscillator.
Pin CLKOUT is an open-drain output and enabled at power-on. When disabled the output
is high-impedance.
The duty cycle of the selected clock is not controlled. However, due to the nature of the
clock generation, all will be 50 : 50 except the 32.768 kHz frequencies.
The STOP bit function can also affect the CLKOUT signal, depending on the selected
frequency. When the STOP bit is set logic 1, the CLKOUT pin will generate a continuous
LOW for those frequencies that can be stopped. For more details of the STOP bit function
see Section 8.11.
Table 35. CLKOUT frequency selection
Bits COF[2:0] CLKOUT frequency (Hz) Typical duty cycle[1]
Effect of STOP bit
no effect
000
001
010
011
100
101
110
111
32768
60 : 40 to 40 : 60
50 : 50
50 : 50
50 : 50
50 : 50
50 : 50
50 : 50
-
16384
no effect
8192
no effect
4096
CLKOUT = LOW
CLKOUT = LOW
CLKOUT = LOW
CLKOUT = LOW
-
2048
1024
1[2]
CLKOUT = high-Z
[1] Duty cycle definition: % HIGH-level time : % LOW-level time.
[2] 1 Hz clock pulses will be affected by offset correction pulses.
8.8.1 CLKOE pin
The CLKOE pin can be used to block the CLKOUT function and force the CLKOUT pin to
a high-impedance state. The effect is the same as setting COF[2:0] = 111.
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SPI Real time clock/calendar
8.9 Offset register
The PCF2123 incorporates an offset register (address 0Dh) which can be used to
implement several functions, such as:
• Ageing adjustment
• Temperature compensation
• Accuracy tuning
The offset is made once every two hours in the normal mode, or once every hour in the
course mode. Each LSB will introduce an offset of 2.17 ppm for normal mode and
4.34 ppm for course mode. The values of 2.17 ppm and 4.34 ppm are based on a nominal
32.768 kHz clock. The offset value is coded in two’s complement giving a range of
+63 LSB to −64 LSB.
Table 36. Register Offset_register
OFFSET[6:0]
Offset value in
decimal
Offset value in ppm
Normal mode
MODE = 0
Course mode
MODE = 1
0 1 1 1 1 1 1
0 1 1 1 1 1 0
:
+63
+62
:
+136.71
+134.54
:
+273.42
+269.08
:
0 0 0 0 0 1 0
0 0 0 0 0 0 1
0 0 0 0 0 0 0
1 1 1 1 1 1 1
1 1 1 1 1 1 0
:
+2
+1
0[1]
−1
−2
:
+4.34
+2.17
0
+8.68
+4.34
0
−2.17
−4.34
:
−4.34
−8.68
:
1 0 0 0 0 0 1
1 0 0 0 0 0 0
−63
−64
−136.71
−138.88
−273.42
−277.76
[1] Default mode.
The correction is made by adding or subtracting 64 Hz clock correction pulses, thereby
changing the period of a single second.
Table 37. Example of converting the offset in ppm to seconds
Offset in ppm
Seconds per
Day
Week
1.31
Month
5.69
Year
68.2
136
2.17
4.34
0.187
0.375
2.62
11.4
In normal mode, the correction is triggered once per two hours and then correction pulses
are applied once per minute until the programmed correction values have been
implement.
In course mode, the correction is triggered once per hour and then correction pulses are
applied once per minute up to a maximum of 60 minutes. When correction values greater
than 60 are used, additional correction pulses are made in the 59th minute (see Table 38).
PCF2123
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SPI Real time clock/calendar
Table 38. Correction pulses for course mode
Correction value
Hour:Minute[1]
Correction pulses on INT per
minute[2]
+1 or −1
+2 or −2
02:00
1
0
02:01 to
02:59
02:00
02:01
1
1
0
02:02 to
02:59
+3 or −3
02:00
02:01
02:02
1
1
1
0
02:03 to
02:59
:
:
:
+59 or −59
02:00 to
02:58
1
02:59
0
1
+60 or −60
+61 or −61
02:00 to
02:59
02:00 to
02:58
1
02:59
2
1
+62 or −62
+63 or −63
−64
02:00 to
02:58
02:59
3
1
02:00 to
02:58
02:59
4
1
02:00 to
02:58
02:59
5
[1] Example is given in a time range from 2:00 to 2:59.
[2] Correction INT pulses are 1⁄128 s wide. For multiple pulses they are repeated at 1⁄64 s interval.
It is possible to monitor when correction pulses are applied. The correction interrupt
enable mode (bit CIE) will generate a 1⁄128 second pulse on INT for every correction
applied. In the case where multiple correction pulses are applied, a 1⁄128 second interrupt
pulse will be generated and repeated every 1⁄64 seconds.
Correction is applied to the 1 Hz clock. Any timer or clock output using a frequency of 1 Hz
or below will also be affected by the correction pulses.
PCF2123
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NXP Semiconductors
SPI Real time clock/calendar
Table 39. Effect of correction pulses
Frequency (Hz)
Effect of correction
CLKOUT
32768
no effect
no effect
no effect
no effect
no effect
no effect
effected
16384
8192
4096
2048
1024
1
Time source clock
4096
64
no effect
no effect
effected
effected
1
1
⁄
60
PCF2123
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SPI Real time clock/calendar
8.10 External clock test mode
A test mode is available which allows for on-board testing. In this mode it is possible to set
up test conditions and control the operation of the RTC.
The test mode is entered by setting bit EXT_TEST in register Control_1. Then
pin CLKOUT becomes an input. The test mode replaces the internal clock signal with the
signal applied to pin CLKOUT.
The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a
maximum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided
down to 1 Hz by a 26 divide chain called a prescaler. The prescaler can be set into a
known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0. (STOP
must be cleared before the prescaler can operate again.)
From a stop condition, the first 1 second increment will take place after 32 positive edges
on pin CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment.
Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When
entering the test mode, no assumption as to the state of the prescaler can be made.
Operation example:
1. Set EXT_TEST test mode (register Control_1, bit EXT_TEST = 1).
2. Set STOP (Control_1, bit STOP = 1).
3. Clear STOP (Control_1, bit STOP = 0).
4. Set time registers to desired value.
5. Apply 32 clock pulses to pin CLKOUT.
6. Read time registers to see the first change.
7. Apply 64 clock pulses to pin CLKOUT.
8. Read time registers to see the second change.
Repeat 7 and 8 for additional increments.
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NXP Semiconductors
SPI Real time clock/calendar
8.11 STOP bit function
The function of the STOP bit is to allow for accurate starting of the time circuits. The STOP
bit function will cause the upper part of the prescaler (F2 to F14) to be held in reset and
thus no 1 Hz ticks will be generated. The time circuits can then be set and will not
increment until the STOP bit is released (see Figure 21 and Table 40).
The STOP bit function will not affect the output of 32.768 kHz, 16.384 kHz, or 8.192 kHz
(see Section 8.8).
OSCILLATOR STOP
oscillator stop flag
DETECTOR
F
0
F
1
F
F
F
14
2
13
OSCILLATOR
1 Hz tick
stop
RESET
RESET
RESET
1 Hz
1024 Hz
CLKOUT source
8192 Hz
16384 Hz
001aai556
Fig 20. STOP bit functional diagram
The lower two stages of the prescaler (F0 and F1) are not reset and because the SPI-bus
is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be
between 0 and one 8.192 kHz cycle (see Figure 21).
8192 Hz
stop released
0 μs to 122 μs
001aaf912
Fig 21. STOP bit release timing
The first increment of the time circuits is between 0.499878 s and 0.500000 s after STOP
bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset
(see Table 40).
PCF2123
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NXP Semiconductors
SPI Real time clock/calendar
Table 40. First increment of time circuits after STOP bit release
Bit
Prescaler bits[1]
1 Hz tick
Time
Comment
STOP
F0F1-F2 to F14
hh:mm:ss
Clock is running normally
0
01-0 0001 1101 0100
12:45:12
prescaler counting normally
STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally
1
XX-0 0000 0000 0000
12:45:12
prescaler is reset; time circuits are frozen
New time is set by user
1
XX-0 0000 0000 0000
08:00:00
prescaler is reset; time circuits are frozen
STOP bit is released by user
0
XX-0 0000 0000 0000
XX-1 0000 0000 0000
XX-0 1000 0000 0000
XX-1 1000 0000 0000
:
08:00:00
08:00:00
08:00:00
08:00:00
:
prescaler is now running
-
-
-
:
11-1 1111 1111 1110
00-0 0000 0000 0001
10-0 0000 0000 0001
:
08:00:00
08:00:01
08:00:01
:
-
0 to 1 transition of F14 increments the time circuits
-
:
11-1 1111 1111 1111
00-0 0000 0000 0000
10-0 0000 0000 0000
:
08:00:01
08:00:01
08:00:01
:
-
-
-
:
11-1 1111 1111 1110
00-0 0000 0000 0001
08:00:01
08:00:02
-
0 to 1 transition of F14 increments the time circuits
013aaa352
[1] F0 is clocked at 32.768 kHz.
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SPI Real time clock/calendar
9. 3-line serial interface
Data transfer to and from the device is made via a 3-wire SPI-bus (see Table 41). The
data lines for input and output are split. The data input and output lines can be connected
together to facilitate a bidirectional data bus. The chip enable signal is used to identify the
transmitted data. Each data transfer is a byte, with the Most Significant Bit (MSB) sent first
(see Figure 23).
Table 41. Serial interface
Symbol Function
Description
CE
chip enable input
when LOW, the interface is reset; pull-down resistor
included; active input may be higher than VDD, but may not
be wired permanently HIGH
SCL
SDI
serial clock input
serial data input
serial data output
when CE is LOW, this input may float; input may be higher
than VDD
when CE is LOW, input may float; input may be higher than
VDD; input data is sampled on the rising edge of SCL
SDO
push-pull output; drives from VSS to VDD; output data is
changed on the falling edge of SCL; will be high-Z when not
driving; may be connected directly to SDI
SDI
SDI
SDO
SDO
two wire mode
single wire mode
001aai560
Fig 22. SDI, SDO configurations
The transmission is controlled by the active HIGH chip enable signal CE. The first byte
transmitted is the command byte. Subsequent bytes will be either data to be written or
data to be read. Data is sampled on the rising edge of the clock and transferred internally
on the falling edge.
data bus
COMMAND
DATA
DATA
DATA
chip enable
001aaf914
Fig 23. Data transfer overview
The command byte defines the address of the first register to be accessed and the
read/write mode. The address counter will auto increment after every access and will
rollover to zero after the last register is accessed. The read/write bit (R/W) defines if the
following bytes will be read or write information.
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SPI Real time clock/calendar
Table 42. Command byte definition
Bit
Symbol
Value
Description
7
R/W
data read or data write selection
write data
0
1
read data
6 to 4 SA
3 to 0 RA
001
subaddress; other codes will cause the device
to ignore data transfer
0h to Fh
register address range
In Figure 24, the register Seconds is set to 45 seconds and the register Minutes is set to
10 minutes.
R/W
addr 02
seconds data 45
minutes data 10
BCD
HEX
BCD
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
SCL
SDI
CE
address
counter
xx
02
03
04
001aaf915
Fig 24. Serial bus write example
R/W
addr 07
months data 11
years data 06
BCD
HEX
BCD
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
1
0
0
1
0
1
1
1
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
0
SCL
SDI
SDO
CE
address
counter
xx
07
08
09
001aaf916
Fig 25. Serial bus read example
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SPI Real time clock/calendar
In Figure 25, the Months and Years registers are read. In this example, pins SDI and SDO
are not connected together. For this configuration, it is important that pin SDI is never left
floating. It must always be driven either HIGH or LOW. If pin SDI is left open, high IDD
currents may result. Short transition periods in the order of 200 ns will not cause any
problems.
9.1 Interface watchdog timer
During read/write operations, the time counting circuits are frozen. To prevent a situation
where the accessing device becomes locked and does not clear the interface by setting
pin CE LOW, the PCF2123 has a built in watchdog timer. Should the interface be active
for more than 1 s from the time a valid subaddress is transmitted, then the PCF2123 will
automatically clear the interface and allow the time counting circuits to continue counting.
CE must return LOW once more before a new data transfer can be executed.
t
< 1 s
w(CE)
CE
data
valid sub-address data data data
WD timer running
WD timer
time
counters
running
time counters frozen
running
001aai563
a. Correct data transfer: read or write
1 s < t
< 2 s
w(CE)
CE
data transfer fail
data
valid sub-address data data data
WD timer
WD timer running
time counters frozen
WD trips
time
counters
running
running
001aai564
b. Incorrect data transfer: read or write
Fig 26. Interface watchdog timer
The watchdog is implemented to prevent the excessive loss of time due to interface
access failure e.g. if main power is removed from a battery backed-up system during an
interface access.
Each time the watchdog period is exceeded, 1 s will be lost from the time counters. The
watchdog will trigger between 1 s and 2 s after receiving a valid subaddress.
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SPI Real time clock/calendar
10. Internal circuitry
PCF2123
V
DD
OSCI
OSCO
TEST
INT
CLKOE
CLKOUT
SCL
SDI
CE
SDO
V
SS
001aai552
Fig 27. Device diode protection diagram of PCF2123
PCF2123
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SPI Real time clock/calendar
11. Limiting values
Table 43. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IDD
Parameter
Conditions
Min
−0.5
−50
−0.5
−0.5
−10
−10
-
Max
+6.5
+50
Unit
V
[1]
supply voltage
supply current
input voltage
mA
V
[1]
[1]
VI
+6.5
+6.5
+10
VO
output voltage
input current
V
II
mA
mA
mW
V
IO
output current
total power dissipation
+10
Ptot
VESD
300
[2]
electrostatic discharge
voltage
HBM
-
±3000
[3]
[4]
Ilu
latch-up current
-
200
mA
°C
Tstg
Tamb
storage temperature
ambient temperature
−65
−40
+150
+85
operating device
°C
[1] With respect to VSS
.
[2] Pass level; Human Body Model (HBM) according to Ref. 8 “JESD22-A114”
[3] Pass level; latch-up testing, according to Ref. 9 “JESD78” at maximum ambient temperature (Tamb(max)).
[4] According to the NXP store and transport requirements (see Ref. 11 “NX3-00092”) the devices have to be
stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products
deviant conditions are described in that document.
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SPI Real time clock/calendar
12. Static characteristics
Table 44. Static characteristics
VDD = 1.1 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 15 kΩ; CL = 7 pF; unless otherwise
specified.
Symbol
Supplies
VDD
Parameter
Conditions
Min
Typ
Max
Unit
[1]
supply voltage
for clock data integrity;
SPI-bus inactive
1.1
-
5.5
V
Tamb = 25 °C
-
0.9
-
-
V
V
SPI-bus active
SPI-bus active
fSCL = 4.5 MHz;
1.6
5.5
IDD
supply current
-
-
250
30
400
80
μA
μA
VDD = 5 V
fSCL = 1.0 MHz;
VDD = 3 V
[2]
SPI-bus inactive;
CLKOUT disabled
Tamb = 25 °C;
VDD = 2.0 V
-
-
-
100
110
120
-
-
-
nA
nA
nA
Tamb = 25 °C;
VDD = 3.0 V
Tamb = 25 °C;
VDD = 5.0 V
[2]
SPI-bus inactive;
CLKOUT disabled;
Tamb = −40 °C to +85 °C
VDD = 2.0 V
VDD = 3.0 V
VDD = 5.0 V
-
-
-
-
-
-
330
350
380
nA
nA
nA
SPI-bus inactive;
CLKOUT enabled at 32 kHz;
Tamb = 25 °C
VDD = 2.0 V
VDD = 3.0 V
VDD = 5.0 V
-
-
-
260
340
520
-
-
-
nA
nA
nA
SPI-bus inactive;
CLKOUT enabled at 32 kHz;
Tamb = −40 °C to +85 °C
VDD = 2.0 V
VDD = 3.0 V
VDD = 5.0 V
-
-
-
-
-
-
450
550
750
nA
nA
nA
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SPI Real time clock/calendar
Table 44. Static characteristics …continued
VDD = 1.1 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 15 kΩ; CL = 7 pF; unless otherwise
specified.
Symbol
Inputs
VIL
Parameter
Conditions
Min
Typ
Max
Unit
LOW-level input voltage
HIGH-level input voltage
input voltage
-
-
-
-
0.3VDD
-
V
V
V
VIH
0.7VDD
−0.5
VI
on pins CE, SDI, SCL, OSCI,
CLKOE, CLKOUT
+5.5
[3]
ILI
input leakage current
VI = VDD or VSS on pins SDI,
SCL, OSCI, CLKOE, CLKOUT
-
0
-
μA
VI = VSS on pin CE
on pin CE
−1
-
0
-
μA
kΩ
pF
Rpd
Ci
pull-down resistance
input capacitance
240
-
550
7
[4]
[5]
on pins SDI, SCL, CLKOE and
CE
-
Outputs
VO
output voltage
on pins CLKOUT and INT
on pin OSCO
−0.5
−0.5
−0.5
0.8VDD
VSS
-
-
-
-
-
-
+5.5
V
V
V
V
V
V
+5.5
on pin SDO
VDD + 0.5
VDD
VOH
VOL
HIGH-level output voltage on pin SDO
LOW-level output voltage on pin SDO
0.2VDD
0.4
on pins CLKOUT and INT;
VSS
VDD = 5 V;
IOL = 1.5 mA
IOH
HIGH-level output current output source current;
VOH = 4.6 V;
1.5
1.5
-
-
-
-
mA
mA
VDD = 5 V on pin SDO
IOL
LOW-level output current output sink current;
VOL = 0.4 V;
VDD = 5 V on pins INT, SDO
and CLKOUT
[3]
[6]
ILO
output leakage current
VO = VDD or VSS
-
0
7
-
μA
CL(itg)
integrated load
capacitance
on pins OSCO and OSCI
3.3
14
pF
Rs
series resistance
-
-
100
kΩ
[1] For reliable oscillator start at power-on: VDD = VDD(min) + 0.3 V.
[2] Timer source clock = 1⁄60 Hz, level of pins CE, SDI, and SCL is VDD or VSS
[3] In case of an ESD event, the value may increase slightly.
[4] Implicit by design.
.
[5] Refers to external pull-up voltage.
(COSCI ⋅ COSCO
)
[6] Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series: CL(itg)
=
.
-------------------------------------------
(COSCI + COSCO
)
PCF2123
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SPI Real time clock/calendar
13. Dynamic characteristics
Table 45. SPI-bus characteristics
VSS = 0 V; Tamb = −40 °C to +85 °C. All timing values are valid within the operating supply voltage and temperature range and
referenced to VIL and VIH with an input voltage swing of VSS to VDD
.
Symbol Parameter Conditions VDD = 1.6 V VDD = 2.4 V VDD = 3.3 V VDD = 5.0 V Unit
Min
Max Min
Max Min
Max Min
Max
Timing characteristics (see Figure 28)
fclk(SCL)
tSCL
SCL clock frequency
SCL time
-
2.9
-
4.54
-
5.71
-
8.0
MHz
ns
ns
ns
ns
ns
ns
ns
ns
s
345
90
200
-
-
220
50
120
-
-
175
45
95
-
-
125
40
70
-
-
tclk(H)
tclk(L)
tr
clock HIGH time
clock LOW time
rise time
-
-
-
-
-
-
-
-
for SCL signal
for SCL signal
100
100
50
50
tf
fall time
-
100
-
100
-
50
-
50
tsu(CE)
th(CE)
trec(CE)
tw(CE)
CE set-up time
CE hold time
CE recovery time
CE pulse width
40
40
30
-
-
35
30
25
-
-
30
25
20
-
-
25
15
15
-
-
-
-
-
-
-
-
-
-
measured after valid
subaddress is
received
0.99
0.99
0.99
0.99
tsu
set-up time
hold time
set-up time for SDI
data
10
-
5
-
3
-
2
-
ns
th
hold time for SDI data 25
-
10
-
-
8
-
-
5
-
-
ns
ns
ns
td(R)SDO
tdis(SDO)
SDO read delay time bus load = 50 pF
-
-
190
70
108
45
85
40
60
27
SDO disable time
no load value; bus will
be held up by bus
capacitance; use RC
time constant with
application values
-
-
-
tt(SDI-SDO) transition time from
SDI to SDO
to avoid bus conflict
0
-
0
-
0
-
0
-
ns
PCF2123
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SPI Real time clock/calendar
t
t
w(CE)
CE
SCL
t
su(CE)
t
t
rec(CE)
t
r
clk(H)
t
t
f
t
h(CE)
clk(L)
80%
SCL
20%
WRITE
t
su
t
h
SDI
R/W
SA2
RA0
b7
b6
b0
Hi Z
SDO
READ
SDI
b7
b6
b0
t
t(SDI-SDO)
t
t
dis(SDO)
d(R)SDO
Hi Z
SDO
b7
b6
b0
001aai554
Fig 28. SPI-bus timing
PCF2123
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14. Application information
1 F
supercapacitor
100 nF
V
CLKOE CLKOUT
INT
CE
DD
OSCI
SCL
SDI
PCF2123
OSCO
SDO
V
SS
001aai557
A 1 farad super capacitor combined with a low VF diode can be used as a standby or back-up
supply. With the RTC in its minimum power configuration i.e. timer off and CLKOUT off, the RTC
may operate for weeks.
Fig 29. Typical application diagram
PCF2123
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15. Package outline
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3 x 3 x 0.85 mm
SOT758-1
B
A
D
terminal 1
index area
A
E
A
1
c
detail X
e
C
y
1
1/2 e
y
v
M
C
M
C
A B
C
1
e
b
w
5
8
L
4
9
e
e
E
2
h
1/2 e
12
1
16
13
terminal 1
index area
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
e
2
D
D
E
L
y
1
v
w
y
1
h
1
h
max.
0.05 0.30
0.00 0.18
3.1 1.75
2.9 1.45
3.1
2.9
1.75
1.45
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
1.5
1.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-03-25
02-10-21
SOT758-1
- - -
MO-220
- - -
Fig 30. Package outline SOT758-1 (HVQFN16) of PCF2123BS/1
PCF2123
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SPI Real time clock/calendar
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 31. Package outline SOT402-1 (TSSOP14) of PCF2123TS/1
PCF2123
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NXP Semiconductors
SPI Real time clock/calendar
HVQFN16
a. SOT758-1 (HVQFN16) of PCF2123BS/1
PCF8885TS
b. SOT402-1 (TSSOP14) of PCF2123TS/1
Fig 32. Three dimensional package drawings of PCF2123BS/1 and PCF2123TS/1
PCF2123
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SPI Real time clock/calendar
16. Bare die outline
Wire bond die; 12 bonding pads
PCF2123U/10
D
A
6
5
4
7
8
P
P
3
4
x
E
9
0
3
2
10
11
12
0
y
P
P
2
1
1
X
e
D
detail X
0
1 mm
scale
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
08-07-24
11-04-06
PCF2123U/10
Fig 33. Bare die outline PCF2123U/10 of PCF2123U/5GA/1 and PCF2123U/10AA/1 (for dimensions see Table 46)
Table 46. Dimensions of PCF2123U/10
Original dimensions are in mm.
[3]
[4]
[3]
[4]
Unit (mm) A[1]
D[2]
E[2]
eD
P1
P2
P3
P4
PCF2123U/5GA/1
nom
PCF2123U/10AA/1
nom 0.20
0.20
1.492
1.449
1.296
0.09
0.081
0.09
0.09
0.081
0.081
1.492
1.449
1.296
0.09
0.081
[1] Nominal die thickness. Compare with wafer thickness given in Table 50.
[2] Dimension includes saw lane.
[3] P1 and P3: pad size.
[4] P2 and P4: passivation opening.
PCF2123
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NXP Semiconductors
SPI Real time clock/calendar
WLCSP12: wafer level chip size package; 12 bumps.
PCF2123U/12
D
6
5
4
7
PC2123-1
8
E
9
10
11
12
x 0
0
y
3
2
e
1
Y
e
X
P
P
3
4
A
1
P
P
A
2
2
A
1
detail Y
detail X
0
0.5
scale
1 mm
pcf2123u_12_do
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
- - -
JEITA
- - -
10-07-13
11-04-06
PCF2123U/12
Fig 34. Bare die outline PCF2123U/12 of PCF2123U/12AA/1 and PCF2123U/12HA/1 (for dimensions see Table 47)
PCF2123
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SPI Real time clock/calendar
Table 47. Dimensions of PCF2123U/12
Original dimensions are in mm.
[1]
[3]
[4]
[3]
[4]
Unit (mm) A[1]
A1
A2
D[2]
E[2]
e
P1
P2
P3
P4
PCF2123U/12AA
max
nom
min
-
0.018
-
-
-
1.296
-
-
0.084
-
0.084
0.081
0.078
0.22
-
0.015 0.2
1.492 1.449
0.09
-
0.081 0.09
0.012
-
-
-
-
-
-
0.198
0.078
-
-
PCF2123U/12HA
max
nom
min
-
0.018
1.296
-
-
0.084
0.084
0.081
0.078
0.17
-
0.015 0.15
0.012
1.492 1.449
0.09
-
0.081 0.09
0.078
-
-
-
0.198
-
[1] Nominal die thickness. Compare with wafer thickness given in Table 50.
[2] Dimension includes saw lane.
[3] P1 and P3: pad size.
[4] P2 and P4: bump size.
Table 48. Bump locations of all PCF2123U types
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip; see Figure 33 and Figure 34.
Symbol
Bump
Coordinates
x
y
SDO
SDI
1
648.0
−575.0
−377.0
−179.0
171.2
369.2
625.7
639.0
421.9
−25.9
−223.9
−441.0
−639.0
2
648.0
SCL
3
648.0
CLKOE
CLKOUT
VDD
4
648.0
5
648.0
6
648.0
OSCI
OSCO
TEST
INT
7
−648.0
−648.0
−648.0
−648.0
−648.0
−648.0
8
9
10
11
12
CE
VSS
PCF2123
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Table 49. Alignment mark dimension and location of all PCF2123U types
Coordinates
x
y
Location[1]
693
Dimension[2]
−516.2
13 μm
16 μm
[1] The x/y coordinates of the alignment mark location represent the position of the REF point (see Figure 35)
with respect to the center (x/y = 0) of the chip; see Figure 33 and Figure 34.
[2] The x/y values of the dimensions represent the extensions of the alignment mark in direction of the
coordinate axis (see Figure 35).
REF
y
x
013aaa231
Fig 35. Alignment mark
PCF2123
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SPI Real time clock/calendar
17. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
18. Packing information
1.492 mm
(1)
~18 μm
1
1
1.449 mm
45 μm
~18 μm
Saw lane
X
1
1
70 μm
detail X
straight edge
of the wafer
013aaa232
(1) Die marking code.
Seal ring plus gap to active circuit ~18 μm.
Fig 36. PCF2123Ux wafer information
Table 50. PCF2123Ux wafer information
Type number
Wafer thickness (μm) Wafer diameter
Marking of bad die
wafer mapping[1]
inking
PCF2123U/5GA/1
PCF2123U/10AA/1
PCF2123U/12AA/1
PCF2123U/12HA/1
687
200
200
150
6 inch
6 inch
6 inch
6 inch
wafer mapping[1]
inking
[1] Wafer mapping information will be distributed to customer’s ftp server.
PCF2123
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SPI Real time clock/calendar
214.50 mm
73.68 mm 71.79 mm
+0
1.2
mm
−0.1
metal frame
0.25
straight edge
of the wafer
214.50 mm ∅ 193.50 mm
plastic film
013aaa350
Fig 37. Film Frame Carrier (FFC) for 6 inch wafer (PCF2123U/10AA/1)
276 mm
60.2 mm
63.5 mm
2.6 mm
plastic frame
0.3
straight edge
of the wafer
276 mm
∅ 250 mm
plastic film
013aaa351
Fig 38. Film Frame Carrier (FFC) for 8 inch wafer (PCF2123U/12AA/1 and PCF2123U/12HA/1)
PCF2123
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SPI Real time clock/calendar
19. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
19.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
19.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
19.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCF2123
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SPI Real time clock/calendar
19.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 39) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 51 and 52
Table 51. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 52. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 39.
PCF2123
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SPI Real time clock/calendar
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 39. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCF2123
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SPI Real time clock/calendar
20. Footprint information for reflow soldering
Footprint information for reflow soldering of HVQFN16 package
SOT758-1
Hx
Gx
D
P
0.025
0.025
C
(0.105)
SPx
SPy
nSPx
Hy Gy
SLy By
Ay
nSPy
SPx tot
SLx
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
occupied area
nSPx nSPy
1
1
Dimensions in mm
Ax
P
Ay
Bx
By
C
D
SLx
SLy
SPx tot
0.650
SPy tot
0.650
SPx
SPy
Gx
Gy
Hx
Hy
0.500 4.000 4.000 2.200 2.200 0.900 0.240 1.500 1.500
0.650 0.650 3.300 3.300 4.250 4.250
07-05-07
Issue date
sot758-1_fr
09-06-15
Fig 40. Footprint information for reflow soldering of SOT758-1 (HVQFN16) package of PCF2123BS/1
PCF2123
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SPI Real time clock/calendar
Footprint information for reflow soldering of TSSOP14 package
SOT402-1
Hx
Gx
P2
(0.125)
(0.125)
Hy Gy
By Ay
C
D2 (4x)
P1
D1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650 0.750 7.200 4.500 1.350 0.400 0.600 4.950 5.300 5.800 7.450
sot402-1_fr
Fig 41. Footprint information for reflow soldering of SOT402-1 (TSSOP14) package of PCF2123TS/1
PCF2123
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NXP Semiconductors
SPI Real time clock/calendar
21. Abbreviations
Table 53. Abbreviations
Acronym
CMOS
BCD
ESD
FFC
Description
Complementary Metal Oxide Semiconductor
Binary Coded Decimal
ElectroStatic Discharge
Film Frame Carrier
HBM
LSB
Human Body Model
Least Significant Bit
MM
Machine Model
MOS
MSB
MSL
PCB
RTC
Metal Oxide Semiconductor
Most Significant Bit
Moisture Sensitivity Level
Printed-Circuit Board
Real Time Clock
SMD
SPI
Surface Mount Device
Serial Peripheral Interface
PCF2123
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22. References
[1] AN10365 — Surface mount reflow soldering description
[2] AN10366 — HVQFN application information
[3] AN10706 — Handling bare die
[4] AN10853 — Handling precautions of ESD sensitive devices
[5] IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[6] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[7] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[8] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[9] JESD78 — IC Latch-Up Test
[10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[11] NX3-00092 — NXP store and transport requirements
[12] SNV-FA-01-02 — Marking Formats Integrated Circuits
23. Revision history
Table 54. Revision history
Document ID
PCF2123 v.5
Modifications:
Release date
20110427
Data sheet status
Change notice
Supersedes
Product data sheet
-
PCF2123 v.4
• Added product type PCF2123U/5GA/1
• Adjusted the bare die outline drawings
• Added 3d package drawings
• Added footprint information
PCF2123 v.4
PCF2123 v.3
PCF2123_2
PCF2123_1
20101222
20101005
20091204
20081119
Product data sheet
Product data sheet
Product data sheet
Product data sheet
-
-
-
-
PCF2123 v.3
PCF2123_2
PCF2123_1
-
PCF2123
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24. Legal information
24.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
24.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
24.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
PCF2123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 27 April 2011
61 of 63
PCF2123
NXP Semiconductors
SPI Real time clock/calendar
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
24.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
25. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCF2123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 27 April 2011
62 of 63
PCF2123
NXP Semiconductors
SPI Real time clock/calendar
26. Contents
1
2
3
4
5
6
General description. . . . . . . . . . . . . . . . . . . . . . 1
8.8
8.8.1
8.9
8.10
8.11
Clock output. . . . . . . . . . . . . . . . . . . . . . . . . . 28
CLKOE pin. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Offset register . . . . . . . . . . . . . . . . . . . . . . . . 29
External clock test mode . . . . . . . . . . . . . . . . 32
STOP bit function. . . . . . . . . . . . . . . . . . . . . . 33
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
9
3-line serial interface . . . . . . . . . . . . . . . . . . . 35
Interface watchdog timer . . . . . . . . . . . . . . . . 37
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 38
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 39
Static characteristics . . . . . . . . . . . . . . . . . . . 40
Dynamic characteristics. . . . . . . . . . . . . . . . . 42
Application information . . . . . . . . . . . . . . . . . 44
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 45
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 48
Handling information . . . . . . . . . . . . . . . . . . . 52
Packing information . . . . . . . . . . . . . . . . . . . . 52
9.1
10
11
12
13
14
15
16
17
18
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
8
8.1
8.1.1
Functional description . . . . . . . . . . . . . . . . . . . 6
Low power operation . . . . . . . . . . . . . . . . . . . . 6
Power consumption with respect to
quartz series resistance . . . . . . . . . . . . . . . . . . 6
Power consumptions with respect to
8.1.2
timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Register overview. . . . . . . . . . . . . . . . . . . . . . . 8
Control registers . . . . . . . . . . . . . . . . . . . . . . . . 9
Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 9
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Register Control_2 . . . . . . . . . . . . . . . . . . . . . 11
Time and date function . . . . . . . . . . . . . . . . . . 12
Register Seconds . . . . . . . . . . . . . . . . . . . . . . 12
OS flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 13
Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 13
Register Days. . . . . . . . . . . . . . . . . . . . . . . . . 14
Register Weekdays. . . . . . . . . . . . . . . . . . . . . 14
Register Months . . . . . . . . . . . . . . . . . . . . . . . 14
Register Years . . . . . . . . . . . . . . . . . . . . . . . . 15
Setting and reading the time. . . . . . . . . . . . . . 15
Alarm function. . . . . . . . . . . . . . . . . . . . . . . . . 17
Register Minute_alarm . . . . . . . . . . . . . . . . . . 17
Register Hour_alarm . . . . . . . . . . . . . . . . . . . 17
Register Day_alarm . . . . . . . . . . . . . . . . . . . . 17
Register Weekday_alarm . . . . . . . . . . . . . . . . 18
Alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Timer functions . . . . . . . . . . . . . . . . . . . . . . . . 20
Register Timer_clkout. . . . . . . . . . . . . . . . . . . 20
Register Countdown_timer . . . . . . . . . . . . . . . 20
Minute and second interrupt. . . . . . . . . . . . . . 20
Countdown timer function. . . . . . . . . . . . . . . . 22
Timer flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 25
Minute and second interrupts . . . . . . . . . . . . . 26
Countdown timer interrupts. . . . . . . . . . . . . . . 26
Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 27
Correction pulse interrupts . . . . . . . . . . . . . . . 27
8.2
8.3
8.3.1
8.3.1.1
8.3.2
8.4
19
Soldering of SMD packages. . . . . . . . . . . . . . 54
Introduction to soldering. . . . . . . . . . . . . . . . . 54
Wave and reflow soldering. . . . . . . . . . . . . . . 54
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 54
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 55
19.1
19.2
19.3
19.4
8.4.1
8.4.1.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.7
8.7.1
8.7.2
8.7.3
8.7.3.1
20
21
22
23
Footprint information for reflow soldering. . 57
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 59
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Revision history . . . . . . . . . . . . . . . . . . . . . . . 60
24
Legal information . . . . . . . . . . . . . . . . . . . . . . 61
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 61
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 62
24.1
24.2
24.3
24.4
25
26
Contact information . . . . . . . . . . . . . . . . . . . . 62
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 April 2011
Document identifier: PCF2123
相关型号：
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