PCF2116AHZ [NXP]

LCD controller/drivers; LCD控制器/驱动器


型号：	PCF2116AHZ
厂家：	NXP
描述：	LCD controller/drivers LCD控制器/驱动器驱动器控制器 CD
文件：	总64页 (文件大小：410K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

PCF2116 family

LCD controller/drivers

1997 Apr 07

Product speciﬁcation

Supersedes data of 1996 Oct 25

File under Integrated Circuits, IC12

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

CONTENTS

9.3

9.4

9.5

9.6

9.7

9.8

9.9

9.10

9.11

Entry mode set

Display on/off control

Cursor/display shift

Function set

Set CGRAM address

Set DDRAM address

Read busy flag and address

Write data to CGRAM or DDRAM

Read data from CGRAM or DDRAM

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

Packages

3.1

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING

INTERFACE TO MICROCONTROLLER

(PARALLEL INTERFACE)

PIN FUNCTIONS

INTERFACE TO MICROCONTROLLER

(I²C-BUS INTERFACE)

Characteristics of the I²C-bus

Bit transfer

7.1

7.2

7.3

RS: register select (parallel control)

R/W: read/write (parallel control)

E: data bus clock

11.1

11.2

11.3

11.4

11.5

11.6

7.4

7.5

7.6

7.7

7.8

7.9

DB0 to DB7: data bus

C1 to C60: column driver outputs

R1 to R32: row driver outputs

VLCD: LCD power supply

V0: VLCD control input

OSC: oscillator

START and STOP conditions

System configuration

Acknowledge

I²C-bus protocol

18.1

LIMITING VALUES

7.10

7.11

7.12

7.13

SCL: serial clock line

SDA: serial data line

SA0: address pin

T1: test pad

HANDLING

DC CHARACTERISTICS

DC CHARACTERISTICS (PCF2116K)

AC CHARACTERISTICS

TIMING CHARACTERISTICS

APPLICATION INFORMATION

FUNCTIONAL DESCRIPTION

8.1

LCD supply voltage generator, PCF2114x and

PCF2116x

8.2

8.3

8.4

8.5

LCD supply voltage generator, PCF2116K

Character generator ROM (CGROM)

LCD bias voltage generator

Oscillator

8-bit operation, 1-line display using internal

reset

4-bit operation, 1-line display using internal

reset

8-bit operation, 2-line display

I²C operation, 1-line display

Initializing by instruction

18.2

8.6

External clock

18.3

18.4

18.5

8.7

Power-on reset

8.8

Registers

8.9

Busy Flag

BONDING PAD LOCATIONS

PACKAGE OUTLINE

8.10

8.11

8.12

8.13

8.14

8.15

8.16

8.17

Address Counter (AC)

Display data RAM (DDRAM)

Character generator ROM (CGROM)

Character generator RAM (CGRAM)

Cursor control circuit

SOLDERING

DEFINITIONS

Timing generator

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I²C COMPONENTS

LCD row and column drivers

Programming MUX 1 : 16 displays with the

PCF2114x

8.18

Programming MUX 1 : 32 displays with the

PCF2114x

8.19

Reset function

INSTRUCTIONS

9.1

9.2

Clear display

Return home

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

FEATURES

GENERAL DESCRIPTION

• Single chip LCD controller/driver

The PCF2116 family of LCD controller/drivers consists of

the PCF2116x, the PCF2114x and the PCF2116K.

The term ‘PCF2116’ is used to refer to all devices for

common information. Specific information is given in

separate paragraphs.

• 1 or 2-line display of up to 24 characters per line, or

2 or 4 lines of up to 12 characters per line

• 5 × 7 character format plus cursor; 5 × 8 for kana

(Japanese syllabary) and user defined symbols

The ‘x’ in ‘PCF2116x’ and ‘PCF2114x’ represents a

specific letter code for a character set in the character

generator ROM (CGROM). The different character sets

currently available are specified by the letters A, C, and G

(see Figs 8 to 10). Other character sets are available on

request.

• On-chip:

– generation of LCD supply voltage (external supply

also possible)

– generation of intermediate LCD bias voltages

– oscillator requires no external components (external

clock also possible)

The PCF2116 is a low-power CMOS LCD controller and

driver, designed to drive a split screen dot matrix LCD

display of 1 or 2 lines by 24 characters or 2 or 4 lines by

12 characters with 5 × 8 dot format. All necessary

functions for the display are provided in a single chip,

including on-chip generation of LCD bias voltages,

resulting in a minimum of external components and lower

system power consumption. The chip contains a character

generator and displays alphanumeric and kana

• Display data RAM: 80 characters

• Character generator ROM: 240 characters

• Character generator RAM: 16 characters

• 4 or 8-bit parallel bus or 2-wire I²C-bus interface

• CMOS/TTL compatible

• 32 row, 60 column outputs

• MUX rates 1 : 32 and 1 : 16

(Japanese) characters. The PCF2116 interfaces to most

microcontrollers via a 4 or 8-bit bus or via the 2-wire

I²C-bus. To allow partial V_DDshutdown the ESD protection

system of the SCL and SDA pins does not use a diode

• Uses common 11 code instruction set

• Logic supply voltage range, V_DD− V_SS: 2.5 to 6 V

• Display supply voltage range, V_DD− V_LCD: 3.5 to 9 V

• Low power consumption

connected to V_DD

The PCF2116K differs from the other members of the

family in that:

• I²C-bus address: 011101 SA0.

• V_LCD/V_OPgeneration is different (see Section 8.1)

• It is available with character set C only (see Fig.9).

APPLICATIONS

• Telecom equipment

• Portable instruments

• Point-of-sale terminals.

ORDERING INFORMATION

TYPE

PACKAGE

NUMBER⁽¹⁾

NAME

DESCRIPTION

VERSION

PCF2116xU/10

−

chip on flexible film carrier

−

PCF2114xU/10

PCF2116xU/12

PCF2114xU/12

PCF2116xHZ

−

chip with bumps on flexible film carrier

−

LQFP128 plastic low profile quad flat package; 128 leads; body 14 × 20 × 1.4 mm

SOT425-1

Note

1. The letter ‘x’ in the type number represents the letter of the required built-in character set: A, C or G.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

BLOCK DIAGRAM

handbook, full pagewidth

C1 to C60

R1 to R32

84 to 77, 115 to 122

68, 65 to 38

35 to 5

76 to 69, 123 to 128,

1 and 4

COLUMN DRIVERS

ROW DRIVERS

BIAS

VOLTAGE

GENERATOR

SHIFT REGISTER

32-BIT

93, 95, 97

DATA LATCHES

LCD

GENERATOR

SHIFT REGISTER

5 x 12-bit

PCF2116

CURSOR + DATA CONTROL

104, 106

109, 112

CHARACTER

GENERATOR

ROM

102

GENERATOR

RAM

OSCILLATOR

OSC

(CGRAM)

(CGROM)

240

CHARACTERS

111

TIMING

GENERATOR

DISPLAY DATA RAM

(DDRAM) 80 CHARACTERS

DISPLAY

ADDRESS

COUNTER

ADDRESS

COUNTER (AC)

POWER - ON

RESET

INSTRUCTION

DECODER

DATA

BUSY

FLAG

INSTRUCTION

I/O BUFFER

105, 103,

98, 96

94, 91,

89, 87

108

110

R/W

113

SCL

SDA

107

SA0

MGA797 - 1

DB0 to DB3 DB4 to DB7

Fig.1 Block diagram (pin numbers for LQFP128 package).

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

PINNING

SYMBOL

LQFP128

FFC PAD

TYPE

DESCRIPTION

LCD row driver output

R31

2 and 3

−

n.c.

−

not connected

R32

−

LCD row driver output

C60 to C30

n.c.

5 to 35

36 and 37

38 to 65

66 and 67

29 to 59

LCD column driver outputs 60 to 30

not connected

−

C29 to C2

n.c.

60 to 87

−

LCD column driver outputs 29 to 2

not connected

−

LCD column driver output 1

LCD row driver outputs

R24 to R17

R8 to R1

n.c.

69 to 76

77 to 84

85 and 86

89 to 96

97 to 104

LCD row driver outputs

−

105

106

107

108

109

110

111

112

113

114

115

116

−

not connected

DB7

I/O

1 bit of 8-bit bidirectional data bus

I²C-bus serial clock input

1 bit of 8-bit bidirectional data bus

I²C-bus serial data input/output

1 bit of 8-bit bidirectional data bus

control input for V_LCD

SCL

DB6

I/O

SDA

DB5

V₀

V_LCD1

DB4

I/O

−

LCD supply voltage input/output 1

1 bit of 8-bit bidirectional data bus

LCD supply voltage input/output 2

1 bit of 8-bit bidirectional data bus

LCD supply voltage input/output 3

1 bit of 8-bit bidirectional data bus

not connected

V_LCD2

DB3

V_LCD3

DB2

n.c.

99 to 101

102

OSC

DB1

oscillator/external clock input

1 bit of 8-bit bidirectional data bus

supply voltage 2

103

I/O

V_DD2

DB0

104

105

I/O

1 bit of 8-bit bidirectional data bus

V_DD1

SA0

106

supply voltage 1

I²C-bus address pin

107

108

data bus clock input (parallel control)

ground (logic) 1

V_SS1

R/W

109

110

read/write input (parallel control)

111

test pad (connect to V_SS

)

V_SS2

112

ground (logic) 2

113

not connected

n.c.

114

−

R9 to R16

R25 to R30

115 to 122

123 to 128

13 to 20

21 to 26

LCD row driver outputs

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

handbook, full pagewidth

102

101

R31

n.c.

OSC

n.c.

100 n.c.

99 n.c.

98 DB2

R32

C60

C59

C58

C57

C56

96 DB3

LCD3

LCD2

94 DB4

C55

LCD1

C54 11

C53 12

91 DB5

C52

C51

SDA

DB6

C50 15

C49 16

88 SCL

87 DB7

86 n.c.

85 n.c.

C48

C47 18

C46 19

C45 20

C44 21

84 R1

83 R2

82 R3

PCF2116

80 R5

C43

C42 23

C41

C40

C39

C38

C37

76 R17

74 R19

R18

C36 29

C35

C34

C33

C32

C31

R20

R21

71 R22

R23

69 R24

68 C1

C30 35

n.c. 36

n.c.

C29 38

MBD451 - 1

Fig.2 Pin configuration (LQFP128).

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

PIN FUNCTIONS

7.9

OSC: oscillator

When the on-chip oscillator is used this pin must be

connected to V_DD. An external clock signal, if used, is input

at this pin.

7.1

RS: register select (parallel control)

RS selects the register to be accessed for read and write

when the device is controlled by the parallel interface.

RS = logic 0 selects the instruction register for write and

the Busy Flag and Address Counter for read. RS = logic 1

selects the data register for both read and write. There is

an internal pull-up on pin RS.

7.10 SCL: serial clock line

Input for the I²C-bus clock signal.

7.11 SDA: serial data line

7.2

R/W: read/write (parallel control)

Input/output for the I²C-bus data line.

R/W selects either the read (R/W = logic 1) or write

(R/W = logic 0) operation when control is by the parallel

interface. There is an internal pull-up on this pin.

7.12 SA0: address pin

The hardware sub-address line is used to program the

device sub-address for 2 different PCF2116s on the same

I²C-bus.

7.3

E: data bus clock

The E pin is set HIGH to signal the start of a read or write

operation when the device is controlled by the parallel

interface. Data is clocked in or out of the chip on the

negative edge of the clock. Note that this pin must be tied

to logic 0 (V_SS) when I²C-bus control is used.

7.13 T1: test pad

Must be connected to V_SS. Not user accessible.

FUNCTIONAL DESCRIPTION (see Fig.1)

7.4

DB0 to DB7: data bus

8.1

LCD supply voltage generator, PCF2114x and

PCF2116x

The bidirectional, 3-state data bus transfers data between

the system controller and the PCF2116. DB7 may be used

as the Busy Flag, signalling that internal operations are not

yet completed. In 4-bit operations the 4 higher order lines

DB4 to DB7 are used; DB0 to DB3 must be left open

circuit. There is an internal pull-up on each of the data

lines. Note that these pins must be left open circuit when

I²C-bus control is used.

The on-chip voltage generator is controlled by bit G of the

‘Function set’ instruction and V₀.

V₀is a high-impedance input and draws no current from

the system power supply. Its range is between V_SSand

_DD− 1 V. When V₀is connected to V_DDthe generator is

switched off and an external voltage must be supplied to

pin V_LCD. This may be more negative than V_SS

7.5

C1 to C60: column driver outputs

When G = logic 1 the generator produces a negative

voltage at pin V_LCD, controlled by the input voltage at

pin V₀. The LCD operating voltage is given by the

relationship:

These pins output the data for pairs of columns.

This arrangement permits optimized chip-on-glass (COG)

layout for 4-line by 12 characters.

V_OP= 1.8V_DD− V₀

7.6

R1 to R32: row driver outputs

Where:

These pins output the row select waveforms to the left and

right halves of the display.

V_OP= V_DD− V_LCD

V_LCD= V₀− (0.8V_DD

)

7.7

V_LCD: LCD power supply

When G = logic 0, the generated output voltage V_LCDis

equal to V₀(between V_SSand V_DD). In this instance:

Negative power supply for the liquid crystal display.

This may be generated on-chip or supplied externally.

V_OP= V_DD− V₀

When V_LCDis generated on-chip the V_LCDpin should be

decoupled to V_DDwith a suitable capacitor. V_DDand V₀

must be selected to limit the maximum value of V_OPto 9 V.

7.8

V₀: V_LCDcontrol input

The input level at this pin determines the generated V_LCD

output voltage.

Figure 3 shows the two generator control characteristics.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

8.2

LCD supply voltage generator, PCF2116K

8.5

Oscillator

In the PCF2116K version, V₀is connected through an

on-chip resistor (R₀) to V_LCD. Resistor R₀has a nominal

value of 1 MΩ and draws a typical current of 4 µA from the

pin V₀. A constant voltage (equal to 1.34V_DD) is always

present across R₀.

The on-chip oscillator provides the clock signal for the

display system. No external components are required.

Pin OSC must be connected to V_DD

8.6 External clock

The voltage range of the PCF2116K is between V_SSand

If an external clock is to be used, it must be input at

_DD− 0.5 V (see Fig.4). When V₀is connected to V_DDthe

pin OSC. The resulting display frame frequency is given by

_frame= ¹⁄_{2304 osc}

. A clock signal must always be present,

generator is switched off and an external voltage must be

supplied to pin V_LCD. This may be more negative than V_SS

otherwise the LCD may be frozen in a DC state.

When G = logic 1 the generator produces a negative

voltage at pin V_LCD, controlled by the input voltage at

pin V₀. The LCD operating voltage is given by the

relationship:

8.7

Power-on reset

The power-on reset block initializes the chip after

power-on or power failure.

V_OP= 2.34V_DD− V₀

8.8

Registers

Where:

The PCF2116 has two 8-bit registers, an Instruction

Select signal (RS) determines which register will be

accessed.

V_OP= V_DD− V_LCD

V_LCD= V₀− (1.34V_DD

)

When G = logic 0, the generated output voltage V_LCDis

equal to V₀(between V_SSand V_DD). In this instance:

The instruction register stores instruction codes such as

‘Display clear’ and ‘Cursor shift’, and address information

for the Display Data RAM (DDRAM) and Character

Generator RAM (CGRAM). The instruction register can be

written to, but not read, by the system controller.

V_OP= V_DD− V₀

8.3

Character generator ROM (CGROM)

The standard character sets A, C and G are available for

The data register temporarily stores data to be read from

the DDRAM and CGRAM. When reading, data from the

DDRAM or CGRAM corresponding to the address in the

Address Counter is written to the data register prior to

being read by the ‘Read data’ instruction.

the PCF2114x and PCF2116x. Standard character set C is

available for the PCF2116K.

8.4

LCD bias voltage generator

The intermediate bias voltages for the LCD display are

also generated on-chip. This removes the need for an

external resistive bias chain and significantly reduces the

system power consumption. The optimum levels depend

on the multiplex rate and are selected automatically when

the number of lines in the display is defined.

8.9

Busy Flag

The Busy Flag indicates the free/busy status of the

PCF2116. Logic 1 indicates that the chip is busy and

further instructions will not be accepted. The Busy Flag is

output to pin DB7 when RS = logic 0 and R/W = logic 1.

Instructions should only be written after checking that the

Busy Flag is logic 0 or waiting for the required number of

clock cycles.

The optimum value of V_OPdepends on the multiplex rate,

the LCD threshold voltage (V_th) and the number of bias

levels and is given by the relationships in Table 1.Using a

5-level bias scheme for 1 : 16 MUX rate allows V_OP< 5 V

for most LCD liquids. The effect on the display contrast is

negligible.

Table 1 Optimum values for V_OP

NUMBER OF BIAS

DISCRIMINATION

MUX RATE

LEVELS

V_OP/V_th

V_on/V_off

1 : 16

1 : 32

3.67

5.19

1.277

1.196

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

9 V

= 1.8 x V

OP(max)

6 = V

G = 1

= 0.8 x V

OP(min)

2.5

3.5

MGA798

a. High-voltage mode V_OP= 1.8V_DD− V₀.

G = 0

6 = V

3.5

MGA799

b. Buffer mode V_OP= V_DD− V₀.

Fig.3 V_OPas a function of V₀control characteristics.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

9 V

G = 1

4 = V

= 1.34 × V

+ 0.5

OP(min)

2.5

3.5

MBH667

a. High-voltage mode V_OP= 2.34V_DD− V₀.

G = 0

6 = V

3.5

MGA799

b. Buffer mode V_OP= V_DD− V₀.

Fig.4 V_OPas a function of V₀control characteristics (PCF2116K).

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

8.10 Address Counter (AC)

8.13 Character generator RAM (CGRAM)

The Address Counter assigns addresses to the DDRAM

and CGRAM for reading and writing and is set by the

instructions ‘Set CGRAM address’ and

‘Set DDRAM address’. After a read/write operation the

Address Counter is automatically incremented or

decremented by 1.The Address Counter contents are

output to the bus (DB0 to DB6) when RS = logic 0 and

R/W = logic 1.

Up to 16 user-defined characters may be stored in the

character generator RAM. The CGROM and CGRAM use

a common address space, of which the first column is

reserved for the CGRAM (see Fig.8). Figure 11 shows the

addressing principle for the CGRAM.

8.14 Cursor control circuit

The cursor control circuit generates the cursor (underline

and/or character blink as shown in Fig.12) at the DDRAM

address contained in the Address Counter. When the

Address Counter contains the CGRAM address the cursor

will be inhibited.

8.11 Display data RAM (DDRAM)

The display data RAM stores up to 80 characters of

display data represented by 8-bit character codes.

RAM locations not used for storing display data can be

used as general purpose RAM. The basic

8.15 Timing generator

DDRAM-to-display mapping scheme is shown in Fig.5.

With no display shift the characters represented by the

codes in the first 12 or 24 RAM locations starting at

address 00 in line 1 are displayed. Subsequent lines

display data starting at addresses 20, 40, or 60 Hex.

Figs 6 and 7 show the DDRAM-to-display mapping

principle when the display is shifted.

The timing generator produces the various signals

required to drive the internal circuitry. Internal chip

operation is not disturbed by operations on the data buses.

8.16 LCD row and column drivers

The PCF2116 contains 32 row and 60 column drivers,

which connect the appropriate LCD bias voltages in

sequence to the display, in accordance with the data to be

displayed. The bias voltages and the timing are selected

automatically when the number of lines in the display is

selected. Figures 13 and 14 show typical waveforms.

The address range for a 1-line display is 00 to 4F; for a

2-line display from 00 to 27 (line 1) and 40 to 67 (line 2);

for a 4-line display from 00 to 13, 20 to 33, 40 to 53 and

60 to 73 for lines 1, 2, 3 and 4 respectively.

For 2 and 4-line displays the end address of one line and

the start address of the next line are not consecutive.

When the display is shifted each line wraps around

independently of the others (Figs 6 and 7).

In 1-line mode (1 : 16) the row outputs are driven in pairs:

R1/R17, R2/R18 for example. This allows the output pairs

to be connected in parallel, providing greater drive

capability.

When data is written into the DDRAM wrap-around occurs

from 4F to 00 in 1-line mode and from 27 to 40 and

67 to 00 in 2-line mode; from 13 to 20, 33 to 40, 53 to 60

and 73 to 00 in 4-line mode.

Unused outputs should be left unconnected.

8.12 Character generator ROM (CGROM)

The character generator ROM generates 240 character

patterns in 5 × 8 dot format from 8-bit character codes.

Figures 8 to 10 show the character sets currently

available.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

non-displayed DDRAM addresses

Display

Position

handbook, 4 columns

22 23 24

(decimal)

00 01 02 03 04

15 16 17 18 19

4C 4D 4E 4F

DDRAM

Address

(hex)

1-line display

non-displayed DDRAM address

24 25 26 27

00 01 02 03 04

40 41 42 43 44

15 16 17 18 19

55 56 57 58 59

line 1

DDRAM

Address

(hex)

64 65 66 67

MLA792

line 2

2-line display

non-displayed DDRAM addresses

9 10 11 12

handbook, 4 columns

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 line 1

20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 line 2

DDRAM

Address

(hex)

40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53

line 3

line 4

60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73

MLA793

4 line display

Fig.5 DDRAM-to-display mapping; no shift.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

Display

Position

(decimal)

Display

Position

(decimal)

22 23 24

16 17 18

22 23 24

14 15 16

01 02 03 04 05

4F 00 01 02 03

DDRAM

Address

(hex)

DDRAM

Address

(hex)

1-line display

line 1

line 2

16 17 18

line 1

01 02 03 04 05

41 42 43 44 45

14 15 16

27 00 01 02 03

DDRAM

Address

(hex)

DDRAM

Address

(hex)

56 57 58

MLA815

67 40 41 42 43

54 55 56 line 2

MLA802

2-line display

9 10 11 12

line 1

01 02 03 04 05 06 07 08 09 0A 0B 0C

21 22 23 24 25 26 27 28 29 2A 2B 2C

41 42 43 44 45 46 47 48 49 4A 4B 4C

13 00 01 02 03 04 05 06 07 08 09 0A

33 20 21 22 23 24 25 26 27 28 29 2A

53 40 41 42 43 44 45 46 47 48 49 4A

73 60 61 62 63 64 65 66 67 68 69 6A

line 2

line 3

line 4

line 2

line 3

DDRAM

Address

(hex)

Address

(hex)

61 62 63 64 65 66 67 68 69 6A 6B 6C

4-line display

line 4

MLA803

4-line display

MLA816

Fig.6 DDRAM-to-display mappi7ng; right shift.

Fig.7 DDRAM-to-display mapping; left shift.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

handbook, full pagewidth

upper

4 bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

lower

6 bits

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111

MLB245 - 1

Fig.8 Character set ‘A’ in CGROM: PCF2116A; PCF2114A.

1997 Apr 07

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PCF2116 family

handbook, full pagewidth

upper

4 bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

lower

4 bits

RAM 1

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111

MLB895

Fig.9 Character set ‘C’ in CGROM: PCF2116C; PCF2114C.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

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PCF2116 family

handbook, full pagewidth

upper

4 bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

lower

6 bits

RAM 1

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111

MLB896

Fig.10 Character set ‘G’ in CGROM: PCF2116G; PCF2114G.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

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PCF2116 family

character codes

(DDRAM data)

CGRAM

address

character patterns

(CGRAM data)

handbook, full pagewidth

higher

order

bits

lower

order

bits

higher

order

bits

lower

order

bits

higher

order

bits

lower

order

bits

character

pattern

example 1

cursor

position

character

pattern

example 2

MGA800 - 1

Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.

CGRAM address bits 0 to 2 designate character pattern line position. The 8th line is the cursor position and display is performed by logical OR with

the cursor. Data in the 8th line will appear in the cursor position.

Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in Fig.11 (bit 4 being at the left end).

As shown in Figs 8 and 11, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1

corresponds to selection for display.

Only bits 0 to 5 of the CGRAM address are set by the ‘Set CGRAM address’ instruction. Bit 6 can be set using the ‘Set DDRAM address’ instruction

or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘Read busy flag and address’ instruction.

Fig.11 Relationship between CGRAM addresses and data and display patterns.

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PCF2116 family

MGA801

cursor

5 x 7 dot character font

alternating display

cursor display example

blink display example

Fig.12 Cursor and blink display examples.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

frame n

frame n 1

state 1 (ON)

state 2 (ON)

handbook, full pagewidth

V /V

ROW 1

ROW 9

ROW 2

LCD

V /V

1-line display

(1:16)

LCD

V /V

LCD

V /V

COL 1

LCD

COL 2

V /V

LCD

0.25 V

0 V

state 1

0.25 V

0 V

state 2

0.25 V

MGA802 - 1

Fig.13 Typical LCD waveforms; 1-line mode.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

frame n

frame n 1

handbook, full pagewidth

state 1 (ON)

state 2 (ON)

ROW 1

LCD

ROW 9

LCD

2-line display

(1:32)

ROW 2

LCD

COL 1

LCD

COL 2

LCD

0.15 V

0 V

state 1

0.15 V

state 2 0 V

0.15 V

MGA803 - 1

123

32 12 3

Fig.14 Typical LCD waveforms; 2-line mode.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

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PCF2116 family

With the ‘Function set’ instruction M and N are set to 0, 0.

Figures 15 to 17 show DDRAM addresses of the display

characters. The second row of each table corresponds to

either the right half of a 1-line display or to the second line

of a 2-line display. Wrap around of data during display shift

or when writing data is non-standard.

8.17 Programming MUX 1 : 16 displays with the

PCF2114x

The PCF2114x can be used in:

•

1-line mode to drive a 2-line display

2 × 12 characters with MUX rate 1 : 16, resulting in

better contrast. The internal data flow of the chip is

optimized for this purpose.

display position

DDRAM address

handbook, full pagewidth

display position

DDRAM address

MLB899

Fig.15 DDRAM-to-display mapping; no shift (PCF2114x).

display position

DDRAM address

handbook, full pagewidth

display position

DDRAM address

MLB900

Fig.16 DDRAM-to-display mapping; right shift (PCF2114x).

display position

DDRAM address

handbook, full pagewidth

display position

DDRAM address

MLB901

Fig.17 DDRAM-to-display mapping; left shift (PCF2114x).

1997 Apr 07

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PCF2116 family

8.18 Programming MUX 1 : 32 displays with the

PCF2114x

INSTRUCTIONS

Only two PCF2116 registers, the Instruction Register (IR)

and the Data Register (DR) can be directly controlled by

the microcontroller. Before internal operation, control

information is stored temporarily in these registers to allow

interface to various types of microcontrollers which

operate at different speeds or to allow interface to

peripheral control ICs.

The PCF2116 operation is controlled by the instructions

shown in Table 3 together with their execution time.

Details are explained in subsequent sections.

To drive a 2-line by 24 characters MUX 1 : 32 display, use

instruction ‘Function set’ M, N to 0, 1. Note that the right

half of the display needs mirrored column connection

compared to a display driven by a PCF2116x.

To drive a 4-line by 12 characters MUX 1 : 32 display the

PCF2116x operating instructions apply. There is no

functional difference between the PCF2114x and the

PCF2116x in this mode. For such an application

set M, N to 1, 1 with the ‘Function set’ instruction.

Instructions are of 4 categories, those that:

8.19 Reset function

1. Designate PCF2116 functions such as display format,

data length, etc.

The PCF2116 automatically initializes (resets) when

power is turned on. After reset the chip has the following

state.

2. Set internal RAM addresses

3. Perform data transfer with internal RAM

4. Others.

Table 2 State after reset

In normal use, category 3 instructions are used most

frequently. However, automatic incrementing by 1 (or

decrementing by 1) of internal RAM addresses after each

data write lessens the microcontroller program load. The

display shift in particular can be performed concurrently

with display data write, enabling the designer to develop

systems in minimum time with maximum programming

efficiency.

STEP

DESCRIPTION

display clear

function set

DL = 1

8-bit interface

M, N = 0 1-line display

G = 0

voltage

generator;

V_LCD= V₀

During internal operation, no instruction other than

‘Read busy flag and address’ will be executed.

display on/off

control

D = 0

C = 0

B = 0

display off

cursor off

blink off

Because the Busy Flag is set to logic 1 while an instruction

is being executed, check to make sure it is on logic 0

before sending the next instruction or wait for the

maximum instruction execution time, as given in Table 3.

An instruction sent while the Busy Flag is HIGH will not be

executed.

entry mode set I/D = 1

S = 0

+1 (increment)

no shift

Default address pointer to DDRAM. The Busy

Flag (BF) indicates the busy state (BF = logic 1)

until initialization ends. The busy state lasts

2 ms. The chip may also be initialized by

software. See Figs 28 and 29.

I²C-bus interface reset

1997 Apr 07

-------

Table 3 Instructions (note 1)

REQUIRED

CLOCK

CYCLES⁽²⁾

INSTRUCTION RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DESCRIPTION

NOP

No operation.

Clear display

Clears entire display and sets DDRAM

address 0 in Address Counter.

165

Return Home

Entry mode set

Display control

Sets DDRAM address 0 in Address Counter.

Also returns shifted display to original position.

DDRAM contents remain unchanged.

I/D

Sets cursor move direction and speciﬁes shift

of display. These operations are performed

during data write and read.

Sets entire display on/off (D), cursor on/off (C)

and blink of cursor position character (B).

Cursor/display

shift

S/C R/L

Moves cursor and shifts display without

changing DDRAM contents.

Function set

Sets interface data length (DL), number of

display lines (N, M) and voltage generator

control (G).

Set CGRAM

address

A_CG

Sets CGRAM address.

Set DDRAM

address

A_DD

A_C

Sets DDRAM address.

Read busy ﬂag

and address

Reads Busy Flag (BF) indicating internal

operation is being performed and reads

Address Counter contents.

Read data

Write data

read data

write data

Reads data from CGRAM or DDRAM.

Writes data to CGRAM or DDRAM.

Notes

1. In the I²C-bus mode the DL bit is don't care. 8-bit mode is assumed.

In the I²C-bus mode a control byte is required when RS or R/W is changed; control byte: Co, RS, R/W, 0, 0, 0, 0, 0; command byte: DB7 to DB0.

f_osc

2. Example: f_osc= 150 kHz, T_cy

= 6.67 µs; 3 cycles = 20 µs, 165 cycles = 1.1 ms.

Philips Semiconductors

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PCF2116 family

Table 4 Command bit identities

BIT

I/D

decrement

display freeze

display off

cursor off

increment

display shift

display on

cursor on

character at cursor position does not blink

character at cursor position blinks

S/C

cursor move

display shift

R/L

left shift

right shift

4 bits

8 bits

voltage generator: V_LCD= V₀

voltage generator; V_LCD= V₀− 0.8V_DD

N, (M = 0)

PCF2116x

PCF2114x

N, (M = 1)

1 line × 24 characters; MUX 1 : 16

2 line × 12 characters; MUX 1 : 16

reserved

2 lines × 24 characters; MUX 1 : 32

4 lines × 12 characters; MUX 1 : 32

internal operation in progress

end of internal operation

last control byte, only data bytes to follow

next two bytes are a data byte and another

control byte

R/W

DB7

DB6

DB5

DB4

IR7

IR6

IR5

IR4

IR3

IR2

IR1

IR0

AC3

AC2

AC1

AC0

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

AC6

AC5

AC4

busy flag and

address counter read

data register

read

instruction

write

MGA804

Fig.18 4-bit transfer example.

1997 Apr 07

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PCF2116 family

R/W

internal

internal operation

not

busy

DB7

IR7

IR3

AC3

busy

instruction

write

busy flag

check

busy flag

check

instruction

write

MGA805

IR7, IR3: instruction 7^thbit, 3^rdbit.

AC3: Address Counter 3^rdbit.

Fig.19 An example of 4-bit data transfer timing sequence.

R/W

internal

internal operation

not

busy

data

busy

data

DB7

instruction

write

busy flag

check

busy flag

check

busy flag

check

instruction

write

MGA806

Fig.20 Example of Busy Flag check timing sequence.

1997 Apr 07

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PCF2116 family

9.1

Clear display

9.4.2

‘Clear display’ writes space code 20 (hexadecimal) into all

DDRAM addresses (The character pattern for character

code 20 must be blank pattern). Sets the DDRAM Address

Counter to logic 0. Returns display to its original position if

it was shifted. Thus, the display disappears and the cursor

or blink position goes to the left edge of the display

(the first line if 2 or 4 lines are displayed). Sets entry mode

I/D = logic 1 (increment mode). S of entry mode does not

change.

The cursor is displayed when C = logic 1 and inhibited

when C = logic 0. Even if the cursor disappears, the

display functions I/D, etc. remain in operation during

display data write. The cursor is displayed using 5 dots in

the 8^thline (see Fig.12).

9.4.3

The character indicated by the cursor blinks when

B = logic 1. The blink is displayed by switching between

display characters and all dots on with a period of

1 second when f_osc= 150 kHz (see Fig.12). At other clock

The instruction ‘Clear display’ requires extra execution

time. This may be allowed for by checking the busy-flag

(BF) or by waiting until 2 ms has elapsed. The latter must

be applied where no read-back options are foreseen, as in

some chip-on-glass (COG) applications.

frequencies the blink period is equal to 150 kHz/f_osc

The cursor and the blink can be set to display

simultaneously.

9.2

Return home

9.5

Cursor/display shift

‘Return home’ sets the DDRAM Address Counter to

logic 0. Returns display to its original position if it was

shifted. DDRAM contents do not change. The cursor or

blink position goes to the left of the display (the first line if 2

or 4 lines are displayed). I/D and S of entry mode do not

change.

‘Cursor/display shift’ moves the cursor position or the

display to the right or left without writing or reading display

data. This function is used to correct a character or move

the cursor through the display. In 2 or 4-line displays, the

cursor moves to the next line when it passes the last

position (40 or 20 decimal) of the line. When the displayed

data is shifted repeatedly all lines shift at the same time;

displayed characters do not shift into the next line.

The Address Counter (AC) content does not change if the

only action performed is shift display, but increments or

decrements with the cursor shift.

9.3

Entry mode set

9.3.1

I/D

When I/D = logic 1 (0) the DDRAM or CGRAM address

increments (decrements) by 1 when data is written into or

read from the DDRAM or CGRAM. The cursor or blink

position moves to the right when incremented and to the

left when decremented. The cursor and blink are inhibited

when the CGRAM is accessed.

9.6

Function set

9.6.1

DL (PARALLEL MODE ONLY)

Defines interface data width when the parallel data

interface is used.

9.3.2

Data is sent or received in bytes (bits DB7 to DB0) when

DL = logic 1, or in two 4-bit nibbles (DB7 to DB4) when

DL = logic 0. When 4-bit width is selected, data is

When S = logic 1, the entire display shifts either to the right

(I/D = logic 0) or to the left (I/D = logic 1) during a DDRAM

write. Thus it looks as if the cursor stands still and the

display moves. The display does not shift when reading

from the DDRAM, or when writing into or reading out of the

CGRAM. When S = logic 0 the display does not shift.

transmitted in two cycles using the parallel bus⁽¹⁾

When using the I²C-bus interface the DL should not

previously have been set to 0 using the parallel interface.

9.6.2

N, M

9.4

Display on/off control

Sets number of display lines.

9.4.1

The display is on when D = logic 1 and off when

D = logic 0. Display data in the DDRAM are not affected

and can be displayed immediately by setting D to logic 1.

(1) In a 4-bit application DB3 to DB0 are left open (internal

pull-ups). Hence in the ﬁrst ‘Function set’ instruction after

power-on, G and H are set to 1. A second ‘Function set’ must

then be sent (2 nibbles) to set G and H to their required

values.

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PCF2116 family

After writing, the address automatically increments or

decrements by 1, in accordance with the entry mode.

Only bits D[4] to D[0] of CGRAM data are valid, bits

D[7] to D[5] are ‘don’t care’.

9.6.3

Controls the V_LCDvoltage generator characteristic.

9.7

Set CGRAM address

9.11 Read data from CGRAM or DDRAM

‘Set CGRAM address’ sets bit 0 to 5 of the CGRAM

address (A_CGin Table 3) into the Address Counter

(binary A[5] to A[0]). Data can then be written to or read

from the CGRAM.

Reads binary 8-bit data D[7] to D[0] from the CGRAM or

DDRAM.

The most recent ‘Set address’ instruction determines

whether the CGRAM or DDRAM is to be read.

Only bits 0 to 5 of the CGRAM address are set by the

‘Set CGRAM address’ instruction. Bit 6 can be set using

the ‘Set DDRAM address’ instruction or by using the

auto-increment feature during CGRAM write. All bits 0 to 6

can be read using the ‘Read busy flag and address’

instruction.

The ‘Read data’ instruction gates the content of the data

again, internal operation increments (or decrements) the

AC and stores RAM data corresponding to the new AC into

the DR.

9.8

Set DDRAM address

Remark: the only three instructions that update the data

‘Set DDRAM address’ sets the DDRAM address (A_DDin

Table 3) into the Address Counter (binary A[6] to A[0]).

Data can then be written to or read from the DDRAM.

• ‘Set CGRAM address’

• ‘Set DDRAM address’

• ‘Read data’ from CGRAM or DDRAM.

Hexadecimal address ranges.

Other instructions (e.g. ‘Write data’, ‘Cursor/Display shift’,

‘Clear display’, ‘Return home’) will not modify the data

ADDRESS

FUNCTION

00 to 4F

1-line by 24; 2114x/2116x

2-line by 12; 2114x

00 to 0B and 0C to 4F

00 to 27 and 40 to 67

2-line by 24; 2114x/2116x

4-line by 12; 2114x/2116x

10 INTERFACE TO MICROCONTROLLER

(PARALLEL INTERFACE)

00 to 13, 20 to 33, 40 to 53

and 60 to 73

The PCF2116 can send data in either two 4-bit operations

or one 8-bit operation and can thus interface to 4-bit or

8-bit microcontrollers.

9.9

Read busy ﬂag and address

‘Read busy flag and address’ reads the Busy Flag (BF).

BF = logic 1 indicates that an internal operation is in

progress. The next instruction will not be executed until

BF = logic 0, so BF should be checked before sending

another instruction.

In 8-bit mode data is transferred as 8-bit bytes using the

8 data lines DB0 to DB7. Three further control lines E, RS,

and R/W are required.

In 4-bit mode data is transferred in two cycles of 4-bits

each. The higher order bits (corresponding to DB4 to DB7

in 8-bit mode) are sent in the first cycle and the lower order

bits (DB0 to DB3 in 8-bit mode) in the second.

Data transfer is complete after two 4-bit data transfers.

It should be noted that two cycles are also required for the

Busy Flag check. 4-bit operation is selected by instruction.

See Figs 18, 19 and 20 for examples of bus protocol.

At the same time, the value of the Address Counter (A_Cin

Table 3) expressed in binary A[6] to A[0] is read out. The

Address Counter is used by both CGRAM and DDRAM,

and its value is determined by the previous instruction.

9.10 Write data to CGRAM or DDRAM

Writes binary 8-bit data D[7] to D[0] to the CGRAM or the

DDRAM.

In 4-bit mode pins DB3 to DB0 must be left open-circuit.

They are pulled up to V_DDinternally.

Whether the CGRAM or DDRAM is to be written into is

determined by the previous specification of CGRAM or

DDRAM address setting.

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PCF2116 family

11 INTERFACE TO MICROCONTROLLER

(I²C-BUS INTERFACE)

11.5 Acknowledge

The number of data bytes transferred between the START

and STOP conditions from transmitter to receiver is

unlimited. Each byte of eight bits is followed by an

acknowledge bit. The acknowledge bit is a HIGH level

signal put on the bus by the transmitter during which time

the master generates an extra acknowledge related clock

pulse. A slave receiver which is addressed must generate

an acknowledge after the reception of each byte. Also a

master receiver must generate an acknowledge after the

reception of each byte that has been clocked out of the

slave transmitter. The device that acknowledges must

pull-down the SDA line during the acknowledge clock

pulse, so that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse (set-up and

hold times must be taken into consideration). A master

receiver must signal an end of data to the transmitter by

not generating an acknowledge on the last byte that has

been clocked out of the slave. In this event the transmitter

must leave the data line HIGH to enable the master to

generate a STOP condition.

11.1 Characteristics of the I²C-bus

The I²C-bus is for bidirectional, two-line communication

between different ICs or modules. The two lines are a

serial data line (SDA) and a serial clock line (SCL).

Both lines must be connected to a positive supply via a

pull-up resistor. Data transfer may be initiated only when

the bus is not busy.

11.2 Bit transfer

One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable during the

HIGH period of the clock pulse as changes in the data line

at this time will be interpreted as a control signal.

11.3 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not

busy. A HIGH-to-LOW transition of the data line, while the

clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock

is HIGH is defined as the STOP condition (P).

11.6 I²C-bus protocol

Before any data is transmitted on the I²C-bus, the device

which should respond is addressed first. The addressing is

always carried out with the first byte transmitted after the

start procedure. The I²C-bus configuration for the different

PCF2116 READ and WRITE cycles is shown in

Figs 25 to 27.

11.4 System conﬁguration

A device generating a message is a ‘transmitter’, a device

receiving a message is the ‘receiver’. The device that

controls the message is the ‘master’ and the devices which

are controlled by the master are the ‘slaves’.

1997 Apr 07

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PCF2116 family

SDA

SCL

data line

stable;

data valid

change

of data

allowed

MBC621

Fig.21 Bit transfer.

SDA

SCL

START condition

STOP condition

MBC622

Fig.22 Definition of START and STOP conditions.

1997 Apr 07

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PCF2116 family

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

SDA

SCL

MGA807

Fig.23 System configuration.

DATA OUTPUT

BY TRANSMITTER

not acknowledge

DATA OUTPUT

BY RECEIVER

acknowledge

SCL FROM

MASTER

clock pulse for

acknowledgement

START

CONDITION

MBC602

Fig.24 Acknowledgement on the I²C-bus.

1997 Apr 07

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PCF2116 family

BM6H8

ull pagewidth

1997 Apr 07

acknowledgement

from PCF2116

(1)

CONTROL BYTE

DATA

CONTROL

DATA

slave address

2n 0 bytes

2 bytes

R/W

acknowledgement

from PCF2116

no acknowledgement

from master

SLAVE

ADDRESS

DATA

n bytes

last byte

R/W

update

MGA809 - 1

data pointer

(1) Last data byte is a dummy byte (may be omitted).

Fig.26 Master reads after setting word address; write word address, set RS/RW; READ data.

ahdnbok,uflapegwidt

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PCF2116 family

acknowledgement

from PCF2116

acknowledgement

from master

no acknowledgement

handbook, full pagewidth

from master

SLAVE

ADDRESS

DATA

last byte

n bytes

R/W

update

data pointer

MGA810 - 1

Fig.27 Master reads slave immediately after first byte; READ mode (RS previously defined).

1997 Apr 07

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PCF2116 family

GM8A-1

h a n d b o o k , f u l l p a g e w i

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PCF2116 family

12 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL

V_DD

PARAMETER

MIN.

−0.5

MAX.

+8.0

UNIT

supply voltage

V_LCD

V_I

LCD supply voltage

_DD− 11

V_DD

input voltage OSC, V₀, RS, R/W, E and DB0 to DB7

output voltage R1 to R32, C1 to C60 and V_LCD

DC input current

_SS− 0.5

_LCD− 0.5

V_DD+ 0.5

+10

V_O

I_I

−10

−50

−

I_O

DC output current

+10

I_DD, I_SS, I_LCDV_DD, V_SSor V_LCDcurrent

+50

P_tot

P_O

T_stg

total power dissipation

power dissipation per output

storage temperature

400

°C

−

100

−65

+150

13 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is

desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).

1997 Apr 07

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PCF2116 family

14 DC CHARACTERISTICS

V_DD= 2.5 to 6 V; V_SS= 0 V; V_LCD= V_DD− 3.5 to V_DD− 9 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

SYMBOL

Supplies

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V_DD

V_LCD

I_DD

supply voltage

2.5

−

6.0

_DD− 3.5

LCD supply voltage

supply current external V_LCD

supply current 1

V_DD− 9

−

note 1

I_DD1

I_DD2

−

200

500

300

µA

supply current 2

V_DD= 5 V; V_OP= 9 V;

_osc= 150 kHz;

T_amb= 25 °C

I_DD3

supply current 3

V_DD= 3 V; V_OP= 5 V;

f_osc= 150 kHz;

−

150

200

µA

T_amb= 25 °C

I_DD

supply current internal V_LCD

supply current 4

notes 1, 2 and 8

I_DD4

I_DD5

−

700

600

1100

900

µA

supply current 5

V_DD= 5 V; V_OP= 9 V;

_osc= 150 kHz;

T_amb= 25 °C

I_DD6

supply current 6

V_DD= 3 V; V_OP= 5 V;

f_osc= 150 kHz;

−

500

800

µA

T_amb= 25 °C

I_LCD

V_LCDinput current

notes 1 and 7

note 3

−

100

1.8

µA

V_POR

power-on reset voltage level

1.3

Logic

V_IL1

LOW level input voltage E, RS,

R/W, DB0 to DB7 and SA0

V_SS

−

0.3V_DD

V_DD

V_IH1

HIGH level input voltage E, RS,

R/W, DB0 to DB7 and SA0

0.7V_DD

V_SS

V_IL(osc)

V_IH(osc)

V_IL(V0)

V_IH(V0)

I_pu

LOW level input voltage OSC

HIGH level input voltage OSC

LOW level input voltage V₀

HIGH level input voltage V₀

pull-up current at DB0 to DB7

−

_DD− 1.5

V_DD− 0.1

V_DD

V_SS

_DD− 0.5

V_DD− 0.05 −

V_DD

1.00

−

V_I= V_SS

0.04

0.15

µA

I_OL(DB)

LOW level output current

DB0 to DB7

V_OL= 0.4 V; V_DD= 5 V 1.6

−

I_OH(DB)

I_L1

HIGH level output current

DB0 to DB7

V_OH= 4 V; V_DD= 5 V

V_I= V_DDor V_SS

−1.0

−1

−

leakage current OSC, V₀, E, RS,

R/W, DB0 to DB7 and SA0

µA

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

I²C-bus

SDA, SCL

V_IL2

V_IH2

I_L2

LOW level input voltage

HIGH level input voltage

leakage current

note 4

V_SS

−

0.3V_DD

note 4

0.7V_DD

−

V_DD

V_I= V_DDor V_SS

note 5

−1

µA

C_i

input capacitance

−

I_OL(SDA)

LOW level output current (SDA)

V_OL= 0.4 V; V_DD= 5 V 3

−

LCD outputs

R_ROW

R_COL

V_tol1

row output resistance R1 to R32

note 6

−

1.5

kΩ

column output resistance C1 to C60 note 6

bias voltage tolerance R1 to R32

and C1 to C60

note 7

±20

±130

V_tol2

LCD supply voltage (V_LCD

)

note 2

−

±40

±300

tolerance

Notes

1. LCD outputs are open-circuit; inputs at V_DDor V_SS; V₀= V_DD; bus inactive; internal or external clock with duty cycle

50% (I_DD1only).

2. LCD outputs are open-circuit; LCD supply voltage generator is on; load current at V_LCD= 20 µA.

3. Resets all logic when V_DD< V_POR

4. When the voltages are above or below the supply voltages V_DDor V_SS, an input current may flow; this current must

not exceed ±0.5 mA.

5. Tested on sample basis.

6. Resistance of output terminals (R1 to R32 and C1 to C60) with load current = 150 µA; V_OP= V_DD− V_LCD= 9 V;

outputs measured one at a time; (external V_LCD).

7. LCD outputs open-circuit; external V_LCD

8. Maximum value occurs at 85 °C.

15 DC CHARACTERISTICS (PCF2116K)

V_DD= 2.5 to 6 V; V_SS= 0 V; V_LCD= V_DD− 3.5 to V_DD− 9 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

SYMBOL

V_DD

PARAMETER

supply voltage

CONDITIONS

MIN.

2.5

_DD− 9

TYP.

MAX.

6.0

UNIT

−

V_LCD

V₀

LCD supply voltage

−

_DD− 3.5

_DD− 0.5

voltage generator control input

voltage

V_SS

R₀

voltage generator control input

resistance

T_amb= 25 °C; note 1

700

1000 1300

kΩ

Note

1. R₀has a temperature coefficient of resistance of +0.6%/K.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

16 AC CHARACTERISTICS

V_DD= 2.5 to 6.0 V; V_SS= 0 V; V_LCD= V_DD− 3.5 V to V_DD− 9 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

100

UNIT

f_FR

LCD frame frequency (internal clock); note 1

external clock frequency

f_osc

150

225

kHz

Bus timing characteristics: Parallel Interface; notes 1 and 2

WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2116)

T_cy

enable cycle time

enable pulse width

address set-up time

address hold time

data set-up time

data hold time

500

220

−

PW_EH

t_ASU

t_AH

t_DSW

t_HD

READ OPERATION (READING DATA FROM PCF2116 TO MICROCONTROLLER)

T_cy

enable cycle time

enable pulse width

address set-up time

address hold time

data delay time

500

220

−

PW_EH

t_ASU

t_AH

−

t_DHD

t_HD

150

100

data hold time

Timing characteristics: I²C-bus interface; note 2

f_SCL

SCL clock frequency

tolerable spike width on bus

bus free time

−

100

−

kHz

µs

t_SW

−

t_BUF

4.7

t_SU;STA

t_HD;STA

t_LOW

t_HIGH

t_r

set-up time for a repeated START condition

START condition hold time

SCL LOW time

−

4.7

−

SCL HIGH time

−

SCL and SDA rise time

SCL and SDA fall time

data set-up time

−

t_f

−

0.3

−

t_SU;DAT

t_HD;DAT

t_SU;STO

250

data hold time

−

set-up time for STOP condition

−

Notes

2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to

V_ILand V_IHwith an input voltage swing of V_SSto V_DD

V_DD= 5 V.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

17 TIMING CHARACTERISTICS

book, full pagewidth

IH1

IL1

IH1

IL1

R/W

IL1

IH1

IL1

DSW

IH1

IL1

Valid Data

DB0 to DB7

IL1

MLA798 - 1

Fig.29 Parallel bus write operation sequence; writing data from microcontroller to PCF2116.

dbook, full pagewidth

IH1

IL1

IH1

IL1

IH1

R/W

IH1

IL1

DHR

DDR

OH1

OL1

DB0 to DB7

OL1

MLA799 - 1

Fig.30 Parallel bus read operation sequence; reading data from PCF2116 to microcontroller.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

18 APPLICATION INFORMATION

handbook, 4 columns

P20

P21

P22

R/W

R1 to R32

LCD

P80CL51

PCF2116

C1 to C60

DB0 to DB7

P10 to P17

MGA812 - 1

Fig.31 Direct connection to 8-bit microcontroller; 8-bit bus.

handbook, 4 columns

R/W

P10

P11

P12

R1 to R32

LCD

P80CL51

PCF2116

C1 to C60

DB4 to DB7

P14 to P17

MGA813 - 1

Fig.32 Direct connection to 8-bit microcontroller; 4-bit bus.

R7 to R16

R25 to R32

handbook, full pagewidth

LCD

100 nF

R1 to R8

R17 to R24

2 x 24 CHARACTER

LCD DISPLAY

(SPLIT SCREEN)

OSC PCF2116

100

kΩ

C1 to C60

MGA816 - 1

DB0 to DB7 E RS R/W

Fig.33 Typical application using parallel interface.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

andbook, full pagewidth

LCD

R1 to R16

100 nF

2 x 24 CHARACTER

LCD DISPLAY

(SPLIT SCREEN)

R17 to R24

OSC PCF2116

100

kΩ

100

DD DD

C1 to C60

SA0

LCD

100 nF

R1 to R16

2 x 12 CHARACTER

LCD DISPLAY

OSC PCF2114

100

kΩ

C1 to C60

SA0

MGA817 - 1

SCL SDA

MASTER TRANSMITTER

PCF84C81

Fig.34 Application using I²C-bus interface.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

18.1 8-bit operation, 1-line display using internal

reset

18.3 8-bit operation, 2-line display

For a 2-line display, the cursor automatically moves from

the first to the second line after the 40^thdigit of the first line

has been written. Thus, if there are only 8 characters in the

first line, the DDRAM address must be set after the eighth

character is completed (see Table 7). Note that both lines

of the display are always shifted together; data does not

shift from one line to the other.

Table 6 shows an example of a 1-line display in 8-bit

operation. The PCF2116 functions must be set by the

‘Function set’ instruction prior to display. Since the display

data RAM can store data for 80 characters, the RAM can

be used for advertising displays when combined with

display shift operation. Since the display shift operation

changes display position only and DDRAM contents

remain unchanged, display data entered first can be

displayed when the Return Home operation is performed.

18.4 I²C operation, 1-line display

A control byte is required with most instructions

(see Table 8).

18.2 4-bit operation, 1-line display using internal

reset

18.5 Initializing by instruction

The program must set functions prior to 4-bit operation.

Table 5 shows an example. When power is turned on, 8-bit

operation is automatically selected and the PCF2116

attempts to perform the first write as an 8-bit operation.

Since nothing is connected to DB0 to DB3, a rewrite is

then required. However, since one operation is completed

in two accesses of 4-bit operation, a rewrite is required to

set the functions (see Table 5 step 3).

If the power supply conditions for correctly operating the

internal reset circuit are not met, the PCF2116 must be

initialized by instruction. Tables 9 and 10 show how this

may be performed for 8-bit and 4-bit operation.

Thus, DB4 to DB7 of the function set are written twice.

Table 5 4-bit operation, 1-line display example; using internal reset

STEP

INSTRUCTION

DISPLAY

OPERATION

power supply on (PCF2116 is initialized by

the internal reset circuit)

Initialized. No display appears.

function set

R/W DB7 DB6 DB5 DB4

Sets to 4-bit operation. In this instance operation

is handled as 8-bits by initialization and only this

instruction completes with one write.

function set

Sets to 4-bit operation, selects 1-line display and

V_LCD= V₀. 4-bit operation starts from this point

and resetting is needed.

display on/off control

Turns on display and cursor. Entire display is

blank after initialization.

entry mode set

Sets mode to increment the address by 1 and to

shift the cursor to the right at the time of write to

the DD/CGRAM. Display is not shifted.

write data to CGRAM/DDRAM

Writes ‘P’. The DDRAM has already been

selected by initialization at power-on. The cursor

is incremented by 1 and shifted to the right.

1997 Apr 07

Table 6 8-bit operation, 1-line display example; using internal reset (character set ‘A’)

STEP

INSTRUCTION

DISPLAY

OPERATION

Initialized. No display appears.

power supply on (PCF2116 is initialized by the internal reset

function)

function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Sets to 8-bit operation, selects 1-line display and

V_LCD= V₀.

display mode on/off control

Turns on display and cursor. Entire display is blank after

initialization.

entry mode set

Sets mode to increment the address by 1 and to shift the

cursor to the right at the time of the write to the

DD/CGRAM. Display is not shifted.

write data to CGRAM/DDRAM

Writes ‘P’. The DDRAM has already been selected by

initialization at power-on. The cursor is incremented by 1

and shifted to the right.

write data to CGRAM/DDRAM

PH_

Writes ‘H’.

write data to CGRAM/DDRAM

PHILIPS_

Writes ‘S’.

entry mode set

Sets mode for display shift at the time of write.

Writes space.

write data to CGRAM/DDRAM

PHILIPS M_ Writes ‘M’.

STEP

INSTRUCTION

DISPLAY

OPERATION

write data to CGRAM/DDRAM

MICROKO

ICROCO

Writes ‘O’.

cursor or display shift

Shifts only the cursor position to the left.

Writes ‘C’ correction. The display moves to the left.

Shifts the display and cursor to the right.

Shifts only the cursor to the right.

Writes ‘M’.

cursor or display shift

write data to CGRAM/DDRAM

cursor or display shift

MICROCO

MICROCO_

Z18

cursor or display shift

write data to CGRAM/DDRAM

ICROCOM_

Return Home

PHILIPS M

Returns both display and cursor to the original position

(address 0).

Table 7 8-bit operation, 2-line display example; using internal reset

STEP

INSTRUCTION

DISPLAY

OPERATION

Initialized. No display appears.

power supply on (PCF2116 is initialized by the internal reset

function)

function set

Sets to 8-bit operation, selects 2-line display and voltage

generator off.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

display on/off control

Turns on display and cursor. Entire display is blank after

initialization.

entry mode set

Sets mode to increment the address by 1 and to shift the

cursor to the right at the time of write to the CG/DDRAM.

Display is not shifted.

Write data to CGRAM/DDRAM

Writes ‘P’. The DDRAM has already been selected by

initialization at power-on. The cursor is incremented by 1

and shifted to the right.

write data to CGRAM/DDRAM

Writes ‘S’.

PHILIPS_

set DDRAM address

Sets DDRAM address to position the cursor at the head of

the 2nd line.

PHILIPS

write data to CGRAM/ DDRAM

Writes ‘M’.

PHILIPS

STEP

INSTRUCTION

write data to CGRAM/ DDRAM

DISPLAY

PHILIPS

OPERATION

Writes ‘O’.

MICROCO_

write data to CGRAM/ DDRAM

Sets mode for display shift at the time of write.

PHILIPS

MICROCO_

write data to CGRAM/ DDRAM

Writes ‘M’. Display is shifted to the left. The ﬁrst and

second lines shift together.

PHILIPS

ICROCOM_

return Home

Returns both display and cursor to the original position

(address 0).

PHILIPS

MICROCOM

Table 8 Example of I²C operation; 1-line display (using internal reset, assuming SA0 = V_SS; note 1)

STEP

I²C BYTE

DISPLAY

OPERATION

Initialized. No display appears.

I²C START

slave address for write

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack

During the acknowledge cycle SDA will be pulled-down by the

PCF2116.

send a control byte for function set

Co RS R/W

Ack

Control byte sets RS and R/W for following data bytes.

function set

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

Selects 1-line display and V_LCD= V₀; SCL pulse during

acknowledge cycle starts execution of instruction.

display on/off control

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

Turns on display and cursor. Entire display shows character

Hex 20 (blank in ASCII-like character sets).

entry mode set

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

Sets mode to increment the address by 1 and to shift the cursor

to the right at the time of write to the DDRAM or CGRAM.

Display is not shifted.

I²C START

For writing data to DDRAM, RS must be set to 1. Therefore a

control byte is needed.

slave address for write

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack

send a control byte for write data

Co RS R/W

Ack

write data to DDRAM

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

Writes ‘P’. The DDRAM has been selected at power-up.

The cursor is incremented by 1 and shifted to the right.

STEP

I²C BYTE

DISPLAY

OPERATION

write data to DDRAM

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

Writes ‘H’.

PH_

12 to 15

write data to DDRAM

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

Writes ‘S’.

PHILIPS_

(optional I²C stop) I²C start + slave address for write

(as step 8)

control byte

Co RS R/W

Ack

PHILIPS_

PHILIPS

Return Home

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

Sets DDRAM address 0 in Address Counter. (also returns

shifted display to original position. DDRAM contents

unchanged). This instruction does not update the Data Register

control byte for read

Co RS R/W

Ack

DDRAM content will be read from following instructions.

The R/W has to be set to 1 while still in I²C-write mode.

PHILIPS

I²C START

slave address for read

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack

During the acknowledge cycle the content of the DR is loaded

into the internal I²C interface to be shifted out. In the previous

instruction neither a ‘Set address’ nor a ‘Read data’ has been

performed. Therefore the content of the DR was unknown.

PHILIPS

read data: 8 × SCL + master acknowledge; note 2

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

8 × SCL; content loaded into interface during previous

acknowledge cycle is shifted out over SDA. MSB is DB7. During

master acknowledge content of DDRAM address 01 is loaded

into the I²C interface.

STEP

I²C BYTE

DISPLAY

OPERATION

read data: 8 × SCL + master acknowledge; note 2

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

8 × SCL; code of letter ‘H’ is read ﬁrst. During master

acknowledge code of ‘I’ is loaded into the I²C interface.

PHILIPS

read data: 8 × SCL + no master acknowledge; note 2

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack

No master acknowledge; After the content of the I²C interface

data is loaded to the interface register, Data Register (DR) is not

updated, Address Counter (AC) is not incremented and cursor is

not shifted.

PHILIPS

I²C STOP

PHILIPS

Notes

1. X = don’t care.

2. SDA is left at high-impedance by the microcontroller during the READ acknowledge.

Table 9 Initialization by instruction, 8-bit interface (note 1)

STEP

DESCRIPTION

power-on or unknown state

wait 2 ms after V_DDrises above V_POR

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction.

Function set (interface is 8-bits long).

wait 2 ms

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction.

Function set (interface is 8-bits long).

wait more than 40 µs

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction.

Function set (interface is 8-bits long).

BF can be checked after the following instructions. When BF is not checked,

the waiting time between instructions is the speciﬁed instruction time (see

Table 3).

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set (interface is 8-bits long). Specify the number of display lines and

voltage generator characteristic.

Display off.

Clear display.

Entry mode set.

I/D

Initialization ends

Note

1. X = don’t care.

Table 10 Initialization by instruction, 4-bit interface. Not applicable for I²C-bus operation

STEP

DESCRIPTION

power-on or unknown state

wait 2 ms after V_DDrises above V_POR

R/W

DB7

DB6

DB5

DB4 BF cannot be checked before this instruction.

Function set (interface is 8-bits long).

wait 2 ms

R/W

DB7

DB6

DB5

DB4 BF cannot be checked before this instruction.

Function set (interface is 8-bits long).

wait 40 µs

R/W

DB7

DB6

DB5

DB4 BF cannot be checked before this instruction.

Function set (interface is 8-bits long).

BF can be checked after the following instructions. When BF is not checked, the waiting time

between instructions is the speciﬁed instruction time. (See Table 3).

R/W

DB7

DB6

DB5

DB4 Function set (set interface to 4-bits long).

Interface is 8-bits long.

Function set (interface is 4-bits long).

Specify number of display lines and voltage generator characteristic.

Display off.

Clear display.

Entry mode set.

I/D

Initialization ends

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

DISPLAY LAYOUT: COLUMNS

handbook, full pagewidth

PCF2116 column

output numbers

15 31

4545

3115

LCD column

numbers

120

PCF2116 column

output numbers

C16

3046

6060

46 30

DISPLAY LAYOUT: ROWS

R9 to R16

R8 to R1

MGA814 - 1

R17 to R24

R32 to R25

2 x 24 character display

Fig.35 Example of 2 × 24 display layout (PCF2116x).

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

DISPLAY LAYOUT: COLUMNS

15 46

handbook, full pagewidth

PCF2116 column

output numbers

LCD column

numbers

DOT MATRIX LCD

PCF2116 column

output numbers

C16

DISPLAY LAYOUT: ROWS

R8 to R1

R9 to R16

MGA815 - 2

R17 to R24

R32 to R25

Fig.36 Example of 4 × 12 display layout (PCF2114x/PCF2116x).

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

ook, full pagewidth

display glass

dot matrix

COLUMN LAYOUT

1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

ROW LAYOUT

1 to 8

16 to 9

MLB897

line by 24 characters display

Fig.37 Display example (PCF2114x); 1-line by 24 characters.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

book, full pagewidth

display glass

dot matrix

COLUMN LAYOUT

1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

ROW LAYOUT

1 to 8

16 to 9

MLB898

lines by 12 characters display

Fig.38 Display example (PCF2114x); 2-lines by 12 characters.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

handbook, full pagewidth

PCF2116

CHIP-ON-GLASS

4 LINE BY

R16

R17

R24

R25

R32

12 CHARACTER

2116

C60

MGA818 - 1

SCL

SDA

LCD

Fig.39 Chip on glass application.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

19 BONDING PAD LOCATIONS

handbook, full pagewidth

C30

C31

C32

C33

C34

C35

C36

C37

C38

C39

C40

C41

C42

C43

C44

C45

R24

R23

R22

R21

R20

R19

R18

R17

≈ 6.99

DB7

SCL

C46

C47

C48

C49

C50

C51

C52

C53

C54

C55

C56

C57

C58

C59

C60

R32

DB6

SDA

DB5

PCF2114

PCF2116

LCD1

DB4

LCD2

DB3

LCD3

DB2

MLB969

≈ 5.64 mm

Chip dimensions: approximately 5.64 × 6.99 mm.

Pad area: 0.0121 mm².

Bonding pad dimensions: 110 × 110 µm.

Fig.40 Bonding pad locations.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

Table 11 Bonding pad locations (dimensions in µm)

All x/y coordinates are referenced to centre of chip,

see Fig.40.

SYMBOL

C50

PAD

SYMBOL

OSC

PAD

2626

2339

2169

1999

1829

1659

1489

1319

1149

979

−1060

−890

−720

−550

−380

582

−2445

−2211

−2034

−1806

−1627

−1437

−1245

−1056

−867

−672

−486

−297

−3300

−3013

−2760

−2590

−2420

−2250

−2080

−1910

−1740

−1570

−1400

−1230

C49

C48

C47

C46

C45

C44

C43

C42

C41

C40

C39

C38

C37

C36

C35

C34

C33

C32

C31

C30

C29

C28

C27

C26

C25

C24

C23

C22

C21

C20

C19

C18

C17

C16

C15

C14

C13

DB1

V_DD2

DB0

V_DD1

SA0

752

922

V_SS1

R/W

1092

1262

1432

1602

1772

1942

2112

2282

2452

2622

2792

2962

3132

3302

V_SS2

R10

R11

R12

R13

R14

R15

R16

R25

R26

R27

R28

R29

R30

R31

R32

C60

C59

C58

C57

C56

C55

C54

C53

C52

C51

247

417

587

757

927

1097

1267

1436

1606

1776

1946

2116

2286

2456

2626

809

639

469

299

129

−245

−415

−585

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

SYMBOL

C12

PAD

−755

3302

3015

2846

2676

2506

2336

2166

1996

1826

1656

1487

1317

1147

977

C11

C10

−925

−1095

−1265

−1435

−1605

−1775

−1945

−2115

−2285

−2455

−2625

R24

R23

R22

R21

R20

R19

R18

R17

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

807

637

467

297

DB7

SCL

DB6

SDA

DB5

V₀

−290

−479

−716

−976

−1202

−1388

−1580

−1808

−1985

−2213

−2390

−2621

V_LCD1

DB4

V_LCD2

DB3

V_LCD3

DB2

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

20 PACKAGE OUTLINE

LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm

SOT425-1

102

103

(A )

w M

pin 1 index

detail X

128

w M

10 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 20.1 14.1

0.17 0.09 19.9 13.9

22.15 16.15

21.85 15.85

0.75 0.70

0.45 0.58

0.81 0.81

0.59 0.59

1.6

0.25

1.0

0.2 0.12 0.1

0.5

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

96-04-02

SOT425-1

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

If wave soldering cannot be avoided, the following

conditions must be observed:

21 SOLDERING

21.1 Introduction

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)

soldering technique should be used.

There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when

through-hole and surface mounted components are mixed

on one printed-circuit board. However, wave soldering is

not always suitable for surface mounted ICs, or for

printed-circuits with high population densities. In these

situations reflow soldering is often used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves

downstream and at the side corners.

Even with these conditions, do not consider wave

soldering LQFP packages LQFP48 (SOT313-2),

LQFP64 (SOT314-2) or LQFP80 (SOT315-1).

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

21.2 Reﬂow soldering

Reflow soldering techniques are suitable for all LQFP

packages.

Maximum permissible solder temperature is 260 °C, and

maximum duration of package immersion in solder is

10 seconds, if cooled to less than 150 °C within

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Several techniques exist for reflowing; for example,

thermal conduction by heated belt. Dwell times vary

between 50 and 300 seconds depending on heating

method. Typical reflow temperatures range from

215 to 250 °C.

21.4 Repairing soldered joints

Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron

(less than 24 V) applied to the flat part of the lead. Contact

time must be limited to 10 seconds at up to 300 °C. When

using a dedicated tool, all other leads can be soldered in

one operation within 2 to 5 seconds between

270 and 320 °C.

Preheating is necessary to dry the paste and evaporate

the binding agent. Preheating duration: 45 minutes at

45 °C.

21.3 Wave soldering

Wave soldering is not recommended for LQFP packages.

This is because of the likelihood of solder bridging due to

closely-spaced leads and the possibility of incomplete

solder penetration in multi-lead devices.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

22 DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

23 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

24 PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

NOTES

1997 Apr 07

Philips Semiconductors – a worldwide company

Argentina: see South America

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +31 40 27 82785, Fax. +31 40 27 88399

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. +64 9 849 4160, Fax. +64 9 849 7811

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. +43 1 60 101, Fax. +43 1 60 101 1210

Norway: Box 1, Manglerud 0612, OSLO,

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Belgium: see The Netherlands

Brazil: see South America

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,

Tel. +48 22 612 2831, Fax. +48 22 612 2327

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,

Tel. +359 2 689 211, Fax. +359 2 689 102

Portugal: see Spain

Romania: see Italy

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,

Tel. +1 800 234 7381

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. +7 095 755 6918, Fax. +7 095 755 6919

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. +65 350 2538, Fax. +65 251 6500

Colombia: see South America

Czech Republic: see Austria

Slovakia: see Austria

Slovenia: see Italy

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. +45 32 88 2636, Fax. +45 31 57 0044

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,

Tel. +27 11 470 5911, Fax. +27 11 470 5494

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. +358 9 615800, Fax. +358 9 61580920

South America: Rua do Rocio 220, 5th floor, Suite 51,

04552-903 São Paulo, SÃO PAULO - SP, Brazil,

Tel. +55 11 821 2333, Fax. +55 11 829 1849

France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

Spain: Balmes 22, 08007 BARCELONA,

Tel. +34 3 301 6312, Fax. +34 3 301 4107

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,

Tel. +46 8 632 2000, Fax. +46 8 632 2745

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. +30 1 4894 339/239, Fax. +30 1 4814 240

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. +41 1 488 2686, Fax. +41 1 481 7730

Hungary: see Austria

India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874

Indonesia: see Singapore

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,

Tel. +66 2 745 4090, Fax. +66 2 398 0793

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. +90 212 279 2770, Fax. +90 212 282 6707

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,

Tel. +1 800 234 7381

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Uruguay: see South America

Vietnam: see Singapore

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. +381 11 625 344, Fax.+381 11 635 777

Middle East: see Italy

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,

Internet: http://www.semiconductors.philips.com

Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

SCA54

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

417067/1200/04/pp64

Date of release: 1997 Apr 07

Document order number: 9397 750 01754

PCF2116AHZ [NXP]

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