PCF2129AT [NXP]
Integrated RTC, TCXO and quartz crystal; 集成RTC , TCXO和石英晶体型号: | PCF2129AT |
厂家: | NXP |
描述: | Integrated RTC, TCXO and quartz crystal |
文件: | 总68页 (文件大小:471K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PCF2129A
Integrated RTC, TCXO and quartz crystal
Rev. 01 — 13 January 2010
Product data sheet
1. General description
The PCF2129A is a CMOS1 real time clock and calendar with an integrated Temperature
Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal optimized
for very high accuracy and very low power consumption. The PCF2129A has a selectable
I2C-bus or SPI-bus, a backup battery switch-over circuit, a programmable watchdog
function, a timestamp function, and many other features.
2. Features
Temperature Compensated Crystal Oscillator (TCXO) with integrated capacitors
Accuracy: ±3 ppm from −15 °C to +60 °C
Integration of a 32.768 kHz quartz crystal and oscillator in the same package
Provides year, month, day, weekday, hours, minutes, and seconds
Timestamp function
with interrupt capability
detection of two different events on one multilevel input pin (e.g. for tamper
detection)
Two line bidirectional 1 MHz Fast-mode Plus (Fm+) I2C-bus interface (IOL = 20 mA at
pin SDA)
3 line SPI-bus with separate data input and output (maximum speed 6.5 Mbit/s)
Battery backup input pin and switch-over circuitry
Battery backed output voltage pin
Battery low detection function
Extra power fail detection function with input and output pins
Power-On Reset Override (PORO)
Oscillator stop detection function
Interrupt output (open-drain)
Programmable 1 second or 1 minute interrupt
Programmable watchdog timer with interrupt and reset capability
Programmable alarm function with interrupt capability
Programmable square wave open-drain output pin
Clock operating voltage: 1.2 V to 4.2 V
Low supply current: typical 0.65 μA at VDD = 3.0 V and Tamb = 25 °C
Automatic leap year correction
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 17.
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
3. Applications
Electronic metering for electricity, water, and gas
Timekeeping instruments with high precision
GPS equipment to reduce time to first fix
Applications that require an accurate process timing
Products with long automated unattended operation time
4. Ordering information
Table 1.
Ordering information
Type number Package
Name
Description
Version
PCF2129AT/1 SO20
plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
5. Marking
Table 2.
Marking codes
Type number
PCF2129AT/1
Marking code
PCF2129AT
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
2 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
6. Block diagram
INT
TCXO
TEMP
OSCI
Control_1
Control_2
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
DIVIDER
AND
TIMER
32.768 kHz
OSCO
Control_3
CLKOUT
BBS
Seconds
Minutes
internal
power
supply
Hours
1 Hz
V
DD
Days
BATTERY BACK UP
SWITCH-OVER
CIRCUITRY
V
BAT
Weekdays
Months
LOGIC
CONTROL
V
SS
Years
OSCILLATOR
MONITOR
Second_alarm
Minute_alarm
Hour_alarm
Day_alarm
Weekday_alarm
CLKOUT_ctl
Watchdg_ctl
Watchdg_val
Timestp_ctl
Sec_timestp
Min_timestp
Hour_timestp
Day_timestp
Mon_timestp
Year_timestp
Aging_offset
Internal_reg
Internal_reg
RESET
SPI-BUS
INTERFACE
ADDRESS
REGISTER
SDA/CE
SDO
SERIAL BUS
INTERFACE
SELECTOR
SDI
SCL
IFS
PCF2129A
2
I C-BUS
INTERFACE
R
PU
TS
TEMPERATURE
SENSOR
TEMP
001aaj703
Fig 1. Block diagram of PCF2129A
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
3 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
7. Pinning information
7.1 Pinning
1
2
20
19
18
17
16
15
14
13
12
11
SCL
SDI
V
V
DD
BAT
3
SDO
BBS
INT
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
4
SDA/CE
IFS
5
PCF2129A
6
TS
7
CLKOUT
8
V
SS
9
n.c.
n.c.
10
001aaj704
Top view. For mechanical details, see Figure 43.
Fig 2. Pin configuration for PCF2129A (SO20)
7.2 Pin description
Table 3.
Pin description of PCF2129A
Symbol
Pin
Description
SCL
1
combined serial clock input for both I2C-bus and SPI-bus; may
float when CE inactive
SDI
2
3
4
serial data input for SPI-bus; may float when CE inactive
SDO
serial data output for SPI-bus, push-pull
combined serial data input and output for the I2C-bus and chip
enable input (active LOW) for the SPI-bus
SDA/CE
IFS
5
interface selector input
connect to pin VSS to select the SPI-bus
connect to pin BBS to select the I2C-bus
timestamp input (active LOW) with 200 kΩ internal pull-up resistor
TS
6
(RPU
)
CLKOUT
VSS
7
clock output (open-drain)
8
ground supply voltage
n.c.
9 to 16
17
not connected; do not connect; do not use as feed through
interrupt output (open-drain; active LOW)
output voltage (battery backed)
battery supply voltage (backup)
supply voltage
INT
BBS
VBAT
VDD
18
19
20
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
4 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8. Functional description
The PCF2129A is a Real Time Clock and calendar (RTC) with an on-chip Temperature
Compensated crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal integrated
into the same package.
Address and data are transferred by a selectable 1 MHz Fast-mode Plus (Fm+) I2C-bus or
a 3 line SPI-bus with separate data input and output (see Section 9). The maximum speed
of the SPI-bus is 6.5 Mbit/s.
The PCF2129A contains 28 8-bit registers, that are used for many different functions,
such as clock, alarm, watchdog, timestamp etc. (see Section 8.1).
The PCF2129A has a backup battery input pin and backup battery switch-over circuit
which monitors the main power supply and automatically switches to the backup battery
when a power failure condition is detected (see Section 8.5.1). Accurate timekeeping is
maintained even when the main power supply is interrupted.
A battery low detection circuit monitors the status of the battery (see Section 8.5.3). When
the battery voltage goes below a threshold value, a flag is set to indicate that the battery
must be replaced soon. This ensures the integrity of the data during periods of battery
backup.
8.1 Register overview
The PCF2129A contains 28 8-bit registers (see Table 4) with an auto-incrementing
address register: the built-in address register will increment automatically after each read
or write of a data byte up to the register 1Bh. After register 1Bh the auto-incrementing will
wrap around to address 00h.
• The first three registers (memory address 00h, 01h, and 02h) are used as control
registers (see Section 8.2).
• The memory addresses 03h through to 09h are used as counters for the clock
function (seconds up to years). The date is automatically adjusted for months with
fewer than 31 days, including corrections for leap years. The clock can operate in
12-hour mode with an AM/PM indication or in 24-hour mode (see Section 8.8).
• Addresses 0Ah through 0Eh define the alarm function. It can be selected that an
interrupt is generated when an alarm event occurs (see Section 8.9).
• The register 0Fh defines the temperature measurement period and the clock out
mode. The temperature measurement can be selected from every 4 minutes (default)
down to every 30 seconds (see Table 9). CLKOUT frequencies of 32.768 kHz
(default) down to 1 Hz for use as a system clock, a microcontroller clock etc. can be
chosen (see Section 8.3.2).
• Address registers 10h and 11h are used for the watchdog timer functions. The
watchdog timer has four selectable source clocks allowing for timer periods from less
than 1 ms to greater than 4 hours. An interrupt will be generated when the watchdog
times out.
• Address registers 12h to 18h are used for the timestamp function. When the trigger
event happens, the actual time is saved in the timestamp registers (see Section 8.11).
• Address register 19h is used for the correction of the crystal aging effect (see
Section 8.4.1).
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
5 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
• Address registers 1Ah and 1Bh are for internal use only.
• The registers Seconds, Minutes, Hours, Days, Months, and Years are all coded in
Binary Coded Decimal (BCD) format to simplify application use. Other registers are
either bit-wise or standard binary.
address register
00h
01h
02h
03h
...
auto-increment
19h
1Ah
1Bh
wrap around
001aaj398
Fig 3. Handling address registers
When one of the RTC registers is read, the content of all counters is temporarily frozen.
This prevents a faulty reading of the clock and calendar during a carry condition (see
Section 8.8.8).
Table 4.
Register overview
Bit positions labeled as - are not implemented and will return 0 when read. Bits labeled as T must always be written with
logic 0. Bits labeled as X are undefined at power-on and unchanged by subsequent resets.
Address Register name
Bit
7
Reset value
6
5
4
3
2
1
0
Control registers
00h
Control_1
EXT_
TEST
T
STOP
TSF1
POR_
OVRD
12_24
MI
SI
0000 0000
01h
02h
Control_2
Control_3
MSF
WDTF TSF2
AF
T
TSIE
BLF
AIE
BIE
T
0000 0000
0000 0000
PWRMNG[2:0]
BTSE
BF
BLIE
Time and date registers
03h
04h
05h
Seconds
Minutes
Hours
OSF
SECONDS (0 to 59)
MINUTES (0 to 59)
1XXX XXXX
- XXX XXXX
- - XX XXXX
- - XX XXXX
- - XX XXXX
- - - - - XXX
- - - X XXXX
XXXX XXXX
-
-
-
AMPM HOURS (1 to 12) in 12 h mode
HOURS (0 to 23) in 24 h mode
DAYS (1 to 31)
06h
07h
08h
09h
Days
-
-
-
-
-
-
Weekdays
Months
Years
-
-
-
-
WEEKDAYS (0 to 6)
MONTHS (1 to 12)
YEARS (0 to 99)
Alarm registers
0Ah
0Bh
0Ch
Second_alarm
AE_S
AE_M
AE_H
SECOND_ALARM (0 to 59)
MINUTE_ALARM (0 to 59)
1XXX XXXX
1XXX XXXX
1 - XX XXXX
1 - XX XXXX
1 - XX XXXX
Minute_alarm
Hour_alarm
-
AMPM HOUR_ALARM (1 to 12) in 12 h mode
HOUR_ALARM (0 to 23) in 24 h mode
DAY_ALARM (1 to 31)
0Dh
0Eh
Day_alarm
AE_D
-
-
Weekday_alarm AE_W
-
-
-
WEEKDAY_ALARM (0 to 6) 1 - - - - XXX
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
6 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
Table 4.
Register overview …continued
Bit positions labeled as - are not implemented and will return 0 when read. Bits labeled as T must always be written with
logic 0. Bits labeled as X are undefined at power-on and unchanged by subsequent resets.
Address Register name
Bit
7
Reset value
6
5
4
-
3
-
2
1
0
CLKOUT control register
0Fh
CLKOUT_ctl
TCR[1:0]
-
COF[2:0]
-
00 - - - 000
Watchdog registers
10h
11h
Watchdg_tim_ctl WD_CD T
TI_TP
-
-
TF[1:0]
000 - - - 11
Watchdg_tim_val WATCHDG_TIM_VAL[7:0]
XXXX XXXX
Timestamp registers
12h
13h
14h
15h
Timestp_ctl
Sec_timestp
Min_timestp
Hour_timestp
TSM
TSOFF
-
1_O_16_TIMESTP[4:0]
00 - X XXXX
- XXX XXXX
- XXX XXXX
- - XX XXXX
- - XX XXXX
- - XX XXXX
- - - X XXXX
XXXX XXXX
-
-
-
SECOND_TIMESTP (0 to 59)
MINUTE_TIMESTP (0 to 59)
-
AMPM HOUR_TIMESTP (1 to 12) in 12 h mode
HOUR_TIMESTP (0 to 23) in 24 h mode
DAY_TIMESTP (1 to 31)
16h
17h
18h
Day_timestp
Mon_timestp
Year_timestp
-
-
-
-
-
MONTH_TIMESTP (1 to 12)
YEAR_TIMESTP (0 to 99)
Aging offset register
19h Aging_offset
Internal registers
-
-
-
-
AO[3:0]
- - - - 1000
1Ah
1Bh
Internal_reg
Internal_reg
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- - - - - - - -
- - - - - - - -
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
7 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.2 Control registers
PCF2129A has 28 8-bit registers. The first 3 registers with the addresses 00h, 01h, and
02h are used as control registers.
8.2.1 Register Control_1
Table 5.
Bit
Control_1 - control and status register 1 (address 00h) bit description
Symbol
Value
Description
Reference
[1]
7
EXT_TEST
0
1
0
0
1
normal mode
Section 8.13
external clock test mode
unused
[2]
[1]
6
5
T
-
STOP
RTC source clock runs
RTC clock is stopped;
Section 8.14
RTC divider chain flip-flops are
asynchronously set logic 0;
CLKOUT at 32.768 kHz, 16.384 kHz, or
8.192 kHz is still available
[1]
4
3
TSF1
0
1
no timestamp interrupt generated
Section 8.11.1
Section 8.7.2
flag set when TS input is driven to an
intermediate level between power supply and
ground;
flag must be cleared to clear interrupt
POR_OVRD
0
Power-On Reset Override (PORO) facility
disabled;
set logic 0 for normal operation
PORO enabled
[1]
[1]
1
0
1
0
1
0
1
2
1
0
12_24
MI
24 hour mode selected
12 hour mode selected
minute interrupt disabled
minute interrupt enabled
second interrupt disabled
second interrupt enabled
Table 18
[1]
[1]
Section 8.12.1
SI
[1] Default value.
[2] When writing to the register this bit has always to be set logic 0.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
8 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.2.2 Register Control_2
Table 6.
Control_2 - control and status register 2 (address 01h) bit description
Bit
Symbol
Value
Description
Reference
[1]
7
MSF
0
1
no minute or second interrupt generated
Section 8.12
flag set when minute or second interrupt
generated;
flag must be cleared to clear interrupt
[1]
6
WDTF
0
1
no watchdog timer interrupt or reset
generated
Section 8.12.3
flag set when watchdog timer interrupt or
reset generated;
flag cannot be cleared by using the
interface (read-only)
[1]
[1]
5
4
TSF2
AF
0
1
no timestamp interrupt generated
flag set when TS input is driven to ground;
flag must be cleared to clear interrupt
no alarm interrupt generated
Section 8.11.1
Section 8.9.6
0
1
flag set when alarm triggered;
flag must be cleared to clear interrupt
unused
[2]
[1]
3
2
T
0
0
1
0
1
0
-
TSIE
no interrupt generated from timestamp flag
interrupt generated when timestamp flag set
no interrupt generated from the alarm flag
interrupt generated when alarm flag set
unused
Section 8.12.5
[1]
[2]
1
0
AIE
T
Section 8.12.4
-
[1] Default value.
[2] When writing to the register this bit has always to be set logic 0.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
9 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.2.3 Register Control_3
Table 7.
Bit
Control_3 - control and status register 3 (address 0Fh) bit description
Symbol
Value
Description
Reference
[1]
7 to 5 PWRMNG[2:0]
control of the battery switch-over, battery low Section 8.5
detection, and extra power fail detection
functions
[2]
4
BTSE
0
1
no timestamp when battery switch-over
occurs
Section 8.11.4
time-stamped when battery switch-over
occurs
[2]
[2]
3
2
BF
0
1
no battery switch-over interrupt generated
flag set when battery switch-over occurs;
flag must be cleared to clear interrupt
battery status ok;
Section 8.5.1
Section 8.5.3
BLF
0
1
0
no battery low interrupt generated
battery status low;
flag cannot be cleared using the interface
[2]
[2]
1
0
BIE
no interrupt generated from the battery
flag (BF)
Section 8.12.6
Section 8.12.7
1
0
interrupt generated when BF is set
BLIE
no interrupt generated from battery low
flag (BLF)
1
interrupt generated when BLF is set
[1] Values see Table 13.
[2] Default value.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
10 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.3 Register CLKOUT_ctl
Table 8.
CLKOUT_ctl - CLKOUT control register (address 03h) bit description
Symbol Value Description
see Table 9 temperature measurement period
unused
see Table 10 CLKOUT frequency selection
Bit
7 to 6 TCR[1:0]
5 to 3 -
-
2 to 0 COF[2:0]
8.3.1 Temperature compensated crystal oscillator
The frequency of tuning fork quartz crystal oscillators are temperature-dependent. In the
PCF2129A the frequency drift caused by temperature variation is corrected by adjusting
the load capacitance of the crystal oscillator.
The load capacitance is changed by switching between two load capacitance values using
a modulation signal with a programmable duty cycle. Every chip is calibrated in order to
produce, at the measured temperature, the correct duty cycle which compensates for the
frequency shift.
The frequency accuracy can be evaluated by measuring the frequency of the square
wave signal available at the output pin CLKOUT. However, the selection of
fCLKOUT = 32.768 kHz (default value) leads to inaccurate measurements. The most
accurate frequency measurement occurs when fCLKOUT = 1 Hz is selected (see Table 10).
8.3.1.1 Temperature measurement
The PCF2129A has a temperature sensor circuit used to perform the temperature
compensation of the frequency. The temperature is measured immediately after power-on
and then periodically with a period set by the temperature conversion rate TCR[1:0] in the
register CLKOUT_ctl.
Table 9.
Temperature measurement period
Temperature measurement period
TCR[1:0]
[1]
00
01
10
11
4 min
2 min
1 min
30 seconds
[1] Default value.
8.3.2 Clock output
A programmable square wave is available at pin CLKOUT. Operation is controlled by the
COF control bits in register CLKOUT_ctl. Frequencies of 32.768 kHz (default) down to
1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge
pump, or for calibration of the oscillator.
CLKOUT is an open-drain output and enabled at power-on. When disabled, the output is
high-impedance.
The duty cycle of the selected clock is not controlled, however, due to the nature of the
clock generation, all but the 32.768 kHz frequencies will be 50 : 50.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
11 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
Table 10. CLKOUT frequency selection
COF[2:0]
CLKOUT frequency (Hz)
Typical duty cycle[1]
000
001
010
011
100
101
110
111
32768
60 : 40 to 40 : 60
50 : 50
50 : 50
50 : 50
50 : 50
50 : 50
50 : 50
-
16384
8192
4096
2048
1024
1
CLKOUT = high-Z
[1] Duty cycle definition: % HIGH-level time : % LOW-level time.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
12 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.4 Register Aging_offset
Table 11. Aging_offset - crystal aging offset register (address 19h) bit description
Bit
Symbol
Value
Description
7 to 4 -
-
unused
3 to 0 AO[3:0]
see Table 12 aging offset value
8.4.1 Crystal aging correction
The PCF2129A has an aging offset register Aging_offset to correct the crystal aging
effects2.
The accuracy of the frequency of a quartz crystal depends on the aging. Crystal suppliers
usually specify the first year aging (typically ±1 ppm, maximum ±3 ppm) and/or the 10
years aging (typically ±5 ppm). The aging offset adds an offset, positive or negative, in the
temperature compensation circuits which allows to correct the aging effect.
The change in ppm per AO[3:0] value is different at different temperatures. At 25 °C, the
aging offset bits allow a frequency correction of typically 1 ppm per AO[3:0] value, from
−7 ppm to +8 ppm.
Table 12. Frequency correction at 25 °C, typical
AO[3:0]
ppm
Decimal
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
+8
+7
+6
+5
+4
+3
+2
+1
0
1
2
3
4
5
6
7
[1]
8
9
−1
−2
−3
−4
−5
−6
−7
10
11
12
13
14
15
[1] Default value.
2. For further information please refer to the application note Ref. 3 “AN10857”.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
13 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.5 Power management functions
The PCF2129A has two power supply pins and one power output pin:
• VDD - the main power supply input pin
• VBAT - the battery backup input pin
• BBS - battery backed output voltage pin (equal to the internal power supply)
The PCF2129A has two power management functions implemented:
• Battery switch-over function
• Battery low detection function
The power management functions are controlled by the control bits PWRMNG[2:0] in
register Control_3:
Table 13. Power management control bit description
PWRMNG[2:0]
Function
[1]
000
battery switch-over function is enabled in standard mode;
battery low detection function is enabled
001
010
011
100
101
111
battery switch-over function is enabled in standard mode;
battery low detection function is disabled
battery switch-over function is enabled in standard mode;
battery low detection function is disabled
battery switch-over function is enabled in direct switching mode;
battery low detection function is enabled
battery switch-over function is enabled in direct switching mode;
battery low detection function is disabled
battery switch-over function is enabled in direct switching mode;
battery low detection function is disabled
[2]
battery switch-over function is disabled, only one power supply (VDD);
battery low detection function is disabled
[1] Default value.
[2] When the battery switch-over function is disabled, the PCF2129A works only with the power supply VDD
;
V
BAT must be put to ground and the battery low detection function is disabled.
8.5.1 Battery switch-over function
The PCF2129A has a backup battery switch-over circuit which monitors the main power
supply VDD and automatically switches to the backup battery when a power failure
condition is detected.
One of two operation modes can be selected:
• Standard mode: the power failure condition happens when:
V
DD < VBAT AND VDD < Vth(sw)bat
• Direct switching mode: the power failure condition happens when VDD < VBAT
.
Direct switching from VDD to VBAT without requiring VDD to drop below Vth(sw)bat
Vth(sw)bat is the battery switch threshold voltage. Typical value is 2.5 V.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
14 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
When a power failure condition occurs and the power supply switches to the battery the
following sequence occurs:
1. The battery switch flag BF (register Control_3) is set logic 1.
2. An interrupt is generated if the control bit BIE (register Control_3) is enabled
(see Section 8.12.6).
3. If the control bit BTSE (register Control_3) is logic 1, the timestamp registers store the
time and date when the battery switch occurred (see Section 8.11.4).
4. The battery switch flag BF is cleared via the interface; it must be cleared to clear the
interrupt.
The interface is disabled in battery backup operation:
• Interface inputs are not recognized, preventing extraneous data being written to the
device
• Interface outputs are high-impedance
8.5.1.1 Standard mode
If VDD > VBAT OR VDD > Vth(sw)bat the internal power supply is VDD
.
If VDD < VBAT AND VDD < Vth(sw)bat the internal power supply is VBAT
.
backup battery operation
V
DD
V
BBS
V
BBS
V
BAT
internal power supply (= V
)
BBS
V
th(sw)bat
(= 2.5 V)
V
(= 0 V)
DD
BF
INT
cleared via interface
001aaj311
Fig 4. Battery switch-over behavior in standard mode with bit BIE logic 1 (enabled)
8.5.1.2 Direct switching mode
If VDD > VBAT the internal power supply is VDD
.
If VDD < VBAT the internal power supply is VBAT
.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
15 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
The direct switching mode is useful in systems where VDD is higher than VBAT at all times.
The direct switching mode is not recommended if the VDD and VBAT values are similar
(e.g. VDD = 3.3 V, VBAT ≥ 3.0 V). In direct switching mode the power consumption is
reduced compared to the standard mode because the monitoring of VDD and Vth(sw)bat is
not performed.
backup battery operation
V
DD
V
BBS
V
BBS
V
BAT
internal power supply (= V
)
BBS
V
th(sw)bat
(= 2.5 V)
V
(= 0 V)
DD
BF
INT
cleared via interface
001aaj312
Fig 5. Battery switch-over behavior in direct switching mode with bit BIE logic 1
(enabled)
8.5.1.3 Battery switch-over disabled: only one power supply (VDD
)
When the battery switch-over function is disabled:
• The power supply is applied on the VDD pin
• The VBAT pin must be connected to ground
• The internal power supply, available at the output pin BBS, is equal to VDD
• The battery flag (BF) is always logic 0
8.5.1.4 Battery switch-over architecture
The architecture of the battery switch-over circuit is shown in Figure 6.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
16 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
comparators
logic
switches
V
DD(int)
V
CC
V
DD
V
V
th(sw)bat
V
DD
V
DD(int)
V
BBS
LOGIC
V
CC
(internal
power supply)
th(sw)bat
V
BAT
V
BAT
001aag061
V
DD(int)
Fig 6. Battery switch-over circuit, simplified block diagram
The internal power supply (available on pin BBS) is equal to VDD or VBAT. It has to be
assured that there are decoupling capacitors on the pins VDD, VBAT, and BBS.
8.5.2 Battery backup supply
The VBBS voltage on the output pin BBS is equal to the internal power supply and depends
on the selected battery switch-over function mode:
Table 14. Output pin BBS
Battery switch-over function mode
Conditions
VBBS equals
VDD
standard
VDD > VBAT OR VDD > Vth(sw)bat
VDD < VBAT AND VDD < Vth(sw)bat
VDD > VBAT
VBAT
direct switching
disabled
VDD
VDD < VBAT
VBAT
only VDD available,
VDD
VBAT must be put to ground
001aaj431
0
V
− V
DD
BBS
(mV)
−200
V
V
= 3 V
= 2 V
DD
−400
−600
−800
DD
0
2
4
6
8
I
(mA)
BBS
Fig 7. Typical driving capability of VBBS: (VBBS − VDD) with respect to the output load
current IBBS
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
17 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
The output pin BBS can be used as a supply for battery backup devices such as SRAM
(see Ref. 3 “AN10857”). For this case, Figure 7 shows the typical driving capability when
V
BBS is driven from VDD.
8.5.3 Battery low detection function
The PCF2129A has a battery low detection circuit which monitors the status of the battery
VBAT
.
When VBAT drops below the threshold value Vth(bat)low (typically 2.5 V) the BLF flag
(register Control_3) is set to indicate that the battery is low and that it must be replaced. A
low battery will not ensure data integrity during periods of backup battery operation.
Monitoring of the battery voltage also occurs during battery operation.
When VBAT drops below the threshold value Vth(bat)low, the following sequence occurs (see
Figure 8):
1. The battery low flag BLF is set logic 1.
2. An interrupt is generated if the control bit BLIE (register Control_3) is enabled
(see Section 8.12.7).
3. The flag BLF remains logic 1 until the battery is replaced. BLF cannot be cleared
using the interface. It is cleared automatically by the battery low detection circuit when
the battery is replaced.
V
DD
= V
BBS
internal power supply (= V
)
BBS
V
BAT
V
th(bat)low
(= 2.5 V)
V
BAT
BLF
INT
001aaj322
Fig 8. Battery low detection behavior with bit BLIE logic 1 (enabled)
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
18 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.6 Oscillator stop detection function
The PCF2129A has an on-chip oscillator detection circuit which monitors the status of the
oscillation: whenever the oscillation stops, a reset occurs and the oscillator stop flag OSF
(in register Seconds) is set logic 1.
• Power-on:
a. The oscillator is not running, the chip is in reset (OSF is logic 1).
b. When the oscillator starts running and is stable after power-on, the chip exits from
reset.
c. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) via the interface.
• Power supply failure:
a. When the power supply of the chip (VDD or VBAT) drops below a certain value
(Vlow), typically 1.2 V, the oscillator stops running and a reset occurs.
b. When the power supply returns to normal operation, the oscillator starts running
again, the chip exits from reset.
c. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) via the interface.
V
DD
V
DD
V
BBS
V
BAT
V
BBS
V
BBS
V
th(sw)bat
(= 2.5 V)
V
battery discharge
internal power supply
BBS
V
low
(= 1.2 V)
V
BAT
V
SS
V
SS
(1)
(2)
OSF
001aaj409
(1) Theoretical state of the signals since there is no power.
(2) The oscillator stop flag (OSF), set logic 1, indicates that the oscillation has stopped and a reset has
occurred since the flag was last cleared (OSF set logic 0). In this case the integrity of the clock
information is not guaranteed. The OSF flag is cleared using the interface.
Fig 9. Power failure event due to battery discharge: reset occurs
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
19 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.7 Reset function
The PCF2129A has a Power-On Reset (POR) and a Power-On Reset Override (PORO)
function implemented.
8.7.1 Power-On Reset (POR)
The POR is active whenever the oscillator is stopped. The oscillator is also considered to
be stopped during the time between power-on and stable crystal resonance (see
Figure 10). This time may be in the range of 200 ms to 2 s depending on temperature and
supply voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF set
logic 1).
chip in reset
chip not in reset
V
DD
oscillation
internal
reset
t
001aaf897
Fig 10. Dependency between POR and oscillator
After POR, the following mode is entered:
• 32.768 kHz CLKOUT active
• Power-On Reset Override (PORO) available to be set
• 24 hour mode is selected
• Battery switch-over is enabled
• Battery low detection is enabled
The register values after power-on are shown in Table 4.
8.7.2 Power-On Reset Override (PORO)
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a mechanism has been built in to
disable the POR and hence speed up on-board test of the device.
osc stopped
0 = stopped, 1 = running
OSCILLATOR
reset
SCL
RESET
OVERRIDE
0 = override inactive
1 = override active
SDA/CE
CLEAR
0 = clear override mode
1 = override possible
POR_OVRD
001aaj324
Fig 11. Power-On Reset (POR) system
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
20 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
The setting of the PORO mode requires that POR_OVRD in register Control_1 is set logic
1 and that the signals at the interface pins SDA/CE and SCL are toggled as illustrated in
Figure 12. All timings shown are required minimums.
power up
8 ms
minimum 500 ns
minimum 2000 ns
SDA/CE
SCL
reset override
001aaj326
Fig 12. Power-On Reset Override (PORO) sequence, valid for both I2C-bus and SPI-bus
Once the override mode is entered, the device is immediately released from the reset
state and the set-up operation can commence.
The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be
logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0
during normal operation has no effect except to prevent accidental entry into the PORO
mode.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
21 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.8 Time and date function
The majority of this registers are coded in the Binary Coded Decimal (BCD) format.
8.8.1 Register Seconds
Table 15. Seconds - seconds and clock integrity register (address 03h) bit description
Bit
Symbol
Value
Place value Description
7
OSF
0
1[1]
-
-
clock integrity is guaranteed
clock integrity is not guaranteed:
oscillator has stopped and chip reset
has occurred since flag was last cleared
6 to 4 SECONDS
3 to 0
0 to 5
0 to 9
ten’s place actual seconds coded in BCD format
unit place
[1] Start-up value.
Table 16. Seconds coded in BCD format
Seconds value in Upper-digit (ten’s place)
decimal
Digit (unit place)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
01
02
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
1
:
0
1
0
:
09
10
:
0
0
:
0
0
:
0
1
:
1
0
:
0
0
:
0
0
:
1
0
:
58
59
1
1
0
0
1
1
1
1
0
0
0
0
0
1
8.8.2 Register Minutes
Table 17. Minutes - minutes register (address 04h) bit description
Bit
Symbol
Value
-
Place value Description
- unused
7
-
6 to 4 MINUTES
3 to 0
0 to 5
0 to 9
ten’s place actual minutes coded in BCD format
unit place
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
22 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.8.3 Register Hours
Table 18. Hours - hours register (address 05h) bit description
Bit
Symbol
Value
Place value Description
7 to 6 -
-
-
unused
12 hour mode[1]
5
AMPM
0
-
-
indicates AM
indicates PM
1
4
HOURS
0 to 1
0 to 9
ten’s place actual hours coded in BCD format when in
12 hour mode
3 to 0
unit place
24 hour mode[1]
5 to 4 HOURS
3 to 0
0 to 2
0 to 9
ten’s place actual hours coded in BCD format when in
24 hour mode
unit place
[1] Hour mode is set by the bit 12_24 in register Control_1.
8.8.4 Register Days
Table 19. Days - days register (address 06h) bit description
Bit
Symbol
Value
-
Place value Description
- unused
7 to 6 -
5 to 4 DAYS[1]
0 to 3
0 to 9
ten’s place actual day coded in BCD format
unit place
3 to 0
[1] The RTC compensates for leap years by adding a 29th day to February if the year counter contains a value
which is exactly divisible by 4, including the year 00.
8.8.5 Register Weekdays
Table 20. Weekdays - weekdays register (address 07h) bit description
Bit
Symbol
Value
-
Description
7 to 3 -
unused
2 to 0 WEEKDAYS
0 to 6
actual weekday value, see Table 21
Although the association of the weekdays counter to the actual weekday is arbitrary, the
PCF2129A will assume Sunday is 000 and Monday is 001 for the purposes of determining
the increment for calendar weeks.
Table 21. Weekday assignments
Day[1]
Bit
2
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
Sunday
0
Monday
Tuesday
Wednesday
Thursday
Friday
0
0
0
1
1
Saturday
1
[1] These bits may be re-assigned by the user.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
23 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.8.6 Register Months
Table 22. Months - months register (address 08h) bit description
Bit
Symbol
Value
-
Place value Description
unused
7 to 5 -
-
4
MONTHS
0 to 1
0 to 9
ten’s place actual month coded in BCD format, see
Table 23
3 to 0
unit place
Table 23. Month assignments in BCD format
Month
Upper-digit
(ten’s place)
Digit (unit place)
Bit 4
0
Bit 3
0
Bit 2
Bit 1
0
Bit 0
1
January
February
March
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
April
0
0
0
0
May
0
0
0
1
June
0
0
1
0
July
0
0
1
1
August
September
October
November
December
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
1
0
1
0
8.8.7 Register Years
Table 24. Years - years register (address 09h) bit description
Bit
Symbol
Value
0 to 9
0 to 9
Place value Description
7 to 4 YEARS
3 to 0
ten’s place actual year coded in BCD format
unit place
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
24 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.8.8 Setting and reading the time
Figure 13 shows the data flow and data dependencies starting from the 1 Hz clock tick.
1 Hz tick
SECONDS
MINUTES
12_24 hour mode
HOURS
DAYS
LEAP YEAR
CALCULATION
WEEKDAY
MONTHS
YEARS
001aaf901
Fig 13. Data flow of the time function
During read/write operations, the time counting circuits (memory locations 03h through
09h) are blocked.
This prevents
• Faulty reading of the clock and calendar during a carry condition
• Incrementing the time registers during the read cycle
After this read/write access is completed, the time circuit is released again and any
pending request to increment the time counters that occurred during the read/write access
is serviced. A maximum of 1 request can be stored; therefore, all accesses must be
completed within 1 second (see Figure 14).
t < 1 s
SLAVE ADDRESS
DATA
DATA
STOP
START
013aaa215
Fig 14. Access time for read/write operations
As a consequence of this method, it is very important to make a read or write access in
one go, that is, setting or reading seconds through to years should be made in one single
access. Failing to comply with this method could result in the time becoming corrupted.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
25 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
As an example, if the time (seconds through to hours) is set in one access and then in a
second access the date is set, it is possible that the time may increment between the two
accesses. A similar problem exists when reading. A roll over may occur between reads
thus giving the minutes from one moment and the hours from the next. Therefore it is
advised to read all time and date registers in one access.
8.9 Alarm function
When one or more of the alarm bit fields are loaded with a valid second, minute, hour, day,
or weekday and its corresponding alarm enable bit (AE_x) is logic 0, then that information
is compared with the actual second, minute, hour, day, and weekday (see Figure 15).
example
check now signal
AE_S
AE_M
AE_H
AE_D
AE_W
AE_S = 1
SECOND ALARM
SECOND TIME
=
=
1
0
MINUTE ALARM
MINUTE TIME
HOUR ALARM
HOUR TIME
=
=
=
(1)
set alarm flag AF
DAY ALARM
DAY TIME
WEEKDAY ALARM
WEEKDAY TIME
013aaa236
(1) Only when all enabled alarm settings are matching.
Fig 15. Alarm function block diagram
The generation of interrupts from the alarm function is described in Section 8.12.4.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
26 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.9.1 Register Second_alarm
Table 25. Second_alarm - second alarm register (address 0Ah) bit description
Bit
Symbol
Value
Place value Description
7
AE_S
0
1[1]
-
-
second alarm is enabled
second alarm is disabled
6 to 4 SECOND_ALARM
3 to 0
0 to 5
0 to 9
ten’s place second alarm information coded in BCD
format
unit place
[1] Default value.
8.9.2 Register Minute_alarm
Table 26. Minute_alarm - minute alarm register (address 0Bh) bit description
Bit
Symbol
Value
Place value Description
7
AE_M
0
1[1]
-
-
minute alarm is enabled
minute alarm is disabled
6 to 4 MINUTE_ALARM
3 to 0
0 to 5
0 to 9
ten’s place minute alarm information coded in BCD
format
unit place
[1] Default value.
8.9.3 Register Hour_alarm
Table 27. Hour_alarm - hour alarm register (address 0Ch) bit description
Bit
Symbol
Value
Place value Description
7
AE_H
0
1[1]
-
-
-
hour alarm is enabled
hour alarm is disabled
unused
6
-
-
12 hour mode[2]
5
AMPM
0
-
-
indicates AM
indicates PM
1
4
HOUR_ALARM
0 to 1
0 to 9
ten’s place hour alarm information coded in BCD
format when in 12 hour mode
3 to 0
unit place
24 hour mode[2]
5 to 4 HOUR_ALARM
3 to 0
0 to 2
0 to 9
ten’s place hour alarm information coded in BCD
format when in 24 hour mode
unit place
[1] Default value.
[2] Hour mode is set by the bit 12_24 in register Control_1.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
27 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.9.4 Register Day_alarm
Table 28. Day_alarm - day rearm register (address 0Dh) bit description
Bit
Symbol
Value
Place value Description
7
AE_D
0
1[1]
-
-
-
day alarm is enabled
day alarm is disabled
unused
6
-
-
5 to 4 DAY_ALARM
3 to 0
0 to 3
0 to 9
ten’s place day alarm information coded in BCD
format
unit place
[1] Default value.
8.9.5 Register Weekday_alarm
Table 29. Weekday_alarm - weekday alarm register (address 0Eh) bit description
Bit
Symbol
Value
Description
7
AE_W
0
weekday alarm is enabled
weekday alarm is disabled
unused
1[1]
-
6 to 3 -
2 to 0 WEEKDAY_ALARM
0 to 6
weekday alarm information
[1] Default value.
8.9.6 Alarm flag
When all enabled comparisons first match, the alarm flag AF (register Control_2) is set.
AF will remain set until cleared by using the interface. Once AF has been cleared it will
only be set again when the time increments to match the alarm condition once more. For
clearing the flags see Section 8.10.5
Alarm registers which have their alarm enable bit AE_x at logic 1 are ignored.
minutes counter
minute alarm
AF
44
45
45
46
INT when AIE = 1
001aaf903
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 16. Alarm flag timing diagram
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
28 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.10 Timer functions
The PCF2129A has a watchdog timer function. The timer can be selected by using the
control bit WD_CD in the register Watchdg_tim_ctl.
The watchdog timer has four selectable source clocks. It can be used to detect a
microprocessor with interrupt and reset capability which is out of control (see
Section 8.10.3)
To control the timer function and timer output, the registers Control_2, Watchdg_tim_ctl,
and Watchdg_tim_val are used.
8.10.1 Register Watchdg_tim_ctl
Table 30. Watchdg_tim_ctl - watchdog timer control register (address 10h) bit description
Bit
Symbol
Value
0[1]
1
Description
7
WD_CD
watchdog timer disabled
watchdog timer enabled;
the interrupt pin INT is activated when timed out
unused
6
5
T
0[2]
0[1]
TI_TP
the interrupt pin INT is configured to generate a
permanent active signal when MSF (register Control_2)
is set
1
-
the interrupt pin INT is configured to generate a pulsed
signal when MSF flag is set (see Figure 19)
4 to 2
unused
1 to 0 TF[1:0]
timer source clock for watchdog timer
00
4.096 kHz
64 Hz
01
10
1 Hz
1
11[1]
⁄60 Hz
[1] Default value.
[2] When writing to the register this bit has always to be set logic 0.
8.10.2 Register Watchdg_tim_val
Table 31. Watchdg_tim_val - watchdog timer value register (address 11h) bit description
Bit
Symbol
Value
Description
7 to 0 WATCHDG_TIM_VAL[7:0] 00 to FF countdown period in seconds:
n
--------------------------------------------------------------
CountdownPeriod =
SourceClockFrequency
where n is the countdown value
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
29 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
Table 32. Programmable watchdog timer
TF[1:0] Timer source
clock frequency
Units Minimum timer
period (n = 1)
Units Maximum timer
period (n = 255)
Units
00
01
10
11
4.096
64
kHz
Hz
244
15.625
1
μs
ms
s
62.256
3.984
255
ms
s
1
Hz
s
1
⁄
Hz
60
s
15300
s
60
8.10.3 Watchdog timer function
The watchdog timer function is enabled or disabled by the WD_CD bit of the register
Watchdg_tim_ctl (see Table 30).
The two bits TF[1:0] in register Watchdg_tim_ctl determine one of the four source clock
frequencies for the watchdog timer: 4.096 kHz, 64 Hz, 1 Hz, or 1⁄60 Hz (see Table 32).
When the watchdog timer function is enabled, the 8-bit timer in register Watchdg_tim_val
determines the watchdog timer period.
The watchdog timer counts down from the software programmed 8-bit binary value n in
register Watchdg_tim_val. When the counter reaches 1 the watchdog timer flag WDTF
(register Control_2) is set logic 1 and an interrupt will be generated.
The counter does not automatically reload.
When WD_CD is logic 0 (watchdog timer disabled) and the microcontroller unit (MCU)
loads a watchdog timer value n, then:
• the flag WDTF is reset
• INT is cleared
• the watchdog timer starts again
Loading the counter with 0 will:
• reset the flag WDTF
• clear INT
• stop the watchdog timer
Remark: WDTF is read only. A read of the register Control_2 will automatically reset the
flag WDTF.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
30 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
MCU
n
watchdog
timer value
n = 1
WDTF
INT
001aag062
Counter reached 1, WDTF is logic 1, an interrupt is generated.
Fig 17. WD_CD set logic 1: watchdog activates an interrupt when timed out
• When the watchdog timer counter reaches 1, the watchdog timer flag WDTF (register
Control_2) is set logic 1
• When a minute or second interrupt occurs, the minute/second flag MSF (register
Control_2) is set logic 1 (see Section 8.12.1).
The watchdog timer flag WDTF is read only and cannot be cleared with the interface.
WDTF can be cleared by
• loading a value in register Watchdg_tim_val
• reading of the register Control_2
Writing logic 0 or logic 1 to WDTF has no effect.
8.10.4 Pre-defined timers: second and minute interrupt
PCF2129A has two pre-defined timers which are used to generate an interrupt either once
per second or once per minute. The pulse generator for the minute or second interrupt
operates from an internal 64 Hz clock. It is independent of the watchdog timer. Each of
these timers can be enabled by the bits SI (second interrupt) and MI (minute interrupt) in
register Control_1.
8.10.5 Clearing flags
The flags MSF, AF, and TSFx can be cleared by using the interface. To prevent one flag
being overwritten while clearing another, a logic AND is performed during the write
access. A flag is cleared by writing logic 0 whilst a flag is not cleared by writing logic 1.
Writing logic 1 will result in the flag value remaining unchanged.
Two examples are given for clearing the flags. Clearing a flag is made by a write
command:
• Bits labeled with - must be written with their previous values
• Bits labeled with T have to be written with logic 0
• WDTF is read only and has to be written with logic 0
Repeatedly re-writing these bits has no influence on the functional behavior.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
31 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
Table 33. Flag location in register Control_2
Register
Bit
7
6
5
4
3
2
1
0
Control_2
MSF
WDTF
TSF2
AF
T
-
-
T
Table 34. Example values in register Control_2
Register
Bit
7
6
5
4
3
2
1
0
Control_2
1
0
1
1
0
0
0
0
The following tables show what instruction must be sent to clear the appropriate flag.
Table 35. Example to clear only AF (bit 4)
Register
Bit
7
6
5
4
3
2
1
0
Control_2
1
0
1
0
0
0[1]
0[1]
0
[1] The bits labeled as - have to be rewritten with the previous values.
Table 36. Example to clear only MSF (bit 7)
Register
Bit
7
6
5
4
3
2
1
0
Control_2
0
0
1
1
0
0[1]
0[1]
0
[1] The bits labeled as - have to be rewritten with the previous values.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
32 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.11 Timestamp function
The PCF2129A has an active LOW timestamp input pin TS, internally pulled with an
on-chip pull-up resistor to the internal power supply of the device. It also has a timestamp
detection circuit which can detect two different events:
1. input on the pin TS is driven to an intermediate level between the power supply and
ground.
2. input on the pin TS is driven to ground.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
R1 =
200 kΩ
20 %
TS
R2 =
200 kΩ
5 %
PCF212xA
push-button 1
connected to
cover 1
push-button 2
connected to
cover 2
013aaa176
V
SS
Fig 18. Timestamp detection with two push-buttons on one the TS pin (e.g. for tamper
detection)
The timestamp function is enabled by default after power-on and it can be switched off by
setting the control bit TSOFF (register Timestp_ctl).
A most common application of the timestamp function is described in the application note
Ref. 3 “AN10857”.
See Section 8.12.5 for a description of interrupt generation from the timestamp function.
8.11.1 Timestamp flag
1. When the TS input pin is driven to an intermediate level between the power supply
and ground then the following sequence occurs:
a. The actual date and time are stored in the timestamp registers.
b. The timestamp flag TSF1 (register Control_1) is set.
c. If the TSIE bit (register Control_2) is active, an interrupt on the INT pin is
generated.
The TSF1 flag can be cleared by using the interface. Clearing the flag will clear the
interrupt. Once TSF1 is cleared it will only be set again when a new negative edge on
pin TS is detected.
2. When the TS input pin is driven to ground the following sequence occurs:
a. The actual date and time are stored in the timestamp registers.
b. In addition to the TSF1 flag, the TSF2 flag (register Control_3) is set.
c. If the TSIE bit is active, an interrupt on the INT pin is generated.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
33 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
The TSF1 and TSF2 flags can be cleared by using the interface; clearing both flags
will clear the interrupt. Once TSF2 is cleared it will only be set again when pin TS is
driven to ground once again.
8.11.2 Timestamp mode
The timestamp function has two different modes selected by the control bit TSM
(timestamp mode) in register Timestp_ctl:
• If TSM is logic 0 (default): in subsequent trigger events without clearing the timestamp
flags, the last timestamp event is stored
• If TSM is logic 1: in subsequent trigger events without clearing the timestamp flags,
the first timestamp event is stored
The timestamp function also depends on the control bit BTSE (battery switch timestamp
enable) in register Control_3, see Section 8.11.4.
8.11.3 Timestamp registers
8.11.3.1 Register Timestp_ctl
Table 37. Timestp_ctl - timestamp control register (address 12h) bit description
Bit
Symbol
Value Description
7
TSM
0[1]
in subsequent events without clearing the timestamp
flags, the last event is stored
1
in subsequent events without clearing the timestamp
flags, the first event is stored
6
5
TSOFF
-
0[1]
1
timestamp function active
timestamp function disabled
-
unused
1
4 to 0 1_O_16_TIMESTP[4:0]
[1] Default value.
⁄16 second timestamp information coded in BCD format
8.11.3.2 Register Sec_timestp
Table 38. Sec_timestp - second timestamp register (address 13h) bit description
Bit
Symbol
Value
Place value Description
- unused
7
-
-
6 to 4 SECOND_TIMESTP 0 to 5
ten’s place second timestamp information coded in
BCD format
3 to 0
0 to 9
unit place
8.11.3.3 Register Min_timestp
Table 39. Min_timestp - minute timestamp register (address 14h) bit description
Bit
Symbol
Value
Place value Description
- unused
7
-
-
6 to 4 MINUTE_TIMESTP 0 to 5
3 to 0 0 to 9
ten’s place minute timestamp information coded in
BCD format
unit place
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
34 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.11.3.4 Register Hour_timestp
Table 40. Hour_timestp - hour timestamp register (address 15h) bit description
Bit
Symbol
Value
Place value Description
7 to 6 -
-
-
unused
12 hour mode[1]
5
AMPM
0
-
-
indicates AM
indicates PM
1
4
HOUR_TIMESTP
0 to 1
0 to 9
ten’s place hour timestamp information coded in BCD
format when in 12 hour mode
3 to 0
unit place
24 hour mode[1]
5 to 4 HOUR_TIMESTP
3 to 0
0 to 2
0 to 9
ten’s place hour timestamp information coded in BCD
format when in 24 hour mode
unit place
[1] Hour mode is set by the bit 12_24 in register Control_1.
8.11.3.5 Register Day_timestp
Table 41. Day_timestp - day timestamp register (address 16h) bit description
Bit
Symbol
Value
-
Place value Description
- unused
7 to 6 -
5 to 4 DAY_TIMESTP
3 to 0
0 to 3
0 to 9
ten’s place day timestamp information coded in BCD
format
unit place
8.11.3.6 Register Mon_timestp
Table 42. Mon_timestp - month timestamp register (address 17h) bit description
Bit
Symbol
Value
Place value Description
- unused
7 to 5 -
-
4
MONTH_TIMESTP 0 to 1
0 to 9
ten’s place month timestamp information coded in
BCD format
3 to 0
unit place
8.11.3.7 Register Year_timestp
Table 43. Year_timestp - year timestamp register (address 18h) bit description
Bit
Symbol
Value
0 to 9
0 to 9
Place value Description
7 to 4 YEAR_TIMESTP
3 to 0
ten’s place year timestamp information coded in BCD
format
unit place
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
35 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.11.4 Dependency between Battery switch-over and timestamp
The timestamp function depends on the control bit BTSE in register Control_3:
Table 44. Battery switch-over and timestamp
BTSE BF
Description
[1]
0
1
-
the battery switch-over does not affect the timestamp registers
If a battery switch-over event occurs:
0
1
the timestamp registers store the time and date when the switch-over occurs;
after this event occurred BF is set logic 1
the timestamp registers are not modified;
in this condition subsequent battery switch-over events or falling edges on pin
TS are not registered
[1] Default value.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
36 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.12 Interrupt output, INT
PCF2129A has an interrupt output pin INT which is open-drain, active LOW. Interrupts
may be sourced from different places:
• second or minute timer
• watchdog timer
• alarm
• timestamp
• battery switch-over
• battery low detection
SI
MSF:
MINUTE
SECOND FLAG
to interface:
read MSF
SECONDS COUNTER
MINUTES COUNTER
SI/MI
0
1
MI
SET
CLEAR
PULSE
GENERATOR 1
TRIGGER
CLEAR
TI_TP
INT pin
from interface:
clear MSF
WDTF:
WATCHDOG
TIMER FLAG
to interface:
read WD_CD
WD_CD = 0
WD_CD = 1
WATCHDOG
COUNTER
SET
CLEAR
MCU loading
watchdog counter
to interface:
read AF
AIE
AF: ALARM
FLAG
set alarm
flag, AF
SET
CLEAR
from interface:
clear AF
to interface:
read TSFx
TSIE
TSFx: TIMESTAMP
FLAG
set timestamp
flag, TSFx
SET
CLEAR
from interface:
clear TSF
to interface:
read BF
BIE
BF: BATTERY
FLAG
set battery
flag, BF
SET
CLEAR
from interface:
clear BF
to interface:
read BLF
BLIE
BLF: BATTERY
LOW FLAG
set battery
low flag, BLF
SET
CLEAR
from battery
low detection
001aaj399
circuit: clear BF
When SI, MI, WD_CD, AIE, TSIE, BIE, BLIE are all disabled, INT will remain high-impedance.
Fig 19. Interrupt block diagram
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
37 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
The control bit TI_TP (register Watchdg_tim_ctl) is used to configure whether the
interrupts generated from the second/minute timer (flag MSF in register Control_2) are
pulsed signals or a permanently active signal. All the other interrupt sources generate a
permanently active interrupt signal which follows the status of the corresponding flags.
When the interrupt sources are all disabled, INT remains high-impedance.
• The flags MSF, AF, TSFx, and BF can be cleared by using the interface.
• The flag WDTF is read only. How it can be cleared is explained in Section 8.10.5.
• The flag BLF is read only. It is cleared automatically from the battery low detection
circuit when the battery is replaced.
8.12.1 Minute and second interrupts
Minute and second interrupts are generated by predefined timers. The timers can be
enabled independently from one another by the bits MI and SI in register Control_1.
However, a minute interrupt enabled on top of a second interrupt will not be
distinguishable since it will occur at the same time.
The minute/second flag MSF (register Control_2) is set logic 1 when either the seconds or
the minutes counter increments according to the actually enabled interrupt (see Table 45).
The MSF flag can be read and cleared by the interface.
Table 45. Effect of bits MI and SI on pin INT and bit MSF
MI SI Result on INT
Result on MSF
0
1
0
1
0
0
1
1
no interrupt generated
MSF never set
an interrupt once per minute
an interrupt once per second
an interrupt once per second
MSF set when minutes counter increments
MSF set when seconds counter increments
MSF set when seconds counter increments
When MSF is set logic 1:
• If TI_TP is logic 1 the interrupt is generated as a pulsed signal.
• If TI_TP is logic 0 the interrupt is permanently active signal that remains until MSF is
cleared.
seconds counter
minutes counter
58
59
59
11
00
12
00
01
INT when SI enabled
MSF when SI enabled
INT when only MI enabled
MSF when only MI enabled
001aaf905
In this example, bit TI_TP is logic 1 and the MSF flag is not cleared after an interrupt.
Fig 20. INT example for SI and MI when TI_TP is logic 1
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
38 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
seconds counter
minutes counter
58 59
59 00
11 12
00 01
INT when SI enable
MSF when SI enable
INT when only MI enabled
MSF when only MI enabled
001aag072
In this example, bit TI_TP is logic 0 and the MSF flag is cleared after an interrupt.
Fig 21. INT example for SI and MI when TI_TP is logic 0
The pulse generator for the minute/second interrupt operates from an internal 64 Hz clock
and generates a pulse of 1⁄64 seconds in duration.
8.12.2 INT pulse shortening
If the MSF flag (register Control_2) is cleared before the end of the INT pulse, then the
INT pulse is shortened. This allows the source of a system interrupt to be cleared
immediately when it is serviced, i.e. the system does not have to wait for the completion of
the pulse before continuing; see Figure 22. Instructions for clearing the bit MSF can be
found in Section 8.10.5.
seconds counter
MSF
58
59
INT
(1)
SCL
8th clock
instruction
CLEAR INSTRUCTION
001aaf908
(1) Indicates normal duration of INT pulse.
The timing shown for clearing bit MSF is also valid for the non-pulsed interrupt mode, i.e. when
TI_TP is logic 0, where the INT pulse may be shortened by setting both bits MI and SI logic 0.
Fig 22. Example of shortening the INT pulse by clearing the MSF flag
8.12.3 Watchdog timer interrupts
The generation of interrupts from the watchdog timer is controlled using the WD_CD bit
(register Watchdg_tim_ctl). The interrupt is generated as an active signal which follows
the status of the watchdog timer flag WDTF (register Control_2). No pulse generation is
possible for watchdog timer interrupts.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
39 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
The interrupt is cleared when the flag WDTF is reset. WDTF is a read only bit and cannot
be cleared by using the interface. Instructions for clearing it can be found in
Section 8.10.5.
8.12.4 Alarm interrupts
Generation of interrupts from the alarm function is controlled via the bit AIE (register
Control_2). If AIE is enabled, the INT pin will follow the status of bit AF (register
Control_2). Clearing AF will immediately clear INT. No pulse generation is possible for
alarm interrupts.
minute counter
minute alarm
AF
44
45
45
INT
SCL
8th clock
instruction
CLEAR INSTRUCTION
001aaf910
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 23. AF timing diagram
8.12.5 Timestamp interrupts
Interrupt generation from the timestamp function is controlled using the TSIE bit (register
Control_2). If TSIE is enabled the INT pin follows the status of the flags TSFx. Clearing
the flags TSFx immediately clears INT. No pulse generation is possible for timestamp
interrupts.
8.12.6 Battery switch-over interrupts
Generation of interrupts from the battery switch-over is controlled via the BIE bit (register
Control_3). If BIE is enabled, the INT pin follows the status of bit BF (register Control_3).
Clearing BF immediately clears INT. No pulse generation is possible for battery
switch-over interrupts.
8.12.7 Battery low detection interrupts
Generation of interrupts from the battery low detection is controlled via the BLIE bit
(register Control_3). If BLIE is enabled the INT pin will follow the status of bit BLF (register
Control_3). The interrupt is cleared when the battery is replaced (BLF is logic 0) or when
bit BLIE is disabled (BLIE is logic 0). BLF is read only and therefore cannot be cleared via
the interface.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
40 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.13 External clock test mode
A test mode is available which allows on-board testing. In this mode it is possible to set up
test conditions and control the operation of the RTC.
The test mode is entered by setting bit EXT_TEST logic 1 (register Control_1). Then
pin CLKOUT becomes an input. The test mode replaces the internal clock signal (64 Hz)
with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT
generate an increment of one second.
The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a
maximum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided
down by a 26 divider chain called prescaler (see prescaler in Table 46). The prescaler can
be set into a known state by using bit STOP. When bit STOP is logic 1, the prescaler is
reset to 0. STOP must be cleared before the prescaler can operate again.
From a stop condition, the first 1 second increment will take place after 32 positive edges
on pin CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment.
Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When
entering the test mode, no assumption as to the state of the prescaler can be made.
Operating example:
1. Set EXT_TEST test mode (register Control_1, EXT_TEST is logic 1).
2. Set bit STOP (register Control_1, STOP is logic 1).
3. Set time registers to desired value.
4. Clear STOP (register Control_1, STOP is logic 0).
5. Apply 32 clock pulses to CLKOUT.
6. Read time registers to see the first change.
7. Apply 64 clock pulses to CLKOUT.
8. Read time registers to see the second change.
Repeat 7 and 8 for additional increments.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
41 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.14 STOP bit function
The function of the STOP bit is to allow for accurate starting of the time circuits. STOP will
cause the upper part of the prescaler (F9 to F14) to be held in reset and thus no 1 Hz ticks
are generated. The time circuits can then be set and will not increment until the STOP bit
is released. STOP will not affect the CLKOUT signal but the output of the prescaler in the
range of 32 Hz to 1 Hz (see Figure 24).
The lower stages of the prescaler, F0 to F8, are not reset and because the I2C-bus and the
SPI-bus are asynchronous to the crystal oscillator, the accuracy of re-starting the time
circuits is between 0 and one 64 Hz cycle (0.484375 s and 0.500000 s), see Table 46 and
Figure 25.
Table 46. First increment of time circuits after stop release
Bit
Prescaler bits[1]
1 Hz tick
Time
Comment
STOP
F0 to F8 - F9 to F14
hh:mm:ss
Clock is running normally
0
010000111-010100
12:45:12
prescaler counting normally
STOP bit is activated by user. F0 to F8 are not reset and values cannot be predicted externally
1
xxxxxxxxx-000000
12:45:12
prescaler is reset; time circuits are frozen
prescaler is reset; time circuits are frozen
prescaler is now running
New time is set by user
1
xxxxxxxxx-000000
08:00:00
STOP bit is released by user
0
0
0
0
:
xxxxxxxxx-000000
xxxxxxxxx-100000
xxxxxxxxx-100000
xxxxxxxxx-110000
:
08:00:00
08:00:00
08:00:00
08:00:00
:
0
0
0
:
111111111-111110
000000000-000001
100000000-000001
:
08:00:00
08:00:01
08:00:01
:
0 to 1 transition of F14 increments the time circuits
0
0
0
:
111111111-111111
000000000-000000
100000000-000000
:
08:00:01
08:00:01
:
0
0
111111111-111110
000000000-000001
08:00:01
08:00:02
0 to 1 transition of F14 increments the time circuits
001aaj479
[1] F0 is clocked at 32.768 kHz.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
42 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
LOWER PRESCALER
UPPER PRESCALER
128 Hz
32768 Hz
16384 Hz
8192 Hz
4096 Hz
64 Hz
F
0
F
1
F
2
F
8
F
9
F
F
F
14
10
13
1 Hz tick
OSC
RES
RES
RES
RES
stop
001aaj342
Fig 24. STOP bit functional diagram
64 Hz
stop released
0 ms - 15.625 ms
001aaj343
Fig 25. STOP bit release timing
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
43 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
9. Interfaces
The PCF2129A has a selectable I2C-bus or SPI-bus interface. The selection is done using
the interface selection pin IFS (see Table 47).
Table 47. Interface selection input pin IFS
Pin
Connection
VSS
Bus interface
Reference
Section 9.1
Section 9.2
IFS
SPI-bus
I2C-bus
BBS
V
DD
V
DD
SCL
SDI
R
R
PU
PU
SCL
SDA
SDO
CE
V
SCL
DD
1
2
3
4
5
20
19
18
17
16
V
SCL
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
SDI
SDI
SDO
SDO
BBS
BBS
SDA/CE
IFS
SDA/CE
IFS
PCF2129A
6
15
PCF2129A
15
14
13
12
11
7
14
13
12
11
V
SS
8
V
SS
9
10
V
SS
V
SS
001aaj706
001aaj707
To select the SPI-bus interface, pin IFS has to be
connected to pin VSS
To select the I2C-bus interface pin IFS has to be
connected to pin BBS.
.
a. SPI-bus interface selection
b. I2C-bus interface selection
Fig 26. Interface selection
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
44 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
9.1 SPI-bus interface
Data transfer to and from the device is made via a 3 line SPI-bus (see Table 48). The data
lines for input and output are split. The data input and output line can be connected
together to facilitate a bidirectional data bus (see Figure 27). The SPI-bus is initialized
whenever the chip enable line pin CE is inactive.
SDI
SDI
SDO
SDO
two wire mode
single wire mode
001aai560
Fig 27. SDI, SDO configurations
Table 48. Serial interface
Symbol Function
Description
[1]
SDA/CE chip enable input;
active LOW
when HIGH, the interface is reset;
input may be higher than VDD
when CE is HIGH, input may float;
input may be higher than VDD
when CE is HIGH, input may float;
SCL
serial clock input
SDI
serial data input
input may be higher than VDD
;
input data is sampled on the rising edge of SCL
push-pull output;
SDO
serial data output
drives from VSS to VBBS
;
output data is changed on the falling edge of SCL
[1] The chip enable must not be wired permanently LOW.
9.1.1 Data transmission
The chip enable signal is used to identify the transmitted data. Each data transfer is a
byte, with the Most Significant Bit (MSB) sent first.
The transmission is controlled by the active LOW chip enable signal SDA/CE. The first
byte transmitted is the command byte. Subsequent bytes will be either data to be written
or data to be read (see Figure 28).
data bus
CE
COMMAND
DATA
DATA
DATA
001aaj347
Fig 28. Data transfer overview
The command byte defines the address of the first register to be accessed and the
read/write mode. The address counter will auto increment after every access and will
reset to zero after the last valid register is accessed. The read/write bit (R/W) defines if the
following bytes will be read or write information.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
45 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
Table 49. Command byte definition
Bit
Symbol
Value
Description
7
R/W
data read or write selection
write data
0
1
read data
6 to 5
4 to 0
SA
RA
bin
01
subaddress;
other codes will cause the device to ignore data
transfer
00h to 1Dh register address range
R/W
addr 34
seconds data 45
minutes data 10
BCD
BCD
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
SCL
SDI
SDA/CE
address
counter
xx
02
03
04
001aaj348
In this example, the register Seconds is set to 45 seconds and the register Minutes to 10 minutes.
Fig 29. SPI-bus write example
R/W
addr 34
months data 11
years data 06
BCD
bin
BCD
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
1
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
0
SCL
SDI
SDO
SDA/CE
address
counter
xx
02
03
09
001aaj349
In this example, the registers Months and Years are read. The pins SDI and SDO are not connected together. For this
configuration, it is important that pin SDI is never left floating. It must always be driven either HIGH or LOW. If pin SDI is left
open, high IDD currents may result.
Fig 30. SPI-bus read example
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
46 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
9.2 I2C-bus interface
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines are
connected to a positive supply via a pull-up resistor. Data transfer is initiated only when
the bus is not busy.
9.2.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line remains
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as control signals (see Figure 31).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mbc621
Fig 31. Bit transfer
9.2.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as the START condition S. A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition P (see Figure 32).
SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
mbc622
Fig 32. Definition of START and STOP conditions
For this device a repeated START is not allowed for reading. Therefore a STOP has to be
released before the next START.
9.2.3 System configuration
A device generating a message is a transmitter; a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves.
The PCF2129A can act as a slave transmitter and a slave receiver.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
47 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
SDA
SCL
MASTER
TRANSMITTER
RECEIVER
SLAVE
TRANSMITTER
RECEIVER
MASTER
MASTER
SLAVE
RECEIVER
TRANSMITTER
TRANSMITTER
RECEIVER
mba605
Fig 33. System configuration
9.2.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is illustrated in Figure 34.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
Fig 34. Acknowledgement on the I2C-bus
9.2.5 I2C-bus protocol
After a start condition a valid hardware address has to be sent to a PCF2129A device.
The appropriate I2C-bus slave address is 1010001. The entire I2C-bus slave address byte
is shown in Table 50.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
48 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
Table 50. I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
0
MSB
LSB
R/W
1
0
1
0
0
0
1
The R/W bit defines the direction of the following single or multiple byte data transfer (read
is logic 1, write is logic 0).
For the format and the timing of the START condition (S), the STOP condition (P), and the
acknowledge bit (A) refer to the I2C-bus specification Ref. 13 “UM10204” and the
characteristics table (Table 55). In the write mode a data transfer is terminated by sending
either a STOP condition or the START condition of the next data transfer.
acknowledge
acknowledge
acknowledge
from PCF2129A
from PCF2129A
from PCF2129A
S
1
0
1
0
0
0
1
0
A
A
A
P/S
slave address
register address
00h to 1Dh
0 to n
data bytes
write bit
START/
STOP
001aaj723
Fig 35. Bus protocol, writing to registers
acknowledge
from PCF2129A
acknowledge
from PCF2129A
set register
address
S
1
0
1
0
0
0
1
0
A
A
P
slave address
register address
00h to 1Dh
write bit
STOP
acknowledge
acknowledge
from PCF2129A
from master
no acknowledge
read register
data
S
1
0
1
0
0
0
1
1
A
DATA BYTE
A
LAST DATA BYTE
A
P
slave address
0 to n data bytes
read bit
001aaj724
Fig 36. Bus protocol, reading from registers
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
49 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
10. Internal circuitry
V
V
DD
SCL
SDI
BAT
BBS
SDO
SDA/CE
IFS
INT
TS
CLKOUT
V
SS
PCF2129A
001aaj705
Fig 37. Device diode protection diagram of PCF2129A
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
50 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
11. Limiting values
Table 51. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
−0.5
−50
−0.5
−10
−0.5
−10
−10
−0.5
-
Max
+4.5
+50
Unit
V
VDD
IDD
Vi
supply voltage
supply current
input voltage
input current
output voltage
output current
mA
V
+6.5
+10
II
mA
V
VO
IO
+6.5
+10
mA
mA
V
at pin SDA
+20
VBAT
Ptot
battery supply voltage
total power dissipation
ambient temperature
+4.5
300
mW
°C
V
Tamb
VESD
−40
-
+85
[1]
[2]
[3]
[4]
[5]
electrostatic discharge
voltage
HBM
MM
±3000
±250
±1500
200
-
V
CDM
-
V
Ilu
latch-up current
-
mA
°C
Tstg
storage temperature
−55
+85
[1] Pass level; Human Body Model (HBM) according to Ref. 7 “JESD22-A114”.
[2] Pass level; Machine Model (MM), according to Ref. 8 “JESD22-A115”.
[3] Pass level; Charged-Device Model (CDM), according to Ref. 9 “JESD22-C101”.
[4] Pass level; latch-up testing according to Ref. 10 “JESD78” at maximum ambient temperature (Tamb(max)).
[5] According to the NXP store and transport requirements (see Ref. 12 “NX3-00092”) the devices have to be
stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products
deviant conditions are described in that document.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
51 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
12. Static characteristics
Table 52. Static characteristics
VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
[1]
supply voltage
1.8
1.8
-
-
4.2
4.2
-
V
V
V
V
VBAT
battery supply voltage
calibration supply voltage
low voltage
-
VDD(cal)
Vlow
3.3
1.2
-
-
IDD
supply current
interface active
SPI-bus
fSCL = 6.5 MHz
fSCL = 1.0 MHz
I2C-bus
-
-
-
-
800
200
μA
μA
fSCL = 1.0 MHz
interface inactive (fSCL = 0 Hz)
-
-
200
μA
CLKOUT disabled (COF[2:0] = 111), one power supply VDD
(PWRMNG[2:0] = 111), timestamp detection disabled (TSOFF = 1)[2]
VDD = 2.0 V
VDD = 3.3 V
VDD = 4.2 V
-
-
-
500
700
800
-
nA
nA
nA
1500
-
CLKOUT enabled at 32 kHz (default), one power supply VDD
(PWRMNG[2:0] = 111), timestamp detection disabled (TSOFF = 1)
VDD = 2.0 V
VDD = 3.3 V
VDD = 4.2 V
-
-
-
600
-
-
-
nA
nA
nA
850
1050
CLKOUT disabled (COF[2:0] = 111), power management functions enabled
(default), timestamp detection enabled (default)
VDD = 2.0 V
VDD = 3.3 V
VDD = 4.2 V
-
-
-
1800
2150
2350
-
nA
nA
nA
-
3500
CLKOUT enabled at 32 kHz (default); power management functions enabled
(default), timestamp detection enabled (default)
VDD = 2.0 V
VDD = 3.3 V
VDD = 4.2 V
-
-
-
-
1900
2300
2600
50
-
nA
nA
nA
nA
-
-
IBAT
battery supply current
VDD active;
100
VBAT = 3.0 V
Power management
Vth(sw)bat battery switch threshold
-
-
2.5
2.5
-
-
V
V
voltage
Vth(bat)low
low battery threshold voltage
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
52 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
Table 52. Static characteristics …continued
VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Inputs
VI
Parameter
Conditions
Min
Typ
Max
Unit
input voltage
−0.5
-
-
-
VDD + 0.5
0.25VDD
0.3VDD
V
V
V
VIL
LOW-level input voltage
-
-
Tamb = −20 °C to +85 °C;
VDD > 2.0 V
VIH
HIGH-level input voltage
input leakage current
input capacitance
0.7VDD
-
-
V
ILI
VI = VDD or VSS
−1
0
-
+1
7
μA
pF
[3]
Ci
-
Outputs
VO
output voltage
on pins CLKOUT, INT,
referring to external pull-up
−0.5
−0.5
-
-
5.5
V
V
on pin SDO
VBBS + 0.5
IOL
LOW-level output current
output sink current;
VOL = 0.4 V; VDD = 4.2 V
on pin SDA
20
-
-
-
-
-
-
mA
mA
mA
on all other outputs
1.0
1.0
IOH
HIGH-level output current
output leakage current
output source current;
on pin SDO; VOH = 3.8 V;
VDD = 4.2 V
ILO
VO = VDD or VSS
−1
0
1
μA
[1] For reliable oscillator start-up at power-on: VDD(po)min = VDD(min) + 0.3 V.
[2] Timer source clock = 1⁄60 Hz, level of pins SDA/CE, SDI, and SCL is VDD or VSS
[3] Tested on sample basis.
.
12.1 Current consumption IDD characteristics, typical
001aaj432
2.0
I
DD
(μA)
1.6
1.2
0.8
0.4
0
V
V
= 3 V
= 2 V
DD
DD
−40
−20
0
20
40
60
80
100
Temperature (°C)
CLKOUT disabled; PWRMNG[2:0] = 111; TSOFF = 1; TS input floating.
Fig 38. IDD as a function of temperature
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
53 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
001aaj433
2.0
I
DD
(μA)
1.6
1.2
0.8
0.4
0
CLKOUT enabled at
32 kHz
CLKOUT OFF
1.8
2.2
2.6
3.0
3.4
3.8
4.2
V
DD
(V)
a. PWRMNG[2:0] = 111; TSOFF = 1; Tamb = 25 °C; TS input floating.
001aaj434
4.0
I
DD
(μA)
3.2
CLKOUT enabled at
32 kHz
2.4
1.6
0.8
0
CLKOUT OFF
1.8
2.2
2.6
3.0
3.4
3.8
4.2
V
(V)
DD
b. PWRMNG[2:0] = 000; TSOFF = 0; Tamb = 25 °C; TS input floating.
Fig 39. IDD as a function of VDD
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
54 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
12.2 Frequency characteristics
Table 53. Frequency characteristics
VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = +25 °C, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
fo
output frequency
on pin CLKOUT;
-
32.768
-
kHz
VDD or VBAT = 3.3 V;
COF[2:0] = 000;
AO[3:0] = 1000
Δf/f
frequency stability
V
DD or VBAT = 3.3 V
[1]
[1]
Tamb = −15 °C to +60 °C
-
-
±3
±5
±5
ppm
ppm
Tamb = −25 °C to −15 °C
and
±10
Tamb = +60 °C to +65 °C
[2]
Δfxtal/fxtal relative crystal frequency variation
Δf/ΔV frequency variation with voltage
crystal aging, first year;
VDD or VBAT = 3.3 V
-
-
-
±3
ppm
on pin CLKOUT
±1
-
ppm/V
[1] ±1 ppm corresponds to a time deviation of ±0.0864 seconds per day.
[2] Not production tested. Effects of reflow solder not included (see Ref. 3 “AN10857”).
001aaj650
40
Frequency
stability
(ppm)
10 ppm
5 ppm
10 ppm
0
(1)
−40
−80
(2)
−40
−20
0
20
40
60
80
100
Temperature (°C)
(1) Temperature compensated frequency.
(2) Uncompensated typical tuning-fork crystal frequency.
Fig 40. Characteristic of frequency with respect to temperature
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
55 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
13. Dynamic characteristics
13.1 SPI-bus timing characteristics
Table 54. SPI-bus characteristics
DD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = −40 °C to +85 °C, unless otherwise specified. All timing values are valid within the
V
operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD (see
Figure 41).
Symbol
Parameter
Conditions
VDD = 1.8 V
VDD = 4.2 V
Unit
Min
Max
Min
Max
Pin SCL
fclk(SCL)
tSCL
SCL clock frequency
SCL time
-
2.0
-
6.5
-
MHz
ns
800
100
400
-
-
140
70
70
-
tclk(H)
clock HIGH time
clock LOW time
rise time
-
-
ns
tclk(L)
-
-
ns
tr
for SCL signal
for SCL signal
100
100
30
30
ns
tf
fall time
-
-
ns
Pin CE
tsu(CE_N)
th(CE_N)
trec(CE_N)
tw(CE_N)
Pin SDI
tsu
CE_N set-up time
CE_N hold time
60
40
100
-
-
30
25
30
-
-
ns
ns
ns
s
-
-
CE_N recovery time
CE_N pulse width
-
-
0.99
0.99
set-up time
hold time
set-up time for SDI data
hold time for SDI data
70
70
-
-
20
20
-
-
ns
ns
th
Pin SDO
td(R)SDO
tdis(SDO)
SDO read delay time
SDO disable time
CL = 50 pF
-
225
90
-
-
55
25
-
ns
ns
ns
[1]
-
-
tt(SDI-SDO) transition time from SDI to
SDO
to avoid bus conflict
0
0
[1] No load value; bus will be held up by bus capacitance; use RC time constant with application values.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
56 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
t
w(CE_N)
CE
t
rec(CE_N)
t
t
r
su(CE_N)
t
f
t
t
h(CE_N)
clk(SCL)
80%
SCL
20%
t
clk(L)
t
clk(H)
WRITE
t
su
t
h
SDI
R/W
SA2
RA0
b7
b6
b0
high-Z
SDO
READ
SDI
b7
b6
b0
t
t(SDI-SDO)
t
d(R)SDO
t
dis(SDO)
high-Z
SDO
b7
b6
b0
013aaa152
Fig 41. SPI-bus timing
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
57 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
13.2 I2C-bus timing characteristics
Table 55. I2C-bus characteristics
All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to 30 %
and 70 % with an input voltage swing of VSS to VDD (see Figure 42).
Symbol Parameter
Standard mode
Fast-mode (Fm)
Fast-mode Plus (Fm+) Unit
Min
Max
Min
Max
Min
Max
Pin SCL
[1]
fSCL
SCL clock frequency
0
100
-
0
400
-
0
1000
-
kHz
tLOW
LOW period of the SCL
clock
4.7
1.3
0.5
μs
tHIGH
HIGH period of the SCL
clock
4.0
-
0.6
-
0.26
-
μs
Pin SDA
tSU;DAT data set-up time
tHD;DAT data hold time
Pins SCL and SDA
250
0
-
-
100
0
-
-
50
0
-
-
ns
ns
tBUF
bus free time between a
4.7
-
1.3
-
0.5
-
μs
STOP and START
condition
tSU;STO set-up time for STOP
condition
4.0
4.0
4.7
-
-
-
0.6
0.6
0.6
-
-
-
0.26
0.26
0.26
-
-
-
μs
μs
μs
tHD;STA hold time (repeated)
START condition
tSU;STA set-up time for a
repeated START
condition
[2][3][4]
[2][3][4]
[5]
tr
rise time of both SDA
and SCL signals
-
1000
300
20 + 0.1Cb 300
20 + 0.1Cb 300
-
120
120
0.45
ns
ns
μs
tf
fall time of both SDA and
SCL signals
-
-
tVD;ACK data valid acknowledge
time
0.1
3.45
0.1
0.9
0.05
[6]
[7]
tVD;DAT data valid time
300
-
-
75
-
-
75
-
450
50
ns
ns
tSP
pulse width of spikes
that must be suppressed
by the input filter
50
50
[1] The minimum SCL clock frequency is limited by the bus time-out feature which resets the serial bus interface if either the SDA or SCL is
held LOW for a minimum of 25 ms. The bus time-out feature must be disabled for DC operation.
[2] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region of the SCL’s falling edge.
[3] Cb is the total capacitance of one bus line in pF.
[4] The maximum tf for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, tf is 250 ns. This allows
series protection resistors to be connected between the SDA pin, the SCL pin, and the SDA/SCL bus lines without exceeding the
maximum tf.
[5] tVD;ACK is the time of the acknowledgement signal from SCL LOW to SDA (out) LOW.
[6] tVD;DAT is the minimum time for valid SDA (out) data following SCL LOW.
[7] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
58 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
BIT 0
LSB
(R/W)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
PROTOCOL
t
t
t
HIGH
SU;STA
LOW
1 / f
SCL
SCL
SDA
t
t
t
f
BUF
r
t
t
t
t
t
HD;STA
SU;DAT
VD;DAT
SU;STO
mbd820
HD;DAT
Fig 42. I2C-bus timing diagram; rise and fall times refer to 30 % and 70 %
14. Application information
For information about application configuration see Ref. 3 “AN10857”.
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
59 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
15. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 43. Package outline SOT163-1 (SO20)
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
60 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
16. Soldering
For information about soldering see Ref. 3 “AN10857”.
17. Abbreviations
Table 56. Abbreviations
Acronym
AM
Description
Ante Meridiem
BCD
CDM
CMOS
DC
Binary Coded Decimal
Charged-Device Model
Complementary Metal Oxide Semiconductor
Direct Current
GPS
HBM
I2C
Global Positioning System
Human Body Model
Inter-Integrated Circuit
Integrated Circuit
IC
LSB
Least Significant Bit
Microcontroller Unit
MCU
MM
Machine Model
MSB
PM
Most Significant Bit
Post Meridiem
POR
PORO
PPM
RC
Power-On Reset
Power-On Reset Override
Parts Per Million
Resistance-Capacitance
Real Time Clock
RTC
SCL
SDA
SPI
Serial Clock Line
Serial DAta line
Serial Peripheral Interface
Static Random Access Memory
Temperature Compensated Xtal Oscillator
crystal
SRAM
TCXO
Xtal
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
61 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
18. References
[1] AN10365 — Surface mount reflow soldering description
[2] AN10853 — Handling precautions of ESD sensitive devices
[3] AN10857 — Application and soldering information for PCF2127A and PCF2129A
TCXO RTC
[4] IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[6] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[7] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[8] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[9] JESD22-C101 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[10] JESD78 — IC Latch-Up Test
[11] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[12] NX3-00092 — NXP store and transport requirements
[13] UM10204 — I2C-bus specification and user manual
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
62 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
19. Revision history
Table 57. Revision history
Document ID
Release date
20100113
Data sheet status
Change notice
Supersedes
PCF2129A_1
Product data sheet
-
-
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
63 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
20.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
64 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
22. Tables
Table 1. Ordering information. . . . . . . . . . . . . . . . . . . . . .2
Table 2. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 3. Pin description of PCF2129A . . . . . . . . . . . . . .4
Table 4. Register overview . . . . . . . . . . . . . . . . . . . . . . .6
Table 5. Control_1 - control and status register 1
(address 00h) bit description . . . . . . . . . . . . . . .8
Table 6. Control_2 - control and status register 2
(address 01h) bit description . . . . . . . . . . . . . . .9
Table 7. Control_3 - control and status register 3
(address 0Fh) bit description . . . . . . . . . . . . . .10
Table 8. CLKOUT_ctl - CLKOUT control register
(address 03h) bit description . . . . . . . . . . . . . .11
Table 9. Temperature measurement period . . . . . . . . . .11
Table 10. CLKOUT frequency selection. . . . . . . . . . . . . .12
Table 11. Aging_offset - crystal aging offset register
(address 19h) bit description . . . . . . . . . . . . . .13
Table 12. Frequency correction at 25 ×C, typical . . . . . .13
Table 13. Power management control bit description. . . .14
Table 14. Output pin BBS. . . . . . . . . . . . . . . . . . . . . . . . .17
Table 15. Seconds - seconds and clock integrity
register (address 03h) bit description . . . . . . . .22
Table 16. Seconds coded in BCD format . . . . . . . . . . . .22
Table 17. Minutes - minutes register (address 04h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 18. Hours - hours register (address 05h)
(address 12h) bit description . . . . . . . . . . . . . . 34
Table 38. Sec_timestp - second timestamp register
(address 13h) bit description . . . . . . . . . . . . . . 34
Table 39. Min_timestp - minute timestamp register
(address 14h) bit description . . . . . . . . . . . . . . 34
Table 40. Hour_timestp - hour timestamp register
(address 15h) bit description . . . . . . . . . . . . . . 35
Table 41. Day_timestp - day timestamp register
(address 16h) bit description . . . . . . . . . . . . . . 35
Table 42. Mon_timestp - month timestamp register
(address 17h) bit description . . . . . . . . . . . . . . 35
Table 43. Year_timestp - year timestamp register
(address 18h) bit description . . . . . . . . . . . . . . 35
Table 44. Battery switch-over and timestamp . . . . . . . . . 36
Table 45. Effect of bits MI and SI on pin INT and
bit MSF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 46. First increment of time circuits after
stop release . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 47. Interface selection input pin IFS. . . . . . . . . . . . 44
Table 48. Serial interface. . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 49. Command byte definition . . . . . . . . . . . . . . . . . 46
Table 50. I2C slave address byte. . . . . . . . . . . . . . . . . . . 49
Table 51. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 52. Static characteristics . . . . . . . . . . . . . . . . . . . . 52
Table 53. Frequency characteristics . . . . . . . . . . . . . . . . 55
Table 54. SPI-bus characteristics . . . . . . . . . . . . . . . . . . 56
Table 55. I2C-bus characteristics. . . . . . . . . . . . . . . . . . . 58
Table 56. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 57. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 63
bit description . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 19. Days - days register (address 06h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 20. Weekdays - weekdays register
(address 07h) bit description . . . . . . . . . . . . . .23
Table 21. Weekday assignments . . . . . . . . . . . . . . . . . . .23
Table 22. Months - months register (address 08h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 23. Month assignments in BCD format. . . . . . . . . .24
Table 24. Years - years register (address 09h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 25. Second_alarm - second alarm register
(address 0Ah) bit description . . . . . . . . . . . . . .27
Table 26. Minute_alarm - minute alarm register
(address 0Bh) bit description . . . . . . . . . . . . . .27
Table 27. Hour_alarm - hour alarm register
(address 0Ch) bit description . . . . . . . . . . . . . .27
Table 28. Day_alarm - day rearm register
(address 0Dh) bit description . . . . . . . . . . . . . .28
Table 29. Weekday_alarm - weekday alarm register
(address 0Eh) bit description . . . . . . . . . . . . . .28
Table 30. Watchdg_tim_ctl - watchdog timer control
register (address 10h) bit description . . . . . . .29
Table 31. Watchdg_tim_val - watchdog timer value
register (address 11h) bit description . . . . . . . .29
Table 32. Programmable watchdog timer. . . . . . . . . . . . .30
Table 33. Flag location in register Control_2 . . . . . . . . . .32
Table 34. Example values in register Control_2. . . . . . . .32
Table 35. Example to clear only AF (bit 4) . . . . . . . . . . . .32
Table 36. Example to clear only MSF (bit 7). . . . . . . . . . .32
Table 37. Timestp_ctl - timestamp control register
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
65 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
23. Figures
Fig 1. Block diagram of PCF2129A . . . . . . . . . . . . . . . . .3
Fig 2. Pin configuration for PCF2129A (SO20) . . . . . . . .4
Fig 3. Handling address registers . . . . . . . . . . . . . . . . . .6
Fig 4. Battery switch-over behavior in standard
refer to 30 % and 70 % . . . . . . . . . . . . . . . . . . . . 59
Fig 43. Package outline SOT163-1 (SO20) . . . . . . . . . . 60
mode with bit BIE logic 1 (enabled) . . . . . . . . . . .15
Fig 5. Battery switch-over behavior in direct switching
mode with bit BIE logic 1 (enabled) . . . . . . . . . . .16
Fig 6. Battery switch-over circuit, simplified block
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Fig 7. Typical driving capability of VBBS: (VBBS - VDD
)
with respect to the output load current IBBS . . . . .17
Fig 8. Battery low detection behavior with bit BLIE
logic 1 (enabled) . . . . . . . . . . . . . . . . . . . . . . . . .18
Fig 9. Power failure event due to battery discharge:
reset occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Fig 10. Dependency between POR and oscillator . . . . . .20
Fig 11. Power-On Reset (POR) system. . . . . . . . . . . . . .20
Fig 12. Power-On Reset Override (PORO) sequence,
valid for both I2C-bus and SPI-bus . . . . . . . . . . .21
Fig 13. Data flow of the time function. . . . . . . . . . . . . . . .25
Fig 14. Access time for read/write operations . . . . . . . . .25
Fig 15. Alarm function block diagram. . . . . . . . . . . . . . . .26
Fig 16. Alarm flag timing diagram . . . . . . . . . . . . . . . . . .28
Fig 17. WD_CD set logic 1: watchdog activates an
interrupt when timed out . . . . . . . . . . . . . . . . . . .31
Fig 18. Timestamp detection with two push-buttons
on one the TS pin (e.g. for tamper detection) . . .33
Fig 19. Interrupt block diagram . . . . . . . . . . . . . . . . . . . .37
Fig 20. INT example for SI and MI when TI_TP is
logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Fig 21. INT example for SI and MI when TI_TP is
logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Fig 22. Example of shortening the INT pulse by
clearing the MSF flag. . . . . . . . . . . . . . . . . . . . . .39
Fig 23. AF timing diagram . . . . . . . . . . . . . . . . . . . . . . . .40
Fig 24. STOP bit functional diagram . . . . . . . . . . . . . . . .43
Fig 25. STOP bit release timing. . . . . . . . . . . . . . . . . . . .43
Fig 26. Interface selection . . . . . . . . . . . . . . . . . . . . . . . .44
Fig 27. SDI, SDO configurations . . . . . . . . . . . . . . . . . . .45
Fig 28. Data transfer overview. . . . . . . . . . . . . . . . . . . . .45
Fig 29. SPI-bus write example. . . . . . . . . . . . . . . . . . . . .46
Fig 30. SPI-bus read example . . . . . . . . . . . . . . . . . . . . .46
Fig 31. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Fig 32. Definition of START and STOP conditions. . . . . .47
Fig 33. System configuration . . . . . . . . . . . . . . . . . . . . . .48
Fig 34. Acknowledgement on the I2C-bus . . . . . . . . . . . .48
Fig 35. Bus protocol, writing to registers . . . . . . . . . . . . .49
Fig 36. Bus protocol, reading from registers . . . . . . . . . .49
Fig 37. Device diode protection diagram of
PCF2129A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Fig 38. IDD as a function of temperature . . . . . . . . . . . . .53
Fig 39. IDD as a function of VDD . . . . . . . . . . . . . . . . . . . .54
Fig 40. Characteristic of frequency with respect to
temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Fig 41. SPI-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Fig 42. I2C-bus timing diagram; rise and fall times
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
66 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
24. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
8.9.3
8.9.4
8.9.5
8.9.6
8.10
8.10.1
8.10.2
8.10.3
8.10.4
Register Hour_alarm . . . . . . . . . . . . . . . . . . . 27
Register Day_alarm . . . . . . . . . . . . . . . . . . . . 28
Register Weekday_alarm. . . . . . . . . . . . . . . . 28
Alarm flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Timer functions. . . . . . . . . . . . . . . . . . . . . . . . 29
Register Watchdg_tim_ctl . . . . . . . . . . . . . . . 29
Register Watchdg_tim_val . . . . . . . . . . . . . . . 29
Watchdog timer function . . . . . . . . . . . . . . . . 30
Pre-defined timers: second and
minute interrupt . . . . . . . . . . . . . . . . . . . . . . . 31
Clearing flags. . . . . . . . . . . . . . . . . . . . . . . . . 31
Timestamp function . . . . . . . . . . . . . . . . . . . . 33
Timestamp flag. . . . . . . . . . . . . . . . . . . . . . . . 33
Timestamp mode . . . . . . . . . . . . . . . . . . . . . . 34
Timestamp registers. . . . . . . . . . . . . . . . . . . . 34
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8.10.5
8.11
8.11.1
8.11.2
8.11.3
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
Functional description . . . . . . . . . . . . . . . . . . . 5
Register overview. . . . . . . . . . . . . . . . . . . . . . . 5
Control registers . . . . . . . . . . . . . . . . . . . . . . . . 8
Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 8
Register Control_2 . . . . . . . . . . . . . . . . . . . . . . 9
Register Control_3 . . . . . . . . . . . . . . . . . . . . . 10
Register CLKOUT_ctl. . . . . . . . . . . . . . . . . . . 11
Temperature compensated crystal
oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Temperature measurement . . . . . . . . . . . . . . 11
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Register Aging_offset . . . . . . . . . . . . . . . . . . . 13
Crystal aging correction . . . . . . . . . . . . . . . . . 13
Power management functions . . . . . . . . . . . . 14
Battery switch-over function . . . . . . . . . . . . . . 14
Standard mode . . . . . . . . . . . . . . . . . . . . . . . . 15
Direct switching mode . . . . . . . . . . . . . . . . . . 15
Battery switch-over disabled: only
one power supply (VDD) . . . . . . . . . . . . . . . . . 16
Battery switch-over architecture . . . . . . . . . . . 16
Battery backup supply . . . . . . . . . . . . . . . . . . 17
Battery low detection function. . . . . . . . . . . . . 18
Oscillator stop detection function . . . . . . . . . . 19
Reset function . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-On Reset (POR) . . . . . . . . . . . . . . . . . 20
Power-On Reset Override (PORO) . . . . . . . . 20
Time and date function . . . . . . . . . . . . . . . . . . 22
Register Seconds . . . . . . . . . . . . . . . . . . . . . . 22
Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 22
Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 23
Register Days. . . . . . . . . . . . . . . . . . . . . . . . . 23
Register Weekdays. . . . . . . . . . . . . . . . . . . . . 23
Register Months . . . . . . . . . . . . . . . . . . . . . . . 24
Register Years . . . . . . . . . . . . . . . . . . . . . . . . 24
Setting and reading the time. . . . . . . . . . . . . . 25
Alarm function. . . . . . . . . . . . . . . . . . . . . . . . . 26
Register Second_alarm . . . . . . . . . . . . . . . . . 27
Register Minute_alarm . . . . . . . . . . . . . . . . . . 27
8.11.3.1 Register Timestp_ctl . . . . . . . . . . . . . . . . . . . 34
8.11.3.2 Register Sec_timestp. . . . . . . . . . . . . . . . . . . 34
8.11.3.3 Register Min_timestp . . . . . . . . . . . . . . . . . . . 34
8.11.3.4 Register Hour_timestp . . . . . . . . . . . . . . . . . . 35
8.11.3.5 Register Day_timestp. . . . . . . . . . . . . . . . . . . 35
8.11.3.6 Register Mon_timestp . . . . . . . . . . . . . . . . . . 35
8.11.3.7 Register Year_timestp . . . . . . . . . . . . . . . . . . 35
8.3.1
8.3.1.1
8.3.2
8.4
8.4.1
8.5
8.5.1
8.5.1.1
8.5.1.2
8.5.1.3
8.11.4
Dependency between Battery
switch-over and timestamp . . . . . . . . . . . . . . 36
Interrupt output, INT. . . . . . . . . . . . . . . . . . . . 37
Minute and second interrupts. . . . . . . . . . . . . 38
INT pulse shortening . . . . . . . . . . . . . . . . . . . 39
Watchdog timer interrupts . . . . . . . . . . . . . . . 39
Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 40
Timestamp interrupts . . . . . . . . . . . . . . . . . . . 40
Battery switch-over interrupts . . . . . . . . . . . . 40
Battery low detection interrupts . . . . . . . . . . . 40
External clock test mode . . . . . . . . . . . . . . . . 41
STOP bit function. . . . . . . . . . . . . . . . . . . . . . 42
8.12
8.12.1
8.12.2
8.12.3
8.12.4
8.12.5
8.12.6
8.12.7
8.13
8.5.1.4
8.5.2
8.5.3
8.6
8.14
8.7
9
9.1
9.1.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SPI-bus interface . . . . . . . . . . . . . . . . . . . . . . 45
Data transmission . . . . . . . . . . . . . . . . . . . . . 45
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 47
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
START and STOP conditions. . . . . . . . . . . . . 47
System configuration . . . . . . . . . . . . . . . . . . . 47
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 48
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 48
8.7.1
8.7.2
8.8
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.8.7
8.8.8
8.9
10
11
12
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 50
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 51
Static characteristics . . . . . . . . . . . . . . . . . . . 52
8.9.1
8.9.2
continued >>
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
67 of 68
PCF2129A
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
12.1
12.2
Current consumption IDD characteristics,
typical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Frequency characteristics. . . . . . . . . . . . . . . . 55
13
13.1
13.2
Dynamic characteristics . . . . . . . . . . . . . . . . . 56
SPI-bus timing characteristics . . . . . . . . . . . . 56
I2C-bus timing characteristics. . . . . . . . . . . . . 58
14
15
16
17
18
19
Application information. . . . . . . . . . . . . . . . . . 59
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 60
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 61
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 63
20
Legal information. . . . . . . . . . . . . . . . . . . . . . . 64
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 64
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 64
20.1
20.2
20.3
20.4
21
22
23
24
Contact information. . . . . . . . . . . . . . . . . . . . . 64
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 January 2010
Document identifier: PCF2129A_1
相关型号:
PCF2129AT/1
IC REAL TIME CLOCK, PDSO20, 7.50 MM WIDTH, PLASTIC, SOT163-1, MO-013, DSO-20, Timer or RTC
NXP
PCF2129AT/1,512
PCF2129 - Accurate RTC with integrated quartz crystal for industrial applications SOP 20-Pin
NXP
PCF2129AT/1,518
PCF2129 - Accurate RTC with integrated quartz crystal for industrial applications SOP 20-Pin
NXP
PCF2129AT/2,518
PCF2129 - Accurate RTC with integrated quartz crystal for industrial applications SOP 20-Pin
NXP
©2020 ICPDF网 联系我们和版权申明