PCF5079 [NXP]
Dual-band power amplifier controller for GSM, PCN and DCS; 用于GSM ， PCN和DCS的双频带功率放大器控制器
| 型号： | PCF5079 |
| 厂家： | 
NXP |
| 描述： | Dual-band power amplifier controller for GSM, PCN and DCS |
| 文件： | 总28页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCF5079
Dual-band power amplifier
controller for GSM, PCN and DCS
Product specification
2001 Nov 21
File under Integrated Circuits, IC17
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
CONTENTS
13
PACKAGE OUTLINES
14
SOLDERING (TSSOP10)
1
2
3
4
5
6
FEATURES
14.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
APPLICATIONS
GENERAL DESCRIPTION
QUICK REFERENCE DATA
BLOCK DIAGRAM
PINNING
14.2
14.3
14.4
14.5
Suitability of surface mount IC packages for
wave and reflow soldering methods
6.1
6.2
Pin description
Pin configurations
15
SOLDERING (HVSON10)
15.1
15.2
Soldering information
PCB design guidelines
Perimeter pad design
Thermal pad and via design
Stencil design for perimeter pads
Stencil design for thermal pads
Stencil thickness
7
FUNCTIONAL DESCRIPTION
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
General
Power-up mode
OP4 (integrator)
Start-up and initial conditions
Home position voltage
End of burst
Considerations for ramp-down
Configurations
15.2.1
15.2.2
15.2.3
15.2.4
15.2.5
16
17
18
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
Summary of current and voltage definitions
Timing
8
LIMITING VALUES
9
ELECTROSTATIC DISCHARGE (ESD)
DC CHARACTERISTICS
10
11
12
OPERATING CHARACTERISTICS
APPLICATION INFORMATION
12.1
12.2
12.3
12.4
Ramp control
PA protection against mismatch
Detected voltage measurement
Application examples
2001 Nov 21
2
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
1
FEATURES
2
APPLICATIONS
• Compatible with baseband interface family PCF5073x
• Two power sensor inputs
• Global System for Mobile communication (GSM)
• Personal Communications Network (PCN) systems.
• Temperature compensation of sensor signal
• Active filter for Digital-to-Analog Converter (DAC) input
• Power Amplifier (PA) protection against mismatching
• Bias current source for detector diodes
3
GENERAL DESCRIPTION
This CMOS device integrates an amplifier for the detected
RF voltage from the sensor, an integrator and an active
filter to build a PA control loop for cellular systems with a
small number of passive components.
• Generation of pre-bias level for PA at start of burst
(home position)
• Compatible with a wide range of silicon PAs
• Compatible with multislot class 12
• Dual output with internal switch
• Two different transfer functions
• Possibility to adapt dynamic transfer functions
• Very small outline package (3 × 3 mm).
4
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDD
IDD(tot)
Tamb
supply voltage
2.5
−
3.6
−
5.0
10
V
total supply current
ambient temperature
mA
°C
−40
−
+85
ORDERING INFORMATION
PACKAGE
DESCRIPTION
TYPE NUMBER
NAME
VERSION
PCF5079T/C/1
TSSOP10 plastic thin shrink small outline package; 10 leads; body width 3 mm
SOT552-1
SOT650-1
PCF5079HK/C/1 HVSON10 plastic, heatsink very thin small outline package; no leads;
10 terminals; body 3 × 3 × 0.90 mm
2001 Nov 21
3
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
5
BLOCK DIAGRAM
RF
RF
RF
RF
out
PA
PA
in
out
in
D2
D1
CINT1
CINT2
VINT(N)
2
VS2
5
VS1
VCD VCG
4
3
1
S1
C4
SF
D
C1
6 pF
SF
G
10 pF
PU
I
I
bias2
bias1
PU
OP1
D
C2
S5
R1
PU
OP4
6 pF
20 kΩ
OP4
D
OP1
PU
G
30 µA
30 µA
V
V
OP4
DD
DD
IN
OP4
OP4
PU
G
filter
C3
BAND GAP
PU
ref
AND CURRENT
REFERENCE
16.6 pF
G = 0.3
V
PCF5079
V
DD
DD
PU/PD
phases commands
10 µA
10 µA
S4
S3
V
V
home
prebias
6 kΩ
SS
VDAC
CONTROL
LOGIC
R4
V
V
DD
SS
V
7
VDAC
6
10
8
9
V
V
DD
PU
BS
SS
MGT325
AUXDAC3
PCF5073x
Fig.1 Block diagram.
4
2001 Nov 21
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
6
PINNING
Pin description
6.1
SYMBOL
VCG
PIN
TYPE(1)
DESCRIPTION
PA control voltage output (GSM)
1
2
O and A
I and A
O and A
I/O and A
I/O and A
G
VINT(N)
VCD
VS1
VS2
VSS
negative integrator input
PA control voltage (DCS)
sensor signal input 1
sensor signal input 2
reference ground
3
4
5
6
VDAC
PU
7
I and A
I and D
I and D
P
DAC input voltage
8
power-up input
BS
9
band selection input
positive supply voltage
VDD
10
Note
1. O = output, I = input, I/O = input/output, A = analog, D = digital, P = power supply and G = ground
6.2 Pin configurations
handbook, halfpage
handbook, halfpage
VCG
1
2
3
4
5
V
DD
10
9
V
VS2
VS1
VCD
5
4
3
6
7
SS
VINT(N)
VCD
BS
VDAC
8
8
PCF5079T
PU
PCF5079HK
PU
BS
2
1
9
VINT(N)
VCG
VS1
7
VDAC
V
10
DD
6
V
VS2
SS
MGT326
MGU268
Fig.2 Pin configuration (top view) for PCF5079T,
pins are numbered counter-clockwise.
Fig.3 Pin configuration (bottom view) for
PCF5079HK, pins are numbered clockwise.
2001 Nov 21
5
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
7
FUNCTIONAL DESCRIPTION
General
7.4
Start-up and initial conditions
7.1
The PCF5079 is designed to operate in bursts, as required
in TDMA systems. Referring to Fig.4, for each time slot to
be transmitted the PCF5079 must be enabled by setting
signal PU to logic 1. Once pin PU is active, BS is taken
into account to allow correct initialisation of switches S1,
SFD, SFG, S3, S4 and S5, and of the configuration signals
PUG and PUD.
The PCF5079 contains an integrated amplifier for the
detected RF voltage from the sensor, an integrator and an
active filter to build up a PA control loop for cellular
systems with a small number of passive components
suitable for dual-band applications. The active band can
be selected by means of the dedicated input BS.
The feedback switch across the unused driver is kept open
and the output voltage from the unused driver is tied to VSS
to maintain the off state of the unused PA.
The sensor amplifier can amplify signals from an
RF power detector in a range of less than −20 to +15 dBm.
This can comply to the PA output power range of
GSM900/1800/1900 systems when, for example, a
directional coupler with 20 dB attenuation is used for
GSM900 and a directional coupler with 18 dB attenuation
is used for GSM1800.
When pin PU is set to logic 1, at least 5 µs after VDD has
reached its final value, switches S1, the appropriate switch
SFD or SFG and S3 are closed, and switches S4 and S5
are opened. Because switch S1 is closed, the forward
voltage of Schottky diodes D1 and D2 is sampled on
capacitors C1 and C2 respectively.
The external Schottky diodes for power detection (sensor)
are biased by an integrated current source of 30 µA.
Variations of the forward voltage with temperature have no
influence on the measured signal because they are
cancelled by the switched capacitor amplifier OP1.
Moreover, the control voltage on pin VCD or VCG is
initially forced to be at the pre-bias voltage because the
appropriate switch SFD or SFG and S3 are closed, and S4
is opened.
An external DAC with at least 10-bit resolution (for
example, AUXDAC3 of baseband interface family
PCF5073x) is necessary to control the loop.
After a fixed time, defined on-chip, switch S1 is opened
and the circuit is ready.
An integrated active filter smooths the voltage steps of the
DAC during ramp-up and ramp-down.
Once switch S1 is open, a ramp signal applied at
pin VDAC (at least 20 µs after the transition of pin PU from
logic 0 to logic 1) with an amplitude of at least 70 mV, from
CODESTART to CODEKICK, determines the opening of
switch S3 and closing of switch S4 on the home voltage,
with a delay of 3 µs maximum with respect to the ramp.
After switch S3 opens (in a fixed amount of time), the
control voltage on pin VCD or pin VCG rises to the home
position to bias the PA to the beginning of the active range
of its control curve. During this time (typically 2 µs), the
appropriate switch SFD or SFG remains closed. When the
appropriate switch SFD or SFG is opened, switch S5 is
closed, allowing the transfer of any signal coming from
amplifier OP1. After this preset, the control voltage is free
to increase according to the control loop if the RF input is
enabled (see Fig.12).
The operation principle is the same, independently of the
selected standard. The DAC signal and the sensor signal
are added by amplifier OP1. The voltage difference of both
signals is integrated by operational amplifier OP4
dedicated to the selected standard, which delivers the
PA control voltage on an external capacitance, CINT1 or
or CINT2, between pins VINT(N) and VCD or VCG,
respectively. The shape of the rising and falling power
burst edges can be determined by means of the DAC
voltage.
7.2
Power-up mode
The device includes a power-up input (pin PU) to switch
the IC on during time slots that are used in TDMA systems,
and to switch the IC off during the unused slots to reduce
current consumption.
For higher DAC ramp steps, the delay of switch S3
opening (S4 closing) is reduced while the delay between
switch SFD (SFG) opening with respect to S3 opening
(S4 closing) remains unchanged.
7.3
OP4 (integrator)
The operational amplifier OP4 (integrator) consists of a
shared input stage, OP4IN and a dedicated output driver
for each standard, OP4G and OP4D. Depending on the
status of input BS, one driver is active and the other is kept
in power-down mode during active time slots.
2001 Nov 21
6
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
V
DD
PU
time
time
t
d1
>5 µs
V
VDAC
CODE
KICK
>70 mV
CODE
START
0
2
4
6
8 . . .
time (QB)
t
d2
>20 µs
closed
S1
S3
open
time
time
closed
open
t
d3
<3 µs
(max)
closed
open
S4
time
time
closed
open
SF , SF
D
G
t
d4
2 µs (typ)
closed
open
S5
time
V
V
VCD, VCG
V
home
V
prebias
time
MGT327
The maximum value of CODESTART is limited by the isolation requirement of the PA used in the application. The pulse determined by CODEKICK minus
CODESTART applied for two quarter-bits ensures a start-up of the control voltage with very low jitter and high repetitivity. The codes following CODEKICK
have to be chosen to get the best ramp shape and spectrum performance.
Fig.4 Start-up and initialization timing diagram.
2001 Nov 21
7
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
7.5
Home position voltage
codes, applied for a certain number of Quarter-Bits (QB),
is used to balance the energy stored in the summing node
during the time interval between the start of control voltage
on pin VCD or VCG ramping-up and the feedback of a
detected ramp to the sensor input. Also a very slow
ramp-down is avoided when the PA switches off and the
loop gain becomes zero.
Internally, a forward voltage of an on-chip silicon diode is
provided as a default home position. This voltage matches
the requirements at the control input of most PAs and
exhibits the same temperature coefficient.
7.6
End of burst
The amount of energy required at the end of the
ramp-down depends on the overall loop gain and on the
time needed to reach PA conduction from the home
position. At the end of a burst, when pin PU is set to
logic 0, control voltage on pin VCD or VCG is forced
The ramp-down should drive the PA from conduction to
shut off in a controlled way (see Fig.5). To get this result,
correct DAC programming is required, so that the last code
of the DAC ramp-down (CODEEND) is lower than the initial
code of the ramp-up (CODESTART). In this way, the energy
corresponding to the difference between start and end
to VSS
.
PU
time
V
VDAC
CODE
START
CODE
END
time (QB)
. . . i−8
i−6
i−4
i−2
i
closed
open
S1, S3
S4, S5
time
time
closed
open
V
V
VCD, VCG
V
SS
time
(1)
t
A
t
d5
MGT328
<
1 µs
(1) The exact duration of tA depends on both PCF5079 and the application loop characteristics. The contribution of PCF5079 is due mainly to the group
delay of the low-pass filter on the VDAC input (see Fig.11).
Fig.5 End of burst timing diagram.
2001 Nov 21
8
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
7.7
Considerations for ramp-down
Time t1 can be calculated with the preceding simplification.
Now, to define the quantity
Referring to Fig.5, the i-th code can be programmed to
have either the CODEEND or CODESTART value or any
code between, depending on the application preferences.
These codes do not produce any power at the output of the
PA, as CODESTART has been chosen to keep the PA
isolation. The proper conclusion of the ramp-down is
ensured by choosing CODEEND < CODESTART so that the
discharge of the integration capacitance is controlled until
the control voltage on pin VCD or VCG goes below the PA
conduction threshold and by applying at this time the PU
transition from logic 1 to logic 0.
∆VKICK = CODEKICK – CODESTART
(2)
the current/voltage equations around the integrator OP4
can be solved by forcing the current through R1 to be
equal to the current through the integration capacitance
and calculating the ∆V generated on CINT, then
t
1
∆VCINT
=
×
i (τ )dτ
(3)
--------------
∫
CCINT
0
where
gd × ∆VKICK
i(τ) =
(4)
(5)
------------------------------
R1
At the beginning of a burst, the VDAC signal steps applied
at OP1 are not compensated by any signal at the sensor
input up to when pin VCD or VCG voltage is greater than
the PA conduction threshold voltage. In any case, the
initial DAC voltage steps are stored in the capacitance of
amplifier OP1. CODEEND has to be chosen so that the
energy inside the shaded zone cancels the energy
accumulated in the summing node (OP1) at the start of a
burst and not balanced by a feedback signal at the sensor
input.
Substituting equation (4) into equation (3)
t
1
∆ V CINT
=
×
g × ∆VKICKdτ
----------------------------
∫
C
CINT × R1
0
d
Under the hypothesis the voltage is constant:
1
∆VCINT
=
× g × ∆VKICK × t
(6)
----------------------------
CINT × R1
d
C
Equation (6) can be used to calculate time t1 at which the
conduction of the PA is reached, considering that
The exact value of the energy required depends on the
specific PA, on the characteristics of the overall loop and
on the values chosen for the settable parameters inside
the loop.
t = t1
V
home + ∆VCINT = Vconduction
(7)
V
conduction – Vhome
t1 = R1 × CCINT
×
(8)
----------------------------------------------
gd × ∆VKICK
A rough idea can be derived with a simplified analysis of a
ramp-up, ramp-down cycle using the following
simplifications:
Time t1 depends on the time constant of the integrator, by
the PA and by ∆VKICK. The condition to be fulfilled is that
the energy contained in the shaded zone (Fig.5) is at least
equal to the energy accumulated at the beginning:
t1
• The starting conditions for OP1 and OP4 are biasing at
Vhome with zero charge on capacitances
• The initial rising of pin VCD or VCG voltage from Vhome
is caused only by the integration of the constant
CODEKICK
V 2out
(t) dt = k × QB × (CODEEND – CODESTART)2 (9)
∫
OP1
0
where k is the number of quarter-bits during which
CODEEND is applied.
• VDAC is treated as applied directly at the summing
node, initially neglecting the transmission delay through
the internal low-pass filter.
Generally, the integrator OP4 input can be expressed as
Vin(integrator) = gs × ∆Vs – gd × ∆VVDAC
(1)
where gs and gd are respectively the gains of sensor input
and DAC input in the summing amplifier OP1.
Equation (1) holds for closed loop operation. In the time
interval between the rising of pin VCD or VCG voltage due
to CODEKICK (t = 0) and when Vconduction for the PA is
reached (t = t1), ∆Vs is 0 and operation is open loop. In this
time interval, a charge accumulates in the summing node,
which remains uncompensated.
2001 Nov 21
9
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
7.8
Table 1 Operating conditions
POWER-UP INPUT (PU)
Configurations
OPERATING MODE
0
1
disabled; reset
enabled
Table 2 Band selection configuration
BAND SELECT
BAND
DRIVER
SWITCHES
SFG → working;
CONTROL VOLTAGE
INPUT (BS)(1)
0
1
GSM
DCS
OP4G → active;
V
V
VCG → working;
VCD → VSS
OP4D → power-down SFD → open
OP4D → active; SFD → working;
OP4G → power-down SFG → open
V
V
VCD → working;
VCG → VSS
Note
1. BS input has to be set before the PU transition logic 0 to logic 1.
7.9
Summary of current and voltage definitions
Refer to Figs 1, 4 and 12.
SYMBOL
DESCRIPTION
sensor signal of incident RF power or power sensor 1 signal
sensor signal of reflected RF wave or power sensor 2 signal
DAC voltage
VVS1
VVS2
VVDAC
VVCG
VVCD
Vhome
Vprebias
Ibias1
control voltage of PA
control voltage of PA
home position voltage
prebias reference voltage; used at the start-up
bias current for detector diode D1
bias current for detector diode D2
input signal to the power amplifier
output signal from the power amplifier
Ibias2
RFin
RFout
7.10 Timing
Refer to Figs 4 and 5.
SYMBOL
DEFINITION
MIN.
5.0
MAX.
UNIT
td1
td2
td3
td4
td5
delay time; VDD application to PU input transition logic 0 to 1
delay time; PU input transition logic 0 to 1 to VVDAC ramp-up
VVDAC ramp-up detection time
−
−
µs
µs
µs
µs
µs
20
−
3.0
2.6
1.0
delay time; ramp-up detected to VVCD, VVCG = Vhome
delay time; PU input transition logic 1 to 0 to end of burst
−
−
2001 Nov 21
10
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
8
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
+6.0
UNIT
VDD
VI
supply voltage
2.5
V
V
V
DC input voltage on all pins except VS1 and VS2
DC input voltage on pins VS1 and VS2
−0.5 VDD + 0.5
−3.0 VDD + 0.5
VVS1
,
VVS2
II
DC current into any signal pin
total power dissipation
TSSOP10 package
−10 +10
mA
Ptot
−
−
315(1)
844(2)
mW
mW
V
HVSON10 package
Ves
electrostatic handling voltage
human body model; note 3 2000 −
machine model; note 4
pins 4 and 5
all other pins
150
200
−
−
V
V
Tstg
storage temperature
ambient temperature
−65 +150
−40 +85
°C
°C
Tamb
Notes
Tj – Tamb
1. Where Ptot
=
and the thermal resistance between junction and ambient Rth(j-a) = 206.3 K/W.
-----------------------
Rth(j-a)
2. Where Rth(j-a) = 77 K/W on JEDEC 2S2P board (100 × 100 mm).
3. Human body model: C = 100 pF; R = 1.5 kΩ.
4. Machine model: C = 200 pF; L = 0.75 µH; R = 0 Ω.
9
ELECTROSTATIC DISCHARGE (ESD)
The PCF5079 is compliant to the General Quality Specification for integrated circuits “SNW-FQ-611D” under the stress
condition EDSH (human body) and the stress condition ESDM (machine model).
10 DC CHARACTERISTICS
VDD = 2.5 to 5 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITION
MIN. TYP. MAX. UNIT
VDD
supply voltage
2.5
−
3.6
−
5.0
10
10
V
IDD(op)
IDD(idle)
total operating current
total idle current
no load on pins VCD or VCG
mA
µA
no load on pins VCD or VCG;
note 1
−
−
Logic inputs (pins PU and BS)
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
0
−
−
−
−
0.3
VDD
VDD
+5
V
VDD = 2.5 to 3.7 V
0.9
0.95
−5
V
VDD = 3.7 to 5.0 V
V
ILL
LOW-level input leakage current
VIL = 0 V
µA
2001 Nov 21
11
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
SYMBOL
PARAMETER
CONDITION
VIH = 5.0 V
MIN. TYP. MAX. UNIT
ILH
CI
HIGH-level input leakage current
input capacitance
−5
−
+5
µA
−
10
−
pF
Sensor inputs and bias current source (pins VS1 and VS2)
VVS2
VVS1
input voltage
input voltage
−3
−3
−
−
VDD
VDD
V
V
Ibias1
Ibias2
,
bias current source for detector
diodes D1 and D2
VI = 0 V; Tamb = 25 °C; see Fig.6
DD = 2.5 V
V
17
21
−
28
39
45
−
µA
VDD = 5.0 V
33
µA
TCIbias1
TCIbias2
,
temperature coefficient of
Ibias1 and Ibias2
0.07
mA/K
Internal home position voltage
Vhome
internal home position voltage
Tamb = 25 °C
0.550 0.600 0.650
−2.1
V
TCVhome temperature coefficient for Vhome
−
−
mV/K
Note
1. A resistive load on pins VCD or VCG to ground (VSS) does not result in additional current consumption.
MGT332
35
handbook, halfpage
I
bias
(µA)
33
31
29
27
2.5
3
3.5
4
4.5
DD
5
V
(V)
Fig.6 Typical value of Ibias as a function of
VDD at Tamb = 25 °C.
2001 Nov 21
12
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
11 OPERATING CHARACTERISTICS
VDD = 2.5 to 5 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITION
MIN.
TYP. MAX. UNIT
Integrator (OP4G and OP4D)
VDD
supply voltage
2.5
3.6
4
5.0
−
V
BG
gain bandwidth
CL = 120 pF; note 1
−
MHz
dB
V/µs
V/µs
V
PSRR
SRpos
SRneg
VO(min)
VO(max)
power supply ripple rejection
positive slew rate
f = 217 Hz; VDD = 3 V; note 1 50
55
3.2
3.2
−
−
VDD = 3 V; note 2
2.0
−
negative slew rate
VDD = 3 V; note 2
2.0
−
minimum output voltage
maximum output voltage
Tamb = 25 °C; see Fig.7
RL = 350 Ω; see Fig.8
−
0.2
−
0.85VDD
−
V
Capacitors C1, C2 and C4
matching ratio accuracy
between C1, C2 and C4
Low-pass filter for DAC signal (3rd-order Bessel filter)
M
−
1
−
%
f3dB
corner frequency
group delay time
70
100
3.0
130
4.2
kHz
td(group)
see Fig.11
1.8
µs
Notes
1. Guaranteed by design.
2. Slew rates are measured between 10% and 90% of output voltage interval with a load of 40 pF to ground.
MGT333
MGT334
0.258
13
handbook, halfpage
handbook, halfpage
I
TC
L
(mV/K)
(mA)
0.256
0.254
0.252
11
9
7
0.250
2.5
5
2.5
3
3.5
4
4.5
DD
5
3
3.5
4
4.5
DD
5
V
(V)
V
(V)
Fig.7 Temperature coefficient of VO(min) as a
function of VDD
.
Fig.8 Minimum load current as a function of VDD.
2001 Nov 21
13
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
MGT336
MGT335
1
1
handbook, halfpage
handbook, halfpage
V
or V
V
or V
VCG
VCD
VCG
VCD
V
V
DD
DD
(1)
0.96
0.9
0.8
0.7
0.6
(2)
(3)
0.92
0.88
0.84
0.80
2.5
3
3.5
4
4.5
DD
5
300
500
700
900
1100
1300
(Ω)
V
(V)
R
L
(1) IL = 6 mA.
(2) IL = 8 mA.
(3) IL = 10 mA.
V DD = 2.5 V.
VVCD or VVCG
VVCD or VVCG
Fig.9 Minimum
of RL.
as a function
Fig.10 Minimum
as a function
------------------------------------
VDD
------------------------------------
VDD
of VDD
.
MGW101
4
handbook, halfpage
delay
(µs)
3
2
1
0
10
3
4
5
6
10
10
10
f (Hz)
Fig.11 Low-pass filter group delay at pins VCD
and VCG (typical values).
2001 Nov 21
14
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
12 APPLICATION INFORMATION
RF
out
(dBc)
0
−10
−20
−30
−40
−50
−60
−70
−80
−28
−18
−10
0
+543
+553 +561
+571
time (µs)
V
VDAC
typ <0.9V
DD
of PCF5073x
CODE
CODE
END
(1)
START
CODE
KICK
CODE
START
0
2
4
6
8
10 12 14 16
16+n
20+n
24+n
28+n
32+n
time (2 × QB)
18+n
22+n
26+n
30+n
nx (2 × QB)
V
V
VCD, VCG
typ >0.85V
DD
with R = 350 Ω
L
PA conduction
threshold
V
prebias
0
2
4
6
8
10 12 14 16
16+n
20+n
24+n
28+n
32+n
time (2 × QB)
18+n
22+n
26+n
30+n
nx (2 × QB)
APEDAC3
(PCF5073x)
time
time
PU
(PCF5079)
RF
in
time
(2)
t
A
>20 µs
MGT329
<1 µs
(1) The software design must guarantee that CODESTART is applied before the PU transition from logic 0 to logic 1.
(2) The exact duration of tA depends on both PCF5079 and the application loop characteristics. The duration should be long enough to ensure that
VVCD, VVCG is below the PA conduction threshold. The contribution of PCF5079 is mainly due to the group delay of the low-pass filter on the VDAC
input (see Fig.11).
Fig.12 Timing diagram for one time slot with PCF5073x family.
2001 Nov 21
15
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
RF SECTION
V
VCG
1
DD
10
9
CINT1
< 50 pF
VINT(N)
BS
R1
R2
2
3
4
5
1 kΩ
1 kΩ
CINT2
< 50 pF
VCD
VS1
VS2
PU
8
PCF5079
VDAC
7
0 to 2.3 V
V
SS
6
AUXDAC3
PCF5073x
MGT337
Fig.13 Diagram showing external components required.
12.1 Ramp control
CODEKICK and Vhome define the starting conditions for
ramping-up. Ramping-up and ramping-down are defined
by VVDAC. CODEEND and CODESTART define the correct
shut-off of the power module.
The non-linear behaviour of the control curves of the
power modules has a large influence on the loop. Starting
conditions in the flat area of the control curve are critical
and need some attention. Initially the voltage on
pins VCD (VCG) will be at the home position.
Successively, the integrator is moved into the active part
of the control curve.
I
handbook, halfpage
V
L
V
VCD, VCG
R
120 pF
350 Ω
L
MGT338
This is achieved by integrating CODEKICK. When
VCD (VCG) voltage has reached the active region of the
control curve, the loop is closed and the circuit can follow
the ramping function generated at pin VDAC. The top
value of VDAC voltage determines the power of the
transmit burst. Ramping-down is started according to the
decrease of VDAC voltage. The loop follows the leading
function for ramping-down until the RF sensor leaves its
active region. The reason for CODESTART and CODEEND
is to shorten the tail of the slope.
Fig.14 Worst case load on control voltage pins
VCG and VCD.
2001 Nov 21
16
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
12.2 PA protection against mismatch
As two sensor inputs are available in the PCF5079, two
different detector signals can be combined: one for direct
path and one for reflected path. These two voltages, fed to
the sensor inputs, are summed inside the PCF5079
resulting in a decrease in the PA output power if there is an
increase of the VSWR at the antenna port (see Fig.15).
High VSWR at the PA output may occur in systems where
the PA is connected to the antenna via couplers and
switches with low insertion loss, depending on the antenna
matching. The incident and reflected power have to be
monitored and care has to be taken to prevent the
summed RF power does not exceed the defined maximum
value at the PA output.
PA
band select
switch
broad band
coupler
RF HB
in
RF
out
RF LB
in
C1
C2
D2
VS1
VS2
R1
D1
R2
MGT330
Fig.15 Example of PA mismatch protection circuit.
Table 3 Table of components (see Fig.15)
SYMBOL
D1, D2
COMPONENT
DESCRIPTION
detector diode
resistor
Philips 1PS79SB62
R1, R2
C1, C2
−
R = 1 kΩ (decoupling versions)
capacitor
C = 39 pF
band select switch
Motorola; Alpha Industries; M/A; COM GaAs MMIC; or discrete pin diode,
e.g. Philips BAP51-03
−
broad band coupler Murata LCD20 series; TDK HHM 20, 22 series
2001 Nov 21
17
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
12.3 Detected voltage measurement
PCF5079
RF GMSK
MODULATED
SIGNAL
V
DD
GSM: 39 pF
DCS: 8.2 pF
1 kΩ
PROBE
MGU223
Fig.16 Set-up for measuring detected voltage for 900 MHz and 1800 MHz working.
MGU224
10
V
V
VS1, VS2
1
(1)
(2)
−1
10
−2
10
−20
−15
−10
−5
0
5
10
15
P
(dBm)
in
(1) DCS.
(2) GSM.
Fig.17 Detected voltage as a function of incident power for 1PS79SB62 detector diodes.
18
2001 Nov 21
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
12.4 Application examples
RF
RF
in
in
PA
MODULE
V
apc
BS
RF
GSM1800
GSM900
RF
out
out
D2
D1
CINT1
VCD
R1
R2
VS2
VS1
VCD VINT(N) VCG
5
6
4
7
3
2
9
1
PCF5079
8
10
V
VDAC PU
BS
V
DD
SS
0 to 2.3 V
AUXDAC3
PCF5073x
MGT331
Fig.18 Application example of a dual-band PA module with single control input.
19
2001 Nov 21
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100 nF
100 nF
+3.6 V
Murata
LDC15H200J0897
220 µF
V
V
S1
S2
5
7
TXGSM
RF
12
1
2
3
6
16
8
9
10
11
14
4
RF
outGSM
inGSM
HIGH GAIN
UHF AMPLIFIER
MODULE
BGY280
RF
inDCS
39
pF
47 Ω
(1)
47 Ω
TXDCS
15
13
V
V
C1
C2
1 kΩ
47 pF
47 pF
1PS79SB62
Murata
LDC15H180J1747
VS2 VCD
3
VCG VS1
1 4
VINT(N)
5
2
BS
PU
RF
band select
power-up
9
8
7
outDCS
PCF5079
VDAC
control voltage
10
6
8.2
pF
68 Ω
(1)
47 Ω
V
V
DD
SS
+2.4 to 6 V
MGT757
1 kΩ
1PS79SB62
(1) Precise value depends on the PCB design.
Fig.19 Application diagram.
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
13 PACKAGE OUTLINES
TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm
SOT552-1
D
E
A
X
c
y
H
v
M
A
E
Z
6
10
A
(A )
2
A
3
A
1
pin 1 index
θ
L
p
L
1
5
detail X
e
w M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.05
0.95
0.80
0.30
0.15
0.23
0.15
3.10
2.90
3.10
2.90
5.00
4.80
0.70
0.40
0.67
0.34
6°
0°
mm
1.10
0.25
0.50
0.95
0.1
0.1
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
99-07-29
SOT552-1
2001 Nov 21
21
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
HVSON10: plastic, heatsink very thin small outline package; no leads;
10 terminals; body 3 x 3 x 0.90 mm
SOT650-1
y
C
1
X
y
C
B
A
D
E
A
4
A
terminal 1
index area
detail X
v M
B
b
w
M
1
5
L
E
h
Bottom view
6
10
e
D
h
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
b
E
e
y
0
1
2 mm
D
D
E
L
v
w
y
4
h
max.
h
1
0.85 0.30 3.20 2.55 3.20 1.75
0.60 0.18 2.80 2.25 2.80 1.45
0.50
0.30
scale
mm
0.05
0.1
0.90
0.5
0.2
0.1
REFERENCES
JEDEC
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
EIAJ
01-01-22
SOT650-1
MO-229
2001 Nov 21
22
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
14 SOLDERING (TSSOP10)
If wave soldering is used the following conditions must be
observed for optimal results:
14.1 Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
14.2 Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
14.4 Manual soldering
14.3 Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2001 Nov 21
23
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
14.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
BGA, LFBGA, SQFP, TFBGA
WAVE
not suitable
REFLOW(1)
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
PLCC(3), SO, SOJ
not suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2001 Nov 21
24
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
15 SOLDERING (HVSON10)
15.1 Soldering information
The dimensions X and Y indicate respectively the width
and the length of the pad. Note that the calculated
X dimension is the maximum value in order to avoid solder
bridging between adjacent pads.The calculated
Y dimension is the minimum value and therefore pad
design should start with this value and the pad length at
the outside be extended if more solder joint fillets are
required.
Information contained within this chapter is of a preliminary
nature and may change without notice.
15.2 PCB design guidelines
These guidelines are to help the user in developing the
proper PCB design. For the surface mount process refer to
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
The dimension ‘Cpl’ defines the minimum distance
between the inner tip of the pad and the outer edge of the
thermal pad. It is suggested that this dimension be fixed at
0.15 mm to avoid solder bridging issues between the
thermal pad and the perimeter pads.
15.2.1 PERIMETER PAD DESIGN
Referring to Fig.20, dimensions Z and G are respectively
the outside to outside and the inside to inside pad
dimensions.
2.00 REF
0.69
Y =
0.55
1.20
1.00
G =
2.09
3.46
3.27
1.20
1.00
Z =
0.33
0.30
thermal via
Cpl = 0.15
MGW498
X = 0.28
0.50
TYP
Dimensions in mm.
The solder mask opening dimension should be larger than the pad dimension by 125 to 150 µm.
Fig.20 HVSON10 PCB pattern.
15.2.2 THERMAL PAD AND VIA DESIGN
the top metal layer to the inner or bottom layers of the
PCB, thermal vias should be incorporated into the thermal
pad design. The number of thermal vias will depend on the
application and on the power dissipation and electrical
requirements. It is recommended to incorporate an array
of thermal vias at a pitch of 1.0 to 1.2 mm with the via
diameter between 0.3 and 0.33 mm.
The size of the thermal pad should at least match the size
of the exposed die-attach paddle. However, in some
cases, the die-attach paddle size may need to be modified
to avoid solder bridging between the thermal pad and the
perimeter pads. In order to effectively transfer heat from
2001 Nov 21
25
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
15.2.3 STENCIL DESIGN FOR PERIMETER PADS
15.2.4 STENCIL DESIGN FOR THERMAL PADS
For optimum paste release the area and aspect ratios of
the stencil should be greater than 0.66 and 1.5
respectively.
In order to remove the heat effectively from the package
and to enhance electrical performance the die-attach
paddle needs to be soldered to the PCB thermal pad,
preferably with minimum voids.
area of aperture opening
-----------------------------------------------------------------
aperture wall area
L × W
Area ratio =
Aspect ratio =
where:
=
--------------------------
2T(L + W)
It is therefore recommended that smaller, multiple
openings in a stencil should be used instead of one large
opening for printing solder paste in the thermal pad region.
This results typically in 50% to 80% solder paste coverage.
Two examples are shown in Fig.21.
aperture width
-------------------------------------------
stencil thickness
W
-----
T
=
L = aperture length
W = aperture width
T = stencil thickness.
15.2.5 STENCIL THICKNESS
A stencil thickness of 0.125 to 0.150 mm is recommended
but this value needs to be optimized by the user to find the
proper thickness according to application requirements.
MGW499
a. Outline of 0.4 mm2 2 × 2 array giving
b. Outline of 1.2 mm2 2 × 1 array giving
44% solder paste coverage.
60% solder paste coverage.
Fig.21 Examples of thermal pad stencil design.
2001 Nov 21
26
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
16 DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS(1)
STATUS(2)
DEFINITIONS
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
17 DEFINITIONS
18 DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2001 Nov 21
27
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2001
SCA73
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403506/01/pp28
Date of release: 2001 Nov 21
Document order number: 9397 750 07095
相关型号：
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